Visual Basic for Applications
The Datapump Board
Jamieson Olsen
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Background I
D0 Central Track Trigger (CTT)
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Background II
Trigger Electronics
Low Voltage Differential Signal (LVDS) Channel Links
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Background III
LVDS Channel Links
28/
28/
5 Twisted Pairs
1.5 Gbps53MHz clock
DATA DATA
53MHz clockJ108
The PROBLEM:
Can’t probe the LVDS pairs! Can’t use a logic analyzer or ‘scope!
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The Datapump
To debug our trigger hardware it would be useful to have a data pattern generator that would drive channel links.
Likewise, it would be good to have a board that could capture channel link data and read it out.
General purpose – it should work with AFE, Mixer, and DFE boards!
DatapumpDeviceUnderTest
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Hardware Interface
Need some easy way toload test vectors into thetransmitters and readoutthe captured data on thereceivers.
What’s the hardware interface?
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Hardware Interface
OK, use a PC!How should the PC connect to the Datapump?
VME is not portable PCI, PCMCIA, USB, IEEE1394? Huh? Parallel port is fast & easy to program!(More on this later…)
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Datapump Board
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Datapump Board
Three medium-sized Field Programmable Gate Arrays (FPGAs) are used to build the transmitter and receiver circuits.
A small CPLD acts as the parallel port interface “bridge” to the FPGAs.
U3
CPLD
PC
U2
U1
TXATXBTXCTXDTXE
TXFTXGTXHTXJTXK
RXARXBRXCRXD
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Transmitter Circuit
Each transmitter sends 128 28-bit words (loops continuously).
All ten transmitters are synchronized to the same counter and 53MHz clock.
The transmitter test vectors can be read back for verification.
RAM
Counter
LVDSTX
0x00000000xFFFFFFF0xAAAAAAA0x55555550x1234567etc...
OutputPC
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Receiver Circuit
Specify a unique trigger pattern for each receiver. Should include ‘X’ (don’t care) bits.
All receivers are armed simultaneously. Once armed, each receiver waits for the trigger
pattern, then captures 256 data words.
RAMLVDS
RXTriggerLogic
Trigger Pattern:1000 1010 1010 1xx0 xxxx 1110 11xx
PCInput
'Arm' and Status Bits
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Parallel Port
Enhanced Parallel Port (EPP) is used 8-bit bi-directional datapath Three “ports” in the PC I/O space:
Control, Data, Address Setup the control port, then… To write a byte: outp(port, data) To read a byte: inp(port)
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Parallel Ports and VBA
VBA does not include the inp() and outp() functions.
VBA calls functions in a DLL (ntio.dll) called VB_pokeIO(port, data) and VB_peekIO(port)
The peek/poke functions in this DLL “cut through” windows and get right to the hardware ports.
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User Interface
There are lots of test vectors which need to be visible simultaneously.
An Excel spreadsheet is ideal for this application!
VBA talks to the datapump via the parallel port.
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Excel Control Buttons
Configure the datapump FPGAs. Write/Verify the transmitter test
vectors. Specify the trigger pattern for each
receiver. ‘Arm’ and readback the receiver
data.
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Configuration
Must do this each time datapump is power cycled.
Originally this was a C program and DOS batch file, but it was all converted into VBA.
Writes three files to the datapump PLDs. The VBA module is called HEXDUMP, calls
two subs Vbwrite_C() and hexdump().
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Datapump Transmitters
VBA module “datapump”, subroutines Download_Vector() and Verify_Vector()
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Datapump Receivers
VBA module “datapump”, subroutines setup_U1() and readback_U1()
Backup Slides
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EPP Registers
U3
CONFIG
DATA
U2
CONFIG
DATA
U1
CONFIG
DATA
EPP_ADDR
EPP_DATA
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DFE Motherboard