VisualDSP++ 4.0 (Updated March 2007) Release Note...VisualDSP++ 4.0 (Updated June 2006) Release Note...

VisualDSP++ 4.0 (Updated March 2007) Release Note

The following release note concerns the March 2007 Update to the VisualDSP++ 4.0 release. This release

is inclusive of previous Updates. The contents of future Updates will be inclusive of all previous Updates.

The release notes for past Updates are appended to the end of this release note.

Identifying Which Update Is Currently Installed on Your System

The Update level is identified in three places:

1. The Add/Remove Programs Control Panel entry for VisualDSP++ 4.0. 2. The VisualDSP++ GUI’s About box, located at “Help” > “About VisualDSP++”. 3. In the file …\System\VisualDSP.ini, in the ProductName key.

Installing an Update

The procedure for installing an Update to VisualDSP++ is described below. Note that it is different from

previous releases of VisualDSP++. Note that with VisualDSP++’s support for installing multiple instances

of itself, it is possible to “trial” an Update in a new directory before switching over your “golden” tools

installation to the Update.

1. Use the Start Menu to navigate to VisualDSP++’s “Maintain this Installation” item. 2. Select “Go to the Analog Devices website” and click “Next”. This will launch your web browser

and navigate it to the proper URL to download Updates from.

3. Download the VisualDSP++ Update file (.VDU) of interest to your hard disk. Note that these files have a .VDU file extension and cannot be executed directly.

4. Navigate to “Maintain this Installation” again. If you have multiple installations VisualDSP++ on your computer, be doubly sure you are navigating to the installation you wish to Update.

5. Select “Apply a downloaded Update” and click “Next”. Click the “…” browser button and navigate to the .VDU file that you downloaded in step 3. Click “OK”, then “Next”.

6. Follow the on-screen prompts to complete the installation of the Update.

Significant Additions

The primary purpose of VisualDSP++ Updates is to address problems and stabilize the release. Significant

new functionality is not expected to be introduced in an Update. However, incremental support (i.e.,

emulation, example programs, header files, default LDF, errata accommodations, EZ-KIT Lite software,

etc.) for new semiconductor products will be added as these products become available and gain support

within the VisualDSP++ tools.

In this release:

1. The Blackfin compiler, runtime, VDK, and SSL libraries include new workarounds for hardware anomalies 05-00-0311 and 05-00-0312. The C/C++ compiler will automatically enable these

workarounds when building for parts and silicon revisions that require them. Alternatively they

can be enabled using the -workaround switch. The Blackfin assembler has a new warning to

indicate potential instances of anomaly 05-00-0312.

05-00-0311 –

The anomaly is seen when an access of a System MMR Flag register is followed by an access of a

specific MMR. The result of the anomaly can be that flag pins configured as outputs that are "set"

can erroneously transition to "clear". The anomaly impacts all revisions of ADSP-BF53[123] and

ADSP-BF561 parts.

The compiler works around the anomaly:

1. By adding a load of the CHIPID MMR at the start of code generated for C defined event

handlers. System Services’ handlers and VDK’s interrupt templates make similar

accommodations. The related workaround for 05-00-0283 will be used if it is enabled at the same

time as this workaround.

2. By identifying accesses, or potential accesses, of any of the various System MMR Flag registers

associated with the errata and generating a load of CHIPID after each such access. The compiler

relies on use of literal addressing of MMRs to identify these accesses, such as using the various

p macros defined in the cdef.h include files. Any loads and stores that do not

use literal addresses and the type of the access is defined qualified as volatile, will be assumed

to be flag MMR accesses, unless the -no-assume-vols-are-mmrs switch is used. If the

-no-assume-vols-are-mmrs compiler switch is used the compiler will apply the

workaround for suitable literal address accesses only and will make no assumptions for non-literal

loads and stores even if volatile.

To enable this compiler workaround manually the -workaround flags-mmr-anom-311

switch can be used. When the workaround is enabled the macro

__WORKAROUND_FLAGS_MMR_ANOM_311 is defined at compile, assemble and link stages.

05-00-0312 -

The anomaly is seen when SSYNC, CSYNC instructions or loads of registers LCx, LTx, and LBx

are interrupted. The anomaly impacts all Blackfin parts and revisions except ADSP-BF535.

The compiler workarounds are as follows:

1. When the workaround is enabled the compiler builtin functions __builtin_ssync() and

__builtin_csync() have been modified to ensure that interrupts are disabled before the

sync/csync instruction and enabled after.

2. New ssync and csync builtins have been provided that do not disable interrupts. These can

be used in place of the existing builtins for code that has been manually verified as safe against the

anomaly. These new builtins are called __builtin_ssync_int() and

__builtin_csync_int().

3. When the workaround is enabled the compiler will ensure that any loads of the LBx, LTx and

LCx registers are executed with interrupts disabled. It does this by inserting a CLI instruction

before such loads and an STI instruction after. The workaround is not required for hardware loop

LSETUP instructions.

4. The compiler will arrange to save and restore the loop registers (LBx, LTx and LCx) while

interrupts are disabled for C/C++ nested interrupt handlers defined using the

sys/exception.h EX_REENTRANT_HANDLER macro.

The assembler has been modified to include a warning which when enabled will identify potential

causes of the anomaly. This warning can be enabled using the -anomaly-warn 05-00-0312

switch. The warning can be suppressed in assembly code ranges which have manually been

determined to be safe against the anomaly using the assembler’s .MESSAGE directive. The

warning id to use when this is required is 5515.

To enable this compiler workaround manually the -workaround sync-loop-anom-312

switch can be used. When the workaround is enabled the macro

__WORKAROUND_SYNC_LOOP_ANOM_312 is defined at compile, assemble and link stages.

For more information on these anomaly please see the appropriate errata sheets which can be

downloaded from http://www.analog.com/processors/blackfin/support/ICanomalies.html.

Changes to Existing Behaviors, Projects, and Source Code

When addressing problems, we attempt to make any changes backward compatible with existing projects.

However, depending on the nature of a problem, compatibility issues are sometimes unavoidable. This

section highlights any changes in the Update that may require the modification of “working” projects or

otherwise influence existing behavior.

In this release, no changes have been identified.

VisualDSP++ 4.0 (Updated June 2006) Release Note

The following release note concerns the June 2006 Update to the VisualDSP++ 4.0 release. This release is

inclusive of previous Updates. The contents of future Updates will be inclusive of all previous Updates.






















In this release:

1. The Blackfin compiler, runtime, VDK, and SSL libraries include new workarounds for hardware anomalies 05-00-0189 and 05-00-0283. The compiler will automatically enable these workaround

when building for parts and silicon revisions that require them. Alternatively they can be enabled

using the -workaround switch.

05-00-0283 –

One part of the workaround is to include a code sequence in all event handlers. The

sequence makes a mispredicted jump over a dummy MMR read. This must be done

before any SSYNCs in the handler. This sequence is generated by the compiler for

C/C++ based event handlers that use #pragma interrupt or sys/exception.h

defined macros such as EX_INTERRUPT_HANDLER. The two handlers affected in the

runtime libraries are _cplb_hdr and the interrupt dispatcher _despint which have

been modified to include the workaround.

The second part of the workaround is to avoid system MMR writes in the two

instructions after a not-predicted conditional jump. The compiler will insert nop

instructions to avoid this when it identifies the problem sequence.

These workarounds can be enabled using the -workaround stalled-mmr-

write-283 switch. When the workaround is enabled the macro

__WORKAROUND_STALLED_MMR_WRITE_283 is defined at compile, assemble and

link stages

05-00-0198 –

A workaround for this anomaly was already available in the compiler. However the

conditions which cause anomaly have changed to include a new code sequence. The

compiler has been modified to identify this new sequence. The anomaly may occur

where MMR reads or writes occur immediately after a stalled memory read. The

compiler will avoid such code being generated for C/C++ compiled code. The runtime

libraries are safe against this anomaly.

This workaround can be enabled using the -workaround sdram-mmr-read switch.

When the workaround is enabled the macro __WORKAROUND_SDRAM_MMR_READ is

defined at compile, assemble and link stages.

2. There has been a change of compiler behavior relating to MMR (Memory Mapped Register) accesses and volatile variables. New switch -no-assume-vols-are-mmrs has been added.

There are various MMR related hardware errata that the compiler supports workarounds for; 05-

00-0122, 05-00-0157, 05-00-0198, 05-00-0283. Previously the compiler would only implement

these workaround for accesses that it could absolutely determine were to MMRs. This in practice

meant that only literal MMR addresses accesses could be determined accurately. More complex

accesses, for example using addresses stored in variables, might not be identifiable as MMR

accesses and could therefore result in the various anomalies being hit.

The compiler has been modified to try and avoid missing these more complex MMR accesses. If

an access to a variable is defined qualified as volatile, and the compiler cannot determine that

the access is not to an MMR, the compiler now assumes it to MMR accesses unless the new

switch -no-assume-vols-are-mmrs is used.







VisualDSP++ 4.0 (Updated April 2006) Release Note

The following release note concerns the April 2006 Update to the VisualDSP++ 4.0 release. This release is























In this release:

1. Support for new Blackfin silicon revisions has been added:

• ADSP-BF531/2/3 revision 0.4 • ADSP-BF534/6/7 revision 0.3 • ADSP-BF538/9 revision 0.3 • ADSP-BF561 revision 0.5

2. The Blackfin compiler now includes a workaround for ADSP-BF561, ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF534, ADSP-BF536, ADSP-BF537, ADSPBF538, ADSP-BF539

hardware anomaly 05-00-0202 "Possible infinite stall with specific dual dag situation". The

compiler will automatically enable the workaround for the appropriate silicon revisions, or it can

be manually enabled with the use of the compiler switch -workaround

infinite_stall_202. With the workaround enabled, the compiler will avoid producing

code that contains the dual DAG statements that can produce the anomaly.

The macro __WORKAROUND_INFINITE_STALL_202 will be defined at compile, assemble

and link build phases when the workaround is enabled.

3. Anomaly support has been added for errata 05-00-0229 - "SPI Slave Boot Mode Modifies Registers". When the SPI slave boot completes, the final DMA IRQ is cleared but the

DMA5_CONFIG and SPI_CTL registers are not reset to their default states. We work around this

by resetting the registers to their default values at the beginning of the CRT Startup Code. The

only issue would be the unlikely case of booting from flash and also beginning a DMA during

initialization. In this case, users would need to modify the CRT. This problem impacts all

revisions of ADSP-BF531/2/3/8/9.

4. Anomaly support for some ADSP-BF538/9 revisions has been changed. The following changes have been made to the Anomaly workarounds for the ADSP-BF538 and ADSP-BF539 processors:

05-00-0209 only for silicon revisions 0.0

05-00-0227 only for silicon revisions 0.0, 0.1

05-00-0244 only for silicon revisions 0.0, 0.1

5. The compiler driver switch -glite has been added. The -glite switch can be used on its own, or in conjunction with any of the -g, -Og, -debug-types compiler switches. When this

switch is enabled it instructs the compiler to remove any unnecessary debug information for the

code that is compiled. When used on its own, the switch also enables the -g option. NOTE: This

switch can be used to reduce the size of object and executable files, but will have no effect on the

size of the code loaded onto the target.







Problems Addressed

The following table is a list of the problems addressed in this Update. Details on any particular problem

can be found on the Tools Anomaly web page. Note that after the Issues headings in the top half of the

Tools Anomaly web page, problems are detailed in numeric order. The URL is:

http://www.analog.com/processors/technicalSupport/toolsAnomalies.html

Processor

Family

Problem

Number

Tool Description

All 25026 Assembler Cannot set breakpoints in assembly source when "-save-temps" All 25478 VDK VDK logs some PendSemaphore events against the wrong

thread

All 25615 Linker Expert Linker - Unable to elfdump file All 25616 Run Time

Libraries

A zero precision with %f may output a decimal point

All 25617 Run Time Libraries

%f may print too few leading zeros if the '0' flag is used

All 26774 Compiler Compiler asserts at sr.c:268 Blackfin 21035 Simulator BF561: Invalid cache performance category received

Blackfin 24258 Emulator HPUSB/USB-ICE driver may blue screen on PCs with hyper-

threading

Blackfin 25279 Emulator HPUSB is very unstable at higher JTAG frequencies

Blackfin 25598 Run Time

Libraries

Blackfin Radix2 FFT functions in libdsp can trigger

EXCAUSE 23

Blackfin 25680 Compiler inline asm hard-register inputs loaded in wrong order with -O


Libraries

Libdsp functions mean_fr16 and var_fr16 inaccurate for large

N

Blackfin 25779 Loader Max Zero-Fill Block Size Broken on Sept Update

Blackfin 25912 IDDE VDSP crashes when sending email from the help menu


Libraries

cplbtab538.s source file missing from install


Libraries

Startup code to workaround anomaly 05-00-0229

Blackfin 26010 TCPIP

Stack

lan91c111.h wrongly defines two macros

Blackfin 26023 Assembler Dummy Data section can cause a crash

Blackfin 26265 Compiler “No Register Left To Claim" with sysreg_write of FP/SP


Libraries

zero_cross_fr16 returns wrong result

Blackfin 26364 Compiler unsigned long long divide by 0x8000000000000000 wrong

Blackfin 26377 Compiler signed long long divide by 0x8000000000000000 wrong

Blackfin 26396 Compiler Linker elimination failures with variables in user named section

Blackfin 26405 Compiler macdefs.c:3546 assert when load/store bytes from packed struct

Blackfin 26432 Compiler compare of floats can result in incorrect code -O

Blackfin 26514 XML

Files

DMA Traffic Control Registers Missing in Single Core EDN

procs


Libraries

ETSI shr_r library function does not sign extend result


Libraries

float addition/subtract underflow results in large numbers

Blackfin 26709 System

Services

ADI_PWR_CMD_SET_CLKIN still in MHz

Blackfin 26769 Assembler Having LF in data causes corruption.

Blackfin 26850 Compiler __builtin_conj_fr32 produces incorrect results


Libraries

floating-point addition overflow returns NaN instead of +=Inf

Blackfin 27274 Emulator Hardware BP skip count doesn't stitck, other rough edges


Libraries

64-bit floating point division can incorrectly return 0.0


Libraries

LIBDSP 2D FFTs fail for fft sizes > 64

Blackfin 27562 TCPIP

Stack

(4.0) CaesarCipher GettingStartedGuide doesn't work from

scratch

SHARC 9704 Emulator timer stays running when dsp halts

SHARC 23996 Simulator Interrupts Register Window shows default assignments for

IRPTL

SHARC 24248 Emulator status stack getting corrupted on 21161 EZ-KIT

SHARC 26349 Simulator IDDE will not 'step over' (F10) when using an emulator

SHARC 26433 Simulator Can't view local variables in a debug or expressions windows

SHARC 26718 VDK VDK C/C++ ISRs are not safe to use on SHARC processors

SHARC 26778 VDK P11,P14 and P16 interrupts can't be assigned for some

processors

SHARC 26797 VDK A number of LIRPTL bits cannot be set/cleared using the VDK

APIs

SHARC 27222 XML

Files

Cannot view a number of bits in the Interrupt Registers window

SHARC 27486 Loader 369_spi kernel incorrectly initializes ZERO_L48

SHARC 27564 Simulator Error dialog appears when opening PC stack window

TigerSHARC 25878 Compiler empty C ISR, optimization enabled, corrupts stack-pointer

TigerSHARC 26397 Simulator IDCODE register can not be modified in IDDE

VisualDSP++ 4.0 (Updated December 2005) Release Note

The following release note concerns the December 2005 Update to the VisualDSP++ 4.0 release. This

release is inclusive of previous Updates. The contents of future Updates will be inclusive of all previous

Updates. The release notes for past Updates are appended to the end of this release note.





















In this release:

1. Software support for the FPGA EZ-Extender is now available. Refer to the README at …\Blackfin\EZ-Kits\FPGA EZ-Extender for more information.

2. Support has been added for a handful of new processors: ADSP-21375, ADSP-21362, and AD6900. Projects for these processors can be created by selecting these part numbers in the

project processor selector.

3. Support for the following new revisions of processors has been added:

• ADSP-BF538|9 0.2 • ADSP-BF561 0.4 • ADSP-TS201|2|3 2.0

4. The LwIP Ethernet stack has been ported to the ADSP-BF561 EZ-KIT Lite (when paired with a USB-LAN EZ-Extender). Examples can be found in the

…\Blackfin\lwip\src\examples subdirectory.

5. The following workarounds have been determined to be unnecessary for the following parts and disabled:

Workaround for anomaly 05-00-0189 has been disabled for ADSP-BF531, ADSP-BF532,

ADSP-BF533, ADSP-BF561, silicon revision 0.4 and ADSP-BF534, ADSP-BF536, ADSP-

BF537, ADSP-BF538, ADSP-BF539 silicon revision 0.1.

Workaround for anomaly 05-00-0157 has been disabled for ADSP-BF534, ADSP-BF536,

ADSP-BF537, ADSP-BF538, ADSP-BF539, all silicon revisions.

6. The VisualDSP++ Blackfin compiler now includes a workaround for ADSP-BF561, ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF534, ADSP-BF536, ADSP-BF537, ADSP-

BF538, ADSP-BF539 hardware anomaly 05-00-0202 "Possible infinite stall with specific dual dag

situation". The compiler will automatically enable the workaround for the appropriate silicon

revisions, or it can be manually enabled with the use of the compiler switch -workaround

infinite_stall_202. With the workaround enabled, the compiler will avoid producing

code that contains the dual dag statements that can produce the anomaly.

The macro __WORKAROUND_INFINITE_STALL_202 will be defined at compile, assemble



BF538, ADSP-BF539 hardware anomaly 05-00-0245 "Spurious Hardware Error from an access in

the shadow of a conditional branch". The compiler will automatically enable the workaround for

the appropriate silicon revisions, or it can be manually enabled with the use of the compiler switch

-workaround speculative-loads. With the workaround enabled, the compiler attempts

to avoid the speculative loads to reserved memory on not-taken control paths. It performs this by

ensuring that any speculative loads are distanced from the not-taken jump point by re-arranging

code or inserting NOP instructions at the target. The runtime libraries have been reviewed, and

adapted to avoid the anomaly.

The macro __WORKAROUND_SPECULATIVE_LOADS will be defined at compile, assemble and

link build phases when the workaround is enabled.


BF537, ADSP-BF538, ADSP-BF539 hardware anomaly 05-00-0257 "An interrupt or exception

during short Hardware loops may cause the instruction fetch unit to malfunction". The compiler

will automatically enable the workaround for the appropriate silicon revisions, or it can be

manually enabled with the use of the compiler switch -workaround short-loop-

exceptions-257. Hardware loops less than 4 instructions in length may operate incorrectly if

an interrupt or exception is taken at the end of the loop. The workaround implemented in the

compiler is to include a save and restore of the LC0 and LC1 registers in interrupt and exception

handlers. Such functions would be declared using one of the compiler interrupt handler pragmas

or the macros defined in include file sys/exception.h. The compiler would only normally

save and restore LC0 and LC1 if they were required to be saved and restored because the handler

used them and this workaround means that they will always be restored whether used or not. The

VDK’s interrupt handlers are no longer sensitive to this problem.

The macro __WORKAROUND_SHORT_LOOP_EXCEPTIONS_257 will be defined at compile,

assemble and link build phases when the workaround is enabled.

9. The Blackfin runtime libraries now includes a workaround for ADSP-BF566, ADSP-BF561, ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF534, ADSP-BF536, ADSP-BF537, ADSP-

BF538, ADSP-BF539 hardware anomaly 05-00-0258 "Instruction Cache is corrupted when bit 9

and 12 of the ICPLB Data registers differ". The _cplb_mgr and _cplb_init routines (which

are part of the default cache support in the runtime libraries) set bit 9 (reserved) to the same state

as bit 12 (CPLB_L1_CHBL).


BF538, ADSP-BF539 hardware anomaly 05-00-0259 "Non-deterministic ICPLB descriptors

delivered to hardware". In the runtime library code where disabling ICPLBs by an MMR write,

we ensure that these are immediately followed by a CSYNC, and locate both the write and

CSYNC in the same aligned 64-bit word to avoid the anomaly.


BF538, ADSP-BF539 hardware anomaly 05-00-0261 "DCPLB_FAULT_ADDR MMR register

may be corrupted". DCPLB_FAULT_ADDR MMR can be wrong in some circumstances. The

workaround is to ignore DCPLB miss exceptions the first time they are raised from a particular

PC. The fault address is guaranteed to be correct the second time.


BF537, ADSP-BF538, ADSP-BF539 hardware anomaly 05-00-0262 "Stores to data cache may be

lost". The compiler will automatically enable the workaround for the appropriate silicon revisions,

or it can be manually enabled with the use of the compiler switch -workaround lost-

stores-to-data-cache-262. With the workaround enabled, the compiler will ensure that

dual DAG instructions which may trigger the anomaly are not issued. The compiler will attempt to

use any bank information available to determine cases where the workaround is not required.

The macro __WORKAROUND_LOST_STORES_TO_DATA_CACHE_262 will be defined at

compile, assemble and link build phases when the workaround is enabled.


BF537, ADSP-BF538, ADSP-BF539 hardware anomaly 05-00-0264 "A Sync instruction

(CSYNC, SSYNC) or an IDLE instruction will cause an infinite stall in the second to last

instruction in a hardware loop". The compiler will automatically enable the workaround for the

appropriate silicon revisions, or it can be manually enabled with the use of the compiler switch

-workaround pre-loop-end-sync-stall-264. With the workaround enabled, the

compiler will ensure that generated code does not contain the CSYNC, SSYNC or IDLE instruction

as the second last instruction of a hardware loop. The runtime libraries have been reviewed and

adapted to avoid this anomaly.

The macro __WORKAROUND_PRE_LOOP_END_SYNC_STALL_264 will be defined at compile,

assemble and link build phases when the workaround is enabled.






In this release:

1. Some of the problems addressed involve changes to the default LDFs. If your project has a custom LDF that is heavily based on one of the defaults, your LDF may continue suffer from

problems that have been fixed in the default. Custom LDFs should be audited for correctness. In

particular, SHARC VDK projects have two required changes. Relevant TAR numbers are 25490

and 25494.

2. On 2116x processors, a recently-discovered hardware anomaly means that it may be unsafe to write to a DAG register and then use it to perform a memory access in the next instruction. For

example, the following code sequence is unsafe:

i4 = dm(i7,m6);

dm(i4,1) = r4;

The compiler will automatically avoid generating such code sequences and, where appropriate, the

run-time libraries have been modified to avoid this. Due to the workarounds, however, there may

be a small decrease in code performance and/or a small increase in code size.

The assembler will also report instances of this errata.

The anomaly is documented in the IC Anomalies web page, as follows:

21160M: Anomaly 64

21160N: Anomaly 23

21161N: Anomaly 63

3. To improve the performance of the Blackfin floating point support routines, the compiler and support routines have been enhanced to make use of non-default volatile register set for the

support routines. This has resulted in a performance improvement when using the fast

performance floating point support libraries (the default floating point support, also enabled with

the -fast-fp switch). To continue to support cross-compatible code, allowing users to switch

at link time between the Fast Floating Point and IEEE-Conformant libraries, the IEEE-Conformant

libraries also employ the same volatile register sets as their counterpart Fast Floating Point

routines. In some cases users may experience slight performance degradation when using the

IEEE-Conformant floating point support.

Problems Addressed





Processor

Family

Problem

Number

Tool Description


libio(-fast-io) fwrite writes incorrectly when heap insufficient

All 24849 Blackfin Compiler","section elimination broken for files with user

defined sections

All 25020 Compiler else evaluated before if causing problems All 25265 Compiler an asm that clobbers an lreg doesn't zero it All 25388 Compiler array index using mod (%) can be generated incorrectly with -

O

All 25454 IDDE All connections fail after built-in 90-day Test Drive expires All 25817 VDK Event not recalculated when expected Blackfin 20940 Run Time

Libraries

fp libraries: comparison with NaN may be incorrect

Blackfin 24596 IDDE conditional breakpoints on values of pointers don't work

Blackfin 24730 IDDE file specific options not honoured

Blackfin 24955 Compiler rare problem with exception handling

Blackfin 24990 Simulator BF535: ASTAT register assignment not limited to used bits

Blackfin 25028 CRTGen Mixed line endings can cause issues with generated startup

code

Blackfin 25038 Compiler New gnu asm error faults unnecessarily

Blackfin 25045 Compiler misaligned member arrays do not work

Blackfin 25058 Simulator compiled sim Memory stream leads to exe crashing


Libraries

instruction cplb replacement looping over CPLB boundaries

Blackfin 25275 IDDE September update breaks old sessions

Blackfin 25281 VDK Need to work around errata 05-00-0257

Blackfin 25353 Simulator BF535: System MMR CHIPID access returns incorrect value

Blackfin 25357 Simulator BF535: ASTAT to be masked to prevent unused bits from

being set


Libraries

LibDSP vector and matrix functions write beyond end of array


Libraries

BF538/9 TWI def file macros renamed

Blackfin 25411 Simulator BF5xx: Fractional format not properly handled with DAT files

Blackfin 25489 Simulator BF535: unexpected stalls between PushPopReg instruction and

LDST


Libraries

Default CRT clobbers IMASK set by Device Drivers in

init_devtab

Blackfin 25575 Simulator BF535: execution of LINK and UNLINK is not cycle accurate


Libraries

adsp-BF561_ASM.ldf missing comma

Blackfin 25775 CRTGen Generated startup code does not account for SSL MHz/Hz

change

Blackfin 25851 CRTGen Wrong voltage level set by generated CRT

SHARC 24690 IDDE “Param is incorrect” msg box after load symbols and mixed

mode

SHARC 24711 Simulator Sport transmit interrupt does not fire when DMA complete

SHARC 24776 Assembler -swf_screening_fix can corrupt DB instructions

SHARC 24976 Simulator Instruction timeout for sequences of IOP read/write

SHARC 24979 Run Time

Libraries

conflict between a register bit and a conditional mnemonic.

SHARC 25276 Assembler Internal error related to Si anomaly on code that used to build

SHARC 25278 Debug Agent Unable to connect to a ADSP-21369 EZ-Kit using Ice Test

SHARC 25332 Simulator Some interrupts nest when nesting disabled

SHARC 25406 Loader Loader won't stop generating a stream with a section over 64k

SHARC 25490 VDK New section to allow placing of VDK data in external memory

SHARC 25494 VDK seg_int_code not used properly

SHARC 25607 Assembler Symbolic relocation expressions incorrect in .STRUCT

directive

SHARC 25646 VDK Possible memory corruption when using VDK C/C++ ISR's on

SHARC

SHARC 25707 Simulator Interrupted single-instruction loop ends an iteration early

SHARC 25718 VDK LPISUMI should be ignored when we check for interrupt level

TigerSHARC 25008 Compiler Compiler illegally hoists load above conditional

TigerSHARC 25335 Emulator Double halt causes improper PC value (PC-1) and causes

incorrect

TigerSHARC 25465 VDK Thread RunTotalTime calculated incorrectly

TigerSHARC 25473 Emulator EZ-KIT connection fails after built-in 90-day Test Drive expire

TigerSHARC 25513 VDK Thread RunStartTime (in cycles) is not correct

TigerSHARC 25532 Compiler INTERNAL COMPILER ERROR: Unsupported CMUL

opcode

TigerSHARC 25536 Simulator Simulator does not behave as hardware when jumping to ISR

VisualDSP++ 4.0 (Updated September 2005) Release Note

The following release note concerns the September 2005 Update to the VisualDSP++ 4.0 release. This

release is inclusive of previous Updates. The contents of future Updates will be inclusive of all previous

Updates. The release notes for past Updates are appended to the end of this release note.










In this release:

1. Software support and examples for the ADSP-21369 EZ-KIT Lite has been added. The flash programmer driver can be found at …\213xx\Flash Programmer Drivers\ADSP-

21369 EZ-kit Lite. Example applications can be found at …\213xx\EZ-KITs\ADSP-

21369\Examples. This product’s manual has been added to the on-line help system; a PDF

version is available on ADI’s web site.

2. Software examples for the SHARC USB EZ-Extender have been added and can be found at …\213xx\EZ-KITs\USB EZ-EXTENDER. This product’s manual has been added to the on-

line help system; a PDF version is available on ADI’s web site.

3. The scope and functionality of the System Services Library (SSL) has been significantly updated in this release:

Support for the dual-core ADSP-BF561 processor has been included. The SSL now supports the

following Blackfin processors:

a. ADSP-BF531, ADSP-BF532 and ADSP-BF533 b. ADSP-BF534, ADSP-BF536 and ADSP-BF537 c. ADSP-BF561

In addition to the original services, three additional services have been added:

d. Programmable Flag Control – allows control of general purpose I/O pins e. Timer Service – controls general purpose, core and watchdog timers f. Port Control – controls pin muxing for peripheral and flag pins (ADSP-BF534, ADSP-

BF536 and ADSP-BF537 only)

The device driver portfolio has also been expanded. Device drivers are now provided for the

following on-chip peripherals:

g. PPI (ITU-656 and general purpose mode) h. SPI (interrupt driven and DMA driven versions) i. UART (with autobaud detection) j. SPORT (including multichannel) k. TWI (master and slave, ADSP-BF534, ADSP-BF536 and ADSP-BF537 only)

And these off-chip peripherals:

l. AD1871 – Stereo audio, 24 bit, 96 KHz Multi-bit Sigma Delta ADC m. AD7266 – Differential Input, Dual 2 MSPS, 12 bit 3 Channel SAR ADC n. AD7476A – 12 bit, 1 MSPS low-power ADC o. AD7674 – 18 bit, 800 kSPS PulSAR® ADC p. AD1854 – Stereo, 96 KHz Multibit Sigma-Delta DAC q. AD1836 – Multichannel 96 KHz Codec r. AD1938 – 4 ADC, 8 DAC 192 KHz, 24 bit CODEC

An addendum to the Device Drivers and System Services Manual for Blackfin Processors has

been created. This document provides detailed descriptions, including the APIs, of the new

services, a comprehensive list of all changes from the previous release, improvements, bug fixes,

dual-core considerations etc. It is highly recommended to download and review the addendum.

The addendum can be found at:

ftp://ftp.analog.com/pub/tools/patches/Blackfin/VDSP++4.0/DeviceDriversAndSystemSe

rvicesAddendum_Sep2005.pdf

4. The USB device driver has been ported to the ADSP-BF561. Loop-back examples for the ADSP-BF533, ADSP-BF537, and ADSP-BF561 are available at …\Blackfin\EZ-KITs\USB-LAN

EZ-EXTENDER\usb\examples\loopback.

5. When connected to an EZ-KIT Lite via the debug agent USB connection, a new menu item, “Settings”->”Bootload” is now available to issue a hard reset to the board without the need

to exit VisualDSP++.

6. The VisualDSP++ license manager has been improved to address a performance bottleneck. Users with multiple Flex-licensed products on their system may notice a performance increase

when launching VisualDSP++ and building projects.

7. The Blackfin run-time libraries now support the C99 functions snprintf and vsnprintf. Their prototypes are:

#include

int snprintf (char *str, size_t n, const char *format, . . .);

int vsnprintf (char *str, size_t n, const char *format, va_list args);

8. The Blackfin compiler now includes a workaround for ADSP-BF561 hardware anomaly 05-00-0248 "TestSet operation causes stall of the other core". The avoidance is performed by the

compiler automatically issuing a write to an L2 defined variable immediately following a

testset instruction. This is done as part of the code generated for a

__builtin_testset() call. The compiler will automatically enable the workaround for the

appropriate silicon revisions, or you can enable the workaround manually by specifying the

compiler flag -workaround l2-testset-stall.

The macro __WORKAROUND_L1_TESTSET_STALL will be defined at compile, assemble and


9. The default LDFs (non-VDK and VDK) include a workaround for hardware anomaly 05-00-0189 "Speculative (and fetches made at the boundary of reserved memory space) for Instruction or Data

Fetches may cause false Protection Exceptions". The workaround will be automatically enabled

for the appropriate silicon revisions, or the workaround can be enabled manually by defining

macro __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES when linking.

10. The instrumented profiling enabled using the -p[1|2] compiler switch has been overhauled for this Update to resolve a number of problems. Part of the changes to make the support more

flexible is the internal use of dynamically instead of statically allocated buffers. This might

require LDFs to be reconfigured for a larger heap in some cases. The cycle output from

instrumented profiles is now a 64-bit integer.

11. The C/C++ compilers have been modified to report an error for the case where an inline asm statement attempts to use the same register for an input and output. For example:

int f(int a, int b) {

asm("%0 += %1\n" : "+d" (a) : "0" (b) : );

return a;

}

The error issued is:

cc1669: Fatal error: input operand matched to input-output

operand in gnu asm

12. The C/C++ compilers have been modified to detect cases of unreasonable register uses in asm statements. An example would be an attempt to allocate more inputs or outputs to a particular

register class than there are registers of that class. The error issued when this is detected is:

cc1668: fatal error: gnu asm requires too many Dreg regs

13. Certain anomalies on the ADSP-2136x processors are now avoided by the compiler and within the run-time libraries. Their titles are (the specific errata number varies from processor to

processor):

a. Some Core Stalls not executed properly b. Memory write operations can fail under certain conditions while DMA to internal

memory is in progress

The assembler will detect instances of these anomalies, including partial sequences that depend on

code the assembler cannot see; instances of such partial sequences include:

• The first instruction in a possible sequence is in the second DB slot of a branch instruction.

• The last or last two instructions in a possible sequence follow either a CALL or a label.

These anomalies are described in detail on the Analog Devices web site:

www.analog.com/processors/technicalSupport/hardwareAnomalies.html

14. In the TigerSHARC compiler, a new switch, -no-fp-minmax, has been added to disable a specific optimization in the compiler. Discussion: When optimizations are enabled, one of the

optimizations that the compiler may choose is to replace a float compare followed by an

assignment with the float MAX instruction. This can result in incorrect behavior if one of the input

operands is a NaN as it sets the output to be 0xffffffff.

In the following example, there is a test for a float having a greater value than another float:

if ( f1 > f2)

{

f2 = f1;

}

When optimizations are enabled the compiler replaces the float compare and assignment with use

of the float MAX instruction. This will work when both inputs are valid numbers, but if a NaN is

used as input to the MAX instruction it will return a floating-point all ones result (0xffffffff) which

in turn gets assigned to f2, where with a float compare we do not get this behavior.

The new compiler switch will prevent this optimization from taking place.






In this release:

1. The ICE configuration can now be used to configure all EZ-KIT Lite products. Notably, this allows one to connect more than one of the same EZ-KIT Lite board into the same PC by

assigning a unique “DeviceID” to each instantiated board.

This requires a small change in the process for creating debug sessions for some EZ-KIT Lite

products. When creating new sessions for the ADSP-BF533 and ADSP-BF535 EZ-KIT Lites,

choose a debug target of “Blackfin Emulators/EZ-KIT Lite”. When creating new

sessions for SHARC USB EZ-KIT Lites, choose a debug target of “SHARC Emulators/EZ-

KIT Lites”.

2. Within the System Services Library (SSL), a change to the Power Management API and Interrupt Manager API will need to be accommodated by applications. The Power Management service

unit of frequency is now Hz, rather than MHz. Unless overridden with a new command, all values

passed into the service and returned from the service are now in Hz. A bug fix to the Interrupt

Manager required adding an additional parameter to the adi_int_CECUnhook() function.

These changes are described in detail in the addendum described above.

3. In the SHARC compiler with optimizations enabled, the compiler will now convert an arithmetic lshift-by-1 expression into an add instruction. For example, the following code sequence will

generate an add instruction in the assembly file when optimization is enabled:

x[i] = x[i]


problems that have been fixed in the default. Custom LDFs should be audited for correctness.

Relevant TAR numbers are 23698, 23699, 24206, and 23885.

Problems Addressed





Processor

Family

Problem

Number

Tool Description

All 16549 Compiler Generate Preprocessed file produces confusing warning

All 20407 Compiler Compiler should report error for asm input matched to in-out All 22017 Assembler Trailing / on final include path with .IMPORT fails

compilation

All 23850 Compiler NO_INIT sections not properly supported with -ipa All 23985 Compiler Compiler fails to support anonymous structs correctly All 23988 Compiler __attribute__ should support always_inline/never_inline All 24003 Run Time

Libraries

Printing a particular long double causes libio to loop


The strftime function may format integer values incorrectly

All 24103 Compiler Compiler allocates asm output to clobbered reg All 24577 Run Time

Libraries

Printing %f with a precision may not generate all the digits

Blackfin 11099 Simulator Viewing Trace unit's TBUF register drains TBUF

Blackfin 17045 Run Time Libraries

Profiling libraries don't fit into default BSZ sections

Blackfin 20931 IDDE Problematic handling of string defines Blackfin 21723 Simulator BF535: missing stall with video op Blackfin 22230 Run Time

Libraries

BF535 Run-Time Library does not avoid shift anomaly

Blackfin 23403 VDK BF535 VDK libraries have been built without workarounds Blackfin 23535 Run Time

Libraries

Problems with C++ sub-projects in BF561 5-proj setup


LDF files need to workaround anomaly 05-00-0189

Blackfin 23699 VDK LDF files need to workaround anomaly 05-00-0189 Blackfin 23742 Assembler Dwarf info corrupted during PLIT generation Blackfin 23913 Emulator JTAG frequency increase display not persistent Blackfin 23945 Simulator Compiled sim invoked from the command line doesnt print

output

Blackfin 23979 Compiler Compiler driver doesn't pass -sp_fix or -sp_warn to assembler Blackfin 24034 Document-

Help

Incorrect tooltips

Blackfin 24060 Simulator BF561: Memory streams 0xffd00000:ffd0000f don't work Blackfin 24126 Compiler -workaround all causes asm SSYNC/CSYNC warning in

compiled .s

Blackfin 24206 LDF 4k of L1 memory not mapped in default LDF Blackfin 24228 Run Time

Libraries

Multicore applications using I/O can hang on exit

Blackfin 24254 Compiler compiler assertion (brilput.c:3792) with pragma pack/unsigned Blackfin 24284 Compiler ea5003 from compiled code using -O Blackfin 24292 VDK VDK_ISR_CLEAR_EVENTBIT_ does not use call.x Blackfin 24333 Emulator USB-ICE performance severly decreases when using hw

breakpoints

Blackfin 24370 Compiler -decls-weak results in incorrect declarations in assembly Blackfin 24371 Compiler Large values in switch statement cases can cause link errors Blackfin 24372 Emulator EZ-KIT connection fails after built-in 90-day Test Drive

expires

Blackfin 24382 Compiler Compiler makes stack pointer misaligned (breaks interrupts) Blackfin 24431 Compiler Structure parameters handled incorrectly in leaf functions Blackfin 24471 Compiler compiler assertion in eval.c:1257 with -O and long long Blackfin 24500 Run Time

Libraries

Instrumented-code profiler ignores regs_clobbered


int to 64-bit float conversion wrong for minimum integer value

Blackfin 24589 CRTGen cplbHandler fragment not emitted when using_vdk property is true

Blackfin 24926 Compiler errata 05-00-0198 not avoided after UNLINK instruction SHARC 23786 Emulator large memory dump fetches wrong data

SHARC 23915 Assembler 64-bit hex values with an odd number of hex digits are

truncated

SHARC 24268 Compiler no add, just a lshift

SHARC 24587 Debug Agent BTC block writes fail through automation

TigerSHARC 20723 Compiler __builtin_sysreg_read does not work-around erratum 03-00-

0216

TigerSHARC 21937 Disassembler broadcast reg move disassembled incorrectly TigerSHARC 22195 Compiler Optimiser replacing FCOMP with FMAX may cause problems TigerSHARC 23792 IDDE TS201 -fopen to a null file causes VDSP++4.0 to crash TigerSHARC 23885 Run Time

Libraries

Default ADSP-TS201 LDFs do not use all available code

memory

TigerSHARC 23907 Compiler Bad optimization on local pointer results in bad code

TigerSHARC 24048 Run Time Libraries

Invalid floating point operation exceptions in math.h

TigerSHARC 24303 VDK VDK TS201 Interrupt masking is not sufficiently robust TigerSHARC 24576 Run Time

Libraries

The powf() library routine can incorrectly raise FP exceptions

VisualDSP++ 4.0 (Updated June 2005) Release Note

The following release note concerns the June 2005 Update to the VisualDSP++ 4.0 release. This release is












In this release:

1. A new VDK API has been introduced, GetBlockSize(), which has the following details:

C Prototype

unsigned int VDK_GetBlockSize(VDK_PoolID inPoolID)

C++ Prototype

unsigned int VDK::GetBlockSize(VDK::PoolID inPoolID)

Description

Returns the configured block size for the specified memory pool.

2. Performance of the LwIP TCP/IP stack has been increased with some internal changes. The main change is that the stacks’ receive functionality is interrupt driven rather than relying on polling.

The poll period passed to the stack is therefore now ignored.

Furthermore, the performance of the LAN91C111 DMA driver has been improved and the support

for cached buffers by the ADSP-BF537 driver has been improved.

3. The Blackfin compiler now includes a workaround for the hardware anomaly 05-00-0245: “CPLB miss Memory Bandwidth/Performance/Power drain/spurious error:. The compiler will

automatically enable the workaround for the appropriate silicon revisions, or you can enable the

workaround manually by specifying the compiler flag -workaround speculative-loads.

With the workaround enabled the compiler will insert one, two, or three nop instructions after a

conditional jump instruction to avoid a speculative load of memory that may be invalid or reserved

within three instructions of the jump.

The macro __WORKAROUND_SPECULATIVE_LOADS will be defined at compile, assemble and


4. The Blackfin compiler now includes a workaround for the hardware anomaly 05-00-0244: "CSYNC and SSYNC failure after conditional branch". The compiler will automatically enable

the workaround for the appropriate silicon revisions, or you can enable the workaround manually

by specifying the compiler flag -workaround speculative-syncs.

With the workaround enabled the compiler will insert one, two or three nop instructions after a

conditional jump instruction to avoid a CSYNC or SSYNC instruction within three instructions of

the jump.

The macro __WORKAROUND_SPECULATIVE_SYNCS will be defined at compile, assemble


The Blackfin assembler will warn users who write assembly code that can potentially trigger the

anomaly. Warning ea5507 will be issued by the assembler when a CSYNC or SSYNC could

possibly be affected by the hardware anomaly.

5. The Blackfin, SHARC and TigerSHARC compilers have a new feature of the -section switch that allows C++ static constructor functions to be placed into an identified section rather than the

default compiler code section. The new id for -section is sti and an example use for Blackfin is

given below:

ccblkfn -section sti=sdram0 -c++ code.cpp

As with other uses of -section it is the users responsibility to ensure that the identified section to

be used by the compiler is mapped in the LDF.

6. The compilers have a new switch, -enum-is-int, which when used ensures that the type of C/C++ enumerations are integer. Without this switch the compiler will automatically use a long

long enumeration implementation when enumeration field values larger than the maximum

signed integer are used. A new diagnostic (a remark for Blackfin and warning for SHARC and

TigerSHARC), cc1661, will be issued when this happens.

7. A new compiler switch, -implicit-pointers, has been added to make the default error for incompatible pointers a warning.

8. A new #pragma regs_clobbered_call has been added to compilers.

This pragma may be applied to a statement to indicate that the call within the statement uses a

modified volatile register set. The pragma is closely related to #pragma regs_clobbered,

but avoids some of the restrictions that relate to that pragma.






In this release:



Relevant TAR numbers are 23532 and 23533.

2. As a consequence of addressing TAR 23770, some applications that call he fread and fwrite functions may experience slower performance. To address this slow-down, applications should

use the setvbuf function to specify an appropriate buffer size. An appropriate buffer size would

be the size (in memory units) of consecutive scalars and/or small arrays that are read or written

using fread and fwrite, or zero if the application only reads or writes 'large' arrays.

Note that this issue does not affect Blackfin applications that have been built with the switch

-full-io, TigerSHARC applications that have been built with the switch -char-size-8, or

SHARC and TigerSHARC applications that use fread and fwrite on text streams.

Problems Addressed





Processor

Family

Problem

Number

Tool Description

All 17622 Compiler No warning generated for uninitialised variable use within loop

All 22593 Compiler Pragma pure and pragma const don't work

All 22968 Compiler Enum size can change without warning

All 23234 Compiler -unsigned-bitfield does not work always

All 23254 Run Time

Libraries

#pragma system header needs to activate no implicit inclusion

All 23725 Compiler undefined reference using section keyword/pragmas and C++

EH

All 23756 Run Time

Libraries

Concurrent calls to I/O in VDK threads may cause kernel panic

All 23770 Run Time

Libraries

Using fread or fwrite to read or write scalars can be slow

All 23826 Compiler Compiler crash generating debug for C++ function with long

name

All 23940 VDK Multiple pends on a periodic semaphore can cause infinite loop

Blackfin 22463 Simulator BF535: LB0/LB1 don't get bit 0 set in supervisor mode


Libraries

_l1_memcpy and _memcpy_l1 off by one

Blackfin 22754 IDDE 1.0 and 1 evaluate differnetly for float type

Blackfin 22942 Simulator ASTAT bits AC copy and V copy can be wrong

Blackfin 23130 Simulator BF535: incorrect P-reg value after PushPopMultiple instruction


Libraries

Least Significant bit error in 32-bit unsigned division

Blackfin 23224 Simulator BF535: WatchDog Timer not simulated properly

Blackfin 23376 License

Install

VDSP++ 3.5 Emulator Tools won't work w/ pure ++4.0

Package Defs


Libraries

cannot overload malloc/free/realloc/calloc in libc

Blackfin 23436 Assembler .INC/BINARY and -g corrupts DWARF output

Blackfin 23518 Compiler Using long longs in ISR can cause compiler internal error


Libraries

LDF L1_data_a vs. l1_data_a incompatibility

Blackfin 23533 VDK LDF L1_data_a vs. l1_data_a incompatibility

Blackfin 23537 IDDE Problems with debug line info when filename case doesn't

match

Blackfin 23544 Compiler short loaded from packed struct not sign extended on copy to int

Blackfin 23551 Compiler Simple reverse loop failing to compile

Blackfin 23553 Document-

Help

'Upgrading VisualDSP" needs to be modified with vdu

instructions

Blackfin 23567 CRTGen Generated AD6532 CRT compiles with warnings

Blackfin 23671 IDDE Expressions window evaluates expression incorrectly


Libraries

Undefined library symbol when using -multicore on BF561

Blackfin 23802 Emulator Jtag frequency selection fails for any frequency

Blackfin 23811 Simulator BF535: CYCLES and CYCLES2 increment not properly

simulated

Blackfin 23865 Simulator scanf fails for compiled sim

SHARC 22076 IDDE 21161 loader property page doesn't set -id1exe

SHARC 22217 Run Time

Libraries

C++ exceptions code compiled with -Og may not work properly

SHARC 23519 Flash

Programmer

21161N EZ-Kit Flash programmer driver incorrect unlock

sequence

SHARC 23566 Emulator reserved bits incorrect in LIRPTL register

SHARC 23589 VDK Use of Push/PopCriticalRegion in device driver activate

SHARC 23766 VDK SWFA libraries don't link

SHARC 23849 Examples 21364 EZ-KIT Example PLL init code mod

TigerSHARC 21599 Assembler assembler accepts invalid multiplier instruction

TigerSHARC 23435 Compiler Internal compiler error when compiling attached code

TigerSHARC 23462 Assembler cjmp should always be (abs) on TS201

TigerSHARC 23470 Compiler Compiler fails optimised with 64-bit dual add/subtract

TigerSHARC 23490 Compiler A single bit set in a long long bitfield unoptimised can fail

TigerSHARC 23686 Assembler more anomalies fixed in rev 1.2

TigerSHARC 23776 VDK TS202 LDF does not link

TigerSHARC 23844 Document-

Tools

Topics from older Rev of the book are visible in Help via

Search

TigerSHARC 24007 VDK VDK does not install the hardware error interrupt

VisualDSP++ 4.0 (Updated March 2005) Release Note

The following release note concerns the March 2005 Update to the VisualDSP++ 4.0 release. This is the

first in what is anticipated to be a series of Updates. The contents of future product Updates will be

inclusive of all previous Updates. At that time, the release notes for past Updates will be appended to the

end of the current release note.





















In this release:

1. New examples have been added to support the new A/V Extender card and USB/LAN extender cards. Refer to the following new directories:

Blackfin/EZ-KITs/USB-LAN EZ-EXTENDER/usb/examples/talkthrough

Blackfin/EZ-KITs/A-V EZ-EXTENDER/LCD

Blackfin/EZ-KITs/A-V EZ-EXTENDER/ezVideoSensor_EZ_A-V_Extender

2. Support for ADSP-BF533/2/1 revision 0.4 silicon has been added.

3. The Blackfin compiler now includes a workaround for the hardware anomaly 05-00-227: Scratchpad memory bank reads may return incorrect data. The compiler will automatically enable

the workaround for the appropriate silicon revisions, or you can enable the workaround manually

by specifying the compiler flag -workaround scratchpad-read'

With the workaround enabled, when a sequence of three load instructions occurs (or occur as parts

of a multi-issue instruction), where at least one of (2) and (3) is a byte load, a nop will be inserted

between (1) and (2) or (2) and (3):

A load instruction (1);



The macro __WORKAROUND_SCRATCHPAD_READ will be defined at compile, assemble and

link stages when the workaround is enabled.

4. To address ADSP-BF561 hardware anomaly 05-00-120, a modified definition of the testset_t type definition in the ccblkfn.h include file. The change is to define it as a 32-bit int type

rather than a 16-bit type. The change will automatically be enabled for builds targeting appropriate

silicon revisions, or you can enable the workaround manually by specifying the compiler flag

-workaround testset-align.

5. The run-time libraries now include a workaround for anomaly 05-00-0158, and is included for BF531/532/533 libraries which support silicon revisions affected by this anomaly. The

workaround involves setting an additional bit in the DCPLB_DATA registers which specify cache

is enabled. No changes to custom CPLB tables are required.

6. The compiler now offers improved support for inlining, with new pragmas and command-line switches.

#pragma always_inline

This pragma may be applied to a function definition to indicate to the compiler that the function

should always be inlined, and never called “out of line”. The pragma may only be applied to

function definitions with the inline qualifier, and may not be used on functions with variable-

length argument lists. It is invalid for function definitions that have interrupt-related pragmas

associated with them.

If the function in question has its address taken, the compiler cannot guarantee that all calls are

inlined, so a warning is issued.

Examples:

int func1(int a) { // only inlined if -Oa switch on

return a+1;

}

inline int func2(int b) { // probably inlined, if optimizing

return b+2;

}


inline int func3(int c) { // always inlined, even if not

return c+3; // optimizing

}


int func4(int d) { // error: not an inline func.

return d+4;

}

#pragma never_inline

This pragma may be applied to a function definition to indicate to the compiler and that function

should always be called “out of line”, and that the function's body should never be inlined.

This pragma may not be used on function definitions that have the inline qualifier.

Examples:

int func1(int a) { // only inlined if -Oa switch on

return a+1;

}


int func2(int b) { // never inlined, even if -Oa switch on

return b+2;

}


inline int func3(int c) { // error: inline function

return c+3;

}

New compiler switches to control inlining

-always-inline

The -always-inline switch instructs the compiler to always attempt to inline any

call to a function that is defined with the inline qualifier. It is equivalent to applying

#pragma always_inline to all functions in the module that have the inline

qualifier.

-never-inline

The -never-inline switch instructs the compiler to ignore the inline qualifier on

function definitions, so that no calls to such functions will be inlined.






In this release no changes have been identified.

7. Several of the problems addressed involve changes to the default LDFs. If your project has a custom LDF that is heavily based on one of the defaults, your LDF may continue suffer from


Relevant TAR numbers are 22223, 22829, 23046, 23067, 23166, and 23167.

Problems Addressed


can be found on the Tools Anomaly web page. The URL is:


Processor

Family

Problem

Number

Tool Description

All 22359 Compiler compiler does not quote dependency targets

All 22470 Run Time

Libraries

Function add_devtab_entry() fails to link in C++ mode

All 22660 Compiler remarks (cc1124) caused by use of cdef*.h defined macros

All 22707 Compiler Bad debug info for funcs with linkage_name

All 22708 IDDE Trigger in VDK history does not recognise interrupt level

All 22717 Compiler compiler assertion (driver.c:1057) with bad ctor array assign

All 22752 VDK Routing thread thread structure always allocated in def heap

All 22941 Run Time

Libraries

setvbuf fails to make stderr line buffered

All 23058 VDK minimum application size increased

All 23109 Installation Some version of Internet Explorer 5.01 not recognized by install

All 23179 IDDE License Server Installation doesn't append 4.0 package defs

All 23235 Compiler -Wsuppress option does not work with -Wremarks

Blackfin 17204 Utilities meminit does not issue an error message with an illegal switch


Help

Pipeline viewer documentation not correct

Blackfin 20144 Loader elfloader doesn't inform that ADSP-2153x is no longer supported


Libraries

default LDF allows user to place data in mem used by ROM

Bootkrn


Libraries

The time function ignores its argument


Libraries

Some functions should be declared 'static inline'


Libraries

some functions are defined twice

Blackfin 22263 Linker MAP() LDF command is ignored

Blackfin 22374 Compiler Compiler doesn't optimise loop to one cycle any more

Blackfin 22463 Simulator BF535: LB0/LB1 don't get bit 0 set in supervisor mode


Libraries

64-bit Math functions loose precision

Blackfin 22639 Compiler _l1_memcpy and _memcpy_l1 off by one

Blackfin 22696 IDDE Cannot delete workspaces

Blackfin 22754 IDDE 1.0 and 1 evaluate differnetly for float type


Libraries

Missing parens in def_LPBlackfin.h (SEQSTAT_*CAUSE)


Libraries

Executing PGO datasets with command line arguments broken


Libraries

profiling libraries not compiled with -double-size-any

Blackfin 22901 IDDE 16-bit RGB bytes are swapped

Blackfin 23046 VDK LDF allows placement of data in memory used by ROM

Bootkernel

Blackfin 23067 Run Time Default LDFs don't use libetsi*y.dlb

Libraries

Blackfin 23117 Assembler Blackfin Assembler issues incorrect relocation type

Blackfin 23130 Simulator BF535: incorrect P-reg value after PushPopMultiple instruction

Blackfin 23166 VDK BF532 LDF has mispelt section if cache or sdram enabled

Blackfin 23167 VDK AD6532 LDF has wrong start address


Libraries

BF532 LDF doesn’t map some sections to SDRAM with

USE_SDRAM mcro


Help

Blackfin ICE help ""Initializing Registers on reset” incorrect

Blackfin 23224 Simulator BF535: WatchDog Timer not simulated properly

Blackfin 23226 VDK Interrupts can be serviced during VDK startup causing problems


Libraries

___float32_to_unsigned_int32can give wrong results

Blackfin 23274 Compiler Compiler failure with circular buffer op in early exit loop


Libraries

The 64-bit C run-time sqrt function fails to link with -threads


Libraries

Binaries from VDSP3.5 (and earlier) may not link with VDSP4.0

SHARC 22796 IDDE If project built without EL open, changes do not show in EL

SHARC 22812 Debug

Agent

Modifying IOSTAT child registers causes communication time

out

SHARC 22956 Emulator Emulator causes unwanted change in SPIDMAC register

SHARC 23279 Compiler Compiler uses much more stack space when compiling for 2116x

TigerSHARC 22158 VDK VDK switching off of interrupts is not safe

TigerSHARC 22468 Run Time

Libraries

The compiler will fault putc with -char-size-8

TigerSHARC 22620 Emulator TS202 & TS203 have incorrect syscon reset values

TigerSHARC 22666 Compiler Wrong answers given for clip and abs builtin reference code

TigerSHARC 22781 Run Time

Libraries

SW exception handler corrupts IALU conds when invoking

monitor

TigerSHARC 23012 IDDE VDK 3.5 projects for TS fail to compile

TigerSHARC 23268 Assembler assembler accepts invalid instruction line

TigerSHARC 23304 Compiler Compiler fails bad align pragma value in byte-addressing mode

TigerSHARC 23321 Compiler Bad second arg for separate_mem_segments crashes compiler

Date post:	13-Feb-2021
Category:	Documents
Upload:	others
View:	3 times
Download:	0 times

VisualDSP++ 4.0 (Updated March 2007) Release Note...VisualDSP++ 4.0 (Updated June 2006) Release Note...

Documents