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Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder...

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Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun
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Page 1: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Viterbi Decoder: Presentation #5

M1

Overall Project Objective:

Design a high speed Viterbi Decoder

Stage 5: 18th Feb. 2004

Component layout

Design Manager: Yaping Zhan

Omar Ahmad

Prateek Goenka

Saim Qidwai

Lingyan Sun

Page 2: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Status

18-525, Integrated Circuits Design Project

Design Proposal (Done) Architecture Proposal (Done) Gate level Design(Done) Component Layout (DRC & LVS): (Done)

basic components: 100% functional blocks: 100%

To be done: Component Simulation: (10%) Chip Layout Spice Simulation of Entire Chip

Page 3: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Schematic: top level

18-525, Integrated Circuits Design Project

Viterbi Decoder

clk

rst

In_valid

In_data

Out_valid

Out_data

BCU ACS

Trace Back

ML Search

Page 4: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Floorplan

Goal: High speed

clkrst

clkrst

clkrst

clkrst

In_valid In_data

out_dataout_valid

334

624

Page 5: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Underneath

18-525, Integrated Circuits Design Project

Page 6: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Primitive Gates

INV XOR AND

18-525, Integrated Circuits Design Project

Page 7: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

1-Bit Register

18-525, Integrated Circuits Design Project

Page 8: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

1-Bit Full Adder

18-525, Integrated Circuits Design Project

Page 9: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

1-Bit Half Adder

18-525, Integrated Circuits Design Project

Page 10: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

8-Bit Register

18-525, Integrated Circuits Design Project

Page 11: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

8-Bit Adder

18-525, Integrated Circuits Design Project

Page 12: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

8 bit 2:1 Mux

18-525, Integrated Circuits Design Project

Page 13: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

8 bit Comparator

18-525, Integrated Circuits Design Project

Page 14: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Multiplier

18-525, Integrated Circuits Design Project

Page 15: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

BCU

18-525, Integrated Circuits Design Project

clk

rst

In_valid Data_in

out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15

Page 16: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

ACS

18-525, Integrated Circuits Design Project

clk

rst

In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15

out0 t0 out1 t1 out2 t2 out3 t3 out4 t4 out5 t5 out6 t6 out7 t7

Page 17: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

ML Search

18-525, Integrated Circuits Design Project

clk

rst

in0 in1 in2 in3 in4 in5 in6 in7

min

Page 18: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Trace Back

18-525, Integrated Circuits Design Project

clk rst

t0 t1 t2 t3 t4 t5 t6 t7

s0 s1 s2 s3 s4 s5 s6 s7

Page 19: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Top level

BCU

ACS

ML Search

Trace Back

18-525, Integrated Circuits Design Project

Page 20: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Major Component Measurements

Component Dimensions (LXW)(µm)

8 bit Adder 40 x 16

8 bit Register 36 x 9

Multiplier 14 x 25

8 bit Mux 37 x 8

8 bit Comparator 42 x 11

Total Transistor Count: 21,572

18-525, Integrated Circuits Design Project

Page 21: Viterbi Decoder: Presentation #5 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 5: 18 th Feb. 2004 Component layout Design Manager:

Questions?

18-525, Integrated Circuits Design Project


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