CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011 VLP0101-1 Low power On-Chip Amplifier for CCD Array Er. Rahul Malhotra*, Er. Amit Kumar** Bhai Maha Simgh College of Engineering, Sri Muktsar Sahib, India *[email protected], **[email protected]Abstract— The field of Analog VLSI design is an essential part of any electronics system because of our real world is analog, In this paper low power amplifier is presented for CCD array [1]. CCD are used to capture the images modern digital cameras and high resolution cameras consists of CCD array but all the performance of the CCD array is depends on the performance of On-Chip amplifier which is placed at the end of the array in this paper single and two stage amplifier are simulated and the result is presented for the power and bandwidth by varying the sizes of the different transistors all the results are verified by using the Tanner tool (version 7.1) [11]. There are number of analysis presented by the researchers in the literature to improve the power dissipation but most of the structure are compromise sometimes with the area or sometimes with the bandwidth here we have achieve the lesser power dissipation but with the handsome value of bandwidth is also maintained to support this claim the detailed results are presented in the result section. Keywords: Gain, power dissipation, bandwidth, capacitance INTRODUCTION Charge Coupled Devices (CCDs) were invented in the 1970s and originally found application as memory devices Charge Coupled Devices (CCD) have many applications, but the most important is in imaging [3]. The basic operation of the sensor is to convert light into electrons. When light is Incident on the active area of the image sensor it interacts with the atoms that make up the silicon crystal. The energy transmitted by the light (photons) is used to enable an electron to escape from the tight control of one atom to roam more freely about the device as a “conduction” electron, leaving behind an atom shy of one electron. Modern CCD has two types of architecture: 1. Full-Frame (FF) 2. Frame-Transfer (FT) FF CCDs have the simplest architecture and are the easiest to fabricate and operate. They consist of a parallel CCD shift register, a serial CCD shift register and a signal sensing output amplifier. Images are optically projected onto the parallel array which acts as the image plane the architecture is shown in the fig. 1 FT CCDs are very much like FF architectures. The difference is that a separate and identical parallel register, called a storage array, is added which is not light sensitive. The idea is to shift a captured scene from the photosensitive, or image array, very quickly to the storage array [5]. Readout off chip from the storage register is then performed as described in the FF device previously while the storage array is integrating the next frame. The architecture is shown in the fig. 2 Fig. 1 Full Frame architecture Fig. 2 Frame transfer architecture
Transcript
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
VLP0101-1
Low power On-Chip Amplifier for CCD Array
Er. Rahul Malhotra*, Er. Amit Kumar** Bhai Maha Simgh College of Engineering, Sri Muktsar Sahib, India
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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Both of the above architecture are widely used but the
performance of both the architecture are depends on the type
and the quality of the On-chip (output) amplifier which is
fabricated at the last stage of the structure as shown in the fig
above.
ARCHITECTURE OF ON-CHIP AMPLIFIER
Output amplifier has also two type of the architecture
1. Single stage amplifier
2. Two stage amplifier
out
M1
Mc
VRG
VRD
VDD
FD
Detection Node
L=2u
W=22u
L=2u
W=22u
L=2u
W=22u
Fig. 3 Single Stage CCD On-Chip amplifier
The single stage amplifier consists of source follower M1 and load transistor Mc for biasing. The reset FET is connected to the detection node and consists of floating diffusion [6, 7] and the gate of M1. In the ON state it resets the detection node to a reference voltage (VRD) and in the OFF state the floating can receives the next charge packet. The voltage source between the gate and source of the current sink Transistor Mc determines the bias current of the first stage and can be used as a signal injection point to measure the ratio between total capacitance and the effective sense capacitance and the bandwidth in the off state.
The Two stage amplifier further improves the character tics of the amplifier and gives the better result which is shown in the result section of the paper and the architecture of two stages is shown two stage amplifier also improves the sensitivity of the amplifier and this also reduces the noise level of the overall CCD.
Mr
M1
Mc
M2
M3
Vdd
VCS
VRD
FD
Detection node
Reset gate pulse
output
L=2u
W=22u
L=2u
W=22u
L=2u
W=22u
L=2u
W=22u
L=2u
W=22u
Fig. 4 Two Stage CCD On-Chip amplifier
OPTIMIZATION
For optimization of the on-chip amplifier Length and Width
of the individual transistor are varied and the various
optimization results are obtained. The effect of increase and
decrease of Length and Width of the transistor is given as
To achieve maximum gain:
Transistor „M1‟: -The gain can be maximized by increasing
the width of this transistor as this increases the difference in
the output voltage amplitude.
Transistor „MC‟: -The gain can be maximized by decreasing
the width of this transistor as this increases the difference in
the output voltage amplitude.
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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Transistor „M2‟: -The gain can be maximized by increasing
the width of this transistor as this increases the difference in
the output voltage amplitude.
Transistor „M3‟: -The gain can be maximized by decreasing
the width of this transistor as this increases the difference in
the output voltage amplitude.
To achieve maximum bandwidth:
Transistor „M1‟: - The bandwidth of the circuit can be
increased by increasing the width of this transistor as the
increase in width increases the transconductance which helps
in increasing the bandwidth as the impedance decreases.
Transistor „MC‟: - The bandwidth of the circuit can be
increased by increasing the width of this transistor as the
increase in width increases the transconductance which helps
in increasing the bandwidth as the impedance decreases.
Transistor „M2‟: - The bandwidth of the circuit can be
increased by increasing the width parameter of this transistor.
So bandwidth can be increased by changing this parameter.
Transistor „M3‟: - The bandwidth of the circuit can be
increased by increasing the width of this transistor as the
increase in width increases the Tran conductance which helps
in increasing the bandwidth as the impedance decreases,
although the change desired is not that large.
To achieve minimum power dissipation:
Transistor „M1‟: - The power dissipation of the circuit can be
reduced by reducing the width of this transistor as the current
flowing into this transistor reduces with the reduction in the
width while power dissipation can be reduced by increasing
the length because increase in length reduces
transconductance which in turn reduces the amount of current
flowing into the transistor.
Transistor „MC‟: - The power dissipation of the circuit can be
reduced by reducing the width of this transistor as the current
flowing into this transistor reduces with the reduction in the
width while power dissipation can be reduced by increasing
the length because increase in length reduces
transconductance which in turn reduces the amount of current
flowing into the transistor.
Transistor „M2‟: - The power dissipation of the circuit can be
reduced by reducing the width of this transistor as the current
flowing into this transistor reduces with the reduction in the
width.
Transistor „M3‟: - The power dissipation of the circuit can be
reduced by reducing the width of this transistor as the current
flowing into this transistor reduces with the reduction in the
width.
RESULTS
Table 1: When the width of the transistor M3 varied
Transistor
Dimensions
(W× L) μm
M1 Mc
M2
(W×
L) μm
M3
(W× L)
μm
Power
Dissipation
(mW)
Bandwidth
BM
(MHz)
15×25
12×10
20x10
10x25
5.9
302
15×25
12×10
20x10
12x25
5.95
320
15×25
12×10
20x10
15x25
6.0
242
15×25
12×10
20x10
18x25
6.1
207
Table 2: When the width of the transistor M2 varied
Table 3: When the Length of the transistor M3 varied
Transistor
Dimensions
(W× L) μm
M1 Mc
M2
(W×
L) μm
M3
(W× L)
μm
Power
Dissipation
(mW)
Bandwidth
in
(MHz)
15×25
12×10
20x10
10x5
7.0
580
15×25
12×10
20x10
10x10
6.4
594
Transistor
Dimensions
(W× L) μm
M1 Mc
M2
(W× L)
μm
M3
(W× L)
μm
Power
Dissipation
(mW)
Bandwidth
BM
(MHz)
15×25
12×10
20x10
10x25
5.15
69
15×25
12×10
18x10
10x25
5.25
62
15×25
12×10
16x10
10x25
5.2
78
15×25
12×10
14x10
10x25
5.3
70
15×25
12×10
12x10
10x25
5.4
87
15×25
12×10
10x10
10x25
5.7
122
15×25
12×10
8x10
10x25
5.8
148
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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15×25
12×10
20x10
10x15
6.1
596
15×25
12×10
20x10
10x18
6.0
365
15×25
12×10
20x10
10x20
5.9
270
15×25
12×10
20x10
10x25
5.7
122
15×25
12×10
20x10
10x30
5.8
109
Table 4: When the Length of the transistor M2 varied
Transistor
Dimensions
(W× L) μm
M1 Mc
M2
(W×
L) μm
M3
(W×
L) μm
Power
Dissipa
tion
(mW)
Bandwidth
in
(MHz)
15×25
12×10
20x5
10x15
6.4
150
15×25
12×10
20x10
10x15
6.1
490
15×25
12×10
20x15
10x15
5.9
550
15×25
12×10
20x18
10x15
5.8
570
15×25
12×10
20x20
10x15
5.8
326
15×25
12×10
20x25
10x15
5.75
380
The results of the above table are taken from the Tanner T-spice tool by using the 2.0 Mosis model file for the enhancement MOSFET transistor. The power dissipation and the bandwidth are directly, measures from the waveform editor in the Tanner EDA tool.
CONCLUSION AND FUTURE SCOPE
It is observed from the result that in case of single stage On-
Chip amplifier minimum power dissipation and maximum
bandwidth is achieved when the Width of the M1 transistor is
18μm and the Length of the M1 transistor is 25μm meter and
the Width of the Mc transistor is 10μmr and the Length of the
Mc transistor is 16μm. In this case power dissipation is 4.3
milli-watts and the gain of the amplifier is 0.82 and
bandwidth is 617MHz. In case of two stage amplifier
maximum bandwidth is achieved when dimension of
transistor is as M1(15μmx25μm), M2(20μmx10μm),
M3(10μmx15μm) & Mc(12μmx10μm) and for minimum
power dissipation the dimension of all the transistor should be
M1(15μmx25μm), M2(20μmx10μm), M3(10μmx25μm) &
Mc(12μmx10μm). The whole design simulated using
MOSIS/Orbit 2.0μm process by using Tanner tool.
In this thesis Analog simulation is done by using the Tanner
tool and using the enhancement type MOSFET transistor is
used, this thesis can be further extended for the depletion type
MOSFET because in depletion type MOSFET noise level
will get further reduce and the other thing which can be
improved in future is, semiconductor and environmental
noise effect which is not consider in this current thesis.
REFERENCES
[1] Gruner, Sol M. Tate, Mark W. Eikenberry and Eric
interlayer for interconnect, plasma doping, flash and laser
annealing for source and drain doping, elevated source and
drain and three-dimensional MOSFETs for controlling short-
channel effects, would help to overcome the materials and
technological constraints and improve the device performance
in the ultra-small scale. The final remark is a non-technical
issue. We anticipate that this issue will be one of the most
important issues for nano-CMOS technology development in
the next 15 years. We are aware that most of the new mega-
fabs being planned or under construction are in the East and
Southeast Asia, and particularly the Mainland China. In 10 or
15-year’s time, the distribution of semiconductor
manufacturing sites in Asia (including Japan) will be quite
substantial. Currently, Korea and Taiwan are in the first place
for semiconductor memory manufacturing and semiconductor
foundry, respectively. They also lead the technology
development in Asia region. Mainland China seems to be
another super power for semiconductor manufacturing. The
share of China semiconductor manufacturing will keep fast
growing with the support of booming IC design houses,
constructing new fabs with remarkable increase in industrial
investment, and will be the most important huge and rapidly
expending market. As many other industries and other sectors
of electronic products, Mainland China will eventually
become ―the factory of the world‖ in semiconductor
manufacturing in 15 years or longer and will have great
impact on the future nano-CMOS technology.
REFERENCES
[1] G. E. Moore, ―Cramming more components onto integrated circuits‖, [Electronics, vol. 38, no. 8, 1965.
[2] International Technology Roadmap for Semiconductors, 2003 Edition, Semiconductor Industry Association (SIA), Austin, Texas: SEMATECH, USA.
[3] H. Iwai, Future semiconductor manufacturing-challenges and opportunities, IEDM Tech. Dig., 2004, pp. 1-16.
[4] H. Iwai, CMOS downsizing toward sub-100 nm, Solid–State Electron., vol. 48, 2003, pp. [497-503].
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[5] Zhao W, Cao Y. New generation of Predictive Technology Model for sub-45nmearly design exploration IEEE Trans. Electron Devices 2006; 11:2816-23.
[6] T. Morimoto, H. S. Momose, T. Iinuma, et al, A NiSi salicide technology for advanced logic devices, IEDM Tech. Dig., 1991,
653-656.
[7] T. Iizima, A. Nishiyama, Y. Ushiku, et al, A novel selective
Ni3Si contact plug technique for deep-submicron ULSIs, Symp. VLSI
Technology, 1992, pp.70-71. [8] R. Tsuchiya, M. Horiuchi, S. Kimura, et al, Silicon on thin BOX: A new
paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control, IEDM Tech. Dig., 2004, pp.631-634.
[9] T. Ghani, et al., "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," Symp. VLSl Technology, 2000, pp. 174-175.
[10] B. Yu, ―Scaling towards 35 nm gate length CMOS,‖ in Proc. VLSI Symp., Kyoto, AMD, June 12–14, 2001, pp. 9–10.
[11] D. Connelly, C. Faulkner, and D.E. Group, ―Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual gate CMOS,‖ IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1340–1345, May 2003.
[12] J. Knickerbocker et al., IEEE Custom Integrated Circuits Conference (CICC) p. 659 (2005).
[13] G. Anelli, Design and characterization of radiation tolerant integrated circuits in deep submicron CMOS technologies for the LHC experiments, Ph.D. Thesis, Institute National Poly-technique de Grenoble, France, December 2000, also available at http://www.cern.ch/ RD49.
[14] D. Frank et al., ―CMOS device and circuit limits,‖ Proc. IEEE, vol. 89, Mar. 2001.
[15] Davari, R. H. Dennard, and G. G. Shahidi, ―CMOS scaling, the next ten years,‖ Proc. IEEE, vol. 83, p. 595, 1995.
C. Mead, ―Scaling of MOS technology to submicrometer feature sizes,‖ J. VLSI Signal Processing, pp. 9–25, 1994.
[16] Y. Taur and E. Nowak, ―CMOS devices below 0.1 m: How high will performance go?‖ in Proc. Int. Electron Devices Meeting, 1997, p. 215.
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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Abstract—A very simple circuit of the MOSFET amplifier to
realize both very high positive as well as negative resistances at
its input and output terminals is presented. The mathematical
model is the representation of any device or system that
predicts response of the device or system under different types
of excitations. The floating admittance matrix (FAM) approach
is one of the neat methods of mathematical modeling of
electronic devices and its uses in circuits. The zero sum
property of the floating admittance matrix provides a check to
the worker to proceed further or reobserve the first equation
itself. All transfer functions are represented as cofactors of the
floating admittance matrix of the circuit.
Keywords: Amplifier, Common Source FET, Floating
Admittance Matrix, Zero Sum property, Cofactors, Plots
INTRODUCTION
The input resistance of a MOSFET is supposed to be very
high, yet a single-stage MOSFET amplifier is sometimes not
suitable for certain applications, especially, when high gain
along with change in the resistance levels from positive to
negative of very high to very low, is required. This type of
requirement is solved by either cascading or cascoding or
combination of the both in different sections of the amplifier
stages. Fig. 1 shows two stages of the MOSFET amplifier
with RF connected between output of the second stage to the
input of the first stage. It reveals that with proper adjustment
of the feedback resistance, RF, one may realize extremely
value of input and output resistance, both positive and
negative. The common source amplifier is the most versatile
MOSFETs amplifier configuration. The common-source
(CS) amplifier may be viewed as a transconductance
amplifier or as a voltage amplifier. As a transconductance
amplifier, the input voltage is seen to be modulating the
current going to the load. As a voltage amplifier, input
voltage modulates the amount of current flowing through the
MOSFET, changing the voltage across the output resistance
accordingly. The input resistance of a conventional emitter
follower, cathode follower or source follower is limited by
finite value of the passive emitter/carthode/source resistance
as well as the input bias resistance. In fact, the input bias
resistance shorts the input resistance of the amplifier and
hence the effective input resistance is limited to the
maximum value of the input bias resistance. A number of
papers are available in the literature which describes
separate circuits for realization of positive and negative
resistances. The simple single set-up here realizes both
positive and negative input and output resistance and saves
large number of active and passive components. The
importance of the negative resistance is very much felt in the
design of oscillators, multivibrators, filters, and synthesis of
driving-point functions. An attractive method for controlling
of the line loss in the telephone lines to any extend can be
achieved by introducing resistance; which covers very large
range of values, in the impedance boosting-network. The
realization of very high positive as well as negative
resistances of any amplifier is all the more important for
instrumentation.
This paper aims to develop the mathematical model of
common source amplifier in the form of floating admittance
matrix. The floating admittance matrix of the MOSFET is
taken to advantage for derivation of its voltage gain, input
resistance and output resistance in its common source
configuration.
MATHEMATICAL MODEL OF FET
The two stage common source MOSFET amplifier can be
represented as in Fig. 1 with a feedback through RF from
output of the second stage to the input of the first stage.
Fig.1 Two-stage Common Source Amplifier
The a.c. equivalent circuit of Fig.1 is shown in Fig. 2. The
matrix representation of MOSFET as two-port network (four
This graph shows the advantage of PFSCL gate vs MCML in terms of speed of operation.
This enables the extension of CML architecture into the GHz frequency range.
(For the values of Av=6,Vswing=0.4V and Cload=0.1pF)
Monte Carlo Simulations were also carried
out on PFSCL vs MCML gate to
determine the robustness of the logic style
to process variations(eg: tox ) and
variations in Vth(the threshold voltage of
the MOS).
From the simulation result it was found
that PFSCL was more robust and its
robustness increases as the bias current
increases.
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REFERENCES :
1) D. Allstot, S. Chee, S. Kiaei, and
M. Shristawa, “Folded source-
coupled Logic vs. CMOS static
logic for low-noise mixed-signal
ICs,”IEEE Trans. Circuits Syst. I,
vol. 40, pp. 553–563, Sept. 1993.
2) S. Kiaei, S. Chee, and D. Allstot,
“CMOS source-coupled logic for
mixed-mode VLSI,” in Proc. Int.
Symp. Circuits Systems, 1990,
pp.1608–1611.
3) J. Kundan and S. Hasan,
“Enhanced folded source-
coupled logic techniquefor low-
voltage mixed-signal integrated
circuits,” IEEE Trans.Circuits Syst.
II, vol. 47, pp. 810–817, Aug.
2000.
4) J.Kundan and S. Hasan, “Current
mode BiCMOS folded source-
coupled logic circuits,” in Proc.
ISCAS, June 1997, pp. 1880–
1883.
5) ] P. Gray, P. Hurst, S. Lewis, and
R. Meyer, Analysis and design of
analog integrated circuits, 4th
ed. New York: John Wiley &
Sons, 2000.
6) Design of nanometer MOS
Current Mode Logic (MCML):
basic concepts and
perspectives(lecture), Massimo
Alioto,2007
7) Modeling and Evaluation of
Positive-Feedback Source-
Coupled Logic, M. Alioto,
Member, IEEE, L. Pancioni, S.
Rocchi, Member, IEEE, and V.
Vignoli, Member, IEEE, IEEE
Tansactions on Circuits and
Systems—I: Regular Papers vol.
51, NO. 12, December 2004
8) A. Sedra and K. Smith,
Microelectronic Circuits,Oxfords
9) M. Alioto and G. Palumbo,
“Design strategies for source
coupled logic gates,” IEEE Trans.
Circuits Syst. I, vol. 50, pp. 640–
654, May 2003.
10) Modeling and Evaluation of
Positive-Feedback, Source-
Coupled Logic, M. Alioto,
Member, IEEE, L. Pancioni, S.
Rocchi, Member, IEEE, and
V. Vignoli, Member, IEEE, IEEE
Transactions on Circuits and
Systems—I: Vol. 51, No. 12, Dec
2004
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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Comparative Study of Fast Adders using VHDL and FPGA
Nishi Chandra Rajani Bisht
ET Deptt.,H.B.T.I.,Kanpur Associate Professor,ET Deptt.,H.B.T.I,Kanpur
Abstract: Adders are one of the most widely used components in integrated circuits and they are most commonly used in various electronic applications. The major challenge for VLSI designer is to reduce area of chip and the next phase is to increase the speed of operation to achieve fast operations.
Therefore, various adders such as the ripple adder, carry-look-ahead adder, carry select adder etc. are compared and VHDL is used in their comparison. Their comparative study included the use Xilinx 9.2i as the synthesis tool, Xilinx ISE Simulator as the simulation tool and FPGA Spartan-II kit for the implementation of these adders.In this comparison study, area and delay report is generated for these adders and the VHDL codes can be as well implemented on the FPGA Spartan-II kit.
Introduction
One of the most widely used components in integrated circuits are adders, so designing efficient adders has been the goal of research in VLSI design. Addition is a crucial arithmetic function for most digital systems. Various adder structures can be used to execute addition such as serial and parallel structures. They are used not only for addition, but also for other operations such as subtraction, multiplication, division, and address computation .Adders are one of the most widely used components in integrated circuits and they are most commonly used in various electronic applications e.g. Digital signal processing in which adders are used to perform various algorithms like FIR, IIR etc[1]. In past, the major challenge for VLSI designer is to reduce area of chip by using efficient optimization techniques. Apart from aiding a designer in selecting an adder with favorable characteristics, aim is providing insight into design tradeoffs that can save power and enhance performance. The adders studied include linear time ripple carry and manchester carry chain adders, carry skip and carry select adders, carry
lookahead adder and its variations, and carry-save adders. Several researchers had worked on the performance analysis of adders and other researchers on the performance analysis of multipliers. Therefore, lot of research is going on to reduce power consumption. Therefore, there are three performance parameters on which a VLSI designer has to optimize their design i.e. Area, Speed and Power[2]. It is very difficult to achieve all constraints for particular design, therefore depending on demand or application some compromise between constraints has to be made. Hence, the VHDL codes have been formulated for these fast adders and to get area and delay report, Xilinx 9.2i is used as the synthesis tool. In addition to this, Xilinx ISE Simulator is used for simulation and FPGA Spartan –II kit is used for implementation. Fast Parallel Adders Ripple Carry Adder (RCA) It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Ripple carry adder can be designed by cascading full adder in series i.e. carry from previous full adder is connected as input carry for the next stage. Full adder is a basic building block of Ripple carry adder. The major limitation of Ripple carry adder is that as the bit length goes on increasing, delay also increases. Therefore, Ripple carry adder is not suitable if large number bits are to be added. The two Boolean functions for the sum and carry are: SUM = Ai ⊕ Βi ⊕ Ci (i) Cout = Ci+1 = Ai · Bi + (Ai ⊕ Bi) · Ci (ii)
Fig 1. Ripple carry adder Condition Carry Adder (CCA) This adder computes sum and carry depending upon status of previous carry i.e. 1. If ci = 0 then Sout = ai xor bi & ci+1 = ai and bi (iii) 2. If ci = 1 then Sout = ai xnor bi & ci+1=ai or bi (iv) The adder does not consider the case of computing sum and carry directly by using full adder.
Fig 2. Condition carry adder Carry Lookahead Adder (CLA) In the lookahead carry algorithm ,carry for the next stages is calculated in advance based on input signals.As a result this algorithm speed up the operation to perform addition. If ‘‘X’’ and ‘‘Y’’ are two inputs, “ci” is initial carry, “sout” and “cout” are output sum and carry respectively, then Boolean expression for calculating next carry and addition is[3]: Pi = xi xor yi --- Carry Propagation (v) Gi = xi and yi --- Carry Generate (vi) Ci+1 = Gi or (Pi and Ci) --Next Carry (vii)
Fig 3. Carry lookahead adder Given the two Boolean functions for the sum and carry as follows[ref1]: SUM = Ai ⊕ Βi ⊕ Ci (viii) Cout = Ci+1 = Ai · Bi + (Ai ⊕ Bi) · Ci (ix) Manchester Carry Chain Adder Manchester adder is also a type of Carry look-ahead adder.In the case of manchester adder ,there is a slight modification in calculating next carry to be propagated i.e. instead of using Boolean expression Ci+1 = Gi + Ci.Pi to calculate next carry, Manchester carry adder uses expression: Ci+1=Gi+Ci.ti (x) ti = Xi + Yi (xi) Thus, we can say that carry recurrence can be written in terms of ti instead of Pi, which leads to slightly faster adder because in binary addition, ti is easier to produce than Pi (OR instead of XOR). Conventional Carry Skip Adder (CSKA) Carry has to propagate through all N stages in case of N-bit Ripple carry adder, which results in large delay in performing binary addition. On the other hand,it is possible to skip carry over group of n-bits in case of Carry Skip Adder. This results in less delay as compared to ripple carry adder. The logic used for the carry skip is shown in the figure below and also obvious from the equations.
P(0:3)<= ((x(0) or y(0)) and (x(1) or y(1)) and
(x(2) or y(2)) and (x(3) or y(3))); (xii)
Fig 4. Conventional carry skip adder Modified Carry Skip Adder (CLSKAs) In the case of conventional carry skip adder, each block consists of ripple carry adder and skip logic is used after each block to generate carry for next block. The speed of operation is affected by the method of carry propagation from previous block to next block[4]. While in CLSKAs, carry lookahead scheme is used in each block to generate carry for next block. As a result ther is a better performance in terms of speed as look ahead carry adder is faster than ripple carry adder[5]. Figure shows modified CLSKA with fixed block size i.e. 4-bit each.
Fig 5.Modified carry skip adder Carry Select Adder (CSA) In the carry select adder, the principle used to calculate sum is based on assuming input carry from previous stage. One adder calculates the sum assuming input carry of 0 while the other calculates the sum assuming input carry of 1[6]. Then, the actual carry triggers a multiplexer that selects the appropriate sum . Fig. shows the schematic block diagram of 16-bit Carry select adder consists of 4-
blocks each of 4-bit Look ahead carry adder . Carry output of each block is fed into next block as input carry.
Fig 6. Carry select adder Carry Save Adder (CSA) In carry save adder, if sum of two 16-bit binary numbers is to be computed, so 16 half adders are taken at first stage instead of using 16 full adders. Therefore, carry save unit consists of 16 half adders, each of which computes single sum and carry bit based only on the corresponding bits of the two input numbers. It is used to compute sum of three or more n-bit binary numbers. This adder is same as a full adder Let x and y are two 16 bit numbers and produces partial sum and carry as s and c: Si = xi xor yi (xii) Ci = xi and yi (xiii) The final addition is then computed as: 1. Shifting the carry sequence C left by one place. 2. Placing a 0 to the front (MSB) of the partial sum sequence S. 3. Finally, a ripple carry adder is used to add these two together and computing the resulting sum.
Fig 7. Carry save adder
RESULTS AND ANALYSIS The adders namely, ripple carry adder, carry lookahead adder , manchester carry chain adder, carry select adder, carry save adder, condition carry adder, conventional carry skip adder and modified carry skip adder have been designed using VHDL (Very High Speed Integration Hardware Description Language) for 16-bit unsigned data. In order to demonstrate the performance of these adders , the adders are compared on the basis of their delays and area occupied. The delay and area reports are generated for these specified adders. To get the delay and area report, the following tools are used:
1. Xilinx 9.2i is used as the synthesis tool. 2. Xilinx ISE Simulator is used for
simulation. 3. FPGA – Spartan II is used for
implementation.
The delay and area reports of the adders are generated with the help of the synthesis tool i.e. Xilinx 9.2i. The VHDL codes formulated for these adders are firstly simulated using the Xilinx ISE Simulator and further these codes are synthesized using the synthesis tool. The synthesis tool after the synthesis process generates a synthesis report and this report can provide us with the propagation delay and also the number of 4-input LUTs used by the design out of the total number of LUTs. Further, the VHDL codes of the adders after being simulated and synthesized can be implemented on FPGA kit by downloading design codes on the kit. The VHDL codes implemented on the kit such that the codes are converted in the design format (i.e. the programming file) to be downloaded on the kit. The delay and area reports generated for these adders are given in tabular form in table 1.
ADDERS (With Fix Block Size=4 bit)
DELAY (ns)
LUTs (out of 1536)
Ripple Carry Adder
32.997 32
Carry Lookahead Adder
22.792 17
Manchester Carry Chain Adder
31.744 32
Carry Select Adder
26.056 45
Carry Save Adder
35.424 46
Condition Carry Adder
33.378 32
Conventional Carry Skip Adder
17.636 43
Modified Carry Skip Adder
27.163 69
Table 1. Delay and area report of 16-bit fast adders
CONCLUSION
The delay and area reports generated as a result of simulation and synthesis processes run on the VHDL codes of the adders provide us with the performance analysis of these 16-bit adders. According to the reports of these adders, comparison between the delays of the adders concludes that the conventional carry skip adder has minimum propagation delay (17.636 ns) while it occupies 43 LUTs out of total 1536 LUTs on the Spartan II -XC3S50-5-TQ144 FPGA kit. However, carry lookahead adder has next least propagation delay (i.e. 22.792 ns) and least number of LUTs occupied on the FPGA kit (i.e 17 LUTs out of 1536 LUTs).
From the area and delay reports of these adders , it is observed that there are trade-offs between performance parameters i.e Area and Delay. In order to design delay efficient adder, conventional carry skip adders in which it is possible to skip carry over group of n-bits. This results in less delay as compare to ripple carry adder to generate output sum and carry bit for next block. This result in fast operation but at the cost of few more LUT’s due to carry skip logic.
References
1. R.P.P.Singh,Parveen Kumar and Balwinder Singh, “Performance Analysis of fast adders using VHDL”,2009 International Conference on advances in Recent Technologies in Communication and Computing.
2. Nagendra, C.; Irwin, M.J.; Owens, R.M.,“Area-time-power tradeoffs in parallel adders”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 43, Issue 10, Page(s): 689 – 702, 1996.
3. Hasan Krad and Aws Yousif Al-Taie, “Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL”, Journal of Computer Science 4 (4): 305-308, 2008.
4. Wang, Y.; Pai, C.; Song, X., “The design of hybrid carry lookahead/carry-select adders, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 49, Page(s): 16-24, 2002.
5. Min Cha and Earl E. Swartzlander, Jr, “Modified Carry Skip Adder for reducing first block delay”, Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing MI, Page(s): 346-348, 2000.
6. Behnam Amelifard, Farzan Fallah,
Massoud Pedram, “Closing the gap between Carry Select Adder and Ripple Carry Adder: A new class of Low-power and High-performance Adders”, Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) , 2005.
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
VLP0109-1
Organic Thin Film Transistor: Materials,
Structures and Operational Parameters Poornima Mittal
1, Brijesh Kumar
2, B. K. Kaushik
3, Y. S. Negi
4 and Krishna Raj
5
1Electronics and Communication Engineering, Graphic Era University, Dehradun, INDIA
3Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, INDIA
2,4Polymer Science and Technology Group, DPT, Indian Institute of Technology, Roorkee, INDIA
5Department of Electronics Engineering, H.B.T.I., Kanpur, INDIA
ABSTRACT — The Static Random Acess Memory discussed in this paper is based on a Four-Transistor SRAM cell. This paper focuses on the various important parameters viz., Static Noise Margin Analysis and Bit Line Leakage current analysis to characterize Four-Transistor SRAM cell. Maximum allowable SNM is needed to be investigated for efficient operation of SRAM cell. The purpose of this analysis is to measure the SNM of bit cell without flipping the cell contents.Bit line leakage current analysis is also done. Analysis involves bit cell contribution to column leakage and margin available for sum of total cell leakage current in a long column. The performance and results have been validated through simulations using ELDO tool from Mentor Graphics Corporation.
Index Terms – SRAM, Bit Line, Static Noise Margin, DC Source, Word Line
I. INTRODUCTION
Static random-access memory (SRAM) is a critical component across a wide range of microelectronics applications from consumer appliances to high-end workstation and microprocessor applications. For almost all fields of applications, semiconductor memory has been a key enabling technology. It is forecasted that embedded memory in SoC designs will cover up to 90% of the total chip area. A representative example is the use of cache memory in microprocessors. The operational speed could be significantly improved by the application of on-chip cache memory that temporarily stored a fraction of the data and instruction content of the main memory.
The SRAM consists of an array of static memory cells which are connected by horizontal word lines and vertical bit lines. To select a word line out of 2h, a h-bit address has to be applied. The output data is usually organized as a word of b-bits. From the architectural point of view the output word
represents a b-bit input/output (I/O -port). The I/O-port consists of b I/O-blocks, i.e. one block per bit of the output word. Each bit of the I/O-port can be connected to one out of 2w bit lines by a 2w-to-1 column or bit line multiplexer. Any SRAM cell can be accessed by an address word which is (h + b) bits long. This address is applied to the control logic block which controls all the memory operations, e.g. write, read, enable, data- in, data-out..
II. BASIC SRAM ARCHITECTURE A typical static random access memory (SRAM) architecture is as shown in Figure 1. It consists of a matrix of memory cells arranged in an array of 2N rows by 2M columns. The total size of the memory array is 2M x 2N bits. During a read operation, one of the 2N rows (Word lines) is selected by the row address decoders by decoding the row addresses. All the memory cells in the given word line are enabled. The column decoder selects one of the 2M columns and the value of the selected memory cell is read out by the sense amplifier. The data into and out of the memory array is controlled by the Read-Write control circuit.
Figure 1. Static Random Access Memory Architecture
III. SCHEMATIC AND READ/WRITE OPERATION OF 4T SRAM CELL
In four Transistor SRAM celll two NMOS
transistors are used as pass transistors to access the cell and two PMOS transistors which are used as drivers to the cell.
Figure2. Schematic Of The Cell
A. WRITE OPERATION
In order to store a logic ‘1’ to the cell, BL is charged to Vdd and BL’ is charged to ground and vise versa for storing ‘0’. Then the word line is switched to Vdd to turn on the NMOS access transistors. When the access transistors are turned on, the values of the bit lines are written into Q and Q’. The node that is storing logic’1’ will not go to full Vdd because of a voltage drop across the NMOS access transistor. After the write operation the word line voltage is reset to ground to turn off the NMOS access transistors. The node with the logic’1’ stored is pulled up to full Vdd through the PMOS driver transistors.
B. READ OPERATION
The read operation of the cell is different from that of 6T cell. To read from the cell the bit lines are charged to ground instead of Vdd and the word line voltage is set to Vdd to turn on the NMOS access transistors. The node with logic’1’ stored will pull the voltages on the corresponding bit line up to a high (not Vdd because of the voltage drop across the NMOS access transistor) voltage level. The other bit line is pulled to ground. The sense amplifier detects which bit line is at high voltage and which bit line is at ground.
If the cell was storing a logic’0’ the voltage level of BL will be lower than BL’ so the sense amplifier will output a logic‘0’. If the cell was storing logic’1’ then the voltage level of BL will be higher than BL’ then the sense amplifier will output a logic’1’
IV. EXPERIMENTS AND RESULT
A. Static Noise Margin Analysis
SNM quantifies the maximum level of voltage nose which can be present at the internal nodes of a bit cell without flipping the cell contents. Figure 3shows the location Q and Q´, the noise margin sources in the 4T SRAM cell schematic. The purpose of this analysis is to measure the SNM of bit cell. A SRAM cell should be designed such that under all conditions some SNM is reserved to cope withdynamic disturbances caused by a particle, cross talk, voltage supply ripple and thermal noise. I have done SNM analysis for 6T and 4T cell for 0.18µ technology node. The method and results are shown below.
Figure 3. 4T SRAM cell simulated structure
B. Method to calculate Static Noise Margin
To analyze Static Noise Margin, introduce a DC noise source inside the SRAM cell and see where the cell flips .Put the WL (Word Line) at Vdd . Bit Line and Bit Line’ (BL and BL’) are connected to ground.Iinitialize Q’ with Vdd and Q with 0. Now slowly increase VX from 0 and monitor points Q and Q’ to investigate where the cell flips. Static Noise Margin is measured to be 362.3279 mV.
C. Bit Line Leakage Current Analysis
The purpose of this analysis is to characterize the bit cell contribution to column leakage. The main purpose of this test is to see the margin available for the sum of total cell leakage currents in a long column (from unselected WLs) during a read operation. This simulation should be used as guidelines for designing the maximum number of physical rows in a SRAM array.
Figure 4. Bit Line Leakage Current Calculation
D. Method to calculate Bit Line Leakage Current
To do Bit Line Leakage Current Analysis initialize the output Q to ‘0’ and Q’ to Vdd . At this time Word Line (WL) is in off condition and therefore set to 0. BL and BL’ are connected to ground. Now leakage current is measured as the current through MN4 (pass transistor facing the ‘1’).The Bit Line Leakage Current for 4T SRAM cell is measured to be 7.1441 pA.
V. CONCLUSION
The two basic parameters static noise margin and bit line leakage current are successfully measured.All the simulations are done in ELDO tool from Mentor Graphics Corporation. Both the parameters discussed in this paper are very important in characterization of 4T SRAM cell. A SRAM cell is designed such that under all conditions some SNM is reserved to cope with dynamic disturbances caused by particle, cross talk,
voltage supply ripple and thermal noise. Static Noise Margin is measured to be 362.3279 mV. For BLCC it is also seen the margin available for the sum of total cell leakage currents in a long column during a read operation. The Bit Line Leakage Current for 4T SRAM cell is measured to be 7.1441 pA. Objective is also to keep Bit line Leakage Current as low as possible.
VI. REFERENCES
[1]. Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design,” Second-Edition, Pearson Education Asia, 2002.
[2]. S. M. kang and Y. leblebici, “CMOS Digital Integrated Circuits,” Third Edition, Tata McGraw –Hill, 2002.
[4]. Semiconductor Memories, A handbook of design, manufacture and application By “Betty Prince”. [5]. Stephan De Beer, Monuko du Plessis, and Evert Seevinck,”An SRAM Array Based on a Four-Transistor CMOS SRAM Cell”, IEEE Transactions On Circuits and Systems—Fundamental Theory and Applications, Vol. 50, No. 9, September 2003.
[6]. Jinshen Yang ,Li Chen,”A New Loadless 4-Transistor SRAM Cell with a 0.18 μm CMOS Technology”, IEEE,2007.
[7]. Ding-Ming Kwai ,”Review of 6T SRAM Cell” ,Intellectual Property Library Company ,June 3, 2005.
[8]. T-H Joubert, E Seevinck, M du Plessis, “A CMOS REDUCED-AREA SRAM CELL”, ISGAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.
[9]. Bharadwaj S. Amrutur and Mark A. Horowitz,” Speed and Power Scaling of SRAM’s”, IEEE Transactions on Solid State Circuits, Vol.. 35, No. 2, Febraury 2000.
U
Quantitative Analysis and Optimization Techniques
for On-Chip Cache Leakage Power
Vikas Tiwari Shyam Akashe Rajkumar Rajoriya
M.Tech (VLSI Design) Associate Professor. Assist. Professor
Abstract—On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the sub threshold leakage power is becoming one of the dominant total power consumption com- ponents of those caches. In this study, we present optimization techniques to reduce the sub threshold leakage power of on-chip caches assuming that there are multiple threshold voltages, ’s, available. First, we show a cache leakage optimization technique that examines the tradeoff between access time and sub threshold leakage power by assigning distinct ’s to each of the four main cache components—address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second, we show optimization techniques to reduce the leakage power of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high ’s are enough to minimize leakage in a single cache—3 ’s if we include a nominal low for micro- processor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lower leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lower leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today’s processors result in significant leakage and dynamic power reduction without affecting the average memory access time.
various cache access time points. Second, we present how cache
leakage power can be reduced while maintaining the same av-
erage memory access time of a processor memory system using
L1 and L2 cache access statistics for SPEC2K workloads [15].
The reminder of this study is organized as follows. Section II
explains our on-chip cache subthreshold leakage power and ac-
cess time-modeling methodologies. Section III presents a sub-
threshold leakage power optimization technique for a given ac-
cess time constraint and provides a quantitative tradeoff analysis
of on-chip cache subthreshold leakage power and access time.
Section IV presents two-level cache leakage power optimization
techniques using cache access statistics. Section V discusses fu-
ture directions for this line of work and adds some concluding
remarks.
II. ON-CHIP CACHE LEAKAGE POWER AND ACCESS
TIME MODELS
To examine tradeoffs between subthreshold leakage power
and access time of a processor cache memory system, we need
circuit models to estimate the subthreshold leakage power and
access time of caches. Rather than starting from scratch, we
could have built on a widely used cache memory model called
―CACTI‖ [16]. This model estimates access time, dynamic en-
ergy dissipation, and area of caches for given cache configura-
tion parameters such as total size, line size, associativity, and
number of ports. However, it is based on an outdated 0.8- m
CMOS technology and it applies linear scaling to obtain the fig-
ures for smaller process technologies. Furthermore, it does not
provide access time and leakage power when multiple ’s are
available. To address these shortcomings, we designed caches
with the 70-nm Berkeley predictive technology model (BPTM)2
in anticipation of the next generation of process technology.
Then, we derived our subthreshold leakage power and access
time models based on the HSPICE simulations of the designed
cache circuits.
The designed caches ranged from 16 to 1024 KB in size. The
bitlines and wordlines were segmented to improve access time,
and subbanks were employed to reduce dynamic power dissipa-
tion [17] as well; see Table I for the cache subbank organization
used in this study. The caches were broken into four components
for the purposes of assigning distinct ’s: address bus drivers,
Fig. 1. Cache subbank organization.
data bus drivers, decoders, and 6T-SRAM cell arrays with sense
amplifiers. Fig. 1 illustrates the cache subbank organization used
in this study.
The circuit topology and the ratios of transistors in
the decoder circuits are based on the CACTI model but opti-
mized for the 70-nm technology. In addition, modern techniques
for lower voltage are employed for the bitline precharge and
sense-amplifier circuits. For the address and data bus intercon-
nects, we employed an H-tree topology and inserted repeaters
on each branch of the buses to optimize the interconnect delay
of cache buses. To obtain the interconnect capacitance and re-
sistance of long wires such as bitlines, wordlines, address, and
data buses, the lengths of the interconnects are estimated using
SRAM cell dimensions of 1.42 m 0.72 m and the cache or-
ganizations in Table I. Then, for given interconnect length, the
predictor provided in footnote 2 is used to estimate the intercon-
nect capacitance and resistance.
HSPICE simulations were run extensively to obtain leakage
power and access time (or delay) models for wide ranges of
cache sizes and ’s for their four components. We considered
’s between 0.2 and 0.5 V in steps of 0.05 V at 1-V nominal
supply voltage. We measured the leakage power and the delay
of each cache component separately.
A. Leakage Power Models
Fig. 2 shows versus leakage power of the 7 128,
8 256, and 9 512 row decoders that we designed. The
HSPICE simulation results shown in Fig. 2 agree with the
exponential decay in leakage power with a linear increase of
that is characteristic of general CMOS circuits
(1)
To obtain an approximated analytic equation for leakage power
as a function of , we measured the leakage power of the de-
coders at each discrete point, and we applied an exponen-
tially decaying curve fitting method to the measured leakage
power as follows:
(2)
where , and are constants derived from using Origin
6.1, which is a scientific graphing and analysis software curve-
TABLE II
CACHE COMPONENT LEAKAGE POWER MODEL COEFFICIENTS AT 70 C DIE TEMPERATURE AND A TYPICAL CORNER FOR EACH CACHE SIZE
Fig. 2. Leakage power dissipation of the 7 128, 8 256, and 9 512 decoders.
fitting package3—the -squared error is less than 0.001 for each
fitted curves.
The rest of the cache components—address driver, data
driver, and 6T SRAM cell array—show the same leakage
power trend characteristics as the decoder of Fig. 2; leakage
power decreases exponentially with the linear increase of .
Hence, an identical curve-fitting method can be applied for
these components to derive leakage power models like (2). The
coefficients for all of the components in (2) can be found in
Table II.
Once all of the approximated analytic leakage power models
for each component are derived for a cache size, the total
leakage power of the cache can be approximated as the sum
Fig. 3. Delay time of 7 128, 8 256, and 9 512 decoders.
of the leakage power of all the components. Assuming that we
apply four distinct ’s, the analytic approximated equation
for leakage power (LP) is
(3)
where , and represent the ’s for address
bus drivers, data bus drivers, decoders, and 6T-SRAM cell ar-
rays, respectively. Each exponential term evaluates the leakage
power dissipation of one of the four components.
B. Access Time Models
Fig. 3 shows versus delay time of the 7 128, 8 256,
and 9 512 row decoders that we designed. Basically, the
TABLE III
CACHE COMPONENT DELAY MODEL COEFFICIENTS AT 70C DIE TEMPERATURE AND A TYPICAL CORNER FOR EACH CACHE SIZE
CMOS circuit delay of ultra deep submicrometer short-channel
transistors is
(4)
where , and 4 are constants depending on the technology
and transistor sizes. The measured delay time trends in Fig. 3
agree with (4). However, the circuit delay or access time also fits
very well to an exponential growth function with a very small
exponent over our range of interest. It was convenient for some
of our optimizations to approximate delay this way.
To obtain an approximated analytic equation for delay time
as a function of , we measured the delay time of the decoders
at each discrete point, and we fit the following exponential
curve to the measured delay time:
(5)
where , and are constants derived using the same tech-
nique as that used for the leakage power models.
The rest of the cache components show the same delay trend
characteristics as the decoder case of Fig. 3. Hence, the same
curve-fitting technique can be applied for those components to
derive approximated delay time models as functions of like
(5). The coefficients for all the components in (5) can be found
in Table III.
Once all of the approximated delay time models for each
component are extracted for a specific cache size, total delay
or access time of the cache can be approximated as a sum of the
delay times of all the cache components. Assuming that we can
4 was around 2 in submicrometer technology, but it has been decreased to
about 1.3 in the current generation deep-submicrometer technology.
Fig. 4. Access time and leakage power versus cache size of the baseline caches.
apply four distinct ’s, the analytic approximated equation for
the access time (AT) is
(6)
where , and represent the ’s for address
bus drivers, data bus drivers, decoders, and 6T-SRAM cell ar-
rays, respectively. Each exponential term corresponds to the
delay time of one of the four components.
We also define baseline caches in which the of all the
cache components is set to a low- (0.2 V). Fig. 4 shows the
access time and the leakage power of the baseline caches. The
cache access time grows logarithmically and the leakage power
increases linearly with the cache size. Those trends agree with
those of earlier studies on SRAM design. In Fig. 4, we assume a
direct-mapped cache organization and consider only the leakage
power of data arrays, disregarding the leakage of the tag com-
parators and other cache control logic.
III. CACHE LEAKAGE OPTIMIZATION WITH MULTIPLE
ASSIGNMENTS
A. Methodology
In this section, we present a leakage power optimization tech-
nique assuming that we can assign multiple ’s to a cache. To
find the minimum leakage power of caches using a maximum
of four distinct ’s under a specified target access time con-
straint, we formulate the problem as follows:
constraints
(7) Fig. 5. Normalized optimum LP and V versus normalized AT of 512-KB caches—schemes I and II.
(8)
where , and represent the ’s for address
bus drivers, data bus drivers, decoders, and 6T-SRAM arrays,
respectively.
There exist numerous combinations of , and
satisfying a specific target access time. Among those combinations, we find a quadruple of , and producing minimum leakage power using a numerical optimiza-
tion method (e.g., Matlab’s fmincon function). We allowed the
combination that satisfies a specified access time error range
within 5%. We can repeat this procedure with modified objec-
tive and constraint functions to find an optimal combination
for cache memories that have only two or three distinct ’s.
Assuming that we can assign distinct ’s to each compo-
nent of the cache, it is important to determine how many ’s
are cost-effective because an extra mask and process step are
needed for each additional . To examine the dependence of
the optimization results on access time, we sweep the target ac-
cess time from the fastest possible (assigning a low of 0.2 V
to all the cache components) to the slowest possible (assigning
a high of 0.5 V to all the cache components). We present
here the summary of the assignment schemes we examined
in this study.
• Scheme I: Assigning a high- to all of the cache compo-
nents including address bus drivers, data bus drivers, de-
coders, and 6T-SRAM cell arrays. This requires 2 ’s if
we include a nominal or low for the processor’s gen-
eral logic circuits.
• Scheme II: Assigning a high- only to the 6T-SRAM cell
arrays that dominates leakage power but not the overall
cache delay and assigning a default- or low- (0.2 V) to
the rest of the transistors. This requires at least two ’s if
we include a nominal or low for the processor’s logic.
• Scheme III: Assigning a high- to the 6T-SRAM cell ar-
rays and assigning another high- to the peripheral com-
ponents—address bus drivers, data bus drivers, and de-
coders of the cache. This requires at least three ’s if
we include a nominal or low for the processor.
• Scheme IV: Assigning four distinct high ’s to all four
cache components. This requires at least five ’s if we
include a nominal or low for the processor logic.
B. Leakage Power Optimization and Quantitative Tradeoff
Analysis
In Fig. 5, we plot the normalized optimum leakage power and
at different target access times (125%, 150%, 175%, and so
forth) of 512-KB caches employing schemes I and II. The op-
timum leakage power and the are obtained using (7) and (8)
of Section III-A. The parenthesized I and II in Fig. 5 represent
the schemes I and II, respectively. In the graph, the normalized
minimum leakage power and the access time of 100% corre-
spond to the access time and the leakage power of a 512-KB
baseline cache designed with a low (0.2 V) for all four cache
components—the fasted but leakiest cache. The 125% access
time in the axis means that the cache is 25% slower than the
baseline cache.
According to the trends shown in Fig. 5, the leakage power
decreases exponentially as the increases linearly; note that
the axis is a logarithmic scale. The optimization results for the
different cache sizes show almost the same normalized optimum
leakage power and trends as those of the 512-KB caches in
Fig. 5 as long as the same assignment scheme is applied; see
Table IV for the normalized leakage power of all the cache sizes.
Comparing two schemes—scheme I and II—the 512-KB cache
with scheme II dissipates less leakage power than the one with
scheme I at the same access time point when the normalized ac-
cess time constraint is less than 155%. For example, at the 125%
access time point, scheme II shows 6% leakage dissipation of
the baseline 512-KB cache and scheme I shows 13% leakage
dissipation—a 2 difference. However, scheme I shows better
leakage power reduction beyond a 155% normalized access time
point.
Fig. 6 shows the normalized optimum leakage power and versus normalized access time trends for a 512-KB cache of
scheme III. The optimum leakage power and the ’s are ob-
tained using (7) and (8) of Section III-A. In Fig. 6, the of
TABLE IV
PERCENTAGE LEAKAGE POWER OF SCHEMES I–IV NORMALIZED TO LEAKAGE POWER OF EACH CACHE SIZE AT THE 100% AT POINT
Fig. 6. Normalized optimum LP and V versus normalized AT of 512-KB caches—schemes I and III.
the SRAM cell array, denoted as array in the graph, starts to in-
crease first. This implies that the SRAM cell array is responsible
for the most significant fraction of total cache leakage power,
but it has the least impact on increasing the total cache access
time. After the of the SRAM cell arrays are saturated to the
maximum allowed point (0.5 V), the of the peripheral com-
ponents labeled as peri in the graph is increased further to reduce
further leakage power in the peripheral components. However,
this just increases the access time without much further cache
leakage reduction. For example, the leakage power is not de-
creased over the 215% access time point where the for the
peripheral circuit has not reached the maximum value (0.5 V)
in this 512-KB cache case.
This leakage power and versus access time trends also ex-
plain the leakage optimization results shown in Fig. 5: scheme II
shows a better optimization result than scheme I does when the
normalized access time is less than 155%, but it does not beyond
155% access time point. Recall that scheme I assigns a high- to all the cache components. It sacrifices more access time un-
necessarily by increasing the of the peripheral components
with little leakage reduction at the same access time. However,
scheme II assigns the high- to just the SRAM cell arrays
that are responsible for a greater fraction of total cache leakage
power but affects access time less. However, scheme II cannot
Fig. 7. Normalized optimum LP and V versus normalized AT —scheme IV.
reduce leakage power beyond the 155% access time point, be-
cause the leakage power of the peripheral components, where a
low is used, becomes substantial beyond this point.
Fig. 7 shows the normalized optimum leakage power and versus normalized access time trends for a 512-KB cache of
scheme IV. The optimum leakage power and the ’s are ob-
tained again using (7) and (8) of Section III-A. In scheme IV,
we can assign up to 4 distinct ’s for leakage power opti-
mization. According to the results shown in Fig. 7, the of
the 6T-SRAM cell arrays starts to increase first similar to the
scheme III case. Among the peripheral components, the for
the data bus starts to increase first. This implies that the data
bus consisting of 128 b—the assumed bus width between the L2
and L1 caches—has the second most significant impact on the
leakage power. Even though the address bus has the same struc-
ture, the number of bits in the address bus is much smaller than
the data bus. Hence, the leakage power impact of the address
bus much less than the data bus. However, in the case of smaller
caches (e.g., 16–64 KB caches) where the data bus width is 32 b,
both the data and address bus have almost the same impact on
the leakage power. Therefore, the trends for both the data and
address buses will be the same. These trends suggest the di-
rection of optimizations that reduce cache leakage power.
Table IV summarizes the normalized cache leakage power of
schemes I–IV. As expected, we can reduce more leakage power
TABLE V
CACHE DYNAMIC ENERGY CONSUMPTION PER ACCESS AND LEAKAGE POWER
DISSIPATION AT 70 C DIE TEMPERATURE AND A TYPICAL CORNER FOR EACH CACHE SIZE
while achieving the same access time by having more ’s to
control. If the access time is fixed, the caches of schemes III and
IV always show 38%–72% better leakage optimization results
than those of scheme I. There are a few things we should note
from this comparison study. First, as the target access time is
increased to more than the 150% point in scheme II, caches dis-
sipate more leakage power than those employing scheme I. This
implies that the cache peripheral components consume nonneg-
ligible leakage power. The leakage power of those components
becomes substantial when we cut down the leakage power of the
6T-SRAM arrays significantly. Second, the slowest cache ac-
cess time of scheme II ends around 150% in small-size caches.
This means that the peripheral components also play important
roles in both cache leakage power and access time. In other
words, increasing the of 6T-SRAM cell arrays alone gives us
diminishing returns at some point without reducing the leakage
power further. This is why the caches of scheme I give even
better results than those of scheme II as increases. Finally,
there is a negligible difference between caches of schemes III
and IV in terms of leakage power reduction. This implies that
scheme III employing two distinct high ’s—three ’s if
we include a nominal or low for the processor—is enough
to minimize leakage. Finally, as illustrated in Figs. 5–7 and
Table IV, each cache shows a wide range of optimal leakage
power consumption depending on target access time. Hence, the
right tradeoff point between the leakage power and the access
time of the caches will be determined by either system design
specifications or constraints.
IV. LEAKAGE OPTIMIZATION TECHNIQUES
FOR TWO-LEVEL CACHES
A. Methodology
In a processor memory system, the average memory access
time (AMAT) [18] is a key metric for measuring the overall
memory system performance. To evaluate the performance or
AMAT, it is essential to examine the cache miss characteristics
of realistic applications, because the performance or AMAT is a
function of L1 and L2 cache miss rates and cache access times.
In our study, we assume that the memory system hierarchy con-
sists of separate L1 instruction and data caches with a unified L2
cache. Then, the average performance of the processor memory
system can be measured or compared with the AMAT repre-
sented by
(9)
where HitTime and HitTime are the access time of L1 and
L2 caches, Miss Rate and Miss Rate are the miss rate of L1
and L2 caches, and Miss Penalty is the external memory
access and data transfer time. Note that the local miss rate5 is
used as the Miss Rate .
Similarly, we measure the average memory access energy
(AMAE) to compare the dynamic energy dissipation of each
memory system configuration. Assuming that the L1 cache is
accessed every cycle, the AMAE represents the average en-
ergy dissipation per access in the entire microprocessor memory
system that includes L1, L2, and main memory. We can estimate
average memory access energy, as follow:
(10)
where Hit Energy is average energy dissipation per access
given in Table V. We assume a two-channel 1066-MHz
256-MB RAMBUS DRAM RIMM whose sustained transfer
rate is 4.2 GB/s [19] to derive the main memory access time
and dynamic energy dissipation per access. Though the sus-
tained transfer rate is quite high, we should also consider the
RAS/CAS latency of the memory, which is about 20 ns. For the
energy dissipation per access, we used the number given in [20],
which is 3.57 nJ per access. The dynamic energy dissipation
per access can vary depending on the number of RIMMs. We
assume that one RIMM is installed. See Section IV–B and note
that more RIMMs are favorable for our optimization technique,
because our technique prefers a larger L2 cache to a smaller
one for leakage power reduction. The larger L2 cache accesses
DRAM less frequently than the smaller one, resulting in less
energy consumption for accessing the external DRAM. Hence,
if more RIMM modules are installed implying more energy
dissipation per DRAM access, a larger L2 cache will allow
even more energy to be saved.
To obtain L1 and L2 cache miss rates, we use the Simple-
Scalar/Alpha 3.0 tool set [21], which is a suite of functional and
timing simulation tools for the Alpha AXP ISA. In addition, we
collected the results from all 25 of the SPEC2K benchmarks [15]
to perform our evaluation. All SPEC programs were compiled
for a Compaq Alpha AXP-21 264 processor using the Compaq
C and Fortran compilers under the OSF/1 V4.0 operating system
using full compiler optimizations . We completed the ex-
ecution for each benchmark application to get reliable L2 cache
miss rates, because L2 cache accesses are far less frequent than
5This rate is simply the number of misses in a cache divided by the total number of memory accesses to this cache.
TABLE VI
AVERAGE L1 AND L2 CACHE MISS RATES
FROM THE ENTIRE SPEC2K BENCHMARKS
L1 cache accesses; an insufficient number of L2 accesses may
result in unrepresentatively higher L2 cache miss rates.
Table VI shows the average L1 and L2 cache miss rates from
the entire SPEC2 K benchmarks for 16-, 32-, and 64-KB L1
caches, respectively. We used direct-mapped L1 instruction
caches and four-way set associative L1 data caches. Also, we
used eight-way set associative L2 caches. For simplicity, each
L1 cache miss rate is obtained by taking the sum of the number
of total instruction and data cache misses and dividing by the
sum of total instruction and data cache accesses; a 16-KB L1
means instruction and data caches are each 16 KB in size. Since
an L2 miss rate is a function of the L1 cache miss rate, we
measure the separate L2 cache miss rates for each L1 cache size
configuration. Those cache miss characteristics will definitely
affect the leakage optimization direction of two-level cache
memory systems.
B. L2 Cache Leakage Power Optimization
Since an L2 cache’s contribution to leakage power dominates
due to their size, we will examine the leakage power optimiza-
tion of the L2 cache first. Consider caches designed with low- (0.2 V) devices and a baseline cache memory system consisting
of 16 and 128 KB for L1 and L2 caches, respectively. Then,
we have leakage power consumption and AMAT corresponding
to this configuration. Increasing of the 128-KB L2 cache
will reduce the leakage power of the L2 cache, but it will in-
crease the AMAT of the cache memory system because of the in-
creased access or hit time. However, there is a way to reduce the
leakage power of the cache memory system without increasing
the AMAT that significantly impacts on the execution time of
the system.
The key to reducing leakage power without increasing AMAT
is to compensate for the increased L2 access time by reducing
the cache miss rate of the cache memory system. To reduce the
miss rate, we can increase the L2 cache size. The main memory
access penalty is quite significant in term of both time and en-
ergy. Hence, even a slight reduction of L2 cache miss rates re-
sults in a significant improvement in the AMAT. We note that
although area was one of the most important design constraints
in the past, this trend is changing and power is becoming an
Fig. 8. L2 leakage power optimization at a fixed L1 size (16 KB). (1) and (2) are the leakage power consumption of the 256- and 512-KB caches at the same AMAT as the baseline 128-KB cache, respectively.
equally important constraint in many situations [22]. In this ar-
gument, we assume that the same AMAT will approximately
give us the same execution time for a fixed processor core, L1
cache size, and benchmark program, so that we can fairly com-
pare the total leakage energy consumption as well.
Fig. 8 shows the leakage power versus AMAT of L2 caches
with a fixed L1 cache size—16 KB. The leakage power opti-
mization for individual caches is based on scheme III that re-
quires two additional distinct high ’s for L2. Assuming the
AMAT of the fastest 128-KB L2 cache designed with low- (0.2 V) as a baseline, we compare the leakage power of other
caches at the same AMAT point; see the (1) and (2) points in
Fig. 8. The (1) and (2) points are the leakage power consump-
tion of the cache system with the 256- and 512-KB caches at
the same AMAT as the baseline 128-KB cache system. As can
be seen from the plots, the AMAT can be maintained while the
leakage power can be reduced by replacing the baseline 128-KB
L2 cache with a 256-KB L2 cache that is intentionally slowed
down by increasing its ’s to reduce leakage.
This replacement with the double-sized L2 cache reduces
the leakage power by 70% compared to the fastest but leakiest
128-KB L2 cache with the same AMAT. Similarly, the use of a
512-KB L2 cache can further reduce leakage compared to the
256-KB cache; see the vertical line in Fig. 8.
Finally, the employment of larger L2 caches also reduces
the average dynamic power of the memory system, because
the larger L2 caches reduce the number of external memory
accesses that consume a significant amount of dynamic energy.
Table VII summarizes the results for the normalized leakage
power and normalized average memory access energy for each
L1 cache size designed using scheme III at a fixed AMAT. To
compare leakage power and AMAE, the following standard
cache configurations were used: 128-KB L2 with 16-KB L1,
256-KB L2 with 32-KB L1, and 512-KB L2 with 64-KB L1.
The shaded numbers represent the baseline L2 configuration,
leakage power, and AMAE. Table VII shows the counterintu-
itive results that we can reduce both leakage power and AMAE
by employing larger L2 caches while maintaining the same
AMAT.
TABLE VII
L2 CACHE NORMALIZED LEAKAGE AND AMAE AT THE FIXED L1 SIZE (16 KB) AND AMAT
Fig. 9. L1 leakage power optimization at a fixed L2 size (512 KB). (1) and (2) are the leakage power consumption of the 32- and 16-KB caches at the same AMAT as the baseline 64-KB cache, respectively.
C. L1 Cache Leakage Power Optimization
It is rather difficult to improve the L1 cache miss rates fur-
ther, because they are already very low for 16-, 32-, and 64-KB
caches in the case when SPEC2K benchmarks are run. Hence,
the access time of caches become a dominant factor in deter-
mining the AMAT. For example, the access time of a 64-KB
L1 cache increases by 48% compared to the fastest 16-KB L1
cache, because the access time is very sensitive to size in small
caches. Essentially, cache access time increases logarithmically
with size, but has a steeper slope for smaller caches than for
larger caches. This observation explains why the AMAT of a
cache hierarchy with a smaller L1 cache can be faster than one
with a larger L1 caches for a certain range of cache sizes (e.g.,
16 or 64 KB).
Fig. 9 shows the leakage power versus the AMAT of 16-, 32-,
and 64-KB L1 caches using scheme III each with a fixed L2
cache of size 512 KB. Like the comparison performed in Section
IV–B, the leakage power of different caches is compared at the
same AMAT point. The plots show that leakage power can be
reduced by replacing the fastest 64-KB L1 cache with a 32-KB
L1 cache that is intentionally slowed down by increasing its
’s to reduce the leakage power—the resulting cache memory
TABLE VIII
L1 CACHE NORMALIZED LEAKAGE AND AMAE AT THE FIXED L2 SIZE (512 KB) AND AMAT
system still has the same AMAT. Similarly, a slowed 16-KB
cache with increased ’s can replace a 32-KB cache without
changing the AMAT of the L1/L2 hierarchy. The new system
consumes much less leakage power; see points (1) and (2) in
Fig. 9, which are the leakage power consumption of the cache
system with the 32- and 16-KB caches at the same AMAT as
the baseline cache system.
Table VIII shows the results for normalized leakage power
and AMAE as a percentage of each fast but leaky L1 cache
size using scheme III with fixed AMATs. The comparisons were
performed in the same manner as Table VII. The shaded num-
bers represent the baseline L1 configuration, leakage power,
and AMAE. According to the comparisons, we can reduce both
leakage power and AMAE by employing smaller L1 caches.
This is the inverse of the case for L2 caches, where the leakage
of the overall memory system can be reduced by increasing their
size. However, it should be noted that these results are only valid
within the specific set of sizes and simulation environment given
in this discussion. First, a 4-KB L1 cache will have a cache
miss rate that is much higher than a 16-KB cache, but its access
time will not be sufficiently smaller to make the tradeoff worth-
while. Also, the normalized AMAE is rather high because the
total power fraction of L1 caches is relatively small compared to
L2 caches. Second, many SPEC2K benchmark programs have
very high locality compared to real-world larger size applica-
tions. This results in quite low cache miss rates for small-size
L1 caches as shown in Table VI. Third, the operating system
(OS) context switching was not modeled due to our limited sim-
ulation environment. The context switching typically increases
cache miss rates, because cache flushing increases cold start
misses. These factors must be considered if one is to perform
realistic cache leakage power optimizations with the proposed
techniques.
V. CONCLUSION
In this study, we examined the leakage power and access time
tradeoff for caches where multiple ’s are allowed. We used
curve fitting techniques to model subthreshold leakage power
and access time. Our results show that two extra distinct high
’s for caches—3 ’s including the for the micropro-
cessor core logic—are sufficient to yield a significant reduction
in leakage power. Such an arrangement can reduce the leakage
power by as much as 91%. We also show that smaller L1 and
larger L2 caches than are typical in today’s processors result
in significant leakage and dynamic power reduction without af-
fecting the average memory access time. Given that the pro-
cessor core may need a distinct , and each of the caches may
need up to two ’s (scheme III) we could require up to five
distinct ’s for the leakage power optimization of two-level
cache memory systems.
Even though the modeling and optimization techniques pre-
sented in this study have been performed using continuous-do-
main functions, the actual cache latencies are integer numbers of
processor clock cycles. Cache designers or architects can choose
an appropriate discrete point from the continuous-domain re-
sults depending on their target processor core clock frequency.
Furthermore, the circuit techniques combined with microar-
chitectural level controls exemplified by drowsy caches [10] are
designed to reduce the leakage power of L1 caches when sac-
rificing access time is not an option. Such an approach is less
attractive for L2 caches. The same effect can be obtained more
simply by using high- circuits.
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CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
VLP0302-2
BVF Gate: A 4 * 4 BVF gate as shown in figure 3. This is
a reversible double XOR gate and can be used for
duplication of the required inputs to meet the fan-out
requirements. The input vector is I (A, B, C, D), the output
vector is O (P, Q, R, S) and the output is defined by P = A,
Q = A xor B, R = C and S = C xor D. Quantum cost of a
BVF gate is 2. In the proposed design this gate is used to
copy the operand bits and it is shown that the number of
gates required to copy is reduced by 50% with same
quantum cost.
Peres Gate: A 3*3 Peres gate [10] as shown in figure 4. The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by P = A, Q = A xor B and R=AB xor C. Quantum cost of a Peres gate is 4. In the proposed design Peres gate is used because of its lowest quantum cost.
Double Peres gate: A Double Peres Gate as shown
in figure 5. The inputs and outputs are as shown in Table-1.The full adder using DPG is obtained with C=0 and D= Cin and its quantum cost is calculated to be equal to 6 from its quantum realization [11] shown in figure 5.
Inputs Outputs
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 1
0 0 1 1 0 0 1 1
0 1 0 0 0 1 1 0
0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 1 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 0 0
1 1 0 0 1 0 0 1
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 0
1 1 1 1 1 0 1 0
B. REVERSIBLE GATES IMPLEMENTED USING ELEMENTARY QUANTUM GATES Reversible implementations of 3×3 Toffoli, Peres and Fredkin gates using elementary quantum gates are shown in figure 6, figure 7, and figure 8 respectively.
3. PARALLEL MULTIPLIERS
There are two types of multipliers which are known as
sequential and parallel multipliers. The first type
iteratively computes the final product. It needs to use
feedbacks and loops to compensate for the iterative
portion. This design is too slow and not suitable for the
reversible implementation. The second type (i.e., parallel
multiplier), conventionally, consists of two main steps:
Partial product generation
Multi-operand addition
Algorithm 1 (The n×n parallel multiplier):
Inputs: Two n-bit operands
X: xn-1…….. x1, x0 , Y: yn-1…….. y1, y0
V V V+
++
V V V+
++
Fig.2 Fredkin Gate
Fig.3 BVF Gate
Fig.4 Peres Gate
Fig.6 Implementation of the 3×3 Toffoli gate [11]
Fig.7 Implementation of the 3×3 Peres gate [12]
V V+
++
V
Fig.8 Implementation of the 3×3 Fredkin gate [11, 13]
Fig.5 Double Peres Gate
Table 1 Truth Table of Double Peres Gate
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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Output: A 2n-bit product Z: zn-1…….. z1, z0
I. Generate n partial products
P: pin-1…….. pi1, pi0 where, 0 < i < n-1
Such that pij = xj* yi
II. Produce the final product Z= Σ pi
where, 0 < i < n-1
The operation of a 4*4 reversible multiplier is shown in
figure 9. It consists of 16 Partial product bits of the X and
Y inputs to perform 4 * 4 multiplications. However, it can
extended to any other n * n reversible multiplier.
3.1 Partial Product Generation
Partial products can be generated in parallel using 16
Peres gates as shown in figure 10.
An important point that should be considered is that in
an n×n parallel multiplier (in reversible logic) for
generating partial products in parallel, n copies of each bit
of the operands are needed. Therefore, some fan-out gates
are needed. The number of fan-out gates needed for the
reversible 4×4 multiplier is 24. It uses 4*4 BVF gates with
two constant inputs as shown in figure 11.
3.2 Multi-operand Addition (MOA)
As discussed in previous section, next step is an noperand
addition. To implement this part of circuit, we use carry
save adder (CSA). The CSA tree reduces the four
operands to two. Thereafter, a Carry Propagating Adder
(CPA) adds these two operands and produces the final
8-bit product. The proposed four operand adder shown in
figure 12 uses Double Perer Gate (DPG ) gate as a
reversible full adder and Peres gate as half adder.
The proposed reversible multiplier circuit uses 8
reversible DPG gates and 4 Peres gates. The Peres gate
half adder
has quantum cost of 4 and the DPG adder has quantum
cost of 6 and the total quantum cost of this circuit is 64.
4. RESULTS & DISCUSSION
We have encountered three different designs for
reversible multipliers in literatures where all of them, for
the sake of simplicity, have implemented their design for a
4-bit multiplier. Therefore, here in this section, we
compare our proposed multiplier with prior counterparts
based on the 4-bit reversible multiplier. In order to have a
reasonable comparison, first, we examine the detailed
implementation of the previous works. Next, compare the
proposed design based on the quantum cost, and the
number of garbage outputs with the previously mentioned
cases as follows:
x3 x2 x1 x0
y3 y2 y1 y0
p03 p02 p01 p00
p13 p12 p11 p10
p23 p22 p21 p20
p33 p32 p31 p30
z7 z6 z5 z4 z3 z2 z1 z0
Partial Product
Generation
Multi-
Operand
Addition
Fig.10 Partial product generator using Peres gates
Fig.9 The operation of the 4×4 parallel multiplier
Fig.11 Fan-out circuit to duplicate the operand bits
Fig.12 Four-operand Addition
CONFERENCE ON “SIGNAL PROCESSING AND REAL TIME OPERATING SYSTEM (SPRTOS)” MARCH 26-27 2011
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A. Reversible 4-bit multiplier of [10]
For the partial product generation phase of their multiplier,
they used 24 gates of 2×2 Toffoli (TOF2), for preparing
the essential fan-outs. Moreover, 16 Fredkin gates are used
so as to generate the partial products. For the
multi-operand addition phase they used three 4-bit binary
adders, where each of them is composed of 4 TSG, plus
and extra TSG for the generation of the most significant bit
of the final product.
By and large, the overall gate consumption of their
reversible multiplier is equal to (24×TOF2) +
(16×Fredkin) + (13×TSG). The overall critical path of
their multiplier consists of two TOF2, a Fredkin gate, and
seven TSG gates. Unfortunately, there is no reference for
how the TSG can be implemented. Moreover, there is
nothing mentioned in [14] about how a TSG can be built
by means of elementary 2×2 reversible/quantum gates. For
the sake of a fair comparison we assume the QC, and GO
of a TSG gate as equal as that of a fulladder. Nevertheless,
we believe that the QC, and GO of a TSG gate are much
more than that of a FA.
B. Reversible 4-bit multiplier of [11]
For the partial product generation phase of their
multiplier, like that of [10], they used 24 gates of TOF2 for
preparing the necessary fan-outs. Moreover, 16 Peres
gates are used in order to generate the partial products.
For the multi-operand addition phase they used 12
MKG gates where a MKG gate is a 4×4 reversible gate.
Therefore, the overall gates used in their reversible
multiplier is (24×TOF2) + (16×Peres) + (12×MKG). The
overall critical path of their multiplier consists of two
TOF2 gates, a Peres gate, and seven MKG gates. As the
case for TSG, there is also no reference for the
implementation of the MKG. Therefore, although we
believe that the QC, Depth, and GO of a TSG gate is much
more than that of a FA, we assume, for the sake of a fair
comparison, the QC, Depth, and GO of a MKG gate the
same as that of a full-adder.
C. Reversible 4-bit multiplier of [12]
This multiplier and that of [11] are somehow the same
except for the multi-operand addition phase which is
implemented in [12] by means of 8 HNG gates along with
four Peres gates. This modification leads to the following
critical path: (2×TOF2) + (2×Peres) + (6×HNG).
D. The proposed reversible 4-bit multiplier
In the proposed design for the partial product generation
phase, like those of [11] and [12], we take advantage of the
Peres gates in order to generate the partial products. For
the multi-operand addition phase as is shown in Fig. 15,
we use 8 full-adders and 4 halfadders. The critical path of
this new design consists of two TOF2 plus a Peres gate for
the partial product generation phase and 5 full-adders plus
a half-adder for the multi-operand addition phase. Table-2
gives the comparative study of partial product generation
of the circuit.
Partial
Product
generation
No
of
gates
N
No of
Garbage
outputs
GO
Quantum
cost
QC
Proposed 20 32 88
TSG [10] 40 32 104
MKG [11] 40 32 88
HNG [12] 40 32 88
Table-3 gives the comparative study of multi-operand
addition of the proposed design with other existing
designs.
Multi-operand
addition
(MOA)
No
of
gates
N
No of
Garbage
outputs
GO
Quantum
cost
QC
Proposed 12 20 62
TSG [10] 13 26 130
MKG [11] 12 24 120
HNG [12] 12 20 64
Table-4 Comparative study of different reversible
multipliers as shown in Table-4.
Reversible
multipliers
No
of
gates
N
No of
Garbage
outputs
GO
Quantum
cost
QC
Proposed 40 50 150
TSG [10] 13 26 130
MKG [11] 52 56 208
HNG [12] 53 58 234
From the above study in our opinion the proposed design
is better when compared to the other existing designs as
the total circuit cost is much less compared to the other
designs.
4. CONCLUSION
Multiplier is a basic arithmetic cell in computer arithmetic
units. Furthermore, reversible implementation of this unit
is necessary for quantum computers. For this purpose,
various designs can be found in the literature. We
proposed in this paper a novel reversible multiplier, no
increase in quantum cost or the number of garbage outputs
with respect to previous counterparts. In proposed design,
partial products were generated using Peres gates. Next,
the final product was obtained using a multi-operand adder
including CSA tree and carry propagate addition,
REFERENCES
TABLE.2 Partial product generation
TABLE.3 Multi-operand addition (MOA)
TABLE.4 Comparative study of different reversible multipliers
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[1] R. Landauer, "Irreversibility and heat generation in the computing
process", IBM J. Res. Develop., Vol. 5, pp. 183–191, July 1961.
[2] C.H. Bennett, “Logical Reversibility of Computation”, IBM Research and Development, pp. 525-532, November 1973.
[3] T. Toffoli, "Reversible computing", MIT, Tech. Rep., 1980.
[4] E. Fredkin and T. Toffoli, “Conservative logic,” Int‟l J. Theoretical
Physics, Vol. 21, pp.219–253, 1982 [5] A. Peres, “Reversible logic and quantum computers”, Physical
Review A, Vol 32, pp. 3266-3276, 1985. [6] J. A.Smolin and D. P.DiVincenzo, “Five Two-Bit Quantum Gates are
Sufficient to Implement the Quantum Fredkin Gate”, Physical
Review A (Atomic, Molecular, and Optical Physics), Vol. 53, No. 4, pp. 2855-2856, April 1996.
[7] D. Maslov, G. W. Dueck and D. M. Miller, “Simplification of Toffoli
Networks via Templates”. Proc. 16th Symposium on Integrated Circuits and Systems Design, pp. 53-58, September 2003.
[8] W. N. N. Hung, X. Song, G. Yang, J. Yang and M. A Perkowski,
“Quantum Logic Synthesis by Symbolic Reachability Analysis”, Proc. 41st annual conference on Design automation DAC,
pp.838-841, January 2004.
[9] D. Maslov, C. Young, D. M. Miller, and G. W. Dueck, “Quantum Circuit Simplification Using Templates”, Proc. Design Automation
and Test in Europe (DATE), Vol 2, pp.1208-1213, March 2005.
[10] H. Thapliyal and M.B. Srinivas, “Novel Reversible Multiplier Architecture Using Reversible TSG Gate”, Proc. IEEE International
Conference on Computer Systems and Applications, pp. 100-103,
March 2006. [11] M. Shams, M. Haghparast and K. Navi, “Novel Reversible
Multiplier Circuit in Nanotechnology”, World Applied Science
Journal Vol. 3, No. 5, pp. 806-810, 2008. [12] M. Haghparast, S. Jafarali Jassbi, K. Navi and O.Hashemipour,
“Design of a Novel Reversible Multiplier Circuit Using HNG Gate
in Nanotechnology”, World Applied ScienceJournal Vol. 3 No. 6, pp. 974-978, 2008.
[13] M.S. Islam et al., “Low cost quantum realization of reversible
multiplier circuit”, Information technology journal, 8 (2009) 208.
VHDL environment for floating point Arithmetic Logic Unit - ALU design and simulation
ABSTRACTVHDL environment for floating point arithmetic and logic unit design using pipelining is introduced; the novelty in the ALU design.Pipeling provides a high performance ALU. Pipelining is used to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point ALU unit. Each module is divided into sub- modules. Two selection bits are combined to select a particular operation. Each module is independent to each other .all modules in the ALU design are realized using VHDL, design functionalities are validated through VHDL simulation .all components and module is successfully run, Synthesisand Simulation in the Xilinx12.1i software.
Keywords: ALU- Arithmetic Logic Unit, Top-Down design, Validation, Floating point, Test-Vector\
I.INTRODUCTION
Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. Floating point representation is able to retain its resolution and accuracy compared to fixed point representation. Numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16. The typical number that can be represented exactly is of the form:×
Significant digits × Baseexponent
S ×Be
IEEE 754 standard for floating point representation in 1985. Based on this standard ,floating point representation for digital system should be platform –independent and data are interchanged freely among different digital systems.
Arithmetic logic unit (ALU) is a digital circuitthat performs arithmetic and logical
operations. The ALU is a fundamental building block of the central processing unit(CPU) of a computer. e inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation.
In many designs the ALU also takes or generates as inputs or outputs a set of condition codes from or to a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-by-zero, etc. Floating Point Unit also performs arithmetic operations between two values, but they do so for numbers in floating point representation. And the ALU with floating point operations is called a FPU.
Top-down approach (is also known as step-wise design) is essentially the breaking down of a system to gain insight into its compositional sub-systems. In a top-down approach an overview of the system is formulated, specifying but not detailing any first-level subsystems. Each subsystem is then refined in yet greater detail, sometimes in many additional subsystem levels, until the entire specification is reduced to base elements. A top-down model is often specified with the assistance of "black boxes", these make it easier to manipulate. However, black boxes may fail to elucidate elementary mechanisms or be detailed enough to realistically validate the model
In order to stimulate a device off board, a series of logical vectors must be applied to the device inputs. These vectors are called test vectors and are mostly used to stimulate the design inputs and check the outputs against the expected values.
An pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput
(the number of instructions that can be executed in a unit of time).
The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)The origin of pipelining is thought to be the IBM Stretch project(1954) .Implementing pipeline requires various phases of floating point operations be separated and be pipelined into sequential stages. We propose VHDL environment for floating point ALU design and simulation. To ease the description, verification, simulation and hardware realization. VHDL is widely adopted standard and has numerous capabilities that are suited for designs of this sort .the use of VHDL for modeling is especially appealing since it provides formal description of the system and allows the use of specific description styles to cover the different abstraction levels(architectural, register , transfer and logic level) employed in design .
II MATERIAL AND METHODS
The main objective of this paper is to describes the implementation of pipelining in design the floating -point ALU using VHDL.. the sub-objective s are to design a 16-bit floating point ALU operating on the IEEE 754 standard rd .floating point representations ,supporting the four basic arithmetic operations; addition, subtraction, multiplication and division .second sub-objective is to model the behavior of the ALU design using VHDL.Specifications for a 16-bit floating-point ALU design.
i. Input A and B and output result are 16-bit binary floating point.
ii. Operands A and B operate as follows A (operation) B=results Operation can be addition (+), subtraction (-), Multiplication (*), division (/)iii. ‘Selection’ a 2-bit input signal that selects
ALU operation and operate as shown in table1.iv. Status a 4-bit output signal work as a flag an
microprocessor.
Table1: select ALU operation.
v. Clock pulse is only provided to the module which is selected using demux.vi. Concurrent processes are used to allow processes to run in parallel hence pipelining
Fig:1 top level view of the ALU design
ALU is separated into smaller modules: addition,subtraction,moltiplication and division,demux and mux.each arithmetic module is further divided into smaller modules .the top level view of fig.1 shows the top level view of the ALU .it consist of four functional arithmetic modules, three demultiplexes and two multiplexers. the demuxs and muxes are used to route input operands and the clock signal to the correct functional modules .they also route outputs and status signals based on the selector pins.
Output status0000 Normal operation0001 Overflow0010 Underflow0100 Result zero1000 Divide by zero
After a module completes its task, outputs and status signals are sent to the muxes where they multiplexes with other outputs from corresponding modules to produce output result selector pins are routed to these muxes such that only the output from currently operating functional module is sent to the output port. Clock is specifically routed rather then tied permanently to each module since only the selected functional modules need clock signals. This provides power savings since the clock is supplied to the required modules only and avoid invalid results at the output since the clock is used as a trigger in every process.
Pipelining floating point addition module:
Addition module has two 16 bit inputs and one16 bit output selection input is used to enable or disable the module this module is further divided into 4 sub modules zero check, align, add_ sub and normalize module.
Fig: 3 pipeline floating point addition
Zero check modules:
This module detects zero operands early in the operation and based on the detection result it has two status signals. This eliminates the need of sub sequent processes to check for the presence of zero operands table 1 summarize the algorithm
Tab:1 setting zero check bit
Align moduleIn this module operations are perform based on status signal from previous stage zero operands are Checked in the align module as well this module introduces implied into the operands shown in table.
Tab:2 setting of implied bit
Add_ sub moduleThis module performs actual addition and subtraction of operands. Firstly operands are checked via the status signals are carried out results are automatically obtained if either of the operand are zero shown in table 3 normalization is needed if no calculation are done here the operation is done based on the science and the relative magnitude of mantissa i.e. summaries in table 4 status signal is set to one is indicate the need of normalization by the next stage
Zero_a2 &zero_b2
Zero_a1 xor zero_b1
Zero_a2 Result
0 0 X Perform add_sub
0 1 1 b stage20 1 0 a stage2
1 X X 0
Tab:3 check for add_sub module
Tab: 4 add_sub operation
I/P a I/P b Zero_a1 Zero_b10 0 1 10 NZ 1 0NZ 0 0 1NZ NZ 0
Zero_a1 xor zero_b1
a_sign Implied bit for a
Implied bit for b
0 X(do’t care)
0 0
1 1 0 11 0 1 0
Operation a_sign xor b_sign
a>b Result Sign
a + b 0 X a+b +ve(-a)+(-b) 0 X a+b -vea+(-b) 1 Yes a-b +vea+(-b) 1 No b-a -ve(-a)+b 1 Yes a-b -ve(-a)+b 1 No b-a +ve
Normalize module
Input is normalize and packed into the IEEE 754 floating point representation if the normalize status signal is set normalization is perform otherwise MSB is dropped .
Pipeline floating point subtraction module:
Subtraction module has two 16-bits inputs and one 16-bit output. Selection input is used to enable/ disable the entity depend on the operation. This module is divided further into four sub-modules: zero-check alignsadd_sub and normalize module. The subtraction algorithm differs only in the add_sub module where the subtraction operator changes the sign of the result. the reaming three modules are similar to those in the addition module.tab5 and tab 6 summarize the operation
Tab: 5 checks for add_sub module
Operation a_sign xor b_sign
a>b Result sign
(-a)-b 1 X a+b -vea-(-b) 1 X a+b +ve(-a)-(-b) 0 Yes a-b -ve(-a)-(-b) 0 No b-a +vea-b 1 Yes a-b +vea-b 1 No b-a -ve
Tab: 6 add_sub operation and sign fixing
Pipelined floating point multiplication module
Multiplication entity has three 16-bit inputs and two 16-bit outputs. Selection input is used to enable/disable the entity. multiplication module is divided into check-zero, check-sign, add-exponent and normalize –and-concatenate all modules, which are executed concurrently .status signal indicates special result cases such as overflow, underflow and result zero, in this project pipelined floating point multiplication is divided in to three stages(fig-4).stage1 checks whether the
operand is zero and report the result accordingly.stage2 determines the product sign, add exponents and multiply fractions.stage3 normalize and concatanitate the product.
Fig 4. Pipeline structure of multiplication module
Check-zero moduleInitially two operands are checked to determine whether they contain a zero .if one of the operand is zero ,the zero_flag is set to 1 .the output results zero. if neither of them is zero then the inputs with IEEE 754 format is unpacked and assigned to the check sign, add exponent and multiply mantissa modules, the mantissa is packed with hidden bit 1.
Add exponent moduleThe module is activated if the zero flag is set .else zero
is passed to the next stage and exp_flag is set to 0,two extra bit are added the exponent indicating overflow and underflow.
Multiply mantissa moduleIn this stage zero_flag is checked first. if the zero_flag is set to 0,then no calculation and normalization is performed. The mant_flag is set to 0 if both the operands are nonzero after the multiplication is done mant_flag is set to 1 to indicate that this operation is executed.
Check sign moduleThis module determines the product sign of two operands .the product is positive, when the two operands have the same sign; otherwise it is negative. The sign bit are compared using XOR circuit. the sign_flag is set to 1.Normalize and concatenate module
This module checks the overflow and underflow occurs if the 9th bit is 12.overeflow occurs if the 8th bit is 1.if exp_flag, sign_flag and mant_flag are set, the normalization is carried out. Otherwise, 16-zero bits are assigned to the result.
Zero_a2 &zero_b2
Zero_a2 xor zero_b2
Zero_a2
b_sign Result sign
0 0 X X Perform add_sub
NA
0 1 1 0 b_stage2 b_sign=10 1 1 1 b_stage2 b_sign=00 1 0 X a_stage2 a_sign1 X X X 0 NA
During the normalization operation, the mantissa MSB is 1, hence no, normalization is needed. the hidden bit is dropped and the reaming bit is packed and assigned to the output port .normalization module set the mantissa MSB to 1.the current mantissa is shifted left until 1 is encountered .foe each shift the exponent is decreased by 1,if the mantissa MSB is 1,normalization is completed and first bit is the implied bit dropped. Theremaining bits are packed and assigned to the output port. The final normalization product with the correct biased exponent is concatenated with product sign.
Pipelined floating point division module
Division entity has three 16-bit inputs and two 16-bit outputs. Selection input is used to enable or disable the entity. Division module is divided into six modules: check zero, align, dividend check sign, subtract exponent, divide mantissa and normalize concatenate modules. Each module is executed concurrently. Status indicates the special cases such as overflow, underflow, and result zero and divides by zero. Fig shows the pipeline structure of the division module.
Fig: 5 pipeline structure of the division module
Check-zero modules:
Initially two operands are checked to determine whether they contain a zero .if one of the operand is zero, the zero_flag is set to 1 .the output results zero. Ifneither of them is zero then the inputs with IEEE 754 format is unpacked and assigned to the check sign, add exponent and multiply mantissa modules, the mantissa is packed with hidden bit 1.
Add exponent module:
The module is activated if the zero flag is set .else zero is passed to the next stage and exp_flag is set to 0,two extra bit are added the exponent indicating overflow and underflow.Multiply mantissa module:
In this stage zero_flag is checked first. if the zero_flag is set to 0,then no calculation and normalization is performed. The mant_flag is set to 0 if both the operands are nonzero after the multiplication is done mant_flag is set to 1 to indicate that this operation is executed.
Check sign module:
This module determines the product sign of two operands .the product is positive, when the two operands have the same sign; otherwise it is negative. the sign bit are compared using XOR circuit. the sign_flag is set to 1.
Align dividend module:
This module compares both mantissas. if mant_a is greater than or equal to the msant_b then the mant_a must be aligned .for every bit right shift of the mant_a mantissa ,the mant_a exponent is then increased by 1.this increase may result in an exponent overflow, in this case an overflow flag is set. Otherwise, the process continues with the parallel operation of exponent subtraction and mantissa division. Align_flag is set to 1.
Subtract exponent module
This module is activated if the zero flag is set. if not ,zero value is passed to the next stage and exp_flag is set to 0.two extra bits are added to the exponent to indicate overflow .here two exponents are subtracted .the bias is added back. after this the exp_flag is set to 1.Divide mantissa module
In this stage ,align flag is checked first. if align flag is 0 then no mantissa division is performed .mant_flag is set to 0.if both operand are not zero, mant_a is divided by mant_b .in division algorithm ,comparison between two mantissa is done by subtracting the two values and checking the output sign.
III .SIMULATION AND DISCUSSION
Design is verified through simulation, which is done in a bottom –up fashion .small modules are simulated in separate test benches before they are integrated andtested as a whole.Align RTL1:
Simulation Result of Align:
RTL of Demux:
Demux wave:
Multiplexer:
Simulation result of Mux:
RTL of division:
RTL division:
Iv COCLUSION
By simulating with various test vectors the proposed approach of pipeline floating point proposed approachOf pipeline floating point ALU design using VHDL is successfully designed, tested and implemented currently, we are conducting further research that consider the further reduction in the hardware complexity in terms of synthesis and fully download the code into Altera FLEXIOK: EPFIOKIOLC, FPGA chip on LC 84 package for hardware realization
Reference:
[IIANSIWEE Std 754-1985, IEEE Standard forBinary Flooring-Point Arithmetic, IEEE, NewYork, 1985.[2]M. Daumas, C. Finot, "Division of Floating PointExpansions with an Application to the
Computation of a Determinant", Journal o/
Universol Compurer Science, vo1.5, no. 6, pp. 323-338, June 1999.[3]AMD Athlon Processor techmcal brief, AdvanceMicro Devices Inc., Publication no. 22054, Rev. D,Dec. 1999.[4]S. Chen, B. Mulgeew, and P. M. Grant, "A
Clustering techmque for digital communicationsChannel equalization using radial basis functionNetworks,'' IEEE Trans. Neural Networks, vol. 4,pp. 570-578, July 1993.[5] Mamu Bin Ibne Reaz, MEEE, Md. Shabiul Islam, MEEE, Mohd. S. Sulaiman, MEEE. ICSE2002 Proc. 2002,penang-Malaysia.
Simulation of division:
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Figure 2: Unipolar NRZ, Polar NRZ,Unipolar RZ
II TERNARY REPRESENTATION
(a) DECIMAL TO TERNARY CONVERSION
S.NO. Decimal Ternary
1. 0 0 0 0 0
2. 1 0 0 0 1
3. 2 0 0 1 -1
4. 3 0 0 1 0
5. 4 0 0 1 1
6. 5 0 1 -1 -1
7. 6 0 1 -1 0
8. 7 0 1 -1 1
9. 8 0 1 0 -1
10. 9 0 1 0 0
11. 10 0 1 0 1
12. 11 0 1 1 -1
13. 12 0 1 1 0
14. 13 0 1 1 1
15. 14 1 -1 -1 -1
16. 15 1 -1 -1 0
17. 16 1 -1 -1 1
18. 17 1 -1 0 -1
19. 18 1 -1 0 0
20. 19 1 -1 0 1
21. 20 1 -1 1 -1
22. 21 1 -1 1 0
23. 22 1 -1 1 1
24. 23 1 0 -1 -1
25. 24 1 0 -1 0
26. 25 1 0 -1 1
27. 26 1 0 0 -1
28. 27 1 0 0 0
29. 28 1 0 0 1
30. 29 1 0 1 -1
31. 30 1 0 1 0
32. 31 1 0 1 1
33. 32 1 1 -1 -1
34. 33 1 1 -1 0
35. 34 1 1 -1 1
36. 35 1 1 0 -1
37. 36 1 1 0 0
38. 37 1 1 0 1
39. 38 1 1 1 -1
40. 39 1 1 1 0
41. 40 1 1 1 1
Table1: Decimal -Ternary
(b) DECIMAL TO TERNARY CONVERSION
The decimal (base 10) numeral system has ten
possible values (0, 1, 2,3,4,5,6,7,8 or 9) for each
place value. In contrast, the ternary (base 3)
numeral system has three possible values, often
represented as -1, 0 or 1, for each place-value.
Like a decimal to Binary Conversion, it takes
following steps:
Algorithm:
Step-1: Write the decimal number
Step-2 : Divide the decimal value by three (3), write
quotient and remainder
Step-3: If the remainder becomes 2 then the value
of quotient becomes increase by one and the
resultant remainder decrease by 3.
Step-4: Repeat step 2 on the quotient; keep on
repeating until the quotient becomes zero
Step-5 Write all remainder digits in the reverse
order (last remainder first) to form the final result.
Example: (25)10 =(X)3
(25)10 =(1 0 -1 1)3
(c) TERNARY TO DECIMAL CONVERSION
(1 0 -1 1)3 =(X)10
1 *33 +0*3
2 + (-1)*3
1 +1*3
0
27+0+(-3)+1 = 25
(1 0 -1 1)3 =(25)10
(d) TERNARY ADDITION
Ternary addition can be performed by the
following rules:
A B C Carry Sum
0 0 0 0
0 1 0 1
0 -1 0 -1
1 0 0 1
1 1 1 -1
1 -1 0 0
-1 0 0 -1
-1 1 0 0
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-1 -1 -1 1
-1 -1 -1 -1 0
1 1 1 1 0
Table 2: Rules of Ternary addition
Example:
(e) TERNARY SUBSTRACTION
if negative numbers are considered, then by
changing all +1’s to -1’s and vice versa, leaving all
zeroes unchanged, gives the negative of the
corresponding number. Hence it follows that
addition and subtraction may be performed with the
same hardware in the balanced ternary system by
sign changes of the addend or subtrahend,
respectively.
(i) A-B =X
(ii) X=A + B’ where in B’ change all +1 to -1
and vice versa
Here there is no need to convert the negative
magnitude such as (-28) can be represented as
(0 0 -1 0 0 -1)
(f) TERNARY MULTIPLICATION
Ternary multiplication can be performing in
following ways similar to Binary multiplication.
Here the some basic rules are applied for
multiplication
S. No. A B A x B
1 0 0 0
2 0 1 0
3 0 -1 0
4 1 0 0
5 1 1 1
6 1 -1 -1
7 -1 0 0
8 -1 1 -1
9 -1 -1 1
Table 3: Rules for Ternary Multiplication
Example:
(i) (37)10 x (4)10= (148)10
(1 1 0 1 ) 3 * (0 0 1 1]) 3 = [X]3
1 1 0 1
X 0 0 1 1
---------------------------------------
1 1 0 1
1 1 0 1 x
0 0 0 0 x x
0 0 0 0 x x x
----------------------------------------
0 1 -1 -1 1 1 1
----------------------------------------
(0 1 -1 -1 1 1 1)3 = (148)10
(ii) (14)10 x (15)10= (210)10
(1 -1 -1 -1 ) 3 * (1 -1 -1 0]) 3 = [X]3
1 -1 -1 -1
X 1 -1 -1 0
---------------------------------
0 0 0 0
-1 1 1 1 x
-1 1 1 1 x x
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1 -1 -1 -1 x x x
---------------------------------
0 1 0 -1 -1 1 0
---------------------------------
(0 1 0 -1 -1 1 0)3 = (210)10
III PRINCIPLES OF TERNARYDATA
PATTERNS ENCODING
The method for transmitting an 8-bit binary data as
a 6-ternary code includes encoder, decoder. For
each 8- bit binary data has a unique 6-ternay
codeword that is optimized for communication
Ternary data Patterns encoded as three signal
patterns[3]
. The three signal levels are represented as
--, 0 and +. The first 8 bit binary pattern 10100011
is converted in (163)10 and this encoded as in 6-
ternary (1 -1 0 0 0
1)3.
This data patterns is encoded in signal patterns (+ --
0 0 0 +)
Figure3: Binary Data Communication
Figure 4:Ternary Data Communication
The logic circuitry of this method is optimized to
accomplish the translation using a small number of
combinational logic gates. Implement of Ternary
communication increase the speed and performance
over the 8 bit data word communication and also
decrease the size of encoder.
IV PRINCIPLES OF TERNARY DATA
PATTERNS DECODING
The principle of decoding system is very simple and
reverse process of encoding system. Decoding
system receive the 6 ternary pattern. And decoder
circuit converts into the 8-bit binary pattern which
format is understandable by receiver.
V ADVANTAGES OF TERNARY CODES
The Concept of 6-Ternary data communication
between two devices make the system high speed
and high performance and also reduce the size of
the overall circuitry system. This concept relates
generally to electric signal and data processing[5]
.
The encoder converts the 8-bit binary data word
into a 6-ternary data word and decoder also converts
the 6-ternaty data word into a 8 bit binary data
word. Ternary data transmission can be use in a
high speed network. Ternary data transmission
maintains the DC balance in transmission. Binary
data word to ternary conversion has beneficial for
placement of data on an electromagnetic channel.
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Ternary data communication increase the data
carrying can be used to increase the speed of data
transmission. In future, this can be increase the data
capacity in storage media [8]
.
VI CONCLUSION
In this Paper we have discussed about the Ternary
logic in digital communication for providing high
speed & performance. In this Scheme, we have
discussed about the encoding of binary data word to
ternary data word for improving the data word
transmission time & correspondingly high speed
communication as compared to the Binary logic that
is generally used in digital communication. For the
implementation of this scheme, we have discussed
some major algorithms and various conversion
methods that are very useful for understanding this
logic. In this paper, we also tried to light on the
principle of ternary data pattern encoding which is
responsible for ternary data communication.
VII REFERENCES
[1] Glass, A., Ali, B. and Bastaki, E. “Design and
modeling of H-Ternary line encoder for digital data
transmission”. International Conference on Info-
Tech & Info-Net, Beijing, China, 2001, pp 503-
507.
[2] A. Mahadevan, Digital Transceiver using H
Ternary Line Coding Technique, Proceedings of the
World Congress on Engineering 2007 Vol I
[3] A. Srivastava and K. Venkatapathy, “Design and
Implementation of a Low Power Ternary Full
Adder”1996 OPA (Overseas Publishers
Association) Amsterdam B.V. Published in The
Netherlands under license by Gordon and Breach
Science Publishers SA
Printed in Malaysia
[4] Abdullatif Glass and Bahman Ali, Nidhal
Abdulaziz, “H-Ternary Line Decoder for Digital
Data Transmission:
Circuit Design and Modelling”,
[5] Bylanski, P. and Ingram, D., “Digital
transmission systems,” Peter Peregrinus, 1976, pp.
216-246.
[6] Lathi, P., “Modern digital and analog
communication systems (3rd Ed),” Oxford
University Press, 1998, pp.294-353.
[7] Takasaki, Y., “Digital transmission design and
jitter analysis,” Artech House, 1991, pp.35-60.
[8] Sandeep Patel, Howard W. Johnson, “Methods
and apparatus for implementing a type 8B6T
Encoder and decoder “, 1996, patent no 5,525,983.
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Abstract - This Paper introduces the working principle of space vector pulse width modulation (SVPWM), and presents a new circuit realization of SVPWM generator based on a flexible, high computation speed and cost effective field programmable gate array (FPGA) embedded technique. Controlling of the machines using the vector control techniques is becoming more popular nowadays. The need for extensive computations has no more become an objection to the vector control implementation. This is due to the wide availability of high speed digital processors. The method of decoupling the variables and controlling them independently is known as vector control. To relieve the controller from the time consuming computational task of PWM signal generation, a new method of Space Vector PWM signal generation is implemented in FPGA using Hardware Description Language VHDL. The Space Vector PWM pulses are first designed in MATLAB/SIMULNK environment and relevant coding are written to generate the pulses and then by using software conversion tool the M files are converted into VHDL coding. Thus the triggering pulses are given to the inverter circuit and hence the switching pattern generated will reduce the harmonic content and switching losses. Keywords : FPGA- Field Programmable Gate Array, SVM, Space Vector PWM, VHDL, Induction motor drive
1 Introduction The Pulse Width Modulation (PWM) Technique called “Vector Modulation”, which is based on space vector theory, is the most important development in the last few years [1]. Although, several of PWM methods have been created in the past, the vector modulation technique appears to be the best alternative. FPGA’s development reached a level of maturity that made them the good choice of
implementation in many fields [2]. FPGA based embedded implement of SVPWM can make the computing power of processor and the logical processing power of hardware circuit combined, thus the processing efficiency of CPU and the logical units utilization can be improved . Figure 1 shows a SVPWM control system based on FPGA- embedded technique – Figure 1: SVPWM control system based on FPGA-
embedded technique Recent applications of FPGA’s in industrial electronics include mobile- robot path planning and intelligent transportation [3], current control applied to power converters, real-time hardware in the loop testing for control design, Controller implementation, separating and recovering independent source signals, and neural computation. Since the concept of multilevel PWM converter was introduced, various modulation strategies have been developed and studied in detail, such as multilevel sinusoidal PWM, multilevel selective harmonic elimination and space vector modulation. Among these strategies, the space vector PWM (SVPWM) [4]stands out because it offers significant flexibility to optimize switching waveforms and is well suited for digital implementation. Complexity and computational cost of traditional SVPWM techniques increases with the number of levels of the converter, and most of all use trigonometric functions or pre-computed tables. A symmetrical space vector modulation PWM pattern is proposed
“Embedded Implementation of Space Vector PWM using FPGA”
Ashish Gupta
Assistant Professor Department of Electronics Engineering,
in this paper, it shows the advantage of lower THD without increasing the switching losses. Thus this paper demonstrates that a more efficient and faster solution is the use of Field Programmable Gate Array (FPGA’s), it investigates how to generate a variable PWM waveform based on Xilinx FPGA [5].The rest of the paper is organized as follows. Section II introduces the principle of symmetrical space vector PWM method. Section III shows details on FPGA. Section IV shows the m-file coding/Simulink blocks required to generate Space Vector Pulses. Section V explains the experimental results and Section VI is the conclusion
2. Principle of Space Vector PWM In vector coordinates, the combinations of three-phase inverter output voltages form eight space vectors shown in Figure. 2 There are six nonzero space vectors forming an origin centered hexagon, and two zero space vectors (V0-V7) located at the origin. The hexagon is the maximum boundary of the space vector, and the circle is the maximum trajectory of the regular sinusoidal outputs in linear modulation. This figure also explains the PWM output patterns in the six regions (denoted as sector I–VI) separately. In accordance with three-phase to two-phase transformation, the three-phase inputs (Va, Vb, Vc) are transformed into (Vα, Vβ) as the reference vector. Figure 2: Basic Eight Switching Vector and Vector
Representing of Sector 1. As shown in Figure. 3, there are eight possible combinations of on and off patterns for the three upper power switches. The on and off states of the lower power devices are opposite to the upper one and so are easily determined once the states of the upper power transistors are determined. According
to above equations, the eight switching vectors, output line to neutral voltage (phase voltage), and output line-to-line voltages in terms of DC-link Vdc, are given in Table.1 shows the eight inverter voltage vectors (V0 to V7)
Figure 3: Circuit model of PWM inverter with center-taped grounded DC bus.
Table-1 Details of different phase and line
voltages for the eight states.
3. Field Programmable Gate Array
A Field-Programmable Gate Array or FPGA is a silicon chip containing an array of configurable logic blocks (CLBs). Unlike an Application Specific Integrated Circuit (ASIC) which can perform a single specific function for the lifetime of the chip an FPGA can be reprogrammed to perform different function in a matter of microseconds. The design used Xilinx development tools, and is realized in a single FPGA chip with no external memory. The benefits of this design are as follows The whole system is implemented in only a
single chip consequently the circuit is very compact.
Systems of FPGA chip are more reliable because they do not need any control software
Faster design and verification time, design change without penalty.
In this paper programming FPGA using Hardware Description Languages and coding are used to generate the Space Vector Modulation for the inverter circuit. The point to be remember here is that instead of writing the direct VHDL coding firstly the M-File coding is written to generate the SVPWM pulses and then after by using he software converter VHDL coding is generated. Hence the work requires less time and fast operation. The MATLAB/SIMULNK environment is familiar to large number of software programmers and since m-file coding is very much common to most of the programmers it becomes easier to work in this software. A very attractive high-level design/ simulation tool is provided by FPGA and is called XILINX. It is a very flexible design tool, which allows Testing of a high-level structural description of the design and makes possible quick changes and corrections. The circuit description structure is very similar to the way the design could be implemented later. Therefore mapping tool allowing conversion of such a structure into VHDL code would save the designer’s time, which otherwise has to be spent in rewriting the same structure in VHDL and probably making mistakes that will need debugging.
4. Simulation Steps:
(1) Initialize system parameters in MATLAB/ SIMULNK .
(2) Perform M-File coding to (i) Determine sector. (ii) Determine time duration T1, T2, T0. (iii) Determine the switching time (Ta,Tb
and Tc) of each transistor (S1 to S6). (iv) Generate the inverter output voltages
(VAB, VBC, VCA). (v) Generate VHDL Codings through
software convertion tool. (vi) Burn the program in the FPGA kit.
(3) View the SVPWM waveform by XILINX.
4.1 Simulink Model to generate Space Vector PWM
Figure 4.1: Simulink Model for Overall System
Figure 4.2: Subsystem Simulink Model for
“Space Vector PWM Generator”
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Figure 4.3: Subsystem Simulink Model for “Making Switching Time”
5. Results and Discussions
The control scheme is simple in architecture and thus facilitates the realization of the developed SVPWM controller using FPGA based circuit design approach. The designed SVPWM control IC has been realized using single FPGA.The simulation results of internal module and the final output of Space Vector PWM switching pattern has been achieved with a fundamental frequency of 50 Hz. Such a wide frequency control with very high frequency-switching is only possible by utilizing the state-of-art VLSI digital circuit design approach. From the result the switching pattern generated will reduce the harmonic content and switching losses. A comparisons between spwm and svpwm by varying modulation index is shown in the below mentioned table 2 and which evidently shows the greater advantage of controlling the drive by SVPWM technique. Figure 5 shows the Locus comparison of maximum linear control voltage in Sine PWM and SVPWM. Figure 6, 7 and 8 represents the axis converter, Delay time, Output of each inverter respectively. Figure 9, 10 shows the simulation results of Van, Vab, Vac and Simulation results of pulse patterns
Table 2: Comparisons between SPWM and SVPWM by varying modulation index.
Figure 5: Locus comparison of maximum linear control voltage in Sine PWM and SVPWM.
Fig 6: Three to Two axis converter. (Va, Vb, Vc) are transformed into (Vα, Vβ)
Parameter used : Fundamental frequency :50 Hz, Switching frequency:10 KHz , DC Voltage : 600 volts
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Fig 7: Delay time
Fig 8: Output of each inverter
Fig 9: Simulation results of Van, Vab and Vac
Fig 10: Simulation results of pulse patterns
6. Conclusion In this paper, a theoretical study concerning the SVPWM control strategy on the voltage inverter based on FPGA is presented. This aims on one hand to prove the effectiveness of the SVPWM in the contribution in the switching power losses reduction. SVPWM is among the best solution to achieve good voltage transfer and reduced harmonic distortion in the output of an inverter. On the other hand since Field programmable gate array (FPGA) have better advantages compared to microprocessor and DSP control, this modulation technique is implemented in an FPGA by initially generating m-file through Matlab-Simulink environment. The FPGA coding makes it easier in designing the vector modulation pattern generator using field programmable Array. Moreover the MATLAB/ SIMULNK environment is familiar to large number of software programmers and since m-file coding is very much common to most of the programmers it becomes easier for individuals to work in this software. The switching pattern generated will reduce the harmonic content, provides efficient as well as flexible control and reduces the total size of the system. This SVPWM IC can be used for high performance ac drives and power conditioning equipment as a modulator.
References [1] Ying-yu Tzou; Hau-Jean Hsu; Tien-Sung Kuo. Industrial Electronics, Control, and Instrumentation, 1996., Proceedings of the 1996 IEEE IECON 22nd International Conference. “FPGA based SVPWM control IC for 3-phase PWM inverters”. Volume 1, Issue, 5-10 Aug 1996 Pages(s):138-143. [2] J.J. Rodriguez-Andina, M.J. Moure, and M.D. Valdes, “Features, design tools, and application domains of FPGAs”, IEEE Trans. Ind. Electron., vol.54, no.4, pp.1810 – 1823, Aug. 2007. [3] K. Sridharan and T. Priya, “The design of a hardware accelerator for realtime complete visibility graph construction and efficient FPGA implementation,” IEEE Trans. Ind. Electron., vol.52, no.4, pp. 1185 – 1187, Aug. 2005.
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[4] L. Franquelo, M. Prats, R. Portillo, J. Galvan, M. Perales, J. Carrasco, E. Diez, and j. Jimenez, “Three-dimensional space-vector modulation algorithm for four-leg multilevel converters using abc coordinates”, IEEE Trans. Ind. Electron., vol. 53, no.2, pp. 459-466, Apr. 2006. [5]Xilinx Inc.,”Foundation Series ISE 3.11 User Guide’”2000.
