Vls i Curriculum Syl Lab Us 10

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UNIVERSITY OF CALICUTAbstract

Faculty of Engineering – Sce!e " Syllabus of #$Tec Course in VLSI %esign –a&&ro'e( – I!&le!ente( – )it effect fro! te aca(e!ic year *+,, on)ar(s – Or(ersissue($

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -.eneral an( Aca(e!ic /ranc – IV 0E1 Section

No$.A$IV2E,23**42*+,,516 %ate( Calicut Uni'ersity 7$O$ +3$+8$*+,*$- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Rea(9: ,$ U$O$No$.A$IV2E,23**42*+,, (ate( *8$+,$*+,*$

*$ #inutes of te !eeting of /oar( of Stu(ies in Engineering 57$.6 el( on;+$+;$*+,* 5Ite!$No$,6

;$ Or(ers of Vice:Cancellor in te file of e'en No$ (ate( ,<$+=$*+,*$=$ Letter fro! te %ean> Faculty of Engineering (ate( *;$+=$*+,*$

8$ Or(ers of Vice:Cancellor in te file of e'en No$ (ate( +;$+8$*+,*$

O R D E R

As &er &a&er rea( as 5,6 abo'e> an e?&ert co!!ittee )as constitute( )it te

follo)ing !e!bers for te &re&aration of te sce!e " syllabus for te #$Tec course in

VLSI %esign$

a6 %r$Reena$7 5Co:or(inator6> #e!ber> /oar( of Stu(ies in Engineering 57.6

7rofessor in Electronics an( Co!!unication Engineering>%e&t$of$Infor!ation

Tecnology> .o't$Engineering College>Sree@risna&ura!> 7ala@@a( – 4<3 4;;$

b6 7rof$#artin$$#> Scientist2Engineer – E> %OEACC Centre> Calicut> 7$O NIT Ca!&us>

oBi@o(e – 4<; 4+,$

c6 7rof$$S$Lal!oan> Scientist2Engineer – %> %OEACC Centre> Calicut> 7$O$ NIT Ca!:

&us>

oBi@o(e – 4<; 4+,$

Vi(e &a&er rea( as *n( abo'e> te !eeting of /oar( of Stu(ies in Engineering

57$.6 el( on ;+$+;$*+,*> 'i(e ite!$No$ , unani!ously resol'e( to a&&ro'e te Sce!e

" Syllabus of te #$Tec course in VLSI %esign &re&are( by te Co!!ittee$

Vi(e &a&er rea( as ;r( abo'e> te Vice:Cancellor a( or(ere( to see@ te

o&inion of te %ean> Faculty of Engineering regar(ing te a&&ro'al of te !inutes of te

!eeting of te /oar( of Stu(ies in Engineering 57.6 el( on ;+$+;$*+,*Te %ean> Faculty of Engineering 'i(e &a&er rea( as = t abo'e> reco!!en(e( for

te a&&ro'al of te !inutes of te !eeting of te /oar( of Stu(ies in Engineering 57.6

el( on ;+$+;$*+,*$

Cont($$*



:*:

Consi(ering te urgency of te !atter> te Vice:Cancellor as accor(e( sanction

to i!&le!ent te Sce!e " Syllabus of te #$Tec Course in VLSI %esign> subect to

ratification by te Aca(e!ic Council> 'i(e &a&er rea( as 8 t abo'e$

Sanction as terefore been accor(e( for i!&le!enting te Sce!e " Syllabus of

te #$Tec course in VLSI %esign )it effect fro! *+,, a(!ission on)ar(s$

Or(ers are issue( accor(ingly$

5The Syllabus is available in the University website)

S(2: %E7UTY RE.ISTRAR 5.A$IV6 For Registrar$

To

Te 7rinci&als of all affiliate( Engineering Colleges offering #$Tec Course$Co&y to 9: 7$S to V$C27A$ to 7VC2 7$A$ to Registrar2 7$A to C$E2EnDuiry2 E?$Sn2E.Sn2%R>#$Tec2 #$Tec$ Tabulation Section2%ean> Faculty of Engineering2 Cair!an>/OS in Engg 57.6"5U.6 System Administrator (with a request to upload in theuniversity website)2 SF2FC

For)ar(e(2/y Or(er

S(2:

SECTION OFFICER

*



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UN!ERS"# O$ %A&%U"

'"eh DE*REE %OURSE

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!&S DES*N

%urriulum+ Sheme o, E-aminations and Syllabi

(.ith e,,et ,rom /011 admissions)



Sheme o, '"eh ro2ramme in !&S DES*N

(.ith E,,et ,rom the Aademi #ear /011 onwards)

$RS" SE'ES"ER

SlNo

%ourse %ode Name o, the Sub3et 4ours 5 .ee6

L T 7

n t e r n a l

S e m E n d

" o t a l

S e m 7 E

n d E - a m D u r a t i o n

% r e d i t s

,$ VL ,, ,+, C#OS VLSI %esign ; , + ,++ ,++ *++ ; =

*$ VL ,, ,+* A('ance( %igital Syste! %esign ; , + ,++ ,++ *++ ; =

;$ VL ,, ,+;Co!&uter Ai(e( %esign of VLSI

Circuits; , + ,++ ,++ *++ ; =

=$ VL ,, ,+= A('ance( Engineering #ate!atics ; , + ,++ ,++ *++ ; =

8$ VL ,, ,+8 Electi'e , ; , + ,++ ,++ *++ ; =

4$ VL ,, ,+4 576 Se!inar + + * ,++ + ,++ : *

<$ VL ,, ,+< 576Co!&uter Ai(e( %esign of VLSICircuits : Laboratory

+ + * ,++ + ,++ : *

"otal ,8 8 = <++ 8++ ,*++ *=

Eletive 1 : :

,$ VL ,, ,+8A Electronic Syste! %esign

*$ VL ,, ,+8/ %igital Integrate( Circuit %esign

;$ VL ,, ,+8C %esigning )it #icrocontrollers

& 8 &eture+ "7 "utorial+ 8 ratial

=




SE%OND SE'ES"ER

Sl

No%ourse %ode Name o, the Sub3et 4ours 5 .ee6

n t e r n a l

E n d 7 S e m

" o t a l

E n d 7 S e m E - a m

D

u r a t i o n %

r e d i t s

L T 7

,$ VL ,, *+, SOC %esign an( Verification ; , + ,++ ,++ *++ ; =

*$ VL ,, *+* Analog VLSI %esign ; , + ,++ ,++ *++ ; =

;$ VL ,, *+;Testing " Verification of VLSICircuits

; , + ,++ ,++ *++ ; =

=$ VL ,, *+= Electi'e : II ; , + ,++ ,++ *++ ; =

8$ VL ,, *+8 Electi'e : III ; , + ,++ ,++ *++ ; =

4$ VL ,, *+4 576 Se!inar + + * ,++ + ,++ : *

<$ VL ,, *+< 576Testing " Verification of VLSICircuits – Laboratory

+ + * ,++ + ,++ : *

"otal ,8 8 = <++ 8++ ,*++ *=

Eletive : :

,$ VL ,, *+=A Lo) 7o)er VLSI %esign

*$ VL ,, *+=/Syntesis an( O&ti!iBation of %igitalCircuits

;$ VL ,, *+=C%esign of %igital Signal 7rocessingSyste!s

Eletive

,$ VL ,, *+8A ig S&ee( %igital %esign

*$ VL ,, *+8/ #ulti!e(ia Co!&ression TecniDues

;$ VL ,, *+8C %esign for Testability

& 8 &eture+ "7 "utorial+ 8 ratial

8




"4RD SE'ES"ER

Sl

No%ourse %ode Name o, the Sub3et 4ours 5 .ee6 'ar6s

L T 7

n t e r n a l

S e m E n d

" o t a l

E

n d 7 S e m E - a m D u r a t i o n

% r e d i t s

,$ VL ,, ;+, Eletive ! ; , + ,++ ,++ *++ ; =

*$ VL ,, ;+* Eletive ! ; , + ,++ ,++ *++ ; =

;$ VL ,, ;+; 576 In(ustrial Training + + + 8+ : 8+ : ,

=$ VL ,, ;+= 576 #aster Researc 7roect 7ase I + + ** . u i ( e

E C F

,8+ ,8+

: ;++ : 4

"O"A& 4 * ** 88+ *++ <8+ ,8Eletive ! : :

,$ VL ,, ;+,A #i?e( Signal Syste! %esign

*$ VL ,, ;+,/ F7.A Arcitecture " A&&lications

,$ VL ,, ;+,C Gireless Co!!unication Syste!s

Eletive !

,$ VL ,, ;+*A Syste! Verilog

,$ VL ,, ;+*/ ar()are:Soft)are Co:(esign

*$ VL ,, ;+*C VLSI Signal 7rocessing

9E% 8 Evaluation ommittee+ & 8 &eture+ "7 "utorial+ 8 ratial

4




$OUR"4 SE'ES"ER

SlNo

%ourse %odeName o, theSub3et

4ours 5 .ee6nternal

EvaluationESE9

" o t a l

% r e d i t s

L T 7 . u i ( e

E ' a l u a t i o n

C o ! ! i t t e

e

E ? t e r n

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V i ' a V o c e

,$ VL ,, =+,576#aster Researc7roect 7ase II

+ + ;+ ,8+ ,8+ ,8+ ,8+ 4++ ,*

Total : : ;+ ,8+ ,8+ ,8+ ,8+ 4++ ,*

Te stu(ent as to un(erta@e te (e&art!ental )or@ assigne( byO%

' a r 6 s

% r e d i t s

*rand "otal :;<0 ;<

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$RS" SE'ES"ER

!& 11 101 %'OS !&S DES*N

#o(ules ours

#o(ule ,

N"RODU%"ON "O %'OS %R%U"S

#OS Transistors> #OS Transistor S)itces> C#OS Logic> Circuit an( Syste!Re&resentations> #OS Transistor Teory : Intro(uction #OS %e'ice %esignEDuations> Te Co!&le!entary C#OS In'erter:%C Caracteristics> Static Loa(#OS In'erters> Te %ifferential In'erter> Te Trans!ission .ate> Te Tri StateIn'erter> /i&olar %e'ices> Resistance Esti!ation Ca&acitance Esti!ation>In(uctance> S)itcing Caracteristics C#OS:.ate Transistor SiBing> 7o)er%issi&ation> SiBing Routing Con(uctors> Carge Saring> %esign #argining>Reliability$

,+

#o(ule *

%'OS %R%U" AND &O*% DES*NC#OS Logic .ate %esign> /asic 7ysical %esign of Si!&le .ate> C#OS LogicStructures> Cloc@ing Strategies> I2O Structures> Lo) 7o)er %esign

3

#o(ule ;

S#S"E'S DES*N AND DES*N 'E"4OD

%esign Strategies C#OS Ci& %esign O&tions> %esign #eto(s> %esign Ca&tureTools> %esign Verification Tools> %esign Econo!ics> %ata Seets> C#OS Testing :#anufacturing Test 7rinci&les> %esign Strategies for Test> Ci& Le'el TestTecniDues> Syste! Le'el Test TecniDues> Layout %esign for I!&ro'e(Testability$

,*

#o(ule =

%'OS SU= S#S"E' DES*N%ata 7at O&erations:A((ition2Subtraction> 7arity .enerators> Co!&arators>Hero2One %etectors> /inary Counters> ALUs> #ulti&lication> Sifters> #e!oryEle!ents> Control:FS#> Control Logic I!&le!entation$

"utorial ,;

Total ours 8*

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3



1 Neil$ $E$ Geste an( $ Esragian> J7rinci&les of C#OS VLSI %esignK$ * n(

E(ition$ A((ison:Gesley > *+++$

/ %ouglas a$ 7uc@nell an( $ Esragian$> J/asic VLSI %esignK ;r( E(ition$ 7I>

*+++$

: R$ acob /a@er> arry G$ LI$> " %a'i( $ /oyce$> JC#OS Circuit %esignK> ; r(

In(ian re&rint> 7I> *+++$

RE$EREN%E =OO?S@

,$ Se!icon(uctor %e'ices #o(elling an( Tecnology Nan(ita %as .u&ta >A!ita'a %as .u&taM 7rentice all In(ia

*$ O&eration an( #o(eling of Te #OS transistor 9 Yannis Tsi'i(is *2e O?for( Uni:'ersity 7ress

;$ ang " Leblebigi JC#OS %igital IC Circuit Analysis " %esignK: #c.ra) ill>*++;

=$ Geste an( Esragian> J7rinci&les of C#OS VLSI (esignK A((ison:Gesley> *++*

nternal %ontinuous Assessment@ 100 mar6s

Internal continuous assess!ent is in te for! of &erio(ical tests> assign!ents> se!inars ora co!bination of all )ice'er suits best$ Tere )ill be a !ini!u! of t)o tests &er

subect$ Te assess!ent (etails are to be announce( to te stu(ents> rigt at te beginningof te se!ester by te teacer$

End Semester E-amination@ 100 mar6s

uestion attern

Ans)er any 8 Duestions by coosing at least one Duestion fro! eac !o(ule$

'odule 1 'odule / 'odule : 'odule B

uestion , 9 *+ !ar@s

uestion * 9 *+ !ar@s

uestion ; 9 *+ !ar@s

uestion = 9 *+ !ar@s

uestion 8 9 *+ !ar@s


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!& 11 10/ AD!AN%ED D*"A& S#S"E' DES*N

#o(ules ours

#o(ule ,

ntrodution to Di2ital Systems Desi2n

Intro(uction : %esign of Co!binational Syste!s – #ulti&le out&ut co!bination

circuit (esign – #cClus@ey !eto(: Intro(uction to 7L%s 7 7RO# base( (esign :

7AL : Arit!etic 7AL (e'ices – Stu(y base( on 7AL**V,+> C7L%s 5#A;+++A

C7L%6$

,+

#o(ule *

Sequential %iruit Desi2n – #ealy #acine> #oore #acine> State (iagra!s>

State table !ini!iBation> Inco!&letely s&ecifie( seDuential !acine>

Asyncronous seDuential circuit (esign 5fun(a!ental !o(e6

3

#o(ule ;

Asynhronous sequential iruits@ %eri'ation of e?citation table> Racecon(itions an( cycles> Static an( (yna!ic aBar(s> #eto(s for a'oi(ing races an(aBar(s> essential aBar(s> %esigning )it S# carts – State !acine carts>%eri'ation of S# carts> an( RealiBation of S# carts$

,*

#o(ule =

!4D& /asics : Intro(uction to %L : /ea'ioral !o(eling : %ata flo) !o(eling

: Structural !o(eling : /asic language ele!ents – Entity:Arcitecture:Configurations : Sub&rogra!s an( o&erator o'erloa(ing: 7ac@ages an( libraries :

V%L a('ance( features : #o(el si!ulation : ar()are !o(eling e?a!&les$

Syntesis$ Ti!ing Si!ulation$ V%L Syntesis Issues$

"utorial ,;

Total ours 8*

,+



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,$ JFun(a!entals of %igital %esignK> Carles $Rot>r$> 7GS 7ub$Co$>,3$

*$ J%igital %esign Fun(a!entalsK> ennet /ree(ing> 7rentice all> Engle)oo( Cliffs> Ne)

;$ ersey$,3$=$ S!it> PA&&lication S&ecific Integrate( CircuitsP> A((ison:Gesley> ,<

8$ $ /as@er> PA V%L 7ri!erP> A((ison:Geseley Long!an Singa&ore 7te Lt($ ,*

RE$EREN%E =OO?S@

,$ e'in S@aill> PV%L for 7rgra!!able LogicP> A((ison :Gesley> ,4

*$ H$ Na'abi> PV%L Analysis an( #o(eling of %igital Syste!sP> #c.RAG:ill> ,3

;$ Su(a@ar Yala!ancili> JIntro(uctory V%L Fro! Si!ulation to SyntesisK> 7rentice all

In a((ition> !anufacturers %e'ice (ata seets an( a&&lication notes are to be referre( to get

&ractical an( a&&lication oriente( infor!ation$


Internal continuous assess!ent is in te for! of &erio(ical tests> assign!ents> se!inars or aco!bination of all )ice'er suits best$ Tere )ill be a !ini!u! of t)o tests &er subect$ Te

assess!ent (etails are to be announce( to te stu(ents> rigt at te beginning of te se!ester byte teacer$


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!& 11 10: %O'U"ER ADED DES*N O$ !&S %R%U"S

#o(ules ours

#o(ule ,

Various CA% Tools for front en( an( /ac@ en( (esign> Sce!atic e(itors> Layoute(itors> 7lace an( Route tools$ Intro(uction to VLSI #eto(ologies : VLSI7ysical %esign Auto!ation : %esign an( Fabrication of VLSI %e'ices :Fabriction &rocess

,+

#o(ule *

Intro(uction to %esign Tools9 Intro(uction " Fa!iliarity )it %esign Tools fro!'arious 'en(ors e$g$ Syno&sis> #entor Tools etc$

Verilog /asics : #o(eling Le'els : %ata Ty&es : #o(ules an( 7orts : Instances :/asic Language Conce&ts : %ataflo) !o(eling : /ea'ioral !o(eling

#o(eling an( Si!ulation of syste!s2subsyste!s using Verilog %L$Ty&ical case stu(ies$

,*

#o(ule ;

Layout Algorit!s Circuit &artitioning> &lace!ent> an( routing algorit!sM %esign

rule 'erificationM Circuit Co!&actionM Circuit e?traction an( &ost:layout

si!ulation

3

#o(ule =

Auto!atic Test 7rogra! .enerationM Co!binational testing %:Algorit! an(7O%E# algorit!M Scan:base( testing of seDuential circuitsM Testability !easures

for circuits$

"utorial ,;

Total ours 8*

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,$ N$A$ Ser)ani> P Algorit!s for VLSI 7ysical %esign Auto!ation P> ,$

*$ S$$ .ereB> P Algorit!s for VLSI %esign Auto!ation P> ,3$=$ $ /as@er> PA V%L 7ri!erP>

A((ison:Geseley Long!an Singa&ore 7te Lt($ ,*

;$ %recsler> R$> Evolutionary Algorithms for VLSI CAD> lu)er Aca(e!ic 7ublisers>/oston> ,3$

=$ Verilog %L by Sa!ir 7alnit@ar

,*



RE$EREN%E =OO?S@

,$ VERILO. %L SYNTESIS9 A 7RACTICAL 7RI#ER by /as@ar

*$ ill> %$> %$ Sugar(> $ Fisburn an( $ eutBer> Algorithms and Tehni!ues for VLSI Layout Synthesis> lu)er Aca(e!ic 7ublisers> /oston> ,3$


Internal continuous assess!ent is in te for! of &erio(ical tests> assign!ents> se!inars or aco!bination of all )ice'er suits best$ Tere )ill be a !ini!u! of t)o tests &er subect$ Teassess!ent (etails are to be announce( to te stu(ents> rigt at te beginning of te se!ester byte teacer$


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!& 11 10B AD!AN%ED EN*NEERN* 'A"4E'A"%S

5Co!!on )it E%T ,, ,+=6

#o(ules ours

'odule1@ "rans,orms and Di2ital Representations

Signals an( Syste!s> Linear Ti!e In'ariant Syste!s> Te La&lace Transfor!>

7ro&erties> Te Fourier Transfor!> 7ro&erties of Fourier Transfor!> Fourier

Transfor! of SeDuence5Fourier Series6 an( its &ro&erties> Fourier Analysis for

Continuous an( %iscrete Ti!e Signals$ H Transfor! an( its &ro&erties$

%igital Arit!etic9 Fi?e( an( Floating &oint re&resentation> IEEE <8= Floating &oint

stan(ar(s> Floating &oint arit!etic o&erations

'odule / @ &inear Al2ebra

Linear EDuations an( #atri? Algebra9 Fiel(sM syste! of linear eDuations> an( its

solution setsM ele!entary ro) o&erations an( ecelon for!sM !atri? o&erationsM

in'ertible !atrices> LU:factoriBation

Vector S&aces9 Vector s&acesM subs&acesM bases M (i!ensionM coor(inates

,+

'odule:@ 'ultidimensional "rans,orms

Intro(uction> *% ortogonal " unitary transfor!s> 7ro&erties of unitary transfor!s>

,% an( *%: %FT> %CT> Gals> a(a!ar( Transfor!> aar Transfor!> Slant

Transfor!> LT> SV% Transfor!

,+

'odule B@ .avelet "rans,orm

Ga'elet Transfor!9 Continuous9 intro(uction> C:T )a'elets> &ro&erties> in'erse CGT$%iscrete )a'elet transfor! an( ortogonal )a'elet (eco!&osition using arrGa'elets$

,+

"utorial ,;Total ours 8*

,=



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,$ CLinear Algebra an( its A&&lications> %a'i( C$ Lay> ;r( e(ition> 7earson E(ucation

5Asia6 7te$ Lt(> *++8

*$ %igital Arit!etic> #ilos %$ Ercego'ac> To!as Lang> Else'ier;$ JFun(a!entals of %igital I!age 7rocessingK> Anil $ ain> 7I> Ne) %eli

=$ %igital Signal 7rocessing9 a &ractical a&&roac> E!!anuel C Ifeacor> G /arrie er'is>7earson E(ucation 5Singa&ore6 7te$ Lt($> %eli

8$ Ga'elet transfor!s:Intro(uction to teory an( a&&lications> Ragu'eer #$Rao an( AitS$ /a&ar(i@ar> 7erson E(ucation

RE$EREN%E =OO?S@

,$ Scau!Qs Outline for A('ance( Engineering #ate!atics for Engineers an( Scientists>

#urray R$ S&iegel> #. /oo@ Co$> Ne) Yor@*$ A('ance( Engineering #ate!atics> Er)in reysBing> on Giley " Sons> NEG

YOR;$ A('ance( Engineering #ate!atics> AIN> R >IYEN.AR> S R > Narosa> NEG

YOR=$ Signal &rocessing )it fractals9 a Ga'elet : base( a&&roac> Gornell> .regory> 7>

7TR> NEG ERSEY8$ Ga'elet a &ri!er> Cristian /latter> Uni'ersities &ress 5In(ia6 li!ite(> y(eraba(




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,8



!& 11 10<A 7 E&E%"RON% S#S"E' DES*N

5Co!!on )it E%T ,, ,+;6

#o(ules ours'odule 1

7ractical Analog " #i?e( Signal Circuit %esign Issues an( TecniDues9

7assi'e co!&onents9 Un(erstan(ing an( inter&reting (ata seets an( s&ecifications of'arious &assi'e an( acti'e co!&onents> non:i(eal bea'ior of &assi'e co!&onents>$

O& a!&s9 %C &erfor!ance of o& a!&s9 /ias> offset an( (rift$ AC 7erfor!ance ofo&erational a!&lifiers9 ban( )i(t> sle) rate an( noise$ 7ro&erties of a ig Dualityinstru!entation a!&lifier$ %esign issues affecting (c accuracy " error bu(get analysis in

instru!entation a!&lifier a&&lications$ Isolation a!&lifier basics$ Acti'e filers9 (esign oflo) &ass> ig &ass an( ban( &ass filters$

A%Cs an( %ACs9 Caracteristics> interfacing to !icrocontrollers$ Selecting an A%C$

7o)er su&&lies9 Caracteristics> (esign of full )a'e bri(ge regulate( &o)er su&&ly$Circuit layout an( groun(ing in !i?e( signal syste!$

,+

'odule /

7ractical Logic Circuit %esign Issues an( TecniDues9Un(erstan(ing an( inter&reting (ata seets " s&ecifications of 'arious C#OS"/iC#OS fa!ily Logic (e'ices$ Electrical bea'ior 5stea(y state " (yna!ic6 of C#OS" /iC#OS fa!ily logic (e'ices$

/enefits an( issues on !igration of 8:'olt an( ;$; 'olt logic to lo)er 'oltage su&&lies$C#OS2TTL Interfacing /asic (esign consi(erations for li'e insertion$ TA.2IEEE,,=$, (esign consi(erations$

%esign for testability> Esti!ating (igital syste! reliability$ %igital circuit layout an(groun(ing$ 7C/ (esign gui(elines for re(uce( E#I$

,+

'odule :

Electro!agnetic Co!&atibility 5E#C69

Desi2nin2 ,or (E'%)+ E'% re2ulations+ typial noise path+ methods o, noise

ouplin2+ methods o, reduin2 inter,erene in eletroni systems

,4



Cabling of Electronic Syste!s9Ca&aciti'e cou&ling> effect of siel( on ca&aciti'e cou&ling> in(ucti'e cou&ling> effectof siel( on in(ucti'e cou&ling> effect of siel( on !agnetic cou&ling> !agneticcou&ling bet)een siel( an( inner con(uctor> siel(ing to &re'ent !agnetic ra(iation>siel(ing a rece&tor against !agnetic fiel(s> coa?ial cable 'ersus siel(e( t)iste( &air>

ribbon cables$

.roun(ing of Electronic Syste!s9 Safety groun(s> signal groun(s> single:&oint groun(syste!s> !ulti&oint:&oint groun( syste!s> ybri( groun(s> functional groun( layout>&ractical lo) freDuency groun(ing> ar()are groun(s> groun(ing of cable siel(s>groun( loo&s> siel( groun(ing at ig freDuencies$

'odule B

/alancing " Filtering in Electronic Syste!s9 /alancing> &o)er line filtering> &o)ersu&&ly (ecou&ling> (ecou&ling filters> ig freDuency filtering> syste! ban()i(t$

7rotection Against Electrostatic %iscarges 5ES%69Static generation> u!an bo(y !o(el> static (iscarge> ES% &rotection in eDui&!ent

(esign> soft)are an( ES% &rotection> ES% 'ersus E#C$

7ac@aging " Enclosures of Electronic Syste!9 Effect of en'iron!ental factors on

electronic syste! 5en'iron!ental s&ecifications6> nature of en'iron!ent an( safety

!easures$ 7ac@aging1s influence an( its factors$

Cooling in2of Electronic Syste!9 eat transfer> a&&roac to ter!al !anage!ent>

!ecanis!s for cooling> o&erating range> basic ter!al calculations> cooling coices>eat sin@ selection$

,+

"utorial ,;

Total ours 8*

"E>" =OO?S@

,$ Electronic Instru!ent %esign> ,st e(itionM by9 i! R$ Fo)lerM O?for( Uni'ersity 7ress$

*$ Noise Re(uction TecniDues in Electronic Syste!s> *n( e(itionM by9 enry G$ OttM

on Giley " Sons$

;$ %igital %esign 7rinci&les " 7ractices> ;r( e(ition by9 on F$ Ga@erlyM 7rentice all

International> Inc$

=$ O&erational A!&lifiers an( linear integrate( circuits> ;r( e(ition by9 Robert F$

CouglinM 7rentice all International> Inc

8$ Intuiti'e Analog circuit (esign by9 #ar@$ T To!&sonM 7ublise( by Else'ier

,<



RE$EREN%E =OO?S@

,$ 7rinte( Circuit /oar(s : %esign " Tecnology> ,st e(itionM by9 G /ossartM Tata

#c.ra) ill$

*$ A %esigner1s .ui(e to Instru!entation A!&lifiersM by9 Carles itcin an( Le)

CountsM Se!inar #aterials tt&922)))$analog$co!

;$ Errors an( Error /u(get Analysis in Instru!entation A!&lifier A&&licationsM by9

Ea!on NasM A&&lication note AN:8; tt&922)))$analog$co!

=$ 7ractical Analog %esign TecniDuesM by9 A(olofo .arcia an( Ges Free!anM Se!inar

#aterials tt&922)))$analog$co!

8$ Selecting An A2% Con'erterM by9Larry .a((yM A&&lication bulletin

tt&922)))$Ti$co!

4$ /enefits an( issues on !igration of 8:'olt an( ;$; 'olt logic to lo)er 'oltage su&&liesM

A&&lication note S%AA+,,A tt&922)))$Ti$co!

<$ TA.2IEEE ,,=$, (eigns consi(erationsM A&&lication note SCTA+*tt&922)))$Ti$co!

3$ Li'e InsertionM A&&lication note S%YA+,* tt&922)))$Ti$co!

$ 7C/ %esign .ui(elines For Re(uce( E#IM A&&lication note SHHA++

tt&922)))$Ti$co!

In a((ition> National " International ournals in te relate( to&ics> !anufacturer1s (e'ice (ata

seets an( a&&lication notes are to be referre( to get &ractical a&&lication oriente( infor!ation$




uestion attern











,3

http://www.analog.com/




http://www.ti.com/

http://www.ti.com/

http://www.ti.com/

http://www.ti.com/

http://www.ti.com/




http://www.ti.com/

http://www.ti.com/

http://www.ti.com/

http://www.ti.com/

http://www.ti.com/



!& 11 10<= D*"A& N"E*RA"ED %R%U" DES*N

5Co!!on )it E%T ,, ,+8/6

#o(ules ours'odule 1@

C#OS in'erters :static an( (yna!ic caracteristics> C#OS NAN%> NOR an( OR.ates ,+

'odule /@

Static an( %yna!ic C#OS (esign: %o!ino an( NORA logic : co!binational an(

seDuential circuits :#eto( of Logical Effort for transistor siBing :&o)er consu!&tion

in C#OS gates: Lo) &o)er C#OS (esign,,

'odule :@

Arit!etic circuits in C#OS VLSI : A((ers: !ulti&liers: sifter :C#OS !e!ory(esign : SRA# an( %RA# ,*

'odule B@/i&olar gate %esign: /iC#OS logic : static an( (yna!ic bea'iour :%elay an( &o)erconsu!&tion in /iC#OS Logic$ 4

"utorial ,;

Total ours 8*

"E>" =OO?S@

,$ Sung:#o ang " Yusuf Leblebici> C#OS %igital Integrate( Circuits : Analysis " %esign>#.> Secon( E($> ,

*$ an # Rabaey> %igital Integrate( Circuits : A %esign 7ers&ecti'e> 7rentice all> ,<

;$ en #artin> %igital Integrate( Circuit %esign> O?for( Uni'ersity 7ress> *+++

=$ R$ $ /a@er> $ G$ Li> an( %$ E$ /oyce> C#OS circuit (esign> layout> an( si!ulation$ Ne)Yor@9 IEEE 7ress> ,3$

8$ Analysis an( %esign of %igital Integrate( Circuits> Tir( E(ition> %a'i( A$ o(ges> orace.$ ac@son> an( Res'e A$ Sale> #c.ra):ill> *++=$

,






uestion attern











*+



!& 11 10<% DES*NN* ."4 '%RO%ON"RO&&ERS

5Co!!on )it E%T ,, ,+,6

#o(ules ours

#o(ule ,7=it 0<1 'iroontroller

Intro(uction to E!be((e( Syste!s$7=it 'iroontrollers@ A &o&ular 3:bit #icrocontroller 5Intel 3+8,6 is co'ere(un(er tis sectionArhiteture@ C7U /loc@ (iagra!> #e!ory OrganiBation> 7rogra! !e!ory> %ata#e!ory> Interru&tseripherals@ Ti!ers> Serial 7ort> I2O 7ortro2rammin2@ A((ressing #o(es> Instruction Set> 7rogra!!ing

'iroontroller based System Desi2n

Ti!ing Analysis

Case stu(y )it reference to 3:bit 3+8, #icrocontroller$

A ty&ical a&&lication (esign fro! reDuire!ent analysis troug conce&t (esign>

(etaile( ar()are an( soft)are (esign using 3:bit 3+8, #icrocontrollers$

,+

#o(ule *

:/7 =it AR'F/0" roessor %ore

ntrodution@ RISC2AR# %esign 7iloso&y> About te AR#*+T Core> 7rocessorFunctional /loc@ %iagra!

ro2rammers 'odel@ %ata Ty&es> 7rocessor !o(es> Registers> .eneral 7ur&oseRegisters> 7rogra! Status Register> C7,8 Co&rocessor> #e!ory an( !e!ory!a&&e( I2O> 7i&eline> E?ce&tions> Interru&ts an( Vector table> Arcitecture re'isions>AR# 7rocessor Fa!ilies$

%ahe@ #e!ory ierarcy an( cace !e!ory>Cace Arcitecture – /asic Arcitecture of a Cace> /asic o&eration of a cacecontroller> Cace an( !ain !e!ory relationsi&> Set Associati'ityCace 7olicy – Grite &olicy> Cace line re&lace!ent &olicies> allocation &olicy on acace !issInstruction Cace> %ata Cace> Grite /uffer an( 7ysical A((ress TA. RA#

'emory 'ana2ement Units@ o) 'irtual !e!ory )or@s> %etails of te AR###U> 7age Tables> Translation Loo@:asi(e /uffer> %o!ains an( #e!ory access&er!issions

AR' nstrution Set@ %ata 7rocessing instructions> /ranc instructions> Loa( :Store instructions> Soft)are Interru&t Instruction> 7rogra! Status RegisterInstruction> Loa(ing Constants

,*

*,



"humb nstrution Set@ Tu!b register usage> AR#:Tu!b inter)or@ing> /rancinstruction> %ata &rocessing instructions> Loa( : store instructions> stac@ instructions>soft)are interru&t instructions$

nterrupt 4andlin2@ Interru&ts> Assigning interru&ts> Interru&t latency> IR " FIe?ce&tions> /asic interru&t stac@ (esign an( i!&le!entation> Non:neste( Interru&tan(ler

#o(ule ;

AR'F 'iroontroller Arhiteture@ A &o&ular AR# #icrocontroller fro!At!el 5AT,R#*++6 is co'ere( un(er tis section

A"F1R'F/00 Arhiteture@ /loc@ %iagra!> Features> #e!ory #a&&ing

'emory %ontroller ('%)> #e!ory Controller /loc@ %iagra!> A((ress %eco(er>E?ternal #e!ory Areas> Internal #e!ory #a&&ing

E-ternal =us nter,ae (E=)> OrganiBation of te E?ternal /us Interface> E/IConnections to #e!ory %e'ices

E-ternal 'emory nter,ae> Grite Access> Rea( Access> Gait State #anage!ent

A"F1R'F/00 ER4ERA&S

nterrupt %ontroller@ Nor!al Interru&t> Fast Interru&t> AICSystem "imer (S")@ 7erio( Inter'al Ti!er 57IT6> Gatc(og Ti!er 5G%T6> Real:ti!e Ti!er 5RTT6Real "ime %lo6 (R"%)arallel nput5Output %ontroller (O)

#o(ule =

A"F1R'F/00 ER4ERA&S

Universal Synhronous Asynhronous Reeiver "ranseiver (USAR")@ /loc@%iagra!> Functional %escri&tion> Syncronous an( Asyncronous #o(es

Development G Debu22in2 "ools ,or 'iroontroller based Embedded Systems@

Soft)are an( ar()are tools li@e Cross Asse!bler> Co!&iler> %ebugger> Si!ulator>

In:Circuit E!ulator 5ICE6> Logic AnalyBer etc$

/rief Arcitecture of 7o)er 7C$

3

"utorial ,;

Total ours 8*

"E>" =OO?S@

**



, Intel an( /oo@ on JE!be((e( #icrocontrollersK> ,st E(ition* #ua!!a( Ali #aBi(i> anice .illis&ie #aBi(i> Rolin %$ #cinlay> JTe 3+8,

#icrocontroller an( E!be((e( Syste!s using Asse!bly an( CK> *n( E(ition> 7renticeall

; AR# Co!&any Lt($ JAR# Arcitecture Reference #anual– AR# %%I +,++EK

= %a'i( Seal JAR# Arcitecture Reference #anualK> *++, A((ison Gesley> Englan(M#organ auf!ann 7ublisers8 An(re) N Sloss> %o!inic Sy!es> Cris Grigt> JAR# Syste! %e'elo&erQs .ui(e :

%esigning an( O&ti!iBing Syste! Soft)areK> *++4> Else'ier4 AT#EL Cor&oration> JAT,R#*++ AR#*+T /ase( #icrocontroller Re'$ ,<43E:

ATAR#–;+:Se&:+8K< AR# Co!&any Lt($ JAR#*+T Tecnical Reference #anual 5Re' ,6 : AR# %%I

+,8,CK

RE$EREN%E =OO?S@

, Ayala> ennet J3+8, #icrocontroller : Arcitecture> 7rogra!!ing "A&&licationsK> ,st E(ition> 7enra! International 7ublising

* Ste'e Furber> JAR# Syste!:on:Ci& ArcitectureK> *n( E(ition> 7earson E(ucation; 7re(@o> #y@e> J7rogra!!ing an( Custo!iBing te 3+8, #icrocontrollerK> ,st

E(ition> #c.ra) ill International= ScultB> To!as G> JC an( te 3+8, 7rogra!!ing for #ultitas@ingK> ,st E(ition>

7rentice all8 ScultB> To!as G> JC an( te 3+8,9 ar()are> #o(ular 7rogra!!ing an(

#ultitas@ingK> Vol I> *n( E(ition> 7rentice all4 Ste)art> a!es G> #iao> ai > J3+8, #icrocontroller9 ar()are> Soft)are an(

InterfacingK> *n( E(ition> 7rentice all< Arnol($ S$ /erger> JE!be((e( Syste!s %esign : An intro(uction to 7rocesses> Tools

an( TecniDuesK> Eas)er 7ress3 Ra a!al> J#icrocontroller : Arcitecture 7rogra!!ing Interfacing an( Syste!

%esignK ,st E(ition> 7earson E(ucation 7$S #anoaran> 7$S$ annan> J#icrocontroller base( Syste! %esignK> ,st E(ition>

Scitec 7ublications,+ %a'i( Calcutt> Fre( Co)an> assan 7arciBa(e> J3+8, #icrocontrollers – An

A&&lication base( Intro(uctionK> Else'ier,, Aay %es!u@> J#icrocontroller : Teory " A&&licationsK> Tata #c.ra) ill




*;





uestion attern











*=



!& 11 10H ()

SE'NAR 4ours5wee6@ / %redits@ /

ours

Objective: To assess the debating capability of the student to present atechnical topic. Also to impart training to students to face audience and present their ideas and thus creating in them self esteem and courage that areessential for engineers.

In(i'i(ual stu(ents are reDuire( to coose a to&ic of teir interest fro!E!be((e( Syste!s relate( to&ics &referably fro! outsi(e te #$Tec syllabusan( gi'e a se!inar on tat to&ic about ;+ !inutes$ A co!!ittee consisting of atleast tree faculty !e!bers 5&referably s&ecialiBe( in E!be((e( Syste!s6 sallassess te &resentation of te se!inar an( a)ar( !ar@s to te stu(ents$

Eac stu(ent sall sub!it t)o co&ies of a )rite u& of is2er se!inar to&ic$ Oneco&y sall be returne( to te stu(ent after (uly certifying it by te cair!an ofte assessing co!!ittee an( te oter )ill be @e&t in te (e&art!ental library$Internal continuous assess!ent !ar@s are a)ar(e( base( on te rele'ance of te

to&ic> &resentation s@ill> Duality of te re&ort an( &artici&ation$

7er )ee@ *

nternal ontinuous assessment@ 100 mar6s

*8



!& 11 10;() %O'U"ER ADED DES*N O$ !&S %R%U"S

&A=ORA"OR#

#a?i!u! #ar@s – ,++

'odules ours

'odule 1

,$ #o(eling an( si!ulation of Co!binational an( seDuential circuits using Verilog$

*$ #o(eling an( Si!ulation of ALU using Verilog$

;$ #o(eling an( Si!ulation of FS#s using Verilog

=$ #o(eling an( si!ulation of #e!ory an( FIFO in Verilog

,*

'odule /

,$ #o(eling an( si!ulation of UART in Verilog

*$ Si!ulation of N#OS an( C#OS circuits using S7ICE$

;$ #o(eling of #OSFET using C$

,=

Total ours *4

RE$EREN%E =OO?S@

,$ #o(ern %igital Electronics by R 7 ain

*$ Verilog %L by Sa!ir 7alnit@ar$

;$ VERILO. %L SYNTESIS9 A 7RACTICAL 7RI#ER by /as@ar


Internal continuous assess!ent is in te for! of &erio(ical tests$ Tere )ill be a !ini!u! oft)o tests &er subect$ Te assess!ent (etails are to be announce( to te stu(ents> rigt at tebeginning of te se!ester by te teacer$

#i( Ter! Internal Test =+ #ar@s

Laboratory E?&eri!ents " Vi'a Voce ,+ #ar@s

Final Internal Test 8+ #ar@s

"otal 100 'ar6s

*4



SE%OND SE'ES"ER

!& 11 /01 SO% DES*N AND !ER$%A"ON

#o(ules ours

#o(ule ,

System On %hip Desi2n roess@ A canonical SoC %esign> SoC %esign flo))aterfall 's s&iral> to&(o)n 's /otto! u&$ S&ecification reDuire!ent> Ty&es of S&ecification > Syste! %esign &rocess> Syste!le'el (esign issues> Soft I7 Vs ar( I7> %esign for ti!ing closure>Logic (esign issuesVerification strategy> Onci& buses an( interfaces> Lo) 7o)er> #anufacturing teststrategies$

,+

#o(ule *'aro Desi2n roess@ To& le'el #acro %esign> #acro Integration> Soft #acro&ro(uctiBation> %e'elo&ing ar( !acros> %esign issues for ar( !acros> %esign>Syste! Integration )it reusable !acros$

3

#o(ule ;

So% !eri,iation@ Verification tecnology o&tions> Verification !eto(ology>Verification languages> Verification a&&roaces> an( Verification &lans$ Syste! le'el'erification> /loc@ le'el 'erification> ar()are2soft)are co 'erification an( Staticnet list 'erification$Verification arcitecture> Verification co!&onents> Intro(uction to V##> OV# an(

UV#$

,*

#o(ule =

Desi2n o, %ommuniation Arhitetures $or So%s@On ci& co!!unication arcitectures> Syste! le'el analysis for (esigningco!!unication> %esign s&ace e?&loration> A(a&ti'e co!!unication arcitectures>Co!!unication arcitecture tuners> Co!!unication arcitectures for energy2batteryefficient syste!s$

Intro(uction to bus functional !o(els an( bus functional !o(el base( 'erification$

"utorial ,;Total ours 8*

*<



"E>" =OO?S

,$ JSoC Verification #eto(ology an( TecniDuesK> 7ra@as Rasin@ar 7eter 7aterson an(Leena Sing$ lu)er Aca(e!ic 7ublisers> *++,$

*$ JReuse #eto(ology !anual for Syste!OnACi& %esignsK> #icael eating> 7ierre/ricau(> lu)er Aca(e!ic 7ublisers> secon( e(ition>*++,$

RE$EREN%E =OO?S@

,$ J%esign Verification9 Si!ulation an( For!al #eto( base( A&&roacesK> Gillia! $ La!>7rentice all$

*$ JSyste!: on :a: Ci& %esign an( TestK> Rocit Rasu!an> IS/N$

;$ J#ulti&rocessor Syste!sonci&sK> A$A$ erraya> G$Golf> # 7ublisers$

=$ JTe E%A an(/oo@K> %ir@ ansen> lu)er Aca(e!ic 7ublisers$




uestion attern











*3



!& 11 /0/ ANA&O* !&S DES*N

#o(ules ours

#o(ule ,

Analog #OS transistor !o(els Te!&erature effects an( Noise in #OS transistor#OS resistors> caracteriBation of resisti'e> ca&aciti'e ele!ents an( #OS (e'ices$7assi'e an( acti'e C#OS current sin@2 sources– basics of single stage C#OSa!&lifiers co!!on Source> co!!on gate an( source follo)er stages freDuencyres&onse$

,+

#o(ule *

C#OS %ifferential A!&lifiers9 C#OS O&erational A!&lifiers one stage an( t)ostage gain boosting Co!!on !o(e fee(bac@ 5C#F/6 Casco(e an( Fol(e( casca(estructures

3

#o(ule ;

ig 7erfor!ance O&a!&s – ig s&ee(2 ig freDuency o&a!&s>!icro &o)er o&a!&s> lo) noise o&a!&s an( lo) 'oltage o&a!&s$ Current !irrors>filter i!&le!entations$

Su&&ly in(e&en(ent an( te!&erature in(e&en(ent references /an( ga& references7TAT current generation an( constant .! biasing – C#OS co!&arators –#ulti&liers an( )a'e sa&ing circuits – effects (ue to nonlinearity an( !is!atc in#OS circuits

,*

#o(ule =S)itce( Ca&acitor Circuits9 First an( Secon( Or(er S)itce( Ca&acitor Circuits>S)itce( Ca&acitor filters> C#OS oscillators> si!&le an( carge &u!& C#OS 7LLsnon i(eal effects in 7LLs> %elay loc@e( loo&s an( a&&lications> basics of C#OS (atacon'erters – #e(iu! an( ig s&ee( C#OS (ata con'erters> O'er sa!&lingcon'erters$

"utorial ,;

Total ours 8*

"E>" =OO?S

*



,$ JAnalog Integrate( Circuit %esignK> %a'i($ A$ ons an( en #artin> on Giley an(Sons> *++,$

*$ J%esign of Analog C#OS Integrate( CircuitK> /eBa( RaBa'i> Tata #c.ra) ILL> *++*$

;$ JC#OS Analog Circuit %esignK> 7ili& Allen " %ouglas olberg> O?for( Uni'ersity

7ress> *++*$

RE$EREN%E =OO?S@

,$ JAnalog VLSI – Signal Infor!ation an( 7rocessingK> #oa!!e( Is!ail " FeiB > on Giley an(Sons$


Internal continuous assess!ent is in te for! of &erio(ical tests> assign!ents> se!inars or a

co!bination of all )ice'er suits best$ Tere )ill be a !ini!u! of t)o tests &er subect$ Teassess!ent (etails are to be announce( to te stu(ents> rigt at te beginning of te se!ester byte teacer$


uestion attern











;+



!& 11 /0: "ES"N* G !ER$%A"ON O$ !&S %R%U"S

#o(ules ours

#o(ule ,

ntrodution@ Sco&e of testing an( 'erification in VLSI (esign &rocessM Issues in testan( 'erification of co!&le? ci&sM e!be((e( cores an( SOCs

Intro(uction to test bences> )riting test bences in Verilog %L$

#o(ule *

$undamentals o, !&S testin2> Fault !o(els$ Auto!atic test &attern generation>%esign for testability> Scan (esign> Test interface an( boun(ary scan$

#o(ule ;

System "estin2 an( test for SOCs> I((D testing> %elay fault testing> /IST for testingof logic an( !e!ories> Test auto!ation$

#o(ule =

Desi2n !eri,iation "ehniques base( on si!ulation> analytical an( for!ala&&roaces> Functional 'erification> Ti!ing 'erification> For!al 'erification> /asicsof eDui'alence cec@ing an( !o(el cec@ing$

Verification of si!&le I7s9 #e!ory 'erification> FIFO 'erification an( Verificationof RISC C7U

,*

"utorial ,;

Total ours 8*

;,



"E>" =OO?S@

,$ #$ Abra!o'ici> #$ A$ /reuer> A$ %$ Frie(!an> J%igital Syste!s Testing an( Testable%esignK 7iscata)ay> Ne) ersey9 IEEE 7ress> ,=

*$ #$ /usnell an( V$ %$ Agar)al> PEssentials of Electronic Testing for %igital> #e!ory an(

#i?e(:Signal VLSI CircuitsP> lu)er Aca(e!ic 7ublisers> *+++

;$ T$ro&f> PIntro(uction to For!al ar()are VerificationP> S&ringer Verlag> *+++$

=$ 7$ Rasin@ar> 7aterson an( L$ Sing> PSyste!:on:a:Ci& Verification:#eto(ology an(TecniDuesP> lu)er Aca(e!ic 7ublisers> *++,$

8$ Sa!ia #oura( an( Yer'ant Horian> J7rinci&les of Testing Electronic Syste!sK> Giley5*+++6$

RE$EREN%E =OO?S@

,$ JSoC Verification #eto(ology an( TecniDuesK> 7ra@as Rasin@ar 7eter 7aterson an(Leena Sing $lu)er Aca(e!ic 7ublisers> *++,$

*$ JReuse #eto(ology !anual for Syste! On A Ci& %esignsK> #icael eating>

;$ 7ierre /ricau(> lu)er Aca(e!ic 7ublisers> secon( e(ition> *++,$

=$ JSyste!: on :a: Ci& %esign an( TestK> Rocit Rasu!an> IS/N$




uestion attern











;*



!& 11 /0BA &O. O.ER !&S DES*N

#o(ules ours

#o(ule ,

Intro(uction : Si!ulation : 7o)er Analysis:7robabilistic 7o)er Analysis$

,+

#o(ule *

Circuit :Logic : S&ecial TecniDues : Arcitecture an( Syste!s$

3

#o(ule ;

A('ance( TecniDues : Lo) 7o)er C#OS VLSI %esign : 7ysics of 7o)er %issi&ationin C#OS FET %e'ices$

,*

#o(ule =

7o)er Esti!ation : Syntesis for Lo) 7o)er : %esign an( Test of Lo) Voltages :C#OS Circuits$ Lo) 7o)er Static RA# Arcitectures :Lo) Energy Co!&uting UsingEnergy Reco'ery TecniDues – Soft)are %esign for Lo) 7o)er$

"utorial ,;

Total ours 8*

"E>" =OO?S@

,$ .ary Yea& P 7ractical Lo) 7o)er %igital VLSI %esign P> ,<$

*$ ausi@ Roy> Sarat 7rasa(> P Lo) 7o)er C#OS VLSI Circuit %esign P> *+++;$

;$ A$7$Can(ra@asan an( R$G$ /roa(ersen> Lo) &o)er (igital C#OS (esign> lu)er>,8$

RE$EREN%E =OO?S@

,$ C#OS Analog Circuit %esignK> 7ili& Allen " %ouglas olberg> O?for( Uni'ersity 7ress>*++*$

*$ Rabaey> 7e(ra!> JLo) &o)er (esign !eto(ologiesK lu)er Aca(e!ic> ,<

;;






uestion attern











;=



!& 11 /0B= S#N"4ESS AND O"'IA"ON O$ D*"A& %R%U"S

#o(ules ours

#o(ule ,

Intro(uction to Syntesis an( o&ti!iBation9

ig:le'el syntesis9 #oti'ation an( organiBationSce(ulingResource saring%ata &at an( control syntesis

#o(ule *

Logic syntesis9Algorit!s an( rule:base( syste!s> Algebraic an( /oolean !eto(s

Ti!ing issues9SeDuential syntesis an( reti!ingSe!icusto! libraries " library !a&&ingAlgorit!s an( rule:base( syste!sStructural an( /oolean !atcing

,+

#o(ule ;

O&ti!iBation of (igital circuits9 Area> Ti!ing an( &o)er o&ti!iBation$ RTL Co(ingfor area> ti!ing an( &o)er o&ti!iBation$ Syntesis an( .eneration of area> ti!ingan( &o)er re&orts9 RISC C7U a case stu(y$

,+

#o(ule =Intro(uction to )2S) Co(esign7roble! ta?ono!yE!be((e( syste! (esignSoft)are o&ti!iBation7ers&ecti'es

,+

"utorial ,;

Total ours 8*

;8



"E>" =OO?S

,$ .io'anni %e #iceli> JSyntesis an( O&ti!iBation of %igital CircuitsK> #c.ra):ill>,=> 8t &rint$

*$ JLogic SyntesisK> S$ %e'a(as> A$ .os an( $ eutBer> #c.ra) ill> ,=$

;$ R$ .u&ta> JCo:syntesis of ar()are an( Soft)are for E!be((e( Syste!s+ lu)er ,8$

RE$EREN%E =OO?S@

,$ E()ars #$%$> Automati Logi synthesis Tehni!ues for Digital Systems> #ac!illan Ne)Electronic Series> ,*

*$ Sa!ir 7alnit@ar> JVerilog %L9 A .ui(e to %igital %esign an( SyntesisK> 7earson

E(ucation> *++8$




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;4



!& 11 /0B% DES*N O$ D*"A& S*NA& RO%ESSN* S#S"E'S

5Co!!on )it E%T ,, *+,6

#o(ules ours

'odule 1 7 Di2ital Si2nal roessor@

T#S;*+C4<,; or any oter &o&ular %S7 fro! Te?as Instru!ents is co'ere( un(er tis

!o(ule

Arcitecture9

C7U Arcitecture> Internal #e!ory> C7U %ata 7ats control7rogra!!ing9

Instruction Set an( A((ressing #o(es

Co(e Co!&oser Stu(io> Co(e .eneration Tools> Co(e Co!&oser Stu(io %ebugTools

%S7 7eri&erals9#ulticannel /uffere( Serial 7ort> Trans!ission " Rece&tion

Ti!ers

#e!ory of %S79Internal %ata27rogra! #e!ory

E?ternal #e!ory Interface

'odule / 7 Di2ital Si2nal roessin2 Al2orithms@

Filter %esign9FIR %igital filter (esign$

Fourier Transfor!9

%FT> FFT> S&ectral Analysis

%T#F

S&eec 7rocessing Algorit!s

,+

'odule : 7 Di2ital Si2nal roessin2 Appliation@

Real:ti!e I!&le!entation9

I!&le!entation of Real:ti!e FIR %igital filter using %S7$I!&le!entation of Real:ti!e Fast Fourier Transfor! a&&lications using te %S7

I!&le!entation of %T#F Tone .eneration an( %etection$I!&le!entation of S&eec &rocessing a&&lications

,+

'odule B 7 %urrent trends in Di2ital Si2nal roessor@,+

;<



F7.A Tecnology

%S7 Tecnology ReDuire!ents

%esign i!&le!entation

#ulti&ly Accu!ulator 5#AC6 an( Su! of 7ro(uct 5SO76

I!&le!entation of Serial27arallel Con'ol'er using F7.As

F7.A /ase( %S7 Syste! %esign

FIR filters

FIR Teory

%esigning FIR filters

%irect Gin(o) %esign !eto(

Constant Coefficient FIR %esign

%irect FIR %esign

Cooley:Tu@ey FFT Algorit! i!&le!entation using F7.A

"utorial ,;

Total ours 8*

"E>" =OO?S@

,$ %igital Signal 7rocessing I!&le!entation Using te T#S;*+C4+++ %S7 7latfor!> ,st

E(itionM by9 Nai! %anoun*$ %S7 A&&lications using 0C1 an( te T#S;*+C4 %S> ,st E(itionM by9 Rul& Cassaing;$ %igital Signal 7rocessing9 A Syste! %esign A&&roac> ,st E(itionM by9 %a'i( %efatta >

Lucas ose& . " o(@iss Gillia! SM on Giley=$ %igital Signal 7rocessing )it Fiel( 7rogra!!able .ate Arrays9 *n( E(ition> by9 U$ #eyer – /ase> S&ringer

8$ Real : Ti!e %igital Signal 7rocessing9 I!&le!entations> A&&lications> an( E?&eri!ents)it te T#S;*+C88> uo> Sen #> Lee> /ob > on Giley " Sons Lt($

RE$EREN%E =OO?S@

,$ %igital Signal 7rocessing> Tir( E(ition> Sanit $ #itra> Tata #c.RGA ill*$ %igital Signal 7rocessing – A 7ractical .ui(e for Engineers an( Scientists> Ste'en G

S!it> Else'ier

;$ %igital Signal 7rocessing : A Stu(ent .ui(e> ,

st

E(itionM by9 T$$ Terrel an( Li@:)anSar@M #ac!illan 7ressM Lt($

=$ %igital Signal 7rocessing Laboratory> /$ 7reeta! u!ar> Taylor " Francis> CCS %S7A&&lications

8$ Intro(uction to %igital Signal 7rocessing> ,st E(itionM by9 on . 7roa@is> %i!itris .#anola@is

4$ %igital Signal 7rocessing %esign> ,st E(itionM by9 An(re) /ate!an> Garren Yates

;3



<$ A Si!&le a&&roac to %igital Signal &rocessing> ,st E(itionM by9 reig #ar'en " .illian

E)ersM Giely Interscience

3$ %S7 FIRST : A #ulti!e(ia A&&roac> ,st E(itionM by9 A#ES $ #cClellan> Ronal(

Scaffer an( #ar@ A$ Yo(erM 7rentice all

$ Signal 7rocessing First> ,st e(itionM by9 a!es $ #cClellan> Ronal( G$ Scafer an( #ar@

A$ Yo(erM 7earson E(ucation

,+$ %igital Signal 7rocessing> ,st E(itionM by9 O&&enei! A$V an( Scafer R$GM 7

,,$ %igital 7rocessing of S&eec Signals> ,st E(itionM by9 L$R$ Rabiner an( Scafer R$GM 7

,*$ %igital Signal 7rocessing – Arcitecture> 7rogra!!ing an( A&&lications> by9 /$

Ven@atara!ani " #$/as@arM Tata #c.ra) ill

,;$ A 7ractical A&&roac to %igital Signal 7rocessing> by9 $ 7a(!anaban> S$ Ananti "

R$Viayaraes)aranM Ne) Age International 7ublisers

,=$ Teory " A&&lication of %igital Signal 7rocessing> ,st E(itionM by9 Rabiner L$R " .ol( /M

7

,8$ %igital Signal 7rocessing> ,st E(itionM by9 7 Ra!es /abu>,4$ 0C1 Language Algorit! for %S7> ,st E(itionM by9 7aul #$ E!bree an( /ruce i!bleM 7

,<$ tt&922o!eto)n$aol$(e2u)e!eyerbase2in(e?t!l

,3$ )))$s&ringer$(e

In a((ition> National2 International ournals in te fiel(> !anufacturers %e'ice (ata seets an(

a&&lication notes an( researc &a&ers in ournals are to be referre( to get &ractical an(

a&&lication oriente( infor!ation$




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;



!& 11 /0<A 4*4 SEED D*"A& DES*N

5Co!!on )it E%T ,, *+8A6

#o(ules ours

#o(ule ,

ntrodution to hi2h speed di2ital desi2n

FreDuency> ti!e an( (istance : Ca&acitance an( in(uctance effects : ig see(

&ro&erties of logic gates : S&ee( an( &o)er :#o(elling of )ires :.eo!etry an(

electrical &ro&erties of )ires : Electrical !o(els of )ires : trans!ission lines :

lossless LC trans!ission lines : lossy LRC trans!ission lines : s&ecial trans!ission

lines

,+

#o(ule *

ower distribution and noise

7o)er su&&ly net)or@ : local &o)er regulation : IR (ro&s : area bon(ing : onci&

by&ass ca&acitors : sy!biotic by&ass ca&acitors : &o)er su&&ly isolation : Noise

sources in (igital syste! : &o)er su&&ly noise : cross tal@ : intersy!bol interference

3

#o(ule ;

Si2nallin2 onvention and iruits

Signalling !o(es for trans!ission lines :signalling o'er lu!&e( trans!ission !e(ia

: signalling o'er RC interconnect : (ri'ing lossy LC lines : si!ultaneous bi:

(irectional signalling : ter!inations : trans!itter an( recei'er circuits

#o(ule =9

"imin2 onvention and synhronisation

Ti!ing fun(a!entals : ti!ing &ro&erties of cloc@e( storage ele!ents : signals an(

e'ents :o&en loo& ti!ing le'el sensiti'e cloc@ing : &i&eline ti!ing : close( loo&ti!ing : cloc@ (istribution : syncroniBation failure an( !etastability : 7LL an(

%LL base( cloc@ aligners

,*

"utorial ,;

Total ours 8*

"E>" =OO?S@

=+



,$ o)ar( onson an( #artin .raa!> Pig S&ee( %igital %esign9 A an(boo@ of

/lac@ #agicK>;r( E(ition> 57rentice all #o(ern Se!icon(uctor %esign SeriesQ Sub

Series9 7 Signal Integrity Library6> *++4

*$ Ste&en $ all> .arrett G$ all> an( a!es A$ #cCall P ig:S&ee( %igital Syste!

%esign9 A an(boo@ of Interconnect Teory an( %esign 7ractices by P> Giley > *++<

;$ erry /ernstein> $#$ Carrig> Cristo&er #$ %ura!> an( 7atric@ R$ ansen Jig

S&ee( C#OS %esign StylesK> S&ringer Giley *++4

=$ Ra!es arani J%esign of ig:S&ee( Co!!unication Circuits 5Selecte( To&ics in

Electronics an( Syste!s6K Gorl( Scientific 7ublising Co!&any *++4

RE$EREN%E =OO?S@

,$ Gillia! S$ %ally " on G$ 7oultonM %igital Syste!s Engineering> Ca!bri(ge Uni'ersity

7ress> ,3*$ #asa@aBu SoiM ig S&ee( %igital Circuits> A((ison Gesley 7ublising Co!&any>

,4

;$ an #> Rabaey> et allM %igital Integrate( Circuits9 A %esign &ers&ecti'e> Secon(E(ition> *++;






uestion attern











=,

http://www.amazon.com/CMOS-Logic-Circuit-Design-Uyemura/dp/0792384520/ref=sr_1_14?ie=UTF8&s=books&qid=1228895346&sr=1-14








!& 11 /0<= 'U&"'EDA %O'RESSON "E%4NUES

5Co!!on )it E%T ,, *+*6

#o(ules ours'odule 1 7 N"RODU%"ON

S&ecial features of #ulti!e(ia – .ra&ics an( I!age %ata Re&resentations –Fun(a!ental Conce&ts in Vi(eo an( %igital Au(io – Storage reDuire!ents for!ulti!e(ia a&&lications :Nee( for Co!&ression : Ta?ono!y of co!&ressiontecniDues – O'er'ie) of source co(ing

TET CO#7RESSION

Co!&action tecniDues – uff!ann co(ing – A(a&ti'e uff!ann Co(ing –Arit!etic co(ing – Sannon:Fano co(ing – %ictionary tecniDues – LHG fa!ily

algorit!s$

'odule / 7 'A*E %O'RESSON

Transfor! Co(ing – 7E. Stan(ar( – Sub:ban( co(ing algorit!s9 %esign of Filterban@s – Ga'elet base( co!&ression9 I!&le!entation using filters – EHG> S7ITco(ers – 7E. *+++ stan(ar(s : /I.> /I.* stan(ar(s$

,+

'odule : 7 AUDO %O'RESSON

Au(io co!&ression tecniDues : : La) an( A: La) co!&an(ing$ FreDuency (o!ain

an( filtering – /asic sub:ban( co(ing – A&&lication to s&eec co(ing – .$<** –A&&lication to au(io co(ing – #7E. au(io> &rogressi'e enco(ing for au(io – Silenceco!&ression> s&eec co!&ression tecniDues – For!ant an( CEL7 Voco(ers

,+

'odule B 7 !DEO %O'RESSON

Vi(eo co!&ression tecniDues an( stan(ar(s – #7E. Vi(eo Co(ing I9 #7E. – , an(* – #7E. Vi(eo Co(ing II9 #7E. – = an( < – #otion esti!ation an( co!&ensationtecniDues – $*4, Stan(ar( – %VI tecnology – 7LV &erfor!ance – %VI real ti!eco!&ression – 7ac@et Vi(eo$

,+

"utorial ,;

Total ours 8*

=*



"E>" =OO?S@

,$ ali( Sayoo(9 Intro(uction to %ata Co!&ression> #organ auff!an arcourt In(ia>

;r( E(ition> *+,+

*$ %a'i( Salo!on9 %ata Co!&ression – Te Co!&lete Reference> S&ringer Verlag Ne)

Yor@ Inc$> =t E(ition> *++4$

RE$EREN%E =OO?S@

,$ Yun $ Si> uifang Sun9 I!age an( Vi(eo Co!&ression for #ulti!e(ia Engineering :

Fun(a!entals> Algorit!s " Stan(ar(s> CRC &ress> *++;$

*$ 7eter Sy!es9 %igital Vi(eo Co!&ression> #c.ra) ill 7ub$> *++=$

;$ #ar@ Nelson9 %ata co!&ression> /7/ 7ublisers> Ne) %eli> *++3

=$ #ar@ S$ %re)> He:Nian Li9 Fun(a!entals of #ulti!e(ia> 7I> ,st E(ition> *++$

8$ Gat@inson> 9 Co!&ression in Vi(eo an( Au(io> Focal &ress> Lon(on$,8$

4$ an VoBer9 Vi(eo Co!&ression for #ulti!e(ia> A7 7rofes> Ne)Yor@> ,8

<$ .onBaleB an( Goo(s> %igital I!age 7rocessing> ;r( E(> 7I


Internal continuous assess!ent is in te for! of &erio(ical tests> assign!ents> se!inars or a

co!bination of all )ice'er suits best$ Tere )ill be a !ini!u! of t)o tests &er subect$ Teassess!ent (etails are to be announce( to te stu(ents> rigt at te beginning of te se!ester byte teacer$


uestion attern











=;



!& 11 /0<% DES*N $OR "ES"A=&"#

#o(ules ours

#o(ule ,

Intro(uction to test an( (esign for Testability Fun(a!entals9 #o(eling9 #o(eling(igital circuits at logic> register an( structural !o(els$ Le'els of #o(eling> LogicSi!ulation Ty&es of si!ulation> %elay !o(els> ele!ent e'aluation> aBar( (etection> .ate le'el e'ent (ri'en si!ulation> Logic Fault !o(els> Fault (etection an(re(un(ancy> Fault eDui'alence an( fault location$

#o(ule *

Testing for single Stuc@ Faults 5SSF69 Auto!ate( test &attern generation5AT7.2AT.6 for SSFs in co!binational an( seDuential circuits> Functional Testing)it s&ecific fault !o(els> Vector Si!ulation AT7. Vectors> For!ats> Co!&actionan( Co!&ression> Selecting AT7. Tools$

#o(ule ;

%esign for Testability9 Testability tra(eoffs an( tecniDues Scan Arcitectures an(testing Controllability an( Obser'ability> .eneric /oun(ary scan> Full integrate(scan> storage cells for scan (esign> /oar( le'el an( syste! le'el %FT a&&roaces>/oun(ary scan stan(ar(s> Co!&ression TecniDues – Syn(ro!e test ban( signatureanalysis$

#o(ule =

/uilt in Self Test 5/IST69>

/IST conce&ts an( test &attern generation > S&ecific /IST Arcitectures CS/L>/EST>RTS> LOCST> STU#7S> C/IST> CE/S>RT%> SST> CATS> CST7> /IL/O$A('ance( /IST conce&ts an( (esign for self test at /oar( le'el

#e!ory /IST5# /IST69>#e!ory test Arcitectures an( TecniDues – Intro(uction to !e!ory test> Ty&es of!e!ories an( integration> e!be((e( !e!ory testing !o(el> #e!ory testreDuire!ent for #/IST$ E!be((e( core testing Intro(uction to auto!atic in circuittesting TA. testing features$

,*

"utorial ,;

Total ours 8*

"E>" =OO?S@

==



,$ J%igital syste!s Testing an( testable %esignK> #iron Abra!o'ici> #el'in A$ /reur> Artur%$ Frie(!an> aico 7ublising ouse> *++,$

*$ JIntro(uction to VLSI TestingK> Engleoo( cliffs> Robert $ Feugate> r$> Ste'en #$

#entyn> 7rentice all> ,3$

RE$EREN%E =OO?S@

,$ J%esign for test for (igital IC " E!be((e( Core Syste!sK> Alfre( Crouc> 7rentice all$




uestion attern











=8



!& 11 /0H () SE'NAR 4ours5wee6@ /

%redits@ /

oursObjective: To assess the debating capability of the student to present atechnical topic. Also to impart training to students to face audience and present their ideas and thus creating in them self esteem and courage that areessential for engineers.

In(i'i(ual stu(ents are reDuire( to coose a to&ic of teir interest fro!E!be((e( Syste!s relate( to&ics &referably fro! outsi(e te #$Tec syllabusan( gi'e a se!inar on tat to&ic about ;+ !inutes$ A co!!ittee consisting of atleast tree faculty !e!bers 5&referably s&ecialiBe( in E!be((e( Syste!s6 sall

assess te &resentation of te se!inar an( a)ar( !ar@s to te stu(ents$

Eac stu(ent sall sub!it t)o co&ies of a )rite u& of is2er se!inar to&ic$ Oneco&y sall be returne( to te stu(ent after (uly certifying it by te cair!an ofte assessing co!!ittee an( te oter )ill be @e&t in te (e&art!ental library$Internal continuous assess!ent !ar@s are a)ar(e( base( on te rele'ance of teto&ic> &resentation s@ill> Duality of te re&ort an( &artici&ation$

7er )ee@ *

nternal ontinuous assessment@ 100 mar6s

=4



!& 11 /0; () "ES"N* G !ER$%A"ON O$ !&S %R%U"S 7&A=ORA"OR#

#a?i!u! #ar@s – ,++

#o(ules ours

'odule 1

,$ Verilog Si!ulation an( RTL Verification

a6 #e!oryb6 Cloc@ %i'i(er an( A((ress Counterc6 n:/it /inary Counter an( RTL Verification

*$ Finite State #acines I!&le!ent an( Verify Using Verilog File I2O

;$ %ifferent ty&es of T/s for !e!ory an( a((er2subtractor

,*

'odule /

,$ /asic Verification en'iron!ent for FIFO2UART

*$ Verification 7lanning for FIFO2UART

a6 %e'elo&!ent of te test cases as &er te 'erification &lan

b6 .eneration an( Analysis of Co(e co'erage Re&orts;$ Griting assertions for FIFO

,=

Total ours *4

RE$EREN%E =OO?S@

,$ Verilog %L by Sa!ir 7alnit@ar$

*$ T$ ro&f> PIntro(uction to For!al ar()are VerificationP> S&ringer Verlag> *+++$ 7$Rasin@ar> 7aterson an( L$ Sing>

;$ PSyste!:on:a:Ci& Verification:#eto(ology an( TecniDuesP> lu)er Aca(e!ic7ublisers> *++,$

=<




Internal continuous assess!ent is in te for! of &erio(ical tests$ Tere )ill be a !ini!u! oft)o tests &er subect$ Te assess!ent (etails are to be announce( to te stu(ents> rigt at tebeginning of te se!ester by te teacer$

#i( Ter! Internal Test =+ #ar@s

Laboratory E?&eri!ents " Vi'a Voce ,+ #ar@s

Final Internal Test 8+ #ar@s

"otal 100 'ar6s

=3



"4RD SE'ES"ER

!& 11 :01A '>ED S*NA& S#S"E' DES*N

5Co!!on )it E%T ,, ;+,A6

To&ics ours

#o(ule , Intro(uction

7N unctions> /i&olar Vs Uni&olar %e'ices> #OS Transistor o&eration> #OSTransistor as a S)itc> N#OS >7#OS an( C#OS S)itces> C#OS In'erter ACan( %C Caracteristics> Analog Signal 7rocessing> E?a!&le of Analog #i?e( SignalCircuit %esign

3

#o(ule * %igital Sub Circuits

C#OS Logic i!&le!entation basics: Logic gates an( Fli& flo&s –Trans!ission

.ates> T. base( i!&le!entation of !ulti&le?ers> (e:!ulti&le?ers> enco(ers>

(eco(ers$ %igital Circuits li@e ALU> Co!&arator> 7arity generator> Ti!er>

7G#>SRA# an( %RA#> CA#

,+

#o(ule ; Analog Sub circuits

I(eal O&erational A!&lifier> In'erting an( Non:in'erting configuration %ifferential

a!&lifier basics> VCO> 7LL> Co!&arator caracteristics> t)o stage o&en loo&

co!&arator >S)itce( ca&acitor fun(a!entals> S)itce( ca&acitor a!&lifier

,+

#o(ule = %ata Con'erters

DA% 9 Static "%yna!ic Caratersitics>, /it %AC> String %AC> Fully %eco(e(%AC>7G# %AC> Current scaling> 'oltage scaling %ACs

AD% 9 Static "%yna!ic Caracteristics> NyDuist Criteria > Sa!&le " ol( Circuit>uantiBation error> Conce&t of o'er sa!&ling> Counting A%C> Trac@ing A%C>Successi'e a&&ro?i!ation A%C> Flas A%C> %ual Slo&e A%C

Over samplin2 Data %onverters 9 O'er sa!&ling fun(a!entals> %elta –Sig!a

Con'erter basics> W #o(ulator

,,

"utorial ,;

Total ours 8*

"E>" =OO?S@

=



,$ .ray 7aul R> #eyer> Robert .> Analysis an( %esign of Analog Integrate( Circuits> ;r(

e(ition> on Giley " Sons$

*$ acob /a@er> PC#OS #i?e(:Signal circuit (esignP> A on Gilly " Sons> inc$>&ublications> *++;$

;$ 7rofessor /ernar( /oser :KAnalysis an( %esign of VLSI Analog:%igital InterfaceIntegrate( CircuitsK JA((ison Gisely &ublicationsK 5,,6$

RE$EREN%E =OO?S@

,$ % A on> en #artin> Analog Integrate( Circuit %esign> ,st E(ition> on Giley

*$ C#OS Analog Circuit %esign> *n( e(itionM by9 Allen> 7illi& E> olberg > %ouglas R>

O?for( Uni'ersity 7ress> 5In(ian E(ition

;$ en #artin> %igital Integrate( Circuit %esign> on Giley

=$ Se(ra " S!it> #icroelectronics Circuits> 8t E(ition> O?for( Uni'ersity 7ress> 5In(ianE(ition6

8$ an #$ Rabaey> Ananta Ca(ra@asan> /$ Ni@olic >%igital Integrate( Circuits – A %esign7ers&ecti'e *n( E(ition> 7rentice all of In(ia 5Eastern Econo!y E(ition6$

4$ Sung7#o ang+ Yusuf Leblebici> C#OS %igital Integrate( Circuits Analysis " %esign>* n(

E(> Tata #c.ra) ill




uestion attern











8+



!& 11 :01= $*A AR%4"E%"URE AND A&%A"ONS

#o(ules ours

#o(ule ,7rogra!!able logic %e'ices9 RO#> 7LA> 7AL> C7L%> F7.A Features>Arcitectures an( 7rogra!!ing$A&&lications an( I!&le!entation of #SI circuits using 7rogra!!able logic %e'ices$

3

#o(ule *

F7.As9 Fiel( 7rogra!!able .ate Arrays: Logic bloc@s> routing arcitecture> (esignflo)> tecnology!a&&ing for F7.As> Case stu(ies ilin? C=+++ " ALTERA1s FLE 3+++2,++++

F7.As$

Intro(uction to a('ance( F7.As9 ilin? Virte? an( ALTERA Strati?

,+

#o(ule ;

Finite State #acines 5FS#69 To& %o)n %esign> State Transition Table> Stateassign!ents for F7.As>RealiBation of state !acine carts using 7AL> Alternati'erealiBation for state !acine carts using !icro&rogra!!ing> lin@e( state !acine>enco(e( state !acine$

FS# Arcitectures9 Arcitectures Centere( aroun( non registere( 7L%s> %esign ofstate !acines centere( aroun( sift registers> OneXot state !acine> 7etrinets forstate !acines:/asic conce&ts an( &ro&erties> Finite State #acine:Case stu(y$

,*

#o(ule =

Syste! Le'el %esign9 Controller> (ata &at (esigning> Functional &artition> %igitalfront en( (igital (esign tools for F7.As$Syste! le'el (esign using !entor gra&ics2ilin? E%A tool 5F7.AA('antage2ilin? ISE6> %esign flo) using F7.As$

Case stu(ies9 %esign consi(erations using F7.As of &arallel a((er cell> &arallela((er seDuential circuits> counters> !ulti&le?ers> &arallel controllers$

"utorial ,;

Total ours 8*

8,



"E>" =OO?S

,$ Fiel( 7rogra!!able .ate Array Tecnology : S$ Tri!berger> E(r> ,=> lu)er Aca(e!ic7ublications$

*$ Engineering %igital %esign : RICAR% F$TIN%ER> *n( E(ition> Aca(e!ic &ress$

;$ Fun(a!entals of logic (esign:Carles $ Rot> =t E(ition aico 7ublising ouse$

RE$EREN%E =OO?S@

,$ %igital %esign Using Fiel( 7rogra!!able .ate Array> 7$$ Can " S$ #oura(> ,=>7rentice all$

*$ Fiel( &rogra!!able gate array> S$ /ro)n> R$$ Francis> $ Rose> H$.$ Vranesic> *++<> /S




uestion attern











8*



!& 11 :01% .RE&ESS %O''UN%A"ON S#S"E'S

5Co!!on )it E%T ,, ;+*A6

#o(ules ours

'odule 1 7 ntrodution to .ireless Systems@

E'olution of Gireless Co!!unication> Cor(less Tele&ones> 7aging an(

!essaging syste!s> Cellular Syste!s> Analog an( %igital Cellular> #o(ulation

tecniDues> FreDuencies use( an( licensing> S&rea( S&ectru! Tecnologies>

#ulti&le Access TecniDues for Gireless Co!!unications> Satellite:base(

)ireless Co!!unications> .7S

'odule / 7 %ellular Systems@

Cellular carriers an( FreDuencies> Cannel allocation> Cell co'erage> Cell

S&litting> #icrocells> 7icocells> an(off> ,st> *n(> ;r( an( =t .eneration Cellular

Syste!s> .S#> C%#A .7RS> E%.E> EV%O C%#A*+++> U#TS> GC%#A>

LTE> Gireless Geb connecti'ity> #obile I7> Gireless in local loo& 5GLL6

,+

'odule : 7 Radio propa2ation in 'obile Systems@

Antenna /asics> Cellular an( 7CS Antennas> #I#O> #obile Ra(io 7ro&agation9

Free:s&ace &ro&agation !o(el> T)o:Ray #o(el> Out(oor an( in(oor

&ro&agation !o(els> Fa(ing Cannels> Raleig an( Ricean %istribution$

,,

'odule B 7 .ireless &ANs and ANs@

Gireless LANs9 3+*$,,>3+*$,,a2b2g> 3+*$,4:Gi#A> UG/ Co!!unications>

Gireless 7ersonal Area Net)or@s> /lueToot> /lueToot 7rotocol Arcitecture>

IEEE 3+*$,8 stan(ar(s> Hig/ee> Sensor Net)or@s> Interfacing &roble!s an( co:

e?istence strategies in Sensor Net)or@s> #AC an( Routing &rotocols in Sensor

Net)or@s$

"utorial ,;

Total ours 8*

"E>" =OO?S@

8;



,$ Gireless Co!!unications – 7rinci&les an( 7racticeM by Teo(ore S Ra&&a&ort>

7earson E(ucation 7te$ Lt($> %eli

*$ Gireless Co!!unication TecnologyM /y9 /la@e> RoyM %el!ar> Ne) Yor@$

;$ Gireless Co!!unications an( Net)or@ingM /y9 Stallings> Gillia!M 7earson

E(ucation 7te$ Lt($> %eli

=$ /luetoot Re'eale(M /y9 #iller> /rent A> /is(i@ian> Catsci@M A((ison Gesley

Long!an 7te Lt($> %eli

RE$EREN%E =OO?S@

,$ #obile an( 7ersonal Co!!unications Ser'ices an( Syste!sM ,st E(itionM /y9 Ra7an(yaM 7I> Ne) %eli

*$ Fun(a!entals of Gireless Co!!unication by Tse %a'i( an( Vis)anat 7ra!o(>Ca!bri(ge Uni'ersity &ress> Ca!bri(ge

;$ #obile Co!!unicationsM /y9 Sciller> ocen M A((ison Gesley Long!an 7teLt($> %eli

=$ ;. Net)or@s9 Arcitecture> &rotocols an( &roce(ures base( on ;.77 s&ecificationsfor U#TS GC%#A net)or@s> /y asera> Su!it> Narang> an( Nisit> TATA #.>Ne) %eli

8$ #obile Co!!unications EngineeringM Teory an( A&&lications> /y9 Lee> Gillia!C YM #.> Ne) Yor@

4$ Gireless Sensor Net)or@s9 infor!ation &rocessing by a&&roac> HAO> FEN.>.UI/AS an( LEONI%AS > ELSEVIER> Ne) %eli

<$ Gireless Net)or@ E'olution9 *. to ;. by .AR.> VIAY > 7earson E(ucation5Singa&ore6 7te$ lt($> %eli

In a((ition> !anufacturers %e'ice (ata seets> IEEE &ublications an( a&&lication notes are to

be referre( to get &ractical an( a&&lication oriente( infor!ation$




uestion attern

Ans)er any 8 Duestions by coosing at least one Duestion fro! eac !o(ule$'odule 1 'odule / 'odule : 'odule B









8=



!& 11 :0/A S#S"E' !ER&O*

#o(ules ours

#o(ule ,

Intro(uction to functional 'erification languages> Intro(uction to Syste! Verilog>Syste! Verilog (ata ty&es$ Syste! Verilog &roce(ures> Interfaces an( !o(&orts>Syste! Verilog routines$

#o(ule *

Intro(uction to obect oriente( &rogra!!ing> Classes an( Obects> Ineritance>Co!&osition> Ineritance '2s co!&osition> Virtual !eto(s$ 7ara!eteriBe( classes>Virtual interface> Using OO7 for 'erification> Syste! Verilog Verification Constructs

#o(ule ;

Syste! Verilog Assertions9 Intro(uction to assertion> O'er'ie) of &ro&erties an(assertion> /asics of &ro&erties an( seDuences> A('ance( &ro&erties an( seDuences>Assertions in (esign an( for!al 'erification> so!e gui(elines in assertion )riting$

#o(ule =

Co'erage %ri'en Verification an( functional co'erage in SV9 Co'erage %ri'enVerification> Co'erage #etrics> Co(e Co'erage> Intro(uction to functional co'erage>Functional co'erage constructs> Assertion Co'erage> Co'erage !easure!ent>Co'erage Analysis

SV an( C interfacing9 %irect 7rogra!!ing Interface 5%7I6

,*

"utorial ,;

Total ours 8*

"E>" =OO?S@

88





!& 11 :0/= 4ARD.ARE7SO$".ARE %O7DES*N

#o(ules ours#o(ule ,

Intro(uction9 #oti'ation ar()are " soft)are co:(esign> syste! (esignconsi(eration> researc sco&e " o'er'ie)s ar()are Soft)are bac@ groun(9 E!be((e( syste!s> !o(els of (esignre&resentation> te 'irtual !acine ierarcy> te &erfor!ance; !o(eling> ar()areSoft)are (e'elo&!ent

#o(ule *

Co:(esign Conce&ts9 Functions> functional (eco!&osition> 'irtual !acines>

ar()are Soft)are &artitioning> ar()are Soft)are &artitions> ar()are Soft)arealterations> ar()are Soft)are tra(eoffs> co:(esign$

#o(ule ;

#eto(ology for Co:%esign9 A!ount of unification> general consi(eration " basic&iloso&ies> a fra!e)or@ for co:(esign

Unifie( Re&resentation for ar()are " Soft)are9 /enefits of unifie( re&resentation>!o(eling conce&ts$

An Abstract ar()are " Soft)are #o(el9 ReDuire!ent " a&&lications of te!o(els> !o(els of ar()are Soft)are syste!> an abstract ar()are Soft)are

!o(els> generality of te !o(el 7erfor!ance E'aluation9 A&&lication of t e abstract ar()are " Soft)are !o(el>e?a!&les of &erfor!ance e'aluation

,*

#o(ule =

Obect Oriente( TecniDues in ar()are %esign9 #oti'ation for obect oriente(tecniDue> (ata ty&es> !o(eling ar()are co!&onents as classes> (esignings&ecialiBe( co!&onents> (ata (eco!&osition> 7rocessor e?a!&le$

"utorial ,;

Total ours 8*

8<



"E>" =OO?S

,$ Sanaya u!ar> a!es $ Ayler CTe Co:(esign of E!be((e( Syste!s9 A Unifie(ar()are Soft)are Re&resentation+ lu)er Aca(e!ic 7ubliser> *++* $

*$ $ o&etB> JReal:Ti!e Syste!sK> lu)er> ,<$

;$ R$ .u&ta> JCo:syntesis of ar()are an( Soft)are for E!be((e( Syste!sK> lu)er ,8$

RE$EREN%E =OO?S@

,$ S$ All)ort> JIntro(uction to Real:ti!e Soft)are %esignK> S&ringer:Verlag> ,3=$

*$ C$ #$ risna> $ Sin> JReal:ti!e Syste!sK> #c:.ra) ill> ,<

;$ 7eter #ar)e(el> .$ .oosens> JCo(e .eneration for E!be((e( 7rocessors> lu)erAca(e!ic 7ublisers> ,8$




uestion attern











83



!& 11 :0/% !&S S*NA& RO%ESSN*

#o(ules ours

#o(ule ,

An o'er'ie) of %S7 conce&ts:Linear syste! teory: %FT> FFT: realiBation of (igitalfilters: Ty&ical %S7 algorit!s: %S7 a&&lications: %ata flo) gra& re&resentation of%S7 algorit!$: Loo& boun( an( iteration boun( Reti!ing an( its a&&lications$

,*

#o(ule *

Algorit!s for fast con'olution: Algorit!ic strengt re(uction in filters an(transfor!s: %CT an( in'erse %CT: 7arallel FIR filters: 7i&elining of FIR filters:7arallel &rocessing: 7i&elining an( &arallel &rocessing for lo) &o)er$

#o(ule ;

7i&eline interlea'ing in (igital filters: 7i&elining an( &arallel &rocessing for IIR filters:Lo) &o)er IIR filter (esign using &i&elining an( &arallel &rocessing: 7i&eline(a(a&ti'e (igital filters$

#o(ule =

State 'ariable (escri&tion of (igital filters: Roun( off noise co!&utation using state

'ariable (escri&tion: Scaling using slo):(o)n> reti!ing an( &i&elining$

"utorial ,;

Total ours 8*

8



"E>" =OO?S@

,$ $$ 7ari> VLSI %igital Signal 7rocessing Syste!s> on:Giley> ,$

*$ 7irsc> 7$> Arcitectures for %igital Signal 7rocessing> Giley> ,$

RE$EREN%E =OO?S@

,$ Allen> $> Co!&uter Arcitectures for %igital Signal 7rocessing> 7rocee(ings of te IEEE>Vol$<;> No$8> #ay ,38

*$ /ate!an A$> an( Yates> G$> Digital Signal "roessing Design> Co!&uter Science 7ress>Ne) Yor@

;$ S$Y$ ung> $$ Gite ouse> T$ ailat> VLSI and #odern Signal "roessing$ "rentie %all> ,38




uestion attern











4+



!& 11 :0: ()NDUS"RA& "RANN*

4ours5wee6@ :0 (durin2 the period o,trainin2)

%redits@ 1

&b'etive( To enable the student to orrelate theory and industrial ratie*

Te stu(ents a'e to arrange an( un(ergo an in(ustrial training of !ini!u! t)o )ee@sin an in(ustry &referably (ealing )it electronic (esign (uring te se!ester brea@ bet)eense!ester * an( se!ester ; an( co!&lete )itin ,8 calen(ar (ays fro! te start of se!ester ;$Te stu(ents are reDueste( to sub!it a re&ort of te training un(ergone an( &resent te contentsof te re&ort before te e'aluation co!!ittee$ E'aluation co!!ittee )ill a)ar( te !ar@s ofen( se!ester base( on training Duality> contents of te re&ort an( &resentation$

End semester E-amination@ 'ar6s <0

4,



!& 11 :0B()

'AS"ER RESEAR%4ROJE%" 4ASE

4ours5wee6@ //

%redits@ H

&b'etive(To imrove the rofessional ometeny and researh atitude by touhing the areas

whih otherwise not overed by theory or laboratory lasses* The ro'et wor+ aims to develothe wor+ ratie in students to aly theoretial and ratial tools,tehni!ues to solve reallife roblems related to industry and urrent researh*

Te &roect )or@ can be a (esign &roect2e?&eri!ental &roect an(2or co!&utersi!ulation &roect on any of te to&ics in electronics (esign relate( to&ics$ Te &roect )or@ isallotte( in(i'i(ually on (ifferent to&ics$ Te stu(ents sall be encourage( to (o teir &roect

)or@ in te &arent institute itself$ If foun( essential> tey !ay be &er!itte( to continue teir&roect outsi(e te &arent institute> subect to te con(itions in clause ,+ of #$Tec regulations$%e&art!ent )ill constitute an E'aluation Co!!ittee to re'ie) te &roect )or@$ TeE'aluation co!!ittee consists of at least tree faculty !e!bers of )ic internal gui(e an(anoter e?&ert in te s&ecifie( area of te &roect sall be t)o essential !e!bers$

Te stu(ent is reDuire( to un(erta@e te !aster researc &roect &ase , (uring tetir( se!ester an( te sa!e is continue( in te = tse!ester 57ase *6$ 7ase , consist of&reli!inary tesis )or@> t)o re'ie)s of te )or@ an( te sub!ission of &reli!inary re&ort$First re'ie) )oul( igligt te to&ic> obecti'es> !eto(ology an( e?&ecte( results$ Secon(re'ie) e'aluates te &rogress of te )or@> &reli!inary re&ort an( sco&e of te )or@ )ic is to

be co!&lete( in te =t se!ester$ Te E'aluation co!!ittee consists of at least tree faculty!e!bers of )ic internal gui(e an( anoter e?&ert in te s&ecifie( area of te &roect sall bet)o essential !e!bers$

nternal %ontinuous assessment@

4*



SE'ES"ER B

!& 11 B01() 'AS"ERS RESEAR%4ROJE%" 4ASE

4ours5wee6@ :0

%redits@ 1/

&b'etive(To imrove the rofessional ometeny and researh atitude by touhing the areas

whih otherwise not overed by theory or laboratory lasses* The ro'et wor+ aims to develothe wor+ ratie in students to aly theoretial and ratial tools,tehni!ues to solve reallife roblems related to industry and urrent researh$

#aster Researc &roect &ase II is a continuation of &roect &ase I starte( in te tir(se!ester$ Tere )oul( be t)o re'ie)s in te fourt se!ester> first in te !i((le of te se!esteran( te secon( at te en( of te se!ester$ First re'ie) is to e'aluate te &rogress of te )or@>&resentation an( (iscussion$ Secon( re'ie) )oul( be a &re:sub!ission &resentation before tee'aluation co!!ittee to assess te Duality an( Duantu! of te )or@ (one$ Tis )oul( be a &reDualifying e?ercise for te stu(ents for getting a&&ro'al by te (e&art!ental co!!ittee for tesub!ission of te tesis$ At least one tecnical &a&er is to be &re&are( for &ossible &ublicationin ournal or conferences$ Te tecnical &a&er is to be sub!itte( along )it te tesis$ Tefinal e'aluation of te &roect )ill be e?ternal e'aluation$

nternal %ontinuous assessment@

*uide Evaluation %ommittee

$irst Review <0 <0

Seond Review 100 100

"otal 1<0 1<0

End Semester E-amination@

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