PaperSpecial Edition ■ Digital Ｂroadcasting and Transion Systems

VLSI Architecture of PSK Demodulator for Digital BS

and CS Broadcasting

(デジタルBS/CS用PSK同 期復調器の設計)

Masahide Hatanaka†, Toshihiro Masaki† †, Minoru Okada (IIlelllber)†††,

Koso Murakami†

Abstract The digital broadcasting services are expected to be more popular because of their high quality and bandwidth

efficiency. In Japan, a digital broadcasting service was started with a broadcasting satellite (BS) in geostationary orbit at

110 degrees of east longitude. Previously, digital broadcasting services using communications satellites (CS) has already been

introduced in Japan since June 1996. Today, services are provided with three satellites, JCSAT-3 (128•‹E) and JCSAT-4A

(124•‹E) for SkyPerfecTV!. Since both BS and CS are operating at the 12-GHz band and the BS and CS receiversuse similar

blocks, we can reduce the total LSI size by using common components if the BS and CS receivers are implemented on the same

LSI. This paper describes a VLSI demodulator architecture for both the digital BS broadcasting service based on ISDB-S

(Integrated Services Digital Broadcasting Satellite) standard and the new digital CS broadcasting service based on DVB-S

(Digital Video Broadcasting for Satellite) standard. We have also evaluated the LSI's performance with computer simulation

and amount of hardware.

Key words: digital BS broadcasting, digital CS broadcasting, PSK, VLSI

1. Introduction

The digital broadcasting services are expected to be

more popular because of their high quality and band-

width efficiency. In Japan, a digital broadcasting service

with the broadcasting satellite (BS) was started on De-

cember 1, 2000. The satellites for BS digital broadcast-

ing in Japan (BSAT-lb, -2a) are at 110 degrees of east

longitude in satellite orbit. Nleanwhile, in Japan, dig-

ital broadcasting services using communications satel-

lites (CS) has already been introduced since June 1996.

Today, the services are movided with three satellites,

JCSAT-3 (128•‹E) and JCSAT-4A (124•‹E) for SkyPer-

fecTV!.

Both BS and CS are operating at 12GHz band. How-

ever, due to difference between BS and CS in terms of

satellite positions, two receiving antennas are required

for receiving both ones.

The new communication satellite (N-SAT 110) was

launched in October 2000 at the same orbit (110•‹E) as

the BS digital broadcasting satellites, and started ser-

vices in Spring of 2002. Since the new CS satellite occu-

pies the same orbit as that of BS and both BS and new

CS adopt the same digital satellite broadcasting tech-

nology, we can exploit the same antenna and receiver

for receiving both digital BS (DBS) and CS services.

However, the reception of CS still requires the CS re-

ceiver which is different from the DBS receiver, since BS

and CS adopt different standards. BS employs ISDB-

S (Integrated Serviced Digital Broadcasting Satellite)')

standardized by ARIB (Association of Radio Industries

and Businesses) of Japan, while CS uses the other stan-

dard based on DVB-S (Digital Video Broadcasting for

Satellite), which is original standardized by ETSI (Eu-

ropean Telecommunications Standard Institute)2) and

localized by ARIB3). Two demodulators are required

to receive both the services because there are difference

in the baud rate, frame format and modulation scheme.

Since the BS and new CS, and CS receivers use sim-

ilar blocks such as phase locked loop, matched filter,

FEC, and audio and video codec, we can reduce the to-

Appcard in ISCAS2003

Received May 27, 2004: Revised September 22, 2004: Accepted Octo-

ber 25, 2004

†The Graduate School of Information Science and Technology, Os-

aka University

(1-5, Yamada-oka, Suita-shi, Osaka 564-0871, Japan)

††The Collaborative Research Center for Advanced Science and

Technology, Osaka University

(2-1, Yamada-oka, Suita-shi, Osaka 564-0871, Japan)

†††The Graduate School of Information Science, Nara Institute of

Science and Technology

(8916-5, Takayama, Ikoma, Nara 630-0192, Japan)

映 像 情 報 メデ ィ ア学 会 誌Vol.59, No.1,pp.69～ 76 (2005) (69) 69

tal LSI size by common use of these components if the

DBS, new CS, and CS receivers are implemented on the

same LSI.

This paper describes VLSI architecture of demodula-

tor for the digital BS, new CS, and CS receivers.

In the following section, we describe functions and

a hardware architecture of the proposed demodulator.

The simulation and implementation results of the de-

modulator are explained in section 3.

2. Demodulation Function

In DBS, up to eight transport streams are multiplexed

and modulated by phase shift keying(PSK) signaling

format. Each transport stream chooses one format from

binary PSK (BPSK), quadrature PSK (QPSK), and

8PSK, according to the required bit rate andcarrier-to-

noise power ratio (CNR). The frame structure is shown

in Fig. 1. The frame is composed of the unique words

(W1 andW2), transmission and multiplexing configura-tion control(TNICC), phase reference signals, and data.

The unique words are used for frame synchronization.

TNICC indicates the modulation format for each trans-

mission stream. The unique words,TNICC and phase

reference signals aremodulation in BPSK format. The

symbol rate of the DBS is 28.86 Mbaud.

On the other hand, theCS digital broadcasting sys-

tem only uses QPSK. The symbol rate for CS is 21.098

Mbaud. Since both of them use similar blocks for PSK

demodulation, it is possible to design a PSK demodu-

lator that demodulates both the BS and CS. However,

a frame synchronization block for BS is required, since

the frame structure illustrated in Fig. 1 is used in BS.

Furthermore, a re-sampling function is required since

BS and CS have the different symbol rate. Table 1

shows the main features of the BS and CS broadcasting

services.

BS receiver LSIs with 8 bit ADCs has already been

developed -4). However we use 6 bit ADCs in order to

reduce size of LSI. Since the dynamic range decreases

with decrease in the ADC resolution, the more accu-

rate adjustment in signal amplitude is required. In our

LSI, the post-AGC (Automatic Gain Control) function

is added in order to control the amplitude of the signal

according to the carrier-to-noise power ratio (CNR).

The block diagram of the proposed VLSI architec-

ture is shown in Fig. 2. This block was designed on the

premise that 2 channels 6 bit 60 MHz ADC was used. The VLSI is composed of a Post AGC, a Phase Rota-

tor, a Interpolator, a Matched Filter, a Timing Recov-

ery block, a Unique Word Detector, a Carrier Recovery

block, two NC0s, and a CNR Estimator. The behavior

of this LSI is shown as follows.

AD converted inphase (I) and quadrature (Q) signals

are inputted into the Post AGC, where the gain of the

input signals are adjusted according to the control of

the CNR Estimator. The signals are then fed to the

Phase Rotator for rotating its phase according to the

NCO for carrier recovery. and sent to the Interpolator.

The Interpolator interpolates the output signals in time

domain for converting the sampling rate according to

the NCO fortiming recovery. The output signals from

the Interpolator become output signals of demodulation

block via the Matched Filter.

The unique word detector, timing recovery block. and

carrier recovery block respectively perform frame,sym-

bol timing,and carrier phase synchronization.

In the following, we will describe further details of the

Fig. 1 Data format for BS digital broadcasting system

Fig. 2 VLSI architecture

Table 1 The main features of the BS and CS broadcast-

ing services

70(70) 映 像 情 報 メ デ ィ ア 学会 誌Vol.59, No.1 (2005)

components.

2. 1 Complex Multiplier

The Phase Rotator performs phase rotate operation

for removal of both phase and frequency offset. The

Phase Rotator is composed of the COrdinate Rotation

DIgital Computer (CORDIC) algorithm5), which per-

forms the phase rotation of complex value. It is easy to

implement the CORDIC algorithm on VLSI, because

the most of the operations in the CORDIC algorithm

are binary additions and subtractions. Now, let us ex-

plain the principle of the CORDIC algorithm. Let z = x jy and be a complex value and a ro-

tation angle, respectively, where x and y are real and

imaginary components of z. The coordinate for new

complex value z = x' jy' is:

Or rewritten as:

In this equation, the tangent term is represented in

the binary shift operation if the angle is limited to

tan 0 = 2-i'. The small rotation given by:

- The tangent angle of rotation can be represented

by combination of the series of rotations, +0,. The

CORDIC algorithm is

where

(zi ≧ 0),

(otherwise),

where the factor Ki, which is independent of the deci-

sion di, is eliminated from the above algorithm in order

to simplify the notation.

After the end of iterations, The magnitude of the out-

put is magnified with a factor of:

where N is the number of iterations. After eight itera-

tions, for example, the magnitude is 1.64 times larger

than that of the input one. In order to avoid overflow,

the result is divided by two before it is provided to the

interpolator.

2.2 Interpolator

The Interpolator re-samples the output data of the

complex-multiplier according to NCO for timing recov-

ery.

An architecture of the Interpolator is shown in Fig. 4.

The Interpolator is composed of two 8-tap finite impulse

response (FIR) filters for I and Q signals with time-

variant coefficient and a coefficient memory. The word

length of the filter coefficients is 7 bits.

The interpolator re-samples the input signals at twice

as much as symbol rate, 57.72 NIHz(BS) and 42.196

NIHz(CS). This module also outputs the signal indicates

the symbol timing.

2.3 Matched Filter

Both BS and CS employs root roll-off pulse shaping

with a rool-off factor of 0.35.

This Matched Filter(i\IF) is implemented as two

equivalent 8-tap FIR filters. The word length is 7 bits.

The frequency matched filter (FI\IF) is the derivative

of the frequency response of the i\IF. The FMF is used

for estimating the carrier frequency offset.

Fig. 3 Phase rotator

Paper •  VLSI Architecture of PSK Demodulator for Digital BS and CS Broadcasting (71) 71

MF FMF

NIF and FMF exploit the same shift register block.

The frequency response of the MF and the FMF is

shown in Fig. 5.

2. 4 Timing Recovery Block

The block diagram of the Timing Recovery Block is

illustrated in Fig. 6. The Timing Recovery Block is con-

sist of 3 blocks, Timing Error Detector, Mode controller,

and Loop Filter.

The output signals of the F are received by the Tim-

ing Error Detector, and the symbol error and the lock

detection value which shows lock condition are calcu-

lated.

The lock detection values are fed into a low-pass filter

and the Mode Controller controls a Loop Filter accord-

ing to the magnitude of the filter's output values.

The Loop Filter calculates the current symbol rate

according to the control of the Mode Controller.

(1) Timing Error Detector

The block diagram of the Timing Error Detector is

shown in Fig. 7. This module estimates the symbol

timing error and provides the state of symbol timing

synchronization.

The timing estimation is carried out using output sig-

nals of the MF.

The output signals of the MF, I2k-1,I2k, and I2k+1

for inphase and Q2k-1, Q2k and Q2k+1 for quadrature,

are stored onto the registers. The timing error can be

obtained by calculating the formula, (I2k-1 - I2k+1 ) ×

I2k + (Q2k-1 - Q2k+1 ) × Q2k.

TED also provides the state of symbol timing syn-

chronization in order to control the loop filter.

(2) Mode Controller

This block controls the loop filter according to the

state of symbol timing synchronization. The lock de-

tection value from the Timing Error Detector described

above is fed into a low-pass filter in this block. This

block uses the output signals of this filter to detect

a symbol synchronization. The detection algorithm is

shown as follows, and Fig. 8.

(1) As initialization, the value of a state register of the symbol sync (SRss) is set at 0. This means a

symbol synchronization is not established. This

state is called acquisition state.

(2) If the value of the filter output signal (FO88) is

larger than a threshold (t-th1), the value of the

state register sync is set at 1. This means a sym-

bol synchronization is established. This state is

called tracking state.

(3) Once the symbol synchronization is estab-

lished, the synchronism is continued until the

value of the filter output signal becomes nega-

tive. If so, the value of the state register is set at

0 again.

2. 5 Unique Word Detector

(1) Data Format

The BS digital broadcasting system can use three

different modulation formats, Binary PSK (BPSK),

Fig. 4 Architecture of interpolator

Fig. 6 Timing recovery block

Fig. 7 Timing error detector

72(72) 映像情 報メデ ィア学会誌Vol.59, No.1 (2005)

Quadrature PSK (QPSK), and 8PSK. The one of them

is selected according to transmission and multiplexing

configuration control (TMCC) data transmitted with

the audio and video data.

Fig. 1 shows the data format for BS digital broadcast-

ing systems.

A transmission frame consists of a header, 48 data

slots, and burst signals. One data slot transmits 812

symbols and the burst signals are inserted at a period of

203 symbols. One of the three formats, BPSK, QPSK,

and 8PSK is selected for each data slot as the modula-

tion format. The burst signals are transmitted with the

BPSK modulation format.

The header consists of the 32 symbols of front sync

signals (w1), the 128 symbols of TMCC information,

and the 32 symbols of back sync signals (w2 or w3) and

is modulated with the BPSK. The last 20 bits of wl

is OxECD28. The last 20 bits of w2 of Ox0B677 and

the last 20 bits of w3 of OxF4988 (inversion of w2) are

also used. The TMCC information is divided into 8

piece each of which is transmitted by the consecutive 8

transmission frames.

The modulation format of transmitted data slot is not

identified at the receiver until the TMCC information

is decoded. Therefore, this system use only the header

and burst symbols to capture the transmitted carrier.

(2) Frame Synchronization Process

The Unique Word Detector is shown in Fig. 9.

The Unique Word Detector consists of two sync word

detection circuits, 6 bits •~ 20 •~ 2 delay circuit , and

control circuit.

The frame synchronization is established as follows,

and the state diagram is shown in Fig. 10.

(1) As initialization, the control circuit sets the

value of a state register at 0 and the value of

a counter at 0.

(2) The sync word detection circuit searches the

wl.

(3) If the wl is detected, the control circuit sets

the value of the counter at 32 and the value of

state register at 1.

(4) The value of the counter increases by 1 per 1

clock cycle. If the w2 or w3 are detected when the

value of the counter is 192, the value of state reg-

ister is set at 2. If not, the value of state register

is decreased by 1 to 0.

(5) If the w1 is detected when the value of the

counter is 32 or If the w2 or w3 is detected when

the value of the counter is 192, the value of the

state register is increased by 1, but if the value of

the state register is 4, the value is not increased

and keeps the value. If the detector cannot de-

tect the w1, w2, and w3, the value of the state

register is decreased by 1, but if the value of the

state register is 0, the value is not decreased .

(6) When the value of the state register is more

than 2, we consider that the frame synchroniza-

tion is established.

2. 6 Carrier Recovery Block

The carrier recovery block is composed of a frequency

offset estimator, a Phase Error Detector, a Chirp Sig-

nal Generator, a Mode Controller, and a Loop Filter as

shown in Fig. 11. This block has two behavior modes , a BS mode and a CS mode.

Fig. 8 Detection algorithm for symbol synchronization

Fig. 9 Unique word detector

Fig. 10 State diagram of frame synchronization

Fig. 11 Carrier recovery block

Paper□VLSI Architecture of PSK Demodulator for Digital BS and CS Broadcasting (73)73

First, the frequency offset estimator estimates a fre-

quency offset in the BS mode,. While frame synchro-nization signal is active from the Unique Word Detector,

the Phase error detector calculates the phase error value

by using the signals which were modulated in BPSK and

the Mode Controller detects the phase synchronization

with same signals. The frequency offset estimator sus-

pends while the phase synchronization is established. In the CS mode, the frequency offset estimation and

the phase error calculation are performed at the same

time. After the phase synchronization is established,

the frequency offset estimator suspends like in the BS

mode.

(1) Phase Error Detector

The Phase Error Detector (PED) calculates the phase

error value in M-PSK signal.

The PEDs are divided into two types, namely, the

decision directed (DD) type which uses PSK demodu-

lated signals and non decision aided (NDA) type which

uses received signals before demodulation according to

their behavior. The DD type can make the estimation

error of the phase error small in transmission channels

with higher CNR where demodulation error is hardly

happened. However, it is difficult for the PED of DD

type to estimate phase error with lower CNR. Since it

is required to receive and demodulate signals correctly

under the condition that the CNR is very low in the BS

and CS common receiver system, a PED of the NDA

type is adopted. The output of this PED, el is showed

as follows :

Since only the signals with BPSK modulation are fed

into the PED, the M is equal to 2 in the BS mode. Since

only QPSK modulation is used, the M is set to 4 in the

CS mode.

The Real number, eI= Re[z,M], is used as a synchro-

nization detection signal.

(2) Chirp Signal Generator

Fig. 12 shows an example of received signal spec-

trum. The PSK transmitted signal spectrum is bi-

lateral. symmetry as shown in Fig. 12(a). This signal

goes through the multi-path transmission path. The frequency response of the transmission path has a fre-

quency dependence as shown in Fig. 12(b). As a result.

(a) transmitted signal spectrum

(b) frcqucncy rcspons cof transmission multi-path

(c) rcccived signal spcctrum

the spectrum of the received signal is asymmetric spec-

trum as shown in Fig. 12(c).

This LSI estimates a frequency offset by calculating

the product of the NIF and the FNIF output since the

FNIF is the derivative of the frequency response of the

NIF as shown in Fig. 5.

So the estimated frequency offset is much different

from the actual frequency offset if the graph of the fre-

quency characteristic is not flat. Therefore, to eliminate the influence of multi-path,

the Chirp Signal Generator generates a saw-toothed sig-

nal and the signal is added to the frequency offset esti-

mated in the frequency estimator. The control method

of the saw-toothed signal generation is described in (3)

(3) Nlode Controller

This module detects a phase synchronization. The

synchronization detection signals outputted from PED

are fed to low pass filter in the Mode Controller. The

output values of the filter is used to decide whether a

phase synchronization is established. The decision al-

gorithm is showed as follows and in Fig. 13. (1) As initialization, the value of a state register

(SRps) is set at 0 which shows no sync. (acquisi-tion state)

(2) If the output value of the low-path filter (FOps

is larger the a threshold (th1) and continue over

th1 while two frames are received, this block de-

cides that a phase synchronization is established.

(tracking state) (3) Once the phase synchronization is established,

the synchronism is continued until the output sig-

nal of the filter becomes negative. If so, the value

of the register is set at 0 again.

Fig. 12 Received spectrum

74(74) 映像情報 メデ ィア学会誌Vol. 59, No. 1 (2005)

(4) When the phase synchronization is not estab-

lished even though a limited time (time l) has

passed, this block asserts a start signal of the Chirp Generator. (chirp generation state)

(5) While the start signal was asserted, the state

is changed to the phase synchronization state as

soon as the output value becomes larger than the

thl.

This module also controls the behavior mode of the

Loop Filter. The mode is changed to acquisition mode

when the output values of the filter become larger than

the threshold (th1), and is changed to tracking mode

when the output values of the filter become smaller than

another threshold (th2).

In the BS mode, this block judges that there are re-

flect waves when a phase synchronization is not estab-

lished if the number of received BS frames after a frame

synchronization is established is equal to the number

which is assigned by an external input signal. In the

CS mode, this block also judges that there are reflect

waves when a phase synchronization is not established if

the number of received symbols after a timing synchro-

nization is established is equal to the number which is

assigned by an external input signal

2.7 CNR Estimator and Post AGC

The CNR Estimator calculates the mean and the vari-

ance of the received signals with I\IF output. The CNR

of received signals can be estimated by using both of

them. If the obtained CNR is smaller than threshold,

this LSI cannot demodulate the received signals. So,

the input signals of this LSI are doubled in the Post

AGC in order to increase signal intensity and this LSI

performs the demodulation process with these signals. After then, if condition becomes better and the CNR is

larger than another threshold, the Post AGC outputs

the input signal itself since this LSI can demodulate

with input signals. The word length of input signals

8PSK (BS) QPSK (BS)

BPSK (BS) QPSK (CS)

can be reduced by 6 bits with this function, and the

LSI size can also be reduced.

3. A VLSI Design of PSK Demodulator

3. 1 Evaluation of PSK demodulator

In order to confirm behavior of the proposed archi-

tecture, we simulated the performance of this PSK de-

modulator under the condition described in Table 2.

Figure 14 shows the bit error rate (BER) obtained

in the each simulation.

When the CNR is high, the obtained BER is lit-

tle lower than the ideal BER, because the influence of

the quantization error is larger. However, the obtained

BER is nearly equal to the ideal BER except for the

BER at the higher CNR. So, there is no problem for

practical use. 3. 2 Implementation Result

The proposed architecture has been implemented

through the use of Synopsys Design Compiler. Table 3

summarizes the main features of the PSK demodulator.

The maximum clock rate overcomes 60 MHz demand

for presupposed system.

Time_e : elapsed time

Fig. 13 Detection algorithm of phase synchronization

Table 2 Simulation condition

Fig. 14 Simulation results

Table 3 Main features of the PSK dcmodulator

Technology : 0.25μm CMOS

Paper□VLSI Architecture of PSK Demodulator for Digital BS and CS Broadcasting (75)75

4. Conclusion

This paper has described the architecture of the PSK

digital demodulator for the reception of digital BS and

CS broadcasting services. This demodulator can be

used for both the digital BS broadcasting service which

was started in December, 2000 and the new CS digital

broadcasting service which is started in March, 2002.

The two functions, the CNR estimator and the

PostAGC, enables to reduce the word length of input

signals by 6 bits without decreasing demodulation ca-

pability, and to reduce LSI size, too.

The authors would like to express their sincere grat-

itude to Dr. Y. Fujita, Dr. R. Shinkuma, Dr. K. Ku-

mamoto, and Dr. S. Nishi for their help in computer

simulation and valuable comments.

〔References〕

1) "ARIB STD-B20 : Digital Broadcasting System and Related Op-erational Guidelines for Broadcasting Satellites," ARIB (Nov., 1998)

2) "Digital Video Broadcasting (DVB): Framing structure, channel coding and modulation for 11/12 GHz satellite services," ETSI Standard EN 300 421 V1.1.2 (Aug. 1997)

3) "ARIB STD-B1 : Digital Receiver for Digital Satellite Broad-casting Services Using Communication Satellites," ARIB (May 1996)

4) "A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite," IEICE Trans. Electron., E84-C, 2, pp. 166-173 (Feb. 2001)

5) "A Survey of CORDIC Algorithms for FPGAs," Proc. of the 1998 ACM/SIGDA sixth international symposium on Field pro-

grammable gate arrays, pp191-200 (Feb. 1998)

Masahide Hatanaka received the B. E. and M. E. degrees in information systems engineer-ing, from Osaka University, Osaka, Japan, in 1999 and 2000 respectively. He is currently a research as-sociate of the Department of Information Systems Engineering, Osaka University. His research inter-ests include wireless communication and implemen-tation of VLSI circuits.

Toshihiro Masaki received the B. E., M. E., and Ph. D. degrees, all in information systems engi-neering, from Osaka University, Osaka, Japan, in 1993, 1995, and 1997, respectively. He joined the Graduate School of Engineering, Osaka University in 1997 as a research associate, where he was pro-moted to an assistant professor in 2000. He is cur-rently an associate professor of the Collaborative Research Center for Advanced Science and Tech-nology, Osaka University. His research interests include intelligent networking systems, Computer-Aided Design and implementation of VLSI Cir-cuits. He is a member of IEEE and IEICE. He was awarded the young engineer award from IEICE in 1998.

Minoru Okada received the B. E. degree in communications engineering from University of Electro-Communications, Tokyo, Japan, in 1990, and the M.E. and Ph. D. degrees both in commu-nications engineering, from Osaka University, Os-aka, Japan, in 1992 and 1998, respectively. Since 1993, he was with Osaka University as a research associate. From 1999 to 2000, he was with the Uni-versity of Southampton, U. K., as a visiting research fellow. In 2000, he joined the Graduate School of Information Science, at Nara Institute of Science and Technology, Nara, Japan, where he is currently an associate professor. He is a member of IEEE, IE-ICE and ITE. He was awarded the young engineer award from IEICE in 1999. Koso Murakami received the B. E., M. E. and Ph.D degrees from Osaka University, Osaka, Japan in 1971, 1973 and 1991 respectively. From 1973 to 1995, he was with Fujitsu Laboratories Ltd., Kawasaki, Japan and engaged in research and development of digital switching systems, Asyn-chronous Transfer Mode switching systems and photonic switching technologies. From 1990 to 1995, he was a Manager of Communications Net-work Systems Laboratory of the same company and was responsible for research and development of broadband ISDN, Intelligent network, Telecommu-nications Management Network and personal com-munication networks. In April 1995, he joined Os-aka University and was a Professor of Computa-tion Center of the same university from 1995 to 1997. From 1998 to 2001 he was a Professor in the

department of Information Systems Engineering of Osaka University. Since 2002, he has been a Pro-fessor of the Department of Information Network-ing in Graduate School of Information & Technol-ogy, newly established in Osaka University. Sincc April 2001 he has concurrently served as Director of the Collaborative Research Center for Advanced Science and Technology of Osaka University. His research interests extends to ultra high speed net-works and multimedia information networking ar-chitecture. Prof. Murakami is a senior member of IEEE and a member of IPSJ.

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