VLSI Arithmetic
Lecture 10:Multipliers
Prof. Vojin G. OklobdzijaUniversity of California
http://www.ece.ucdavis.edu/acsel
Multiplier Design11 May 2004 47
Multiplication
Algorithm:
in
i
iin
i
i ryXryXXYP ∑∑−
=
−
=
×=×==1
0
1
0
0 p)(0 =
)(1)1(j
njj Xyrpr
p +=+ for j=0,....,n-1
initially
p(n)=XY after n steps
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Multiplication Algorithm*
*from Parhami
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Multiplication Algorithm*
*from Parhami
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Multiplication Algorithm*
*from Parhami
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*from Parhami
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Multiplication*
*from Parhami
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Multiplication*
*from Parhami
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Generating Partial Products
*from G. Bewick
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Generating Partial Products
*from G. Bewick
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Parallel Multipliers
Step 0
Step 1
Step 2
Step 3
Step 4
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Minimum Number of Stages (Dada’s Rule)
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Use of 4:2 Compressors
A. Weinberger 1981M. Santoro 1988
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4:2 Compressor
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Re-designed 4:2 Compressor with 3 XOR Delay (Nagamatsu, Toshiba)CinI1
I2I3I4
0
1
S
C
Cout
Multiplier Design11 May 2004 67
Title
0
2
4
6
8
10
12
14
16
18
20
22
24D
elay
(XO
R G
ates
)
0 10 20 30 40 50 60 70 80 90 100
Multiplier Width (bits)
Critical Path: (Equivalent XOR Gate Delays)
3,2 Counter
9to2 Compressor (Redesigned)
4:2 Compressor (Redesigned)
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Tree Multipliers
*from Parhami
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Reduction using 4:2 Compressors
*from G. Bewick
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Use of Higher-Order Compressors
D. Villeger, V.G. Oklobdzija 1993
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Design of a 13:2 Compressor from a 9:2 Compressor
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Compressor Family Characteristics
Idea !!!!!
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Carry Propagate Adder
Vertical Slices
Horizontal PropagationCarry and Sum Connection to the Final Adder
Partial Product Martix Divided into Vertical Compressor Slices
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Example of a 12 X 12 Multiplication
1 0 1 1 0 1 0 1 0 1 0 01 0 1 1 0 1 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 01 0 1 1 0 1 0 1 0 1 0 0
1 0 1 1 0 1 0 1 0 1 0 00 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 1 0 1 0 1 0 01 0 1 1 0 1 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 01 0 1 1 0 1 0 1 0 1 0 0
Vertical Compressor Slice - VCS
(Partial Product for X*Y = B54 * B1B)
FA FA
FA
FA
0 0 1 1 0 1 0
FA
3-Dimensional View of Partial Product Reduction
Time
Final Adder
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AB
Cin Sum
Carry
Signal Delays in a Full Adder(3,2) Counter
∗ Fast Input
♦ Fast Output
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Three-Dimensional optimization Method: TDM(Oklobdzija, Villeger, Liu, 1996)
Method
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sc
cina b
TDM ArrangementWorst Case
4
4
21
44
sc
cina b
24 3
6 1
1
6
3
Multiplier Design11 May 2004 85
Two cases of signals passing through the next level
0 0 0
sc
cina b
sc
cina b
sc
cina b
1
2 11
100 0
02 2
Best Balanced Case Average Case
sc
cina b
2 221 1 0
3 433
Multiplier Design11 May 2004 86
Example of a Optimized Interconnection
sc
cina b
sc
cina b
sc
cina b
sc
cina b
bit (n-1) positionbit (n) position
2 xor0 xor
1 xor
3 xor3 xor
Example of a not Optimized Interconnection
sc
cina b
sc
cina b
sc
cina b
sc
cina b
bit (n-1) positionbit (n) position
2 xor0 xor
1 xor
4 xor3 xor
Example of Delay Optimization
Multiplier Design11 May 2004 87
The 9th Vertical Compressor Slice of a Multiplier
A B
C S
A B Cin
C S
A B Cin
C S
A B Cin
C S
A B Cin
C S
A B Cin
C S
A B Cin
C S
0 0 0 0 0 0 0 0 0 .5 1 1 2 3
.5 1 11 2 22 2.5
3 3 3.5 4
5 5
Computer Tools
Competing Approaches
Their Schemes
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0
2
4
6
8
10
12
14
16
18
20
22
24
Del
ay (X
OR
Lev
els)
0 20 40 60 80 100
Multiplier Width
Equivalent XOR Delays
TDM
Fadavi-Ardekani
9:2
4:2
3,2
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Tree Multipliers
*from Parhami
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Floor Plan of a Multiplier
*from G. Bewick
RECOMENDATIONS
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THEEND
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