BIRLA INSTITUTE OF TECHNOLOGY

SUBJECT : vlsi VLSI/CMOS DESIGN METHODOLOGIES

Submitted By : KUMAR SAURABH

BE/1221/08

CSE’08

ACKNOWLEDGEMENT

It is my pleasure to acknowledge my deep sense of gratitude to Mr. R.K.LAL who directed and guided me with his timely advice and constant admiration which eased the task of completing the semester assignment

I would also like to thank my friends for their kind co-operation and creative criticism.

I am really grateful to my parents for encouraging me to pursue this assignment.

CONTENTS1.MONOLITHIC INTEGRATION

2.DESIGN STRATEGIES

3.STRUCTURED DESIGN STRATEGIES

4.REGULARITY

5.MODULARITY

6.LOCALITY

7.CMOS CHIP DESIGN OPTIONS

8.STANDARD CELLS BASED DESIGN

9.FULL CUSTOM DESIGN

10.GATE MATRIX LAYOUT STYLE

11.DESIGN QUALITY

12.PACKAGING TECHNOLOGY

13.REFRENCES

VLSI/CMOS DESIGN METHODOLOGIES

MONOLITHIC INTEGRATION-> LESS AREA, MORE COMPACTNESS AT ALL SYSTEM LEVELS-> LESS POWER CONSUMPTION

-> LESS TESTING (MORE COMPLEX TESTING)-> HIGHER RELIABILITY, DUE TO IMPROVED ON-CHIPINTERCONNECTS-> HIGHER SPEED DUE TO REDUCED INTERCONNECTLENGTH-> SIGNIFICANT COST SAVINGS

Examine methods to transfer design description in one domaininto a fully equivalent design description in another domain.-> Guiding Design Organization Principles-> Design Options Avialable to CMOS IC DesignersFast PrototypingLow VolumeCustom DesignLabor IntensiveHigh Volume

-> CAD Tools Needed to Achieve the Design Strategies-> Economics of Design-> Data Sheet Preparation

-> Design Strategies: Hierarchy; Regularity; Modularity; Locality-> CMOS Chip Design Options:+ Programmable Logic+ Programmable Logic Structures+ Programmable Interconnect+ Reprogrammable Gate Arrays+ Sea of Gates & Gate Array Design+ Standard Cell Design+ Full Custom Mask Design+ Symbolic Layout+ Process Migration - Retargeting Designs-> Design Methods:+ Behavioral & RTL Synthesis+ Logic Optimization

+Structural-To-Layout Synthesis

Design StrategiesDesign Parameters By Which Design Success Is Measured:Performance Specs - function, timing, speed, powerSize of Die - manufacturing costTime to Design - engineering cost and scheduleEase of Test Generation & Testability - engineering cost, manufacturingcost, schedule

Design is a continuous tradeoff to achieve performance specs with adequateresults in all the other parameters.

Structured Design StrategiesTechniques evolved for complex harware and software projects.

-> Hierarchy: Subdivide the design into many levels of sub-modules-> Regularity: Subdivide to max number of similar sub-modules at each level-> Modularity: Define sub-modules unambiguously & well defined interfaces-> Locality: Max local connections, keeping critical paths within moduleBoundaries

REGULARITY-> Circuit Level: uniform transistor sizes rather than manually optimizing eachdevice.-> Logic Level: identical gate structures rather than customize every gate.-> Architecure Level: construct architecures that use a number of identicalprocessor structuresDESIGN THE CHIP HIERARCHY INTO LIKE OR SIMILAR MODULES

EXTENDED USE OF REGULARITY SIMPLIFIES THE DESIGN PROCESSREGULARITY CAN EXIST AT ALL LEVELS OF DESIGN HIERARCHY

MODULARITYADDS TO HIERARCHY AND REGULARITY THE QUALITIES OFWELL DEFINED FUNCTIONS AND INTERFACES-> Unambiguous function-> Well defined behavioral, structural, and physical interfaces-> Enables modules to be individually designed and evaluated.

LOCALITY

TIME LOCALITY: modules see a common clock and synchronous timing isapplied.-> Robust clock generation and distribution is critical-> Critical paths, where possible, are to be kept within module boundaries-> Any global module to module signal should have an entire clock cycle totraverse the chip.-> Replicate logic, if necessary, to alleviate cross-chip crossings.-> Locate modules in layout to minimize large or "global" routes betweenmodules.

CMOS CHIP DESIGN OPTIONS-> Programmable Logic-> Programmable Logic Structures-> Programmable Interconnect

-> Reprogrammable Gate Arrays-> Sea of Gates & Gate Array Design-> Standard Cell Design-> Full Custom Mask Design

STANDARD-CELLS (POLYCELL) BASED DESIGN-> Predominant full-custom design style.-> Standardization is achieved at the logic or function level.-> Specific designs for each gate can developed and stored in a softwaredatabase or cell library.+ Behavioral, Structural, and Physical Domain descriptions per cell-> Layout is usually automatically placed and routed using CAD software.Typical Standard Cell Library contents:-> SSI logic: e.g. nand, nor, xor, inverters, buffers, latches, registers+ Each gate can have multiple implementations to provide proper

drive for different fan-outs, e.g. standard size, 2x, 4x-> MSI logic: e.g. decoders, encoders, adders, comparators-> Datapath: e.g. ALUs, adders, register files, shifters-> Memories: e.g. RAM, ROM-> System level blocks: e.g. multipliers, microcontrollers

SSI/LSI blocks: layout style is rows of constant hight blocks separatedby rows of routing.SSI/LSI standard cell concept is extended to higher level functions, oftenavailable as parameterized modules

FULL (or FULLER) CUSTOM DESIGN 22

-> ENTIRE CHIP DESIGNED AT TRANSISTOR LEVEL WITH NOSTANDARD CELLS

+ Very High Development Cost - Smallest Die Area+ Used in Highly Repetitive ImplementationsGATE MATRIX LAYOUT STYLE-> Extensioon of standard cell “Manhattan” style layout to arbitary logicfunctions.-> Transistors palced in a grid, with vertical poly columns to form gatesand interconnect and horizontal metal runners for interconnect.-> Used a sympolic layout method (ASCII symbols -> mask feature)“P” -> pMOS transistor“N” -> nMOS transistor“*” -> contacts and vias“__” -> horizontal metal runners“|” -> vertical poly columns

DESIGN QUALITY

-> ACHIEVE SPECIFICATIONS (Static & Dynamic)-> DIE SIZE->POWER DISSIPATION-> TESTABILITY-> YIELD AND MANUFACTURABILITY->RELIABILITY->TECHNOLOGY UPDATABLE

-> TESTABILITY+ generation of good test vectors+ availablity of reliable test fixture at speed+ design of testable chip-> YIELD AND MANUFACTURABILITY+ functional yield+ parametric yield->RELIABILITY+ premature aging (Infant mortality)+ temperture dependence+ on-chip noise and crosstalk+ latchup->TECHNOLOGY UPDATABLE

+ Easily updated to new design rules

PACKAGING TECHNOLGY-> INCLUDE IMPORTANT PACKAGE RELATEDPARASITICS IN THE CHIP DESIGN AND SIMULATION <--> Package Power & Ground Planes -> on-chip power and ground busses-> Bond Wire Lengths -> on-chip inductive effects-> Thermal Resistance -> temp rise due to on-chip power dissipation-> Package CostIMPORTANT PACAKGE DESIGN CONCERNS:-> hermeticity to prevent penetration of moisture-> thermal conductivity-> thermal expansion coefficient-> pin density-> parasitic inductance and capacitance

-> -paricle protection

REFRENCES1.PRINCIPLE OF CMOS VLSI DESIGN

-WESTE AND ESHRAGHIAN

2.WWW.GOOGLE.COM

3.WWW.WIKEPEDIA.ORG