VLSI Chip Design with the Hardware Description Language VERILOG

Springer-Verlag Berlin Heidelberg GmbH

Ulrich Golze

VLSI Chip Design with the Hardware Description Language VERILOG An Introduction Based on a Large RISe Processor Design

With Peter Blinzer, Elmar Cochlovius,

Michael Schafers, and Klaus-Peter Wachsmann

Springer

Prof. Dr. Ulrich Golze

Department of Integrated Circuit Design (E.I.S.) Technical University of Braunschweig P.O. Box 33 29 D-38023 Braunschweig, Germany E-mail: golze@eis.cs.tu-bs.de

Ulrich Golze received a Diploma in Mathematics and a PhD in Computer Science at the University of Hannover, Germany, an M.A. of Computer and Communication Sciences at the University of Michigan, Ann Arbor, Michigan, USA, and an M.B.A. of Business Administration at the European Business School INSEAD in Fontainebleau, France.

With 176 Figures and 80 Tables Includes Diskette

ISBN 978-3-642-64650-8 ISBN 978-3-642-61001-1 (eBook) DOI 10.1007/978-3-642-61001-1

Additional material to this book can be downloaded from http://extras.springer.com

Library of Congress Cataloging-in-Publication Data applied for

Die Deutsche Bibliothek - CIP-Einheitsaufnahme

VLSI chip design with the hardware description language VERI LOG : an introduction based on a large RISC processor design I Ulrich Golze. - Berlin; Heidelberg; New York; . Barcelona; Budapest; Hong Kong; London; Milan; Paris; Santa Clara; Singapore; Tokyo: Springer.

NE: Golze, Ulrich

Buch, - 1996

This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on micro-film or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable for prosecution under the German Copyright Law.

© Springer-Verlag Berlin Heidelberg 1996 Softcover reprint of the hardcover 1st edition 1996

The use of general descriptive names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.

Cover Design: Meta Design, Berlin Typesetting: Camera ready by author SPIN 10502185 45/3142 - 5 432 1 0 - Printed on acid-free paper

Preface

The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical, and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, designing with hardware description languages (HDL) similar to programming lan­guages is at the center of digital circuit design. HDL based design is one of the centers of this book.

The successful design of small circuits is no problem today, but the demands on a design team are high when designing large real circuits. The second center is therefore a complete design of a real modern RISC processor with an efficiency in the range of a SPARC.

After an introduction also considering the economic importance of chip design as a key technology, Chapter 2 gives an overview of VLSI design (Very Large Scale Integration). The third chapter leads to modern RISC processors and prepares coarse design decisions. Due to the central role of hardware descrip­tion languages, Chapter 4 contains a short and Chapter 11 an extensive intro­duction to the HDL VERILOG and to typical modeling techniques. Numerous examples as well as a VERILOG simulator are included on the disk.

The RISC processor TOOBSIE to be designed is specified externally in Chapter 5 by its behavior, its instructions, and an HDL interpreter as a reference. The internal specification in the next chapter determines a coarse architecture. The central HDL model is the Coarse Structure Model that is completely and executably included on the disk in 013. The datapath pipeline of this model is explained in Chapter 7.

The Coarse Structure Model is suited for a semi-automatic translation int.o a Gate Model based on the component library of the silicon vendor. This Gate Model will be synthesized in Chapter 8 using selected examples. Finally, Chapter 9 treats the subjects testing, testability, tester, and testboard and discloses, whether the produced processor is actually functioning. A general outline concludes the volume.

vi Preface

This book is addressed to computer scientists and electrical engineers, but also managers, hence to practitioners designing chips or considering their appli­cation. It introduces

• modern VLSI design;

• semi-custom design of large chips;

• the hardware description language VERILOG HDL;

• the design of a modern real RISC processor;

• HDL modeling of large designs;

• specification, behavior, structure, HDL model, gate model, test, and testability.

As a textbook, this volume is self-contained and complete. Experts, however, may want to understand the RISC processor design at selected points or even completely, possibly as a base for the development of their own CAD tools and design methods. For this expert, there is an expert volume also containing all graphical "schematics" of the Gate Model (p. 359).

Figures and tables are numbered together per chapter. Chapter numbers beginning with an H such as H5.3 refer to the more hardware-oriented expert volume.

The Team of a Large Project

A project of this size is developed in a team, even worse, in a changing team. The figure on the next page shows a hierarchy without "up" and "down", and every level without a first or last position. Without the assistants of the second ring, the project would not have been accomplished. The students of the third ring were particularly engaged. Peter Blinzer has moved by unusual commit­ment from the outer to the middle ring.

It all began with an idea of Michael Schafers, which the author declared as impractical, not only for reasons of cost. He developed together with Klaus­Peter Wachs mann the training processor and predecessor TOOBSIE1. Later, the daily project management was done by Michael Schafers and also by Klaus­Peter Wachsmann. Together with Elmar Cochlovius joining the team later, they have worked out the external and internal specification with all archi­tectural details (Chapters 5 and 6).

The documentation of a large project is often unpopular, but often also decisive for the project. Elmar Cochlovius has managed (not (mly) this task; he was documenting by himself, and - more difficult - has motivated others to prepare

Preface vii

documentation as a base for this book. In addition to the practical chip design, all three assistants have performed PhD research on design methodology (Chapter 10). As just one example, we mention the research of Elmar Cochlovius on high-level specification with statecharts.

-g .. g.. ID

(\)

Peter Blinzer, Rudiger Bodack, Klaus Meyer, and Sebastian Steibl have worked out the VERILOG models, in particular the Coarse Structure Model, and have commented on them (Chapters 7, H3, H4, ~2, and 03). Peter Blinzer was also the major force for the Gate Model (Chapters 8 and H5).

Gerrit Telkamp has designed simple and complicated testboards and has tested the processor in the tester and on the board. Together with Peter Blinzer, he has prepared Chapter 9 on test. The latter has worked out the production test.

Claude Ackad has prepared as a book within the book the extensive VERILOG introduction (Chapters 4 and 11) and has become unpopular as a quality assurer of our documentation. Thomas Scholz designed operating systems for various testboards.

Matthias Bodenstein did not lose his joy in designing graphics until the last figure. Jiirgen Hannken-Illjes transformed technical schematics into print­able figures using methods of pattern recognition.

Karsten Dageforde, Matthias Mansfeld, Gerrit Mierse, Frank Prielipp, Jorg Reitner, Heiko Stuckenberg, Dirk Wodtke, and Florian Buchholz have delivered important contributions on the (invisible) fourth ring.

viii Preface

The project was performed at the Department of Integrated Circuit Design (E.I.S.) at the Technical University of Braunschweig. It was enabled by the support of LSI Logic Corp., the ESPRIT project EUROCHIP, the Lower Saxony Ministery of Science and Culture (MWK) and the Federal Ministery of Edu­cation and Science (BMBW), and a Volkswagen grant.

We are especially grateful to Wellspring Solutions Corp. for offering the simulator VeriWell to the readers of this book. It is included on the disk without any warranty; there are no restrictions on the use and application purpose.

Without encouragement and criticism of my publisher Springer, this work would not have been completed.

I started learning German at the age of 1 or so, English at 10, and began to prefer American at 24 when studying at the University of Michigan. Unfortunately, it will never be possible to make up for this delay of 9 years. I apologize for all those phrases that you as the reader would have expressed more smoothly.

Formerly, I doubted the value of dedications in books, until I myself started neglecting my family for my book: for Barbara, Christian, and Fabian.

Braunschweig, September 1995 Ulrich Golze

Contents

1 Introduction .................................................................................. 1

2 :Design ofVLSI Circuits .................................................................. 9

2.1 Technological Foundations and Design Styles .. .... .... .......................... 9 2.2 The Design Process ........................................................................ 14 2.3 The Design Phases ......................................................................... 17

3 RISC Architectures........................ ....... ........ ..................... ............ 25

3.1 A Simple RISC Processor ................................................................ 27 3.2 Selection of a Processor Architecture ................................................ 31

3.2.1 Proposals for Architectural Extensions ................................. 32 3.2.2 Evaluation of Proposals ........................................................ 34 3.2.3 Summary of Extensions Accepted ......................................... 36

4 Short Introduction to VERILOG ....................................................... 39

5 ExtemalSpecificationofBehavior .................................................... 47

5.1 The RISC Processor at Work ............................................................ 48 5.1.1 The Assembler ................................................................... 48 5.1.2 The Testboard ..................................................................... 49

5.2 The Instruction Set ......................................................................... 49 5.2.1 Class LD/ST of Load and Store Instructions ............................ 52 5.2.2 Class eTR of Branch Instructions ......................................... 53 5.2.3 Class ALU of Arithmetic and Logic Instructions ..................... 55 5.2.4 Instructions of Class Special ................................................ 56 5.2.5 Synthetic Instructions ......................................................... 57 5.2.6 External Specification ofInterrupts ...................................... 57

5.3 An Interpreter as a VERILOG HDL Model ........................................ 59 5.3.1 Overview ............................................................................ 61 5.3.2 Components ....................................................................... 63 5.3.3 Application ........................................................................ 66

5.4 Specification of Test Strategy ............................................................ 69 5.5 Quantitative Specifications .............................................................. 70

x Contents

6 Internal Specification of Coarse Structure ................................... ...... 73

6.1 Data Flow ...................................................................................... 74 6.1.1 Execution ofInstructions in the Datapath .............................. 75 6.1.2 A Pipeline for the Datapath .................................................. 75 6.1.3 Pipeline Features Visible in Applications .............................. 76

6.2 Timing.......................................................................................... 79 6.2.1 A Simple Clocking Scheme .................................................. 79 6.2.2 The Bus Protocol ................................................................. 80

6.3 Pipeline Stages ............................................................................... 84 6.3.1 Scheme and Naming of a General Pipeline Stage .................... 84 6.3.2 Instruction Fetch Stage IF .................................................... 87 6.3.3 Instruction Decode Stage 10 .................................................. 88 6.3.4 Execute Stage EX ................................................................. 92 6.3.5 Memory Access Stage MA ..................................................... 94 6.3.6 Write-Back Stage WB ........................................................... 95 6.3.7 Summary of Pipeline Actions ............................................... 96

6.4 Caches and Register File ................................................................. 98 6.4.1 Multi-Purpose Cache MPC ................................................... 99 6.4.2 Branch-Target Cache BTC .................................................. 100 6.4.3 Cooperation of MPC and BTC with the Pipeline ...................... 107 6.4.4 The Register File ................................................................ 109

6.5 Internal Specification ofInterrupts ................................................. 110

7 Pipeline of the Coarse Structure Model ............................................ 113

7.1 The Processor CHIP ....................................................................... 118 7.2 The Instruction Fetch Unit IFU ....................................................... 123

7.2.1 I_BUS Multiplexer ............................................................. 126 7.2.2 IFU_AOOR_BUS Multiplexer ............................................... 127 7.2.3 NPC_BUS Multiplexer ........................................................ 128 7.2.4 Branch-Target Cache BTC .................................................. 128 7.2.5 Multi-Purpose Cache MPC .................................................. 129

7.2.5.1 Instruction Write Logic IWL ................................... 130 7.2.5.2 Instruction Cache ICACHE .................................... 131

7.2.6 Branch Decision Logic BOL ................................................. 132 7.2.7 Program Counter Calculator PCC ....................................... 133 7.2.8 Pipeline Disable Logic POL .................................................. 134 7.2.9 Instruction Decode Logic 10L ............................................... 135 7.2.10 Serial-Mode Controller SMC ................................................ 137 7.2.11 External PC Logic EPL ........................................................ 138

7.3 The Instruction Decode Unit IOU ..................................................... 139 7.3.1 Decode Group OG1 ............................................................. 141 7.3.2 Decode Group OG2 ............................................................. 142 7.3.3 Decode Group OG3 ............................................................. 143 7.3.4 Decode Group OG4 ............................................................. 144 7.3.5 Decode Group OG5 ............................................................. 145 7.3.6 Decode Group OG6 ............................................................. 146

7.4 The Arithmetic Logic Unit ALU ....................................................... 147 7.4.1 Module ARITHMETIC ........................................................... 151 7.4.2 Module LOGIC ................................................................... 152 7.4.3 Module SHIFT .................................................................... 152

7.5 The Memory Access Unit MAU ........................................................ 152

Contents xi

7.6 The Forwarding and Register Unit FRU ........................................... 154 7.6.1 Register Address Converter RAC ......................................... 157 7.6.2 Forwarding Comparator CMP ............................................. 157 7.6.3 Forwarding Selection Logic FSL .......................................... 159 7.6.4 Register Access Logic RAL .................................................. 160 7.6.5 Data and Address Pipeline .................................................. 161

7.7 Building a Complete Processor ....................................................... 161

8 Synthesis of Gate Model ................................................................. 163

8.1 The Library of the Silicon Vendor .................................................... 164 8.1.1 Gates ................................................................................ 164 8.1.2 Internal Buffers ................................................................. 165 8.1.3 Flip-Flops .......................................................................... 165 8.1.4 Latches ............................................................................. 166 8.1.5 Input Clock Drivers ............................................................ 166 8.1.6 Input Buffers ..................................................................... 166 8.1.7 Unidirectional Output Buffers ............................................. 166 8.1.8 Bidirectional Tristate Output Buffers .................................... 166 8.1.9 Test Cell as a Megafunction ................................................ 166 8.1.10 Adder as a Megafunction .................................................... 167 8.1.11 Shifter as a Megafunction ................................................... 167 8.1.12 Custom-Specific RAM Library as a Megafunction ................... 167 8.1.13 Internal Buffers as Self-Developed Library Cells .................... 167 8.1.14 Flip-Flops as Self-Developed Library Cells ............................. 167 8.1.15 Multiplexers as Self-Developed Library Cells ......................... 168

8.2 Manual Synthesis ......................................................................... 169 8.2.1 Synchronous Data Transfer ................................................ 169 8.2.2 Registers with Combinational Logic ..................................... 171 8.2.3 Register Pipeline ................................................................ 171 8.2.4 Multiplexers for Data Selection ............................................ 175 8.2.5 Constant Assignment ......................................................... 177 8.2.6 Variable Assignment ......................................................... 177 8.2.7 Indirect Synthesis of Behavioral Parts .................................. 179

8.3 Support by Logic Synthesis ............................................................. 181 8.3.1 Synthesis Tools .................................................................. 181 8.3.2 Example of a Logic Synthesis ............................................... 181

8.4 A Larger Example ......................................................................... 185 8.4.1 Synchronous Data Transfer ................................................ 185 8.4.2 Combinational Logic .......................................................... 187 8.4.3 Multiplexers for Data Selection ............................................ 189 8.4.4 Indirect Synthesis .............................................................. 191 8.4.5 Variable Assignment ......................................................... 194

8.5 The Asynchronous Bus Protocol as a Special Case ............................ 197 8.6 Statistics and Experiences .............................................................. 197 8.7 Simulation and Optimization of the Gate Model ................................ 199

8.7.1 Verification ....................................................................... 200 8.7.2 Optimization ..................................................................... 201 8.7.3 Timing Simulation ............................................................. 202

xii Contents

9 Testing, Testability, Tester, and Testhoard ....................................... 205

9.1 Fault Models and Fault Coverage .................................................... 206 9.2 Automated Tester (ATE) ................................................................ 209

9.2.1 Set-up and Operation of Tester ............................................. 210 9.2.2 Formats and Templates ...................................................... 212

9.3 Design for Testability ..................................................................... 214 9.3.1 Multiplexers for Memory Test ............................................. 215 9.3.2 Scanpath ................................................................ ; .......... 216 9.3.3 Signature Analysis ............................................................ 216 9.3.4 Test Circuits of the Silicon Vendor ....................................... 217

9.4 Functional Test ............................................................................. 220 9.5 Extraction of Test Data ................................................................... 223

9.5.1 Requirements on Test Patterns and Test Blocks ..................... 223 9.5.2 Tristate, Quiescent Current, Process, and Memory Test ......... 224 9.5.3 Functional Test .................................................................. 225 9.5.4 Evaluation of Test Patterns .................................................. 226 9.5.5 Preparation of ATE Test Data .............................................. 227

9.6 ATE Test ...................................................................................... 230 9.6.1 Set-up ofDUT Card ............................................................ 230 9.6.2 Conducting the Tests .......................................................... 232 9.6.3 Test Results ....................................................................... 233

9.7 Testboard ..................................................................................... 235 9.7.1 Backplane ......................................................................... 237 9.7.2 PC-Interface Card and Bus-Interface Card ........................... 238 9.7.3 Memory Card .................................................................... 241 9.7.4 CPU Card ......................................................................... 242 9.7.5 Evaluation ......................................................................... 243

9.8 To Be Honest ................................................................................. 244

10 Summary and Prospect .................................................................. 247

10.1 Efficiency and Complexity .............................................................. 249 10.2 Specification, Analysis, and Simulation of Large VLSI

Designs with Statecharts and Activitycharts .................................... 251 10.3 Fault Models and Test Patterns for HDL Models ............................... 254

HDL Models for Circuits and Architectures -A Supplementary Introduction Based on the

Contents xiii

Hardware Description Language VERILOG ................................... 259

11 HDL Modeling with VERILOG ....................................................... 261

11.1 Syntax Fonnat EBNF ..................................................................... 262 11.2 VERILOG Statements .................................................................... 263

11.2.1 Structural Statements ........................................................ 264 11.2.2 Variable Declaration .......................................................... 270 11.2.3 Operations ........................................................................ 276 11.2.4 Program Control ................................................................ 284 11.2.5 Miscellaneous Statements ................................................... 296 11.2.6 Verilog-XL Statements ....................................................... 2ffl

11.3 Basic Modeling Concepts ................................................................ 302 11.3.1 Parallelism and Event Control of the Simulator ..................... 302 11.3.2 Time Control ..................................................................... 305 11.3.3 Hierarchies of Modules and Instances ................................. 309 11.3.4 Behavior and Structure Models ............................................ 310 11.3.5 Arrays of Variables ............................................................ 311 11.3.6 Modules and Groups .......................................................... 311 11.3.7 Bidirectional Communication ............................................. 312 11.3.8 Some Practical Guidelines .................................................. 315

11.4 Examples ..................................................................................... 315 11.4.1 A Simple Pipeline .............................................................. 315 11.4.2 A Complex Pipeline ............................................................ 318

11.4.2.1 Interfaces ............................................................ 319 11.4.2.2 FIFOs ................................................................... 319 11.4.2.3 ALU ..................................................................... 320 11.4.2.4 Test Module ......................................................... 320 11.4.2.5 VERILOG Model .................................................. 322 11.4.2.6 Simulation Output ................................................ 327

11.4.3 Behavior Model of Processor ASIC ........................................ 327 11.4.3.1 Instructions ......................................................... 327 11.4.3.2 VERILOG Model .................................................. 328 11.4.3.3 Simulation Output ................................................ 331

11.4.4 Structure Model of Processor ASIC ....................................... 332 11.4.4.1 Module memory .................................................... 332 11.4.4.2 Module regcntr .................................................. 333 11.4.4.3 Module a 1 u .......................................................... 333 11.4.4.4 Module controller ............................................ 334 11.4.4.5 Module system .................................................... 335 11.4.4.6 Module application .......................................... 335 11.4.4.7 VERILOG Model .................................................. 335 11.4.4.8 Simulation Output ................................................ 343

11.5 EBNF Syntax of Statements ............................................................. 343

Bibliography ........................................................................................ 347

Index .................................................................................................. 353

Expert Volume ..................................................................................... 359

xiv Contents

DISK

o Read Me First

1 VERILOG Examples

2 VERILOG Source Code of the Interpreter Model

3 VERILOG Source Code of the Coarse Structure Model

3.1 Processor CHIP

3.2 Instruction Fetch Unit IFU

3.3 Instruction Decode Unit IDU

3.4 Arithmetic Logic Unit AlU

3.5 Memory Access Unit MAU

3.6 Forwarding and Register Unit FRU

3.7 Pipeline Control Unit PCU

3.8 Bus Control Unit BCU

3.9 System Environment SYSTEM

3.10 Service Modules 3.10.1 Control File TEST 3.10.2 Statistics TRACE 3.10.3 Memory and Register Output DUMP 3.10.4 Graphic Output GRAPHWAVES 3.10.5 Bus Monitor CHECKBUS 3.10.6 Control MCTRl

4 An Operating System and Larger Examples

4.1 Operating System VOS

4.2 Example Programs 4.2.1 Ackermann Function 4.2.2 Factorial 4.2.3 Quicksort 4.2.4 Dhrystone

4.3 Control File TEST

5 Simulator VeriWell for PC

6 Simulator VeriWell for SUN Spare