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VLSI Circuit Design UltraSparc T2 (8 cores, 65 nm) [Source: http://blogs.sun.com/ontherecord/entry/ultrasparc_t1_world_s_fastest] João Canas Ferreira (FEUP) PCVL 2019-02-14 1/5
VLSI Circuit Design
UltraSparc T2 (8 cores, 65 nm)[Source: http://blogs.sun.com/ontherecord/entry/ultrasparc_t1_world_s_fastest]
João Canas Ferreira (FEUP) PCVL 2019-02-14 1 / 5
VLSI Circuit Design
TopicsI Integrated circuit (IC) design flowI Design of CMOS digital circuits
I MOS transistor modelingI Fabrication process and design rulesI MOS logic families (incl. transmission gates, dynamic families)I Sizing of logic gatesI Latches and flip-flopsI Interconnect modelingI Low-power circuitsI FPGA architecture
I IC DesignI Project: Full-custom layout ⇒ Fabrication dataI Circuit analysis and exercises (lab classes)
João Canas Ferreira (FEUP) PCVL 2019-02-14 2 / 5
Readings
I Digital Integrated Circuits: A Design PerspectiveJan M. Rabaey, Anantha Chandrakasan, Borivoje NikolicPrentice-Hall, 2nd ed.
I Application-Specific Integrated CircuitsMichael J. S. Smith; Addison-Wesley
I CMOS VLSI Design: A Circuits and Systems Perspective, 4/ENeil Weste & David Harris; Addison-Wesley(alternative to Rabaey et al.)
I Digital VLSI Chip Design with Cadence and Synopsys CAD ToolsErik Brunvand; Addison Wesley
I Lecture slides (concise; take notes)
I Solved exams and additional info athttps://paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2018-19
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Class work and grading
I One design project: PI One test on circuit analysis: TI Exam: E
Distributed evaluation
NDist = 0.7× P + 0.3× T
Minimum grade: NDist >= 8.0
Final grade
NFinal = 0.6× NDist + 0.4× E
Conditions: E >= 6.0 and NFinal >= 10.
João Canas Ferreira (FEUP) PCVL 2019-02-14 4 / 5
Contacts
I João Canas Ferreira
Email: [email protected] Room I237
Office hours: Fridays, 14:00–16:00 or by appointment
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