P.E.S. Institute of Technology – Course Information – M. Tech (VLSI DESIGN & EMBEDDED SYSTEM) 2nd Semester Dept of ECE - 5-
Components: mechanisms,29 RTOS system software mechanisms30 RTOS system software mechanisms,31 RTOS system software mechanisms,32 Software application components33 Software application components
Chapter IX34
DebuggingComponents:
Exceptions assert, Checking return codes,
16 80
35 Single-step debugging36 kernel scheduler traces,37 Test access ports,38 Trace ports, Power-On self test and diagnostics,39 Trace ports, Power-On self test and diagnostics,40 External test equipment,41 Application-level debugging.
Chapter X
42 PerformanceTuning:
Basic concepts of drill-down tuning, hardware –
supported profiling and tracing, Buildingperformance monitoring into software 5 8543 Path length, Efficiency, and Call frequency,44 Fundamental optimizations.
Chapter XI
45High availabilityand Reliability
Design:
Reliability and Availability, Similarities anddifferences,
Reliability, Reliable software, 3 88
46Available software, Design trade offs,
Hierarchical applications for Fail-safe designChapter XII
47-52Design of RTOS – PIC microcontroller. ( Chap 13 fromref book 2 - Myke Predko)
12 100
Note: Supported by 2 hours of Lab sessions every week.
Literature:
Book Type Code Title & AuthorPublication info
Edition Publisher year
Reference Book 1Real-Time Embedded Systems and
Components , Sam Siewert1st
CengageLearning India
Edition2007
Reference Book 2Programming and Customizing the PIC
P.E.S. Institute of Technology – Course Information – M. Tech (VLSI DESIGN & EMBEDDED SYSTEM) 2nd Semester Dept of ECE - 6-
Real Time Operating Systems:Laboratory Experiments
USE LINUX/SOLARIS/QNX OS ONLY.
1. Implement simple IPC protocol.
2. Implement Semaphore and Mutex for any given applications.
3. Communicate between 2 PCs using Socket programming or message passing techniques (ie., MPI).
4.Create „n. number of child threads. Each thread prints the message “ I.m in thread number …” and sleeps for 50 ms andthen quits. The main thread waits for complete execution of all the child threads and then quits. Compile and execute inLinux.
5. Implement the multithread application satisfying the following :
i. Four child threads are crated with normal priority.
ii. Thread 1& 2 receives and prints its priority and sleeps for 50ms and then quits.iii. Thread 3&4 prints the priority of the thread 1 &2 and rises its priority to above normal andretrieves the new priority of thread 1, prints it and then quits.iv. The main thread waits for the child thread to complete its job and quits.
6. Implement the usage of send and receive primitives with 512 bytes for data sharing between parent andchild processes using handle inheritance mechanism.
7. Test the program below using multithread application-
1. The main thread creates a child thread with default stack size and name ‘Child_Thread’.
2. The main thread sends user def ined messages and the message ‘WM_QUIT’ randomly to thechild thread.3. The child thread processes the message posted by the main thread and quits when it receivesthe ‘M_QUIT’ messge.4. The main thread checks the termination of the child thread and quits when the child threadcomplete its execution.5. The main thread continues sending the random messages to the child thread till the‘M_QUIT’ message is sent to child thread.6. The messaging mechanism between the main thread and child thread is synchronous.8. Test the program application for creating an anonymous pipe with 512 bytes of size and pass the „ReadHandle. of the pipe to a second process using memory mapped object. The first process writes a message „ Hifrom ‘Pipe Server’. The 2nd process reads the data written by the pipe server to the pipe and displays it on theconsole. Use event object for indicating the availability of data on the pipe and mutex objects for synchronizingthe access in the pipe. For synchronization semaphore / mutex can be used.
9. Create a POSIX based message queue for communicating between several tasks as per the requirementsgiven below:-
i. Use a named message queue with name ‘MyQueue’. ii. Create N tasks with stack size 4000 & priorities (n-1) & n respectively. N can be any number butmore than 4.
P.E.S. Institute of Technology – Course Information – M. Tech (VLSI DESIGN & EMBEDDED SYSTEM) 2nd Semester Dept of ECE - 7-
iii. Tasks creates the specified message queue as Read Write and reads the message present, if any,from the message queue and prints it on the console.iv. Tasks open the message queue and posts the mes sage ‘Hi from Task(n -1)’.v. Handle all possible error scenarios appropriately.
MINI PROJECTS: (optional)
1. Implement protocol converter (refer book 3 given in the RTOS theory)2. Implement System Calls for the RTOS using RTLinux.3. Implement an IP phone.4. Implement Device Driver.
P.E.S. Institute of Technology – Course Information – M. Tech (VLSI DESIGN & EMBEDDED SYSTEM) 2nd Semester Dept of ECE - 8-
Subject: Advanced Microcontrollers
Faculty: Subject code: 10EC 116 Hours: 52
Class #
ChapterTitle/Reference
Literature Topics to be Covered
% of Portion Covered Reference chapter Cumulative
UNIT-1
10% 10% 1
Motivation foradvanced
microcontrollers
Low Power embedded systems 2 On-chip peripherals 3 Low power RF capabilities 4 Examples of applications UNIT -2
20% 30%
9
MSP430 – 16-bitMicrocontroller
family
CPU architecture 10-11 Instruction set 12 Interrupt mechanism 13 Clock system, 14 Memory subsystem 15 bus –architecture 16-18 The assembly language and C
programming for MSP-430microcontrollers
UNIT-3
20% 50%
19
MSP430 – 16-bitMicrocontroller
family
On-chip peripherals 20 WDT, Comparator 21 Op-Amp, Timer 22 Basic Timer, Real Time Clock (RTC) 23-24 ADC, DAC 25 Digital I/O 26 Using the low-power features of
MSP430 27 Clock system 28 low-power modes, Clock request
feature 29-30 Low-power programming and
interrupts UNIT-4
40% 90%
31
ARM -32 bitMicrocontroller
family
Architecture of ARM Cortex M3 32-33 General Purpose Registers 34 Stack Pointer, Link Register 35 Program Counter, Special Register 36 Nested Vector Interrupt Controller 37 Interrupt behavior of ARM Cortex M3 38-39 Exceptions Programming 40-43 Advanced Programming Features 44 Memory Protection 45 Debug Architecture
System on Chip Design options: Programmable logic and structures,Programmable interconnect, programmable gate arrays, Sea of gateand gate array design, standard cell design
, full custom mask design, Behavioral synthesis, RTL synthesis, Logicoptimization and structural tools layout synthesis, layout synthesis,EDA Tools for System, HDL Design, Schematic Design, Layout Design,Floor planning and Chip Composition.
Finite State Machine (FSM) Design, Control Logic Implementation:PLA control implementation, ROM control implementation.
3.8 65.2
Special PurposeSubsystems
(34-40)
Packaging, power distribution, I/O, Clock, Transconductanceamplifier, follower integrated circuits, etc
13.4 78.6
VLSI System Testing &Verification
(41-48)
Introduction, A walk through the Test Process, Reliability, LogicVerification Principles, Silicon Debug Principles, Manufacturing TestPrinciples, Design for Testability, Boundary Scan
15.3 93.9
VLSI Applications(49-52) RISC microcontroller, ATM Switch, etc. 8.1
P.E.S. Institute of Technology – Course Information – M. Tech (VLSI DESIGN & EMBEDDED SYSTEM) 2nd Semester Dept of ECE - 12 -
Low Power VLSI Design
Faculty: Subject Code : 10EC047 Hours: 52
Class#
ChapterTitle/Reference
LiteratureTopics to be Covered
% of Portion CoveredReference
chapterCumulative
UNIT-1
15.3% 15.3%
1
Introduction
Need for low power VLSI chips
2sources of power dissipation on digital Integratedcircuits
3sources of power dissipation on digital Integratedcircuits
4 Emerging low power approaches5 Physics of power dissipation in CMOS devices6 Physics of power dissipation in CMOS devices7 Physics of power dissipation in CMOS devices8 Physics of power dissipation in CMOS devices
UNIT-2
7.6%22.9%
9Device and
Technology Impacton Low power
Dynamic dissipation in CMOS10 Transis tor sizing and gate oxide thickness11 Impact of technology scaling12 technology and device innovation
UNIT-3
11.5% 34.4%
13
Power estimation,simulation Power
analysis
SPICE circuit simulators14 gate level logic simulation15 capacitive power estimation
16static state power, gate level capacitanceestimation
17architecture level analysis, data correlationanalysis in DSP systems
18 Monte Carlo simulationUNIT-4
7.642%
19Probabilistic power
analysis
Random logic signals20 probability and frequency21 probabilistic power analysis techniques22 signal entropy
UNIT-5
7.6% 49.6%
23Low power design
circuit level
Power consumption in circuits24 flip flops and latches design25 high capacitance nodes26 low power digital cells library
UNIT-6
9.6% 59.6%
27
Low power designLogic Level
Gate re organization28 signal gating29 logic encoding30 state machine encoding31 precomputation logic
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