1VLSI Design: CMOS Technology
VLSI DesignCMOS Technology
Frank Sill TorresUniversidade Federal de Minas Gerais (UFMG), Brazil
CMOS VLSI Design 4th Ed. 2
Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
CMOS VLSI Design 4th Ed. 3
Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
CMOS VLSI Design 4th Ed.
Dopants
N-type: One silicon atom has been replaced by atom w/ one extra electron
Extra electron w/o bonding partner
P-type: One silicon atom has been replaced by atom that lacks a bonding electron
Hole formed w/ need for an electron
4
CMOS VLSI Design 4th Ed. 5
p-n Junctions A junction between p-type and n-type semiconductor
forms a diode. Current flows only in one direction
anode cathode
CMOS VLSI Design 4th Ed.
Field Effect Transistor (FET)
6
Positive voltage attracts electrons
Terminal is above material (no connection)
Negative voltage repels electrons and creates holes
CMOS VLSI Design 4th Ed.
Depletion Mode FET
8
Negative Voltage turns off
Normally on (when no voltage is applied)
CMOS VLSI Design 4th Ed.
Enhancement Mode FET
9
Normally off
Positive Voltage turns on Size of gate region is independent of applied voltage
Requires less energy to createa channel
=> usually applied for integrated circuits
CMOS VLSI Design 4th Ed. 10
nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors– SiO2 (oxide) is a very good insulator– Called metal – oxide – semiconductor (MOS)
capacitor– Even though gate is
no longer made of metal*
* Metal gates are returning today!
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+ Body
CMOS VLSI Design 4th Ed. 11
nMOS Parameters
n+ n+
p-type body
polysilicongate
Gate length
L
Gate widthW
SiO2 gate oxide(good isolator, eox = 3.9)
tox – Oxide thickness
tox
CMOS VLSI Design 4th Ed. 12
nMOS Operation Body is usually tied to ground (0 V) When the gate is at a low voltage:
– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
CMOS VLSI Design 4th Ed. 13
nMOS Operation Cont. When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Inverts a channel under gate to n-type– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
CMOS VLSI Design 4th Ed. 14
pMOS Transistor Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)– Gate low: transistor ON– Gate high: transistor OFF– Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
CMOS VLSI Design 4th Ed. 15
Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes
– High VDD would damage modern tiny transistors– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design 4th Ed.
Quiz What are characteristics of a Enhanced mode FET
A. It is based on the Field effectB. Turns on when a negative voltage is appliedC. Length of channel region is dependent on applied
voltageD. Drain and source are always N-type
What is not a FET parameterA. Gate lengthB. Gate WidthC. Gate thicknessD. Body type (N or P)
17
CMOS VLSI Design 4th Ed.
Quiz What are characteristics of a Enhanced mode FET
A. It is based on the Field effectB. Turns on when a negative voltage is appliedC. Length of channel region is dependent on applied
voltageD. Drain and source are always N-type
What is not a FET parameterA. Gate lengthB. Gate WidthC. Gate thicknessD. Body type (N or P)
18
CMOS VLSI Design 4th Ed. 19
Transistors as Switches We can view MOS transistors as electrically
controlled switches Voltage at gate controls path from source to drain
gs
d
g = 0
s
d
g = 1
s
d
gs
d
s
d
s
d
nMOS
pMOS
OFF ON
ON OFF
CMOS VLSI Design 4th Ed. 21
CMOS NAND CellA B Y
0 0
0 1
1 0
1 1
1
1
1
0
OFFOFF
ON
ON
1
1
OFFON
OFF
ON
0
1
ON OFF
ON
OFF
1
0
ON ON
OFF
OFF
0
0A
B
Y
CMOS VLSI Design 4th Ed. 22
CMOS NAND Cell
VDD VDD
In1In2
GND
Out
T3 T2
T1
T0
In1
In2Out
Pull-up Network
Pull-down Network
In1 In2 PUN PDN Out
1 1 OFF ON 00 1 ON OFF 11 0 ON OFF 10 0 ON ON 1
X XXX
CMOS VLSI Design 4th Ed. 24
3-input NAND Cell Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
AB
Y
C
CMOS VLSI Design 4th Ed. 25
CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or
etched Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing process
CMOS VLSI Design 4th Ed. 26
Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
CMOS VLSI Design 4th Ed. 27
Well and Substrate Taps Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND VDD
n+p+
substrate tap well tap
n+ p+
CMOS VLSI Design 4th Ed. 28
Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tapnMOS transistor pMOS transistor
CMOS VLSI Design 4th Ed. 29
Detailed Mask Views Six masks
– n-well– Polysilicon– n+ diffusion– p+ diffusion– Contact– Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
CMOS VLSI Design 4th Ed. 30
Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields
Courtesy of InternationalBusiness Machines Corporation. Unauthorized use not permitted.
CMOS VLSI Design 4th Ed.
Fabrication
Silicon pillar (Ingots)
CMOS VLSI Design 4th Ed. 34
Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)– Remove layer where n-well should be built– Implant or diffuse n dopants into exposed wafer– Strip off SiO2
p substrate
CMOS VLSI Design 4th Ed. 35
Oxidation Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
CMOS VLSI Design 4th Ed. 36
Photoresist Spin on photoresist
– Photoresist is a light-sensitive organic polymer– Softens where exposed to light
p substrate
SiO2
Photoresist
CMOS VLSI Design 4th Ed. 37
Lithography Expose photoresist through n-well mask Strip off exposed photoresist
p substrate
SiO2
Photoresist
CMOS VLSI Design 4th Ed. 39
Etch Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
CMOS VLSI Design 4th Ed. 40
Strip Photoresist Strip off remaining photoresist
– Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step
p substrate
SiO2
CMOS VLSI Design 4th Ed. 41
n-well n-well is formed with diffusion or ion implantation Diffusion
– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si
Ion Implanatation– Blast wafer with beam of As ions– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
CMOS VLSI Design 4th Ed.
Ion Implantation
42
Implantation of N atoms
Oxide removed after Implantation
CMOS VLSI Design 4th Ed. 43
Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
p substraten well
CMOS VLSI Design 4th Ed. 44
Polysilicon Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)– Forms many small crystals called polysilicon– Heavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
CMOS VLSI Design 4th Ed. 46
Polysilicon Patterning Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
CMOS VLSI Design 4th Ed. 48
Self-Aligned Process Enhancement mode transistors require source and
drain region aligned very close to gate Idea: Apply gate material itself as mask to perfectly
align source-drain regions Use oxide and masking to expose where n+ dopants
should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well
contact
CMOS VLSI Design 4th Ed. 49
N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substraten well
n+ Diffusion
CMOS VLSI Design 4th Ed. 50
N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n wellp substrate
n+n+ n+
Source-drain regions perfectly aligned to gate region
CMOS VLSI Design 4th Ed. 51
N-diffusion cont. Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
CMOS VLSI Design 4th Ed. 52
P-Diffusion Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
CMOS VLSI Design 4th Ed. 53
Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
CMOS VLSI Design 4th Ed. 54
Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
CMOS VLSI Design 4th Ed.
Sorenson,2002
Die Cut and Assembly
Good chips are attached to a lead frame package.
Wafer is sliced into chips
CMOS VLSI Design 4th Ed.
Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
Sorenson,2002
CMOS VLSI Design 4th Ed. 58
Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches
CMOS VLSI Design 4th Ed.
Quiz What is not a fabrication step?
A. MetallizationB. EtchingC. Ion implantationD. Mask design
What means self-aligned process?– Metal wires are placed side-by-side– Light removes photoresist– Gate-polysilicon is placed before drain/source regions– Adding of gold wires
59