VLSI Design Lab

P a g e | 1

VICKRAM COLLEGE OF ENGINEERING ENATHI 630561, TAMILNADU

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION

LAB MANUAL

SUBJECT CODE : EC 1356

SUBJECT NAME : VLSI DESIGN LAB SEM / YEAR : VI SEM ESTER/ III YEAR

PREPARED BY

Ms. A. Yasodai Mr.M. Sakthimohan Asst.Prof / ECE Lecturer/ECE

H.O.D / ECE PRINCIPAL

P a g e | 2

INDEX

S.No

DATE

NAME OF THE EXPERIMENTS

MARKS

SIGNATURE

1 STUDY OF SIMULATION TOOLS

2 STUDY OF SYNTHESIS TOOLS

3 STUDY OF DEVELOPMENT TOOL FOR

FPGA USING SCHEMATIC ENTRY AND

VERILOG

4 STUDY OF FPGA BOARD AND TESTING

ON BOARD LEDS AND SWITCHES

5 SIMULATION OF PARALLEL ADDER

6 SIMULATION OF SERIAL ADDER

7 SIMULATION OF TRAFFIC LIGHT

CONTROLLER

8 SIMULATION OF 8- BIT MULTIPLIER

9 DESIGN AND IMPLEMENTATION OF

REAL TIME CLOCK WITH FPGA BOARD

10 DESIGN &IMPLEMENTATION OF

TRAFFIC LIGHT CONTROL WITH FPGA

BOARD

P a g e | 3

VLSI DESIGN FLOW

P a g e | 4

Ex.pt no STUDY OF SIMULATION TOOLS Date:

Aim:

To study the simulation tools using XILINXISE 9.12 Simulator

Apparatus Required:

PC with XILINX Software

Theory:

Simulation is the functional emulation of the circuit design through software

programs that uses models to replicate system, how it will perform that in terms of

timings and results.The approach to verify functionality is to simulate net lists with the

same of stimulus as used describing design model simulation, Save the results in a result

file and compare to see if the results are identical.

To avoid the delays in a design model from causing functional mismatches the

maximum delay in the model must be greater than its maximum delay

The fact that different values are used describing design model stimulation a

potential across exists for functional mismatches to occur due to different values being

the default in the two different domain.

Procedure:

1) Start the XILINX project navigator by using Start program -> XILINX

2) Select the file menu in the select new project

3) Specify the project location and project name in the window and click „Next‟

4) Select family (Sparton 3E), Device(XC 3S400), Package(TQ 144),Speed

grade(-5), Simulator(ISE) from now project wizard window and click „Next. Project will

be displayed and click „Finish‟ to start the project

5) Right click on device name and select „New Source‟

6) Select Verilog module in the new project wizard. Give suitable project name

and click „Next‟ for the define module window.

7) Assign the require points in this window and click „Next‟ to write the Verilog

code

P a g e | 5

8) Write the statement in the verilog code and save.

9) Check for the error using synthesis tools

10) After Synthesis again click on the device named and select new source

11) Select the test bench waveform and give suitable filename and finish

12) Duty cycle will appear for clock select then finish that one

13) Select the behavioural simulation from the scroll down list

14) Give input waveform signals and same

15) Double click on Simulate behavioral model for simulation

16) View the output according to the input

3 to 8 Decoder Logic Diagram:

P a g e | 6

3 to 8 Decoder Truth Table:

P a g e | 7

Program:

3-8 decoder

module decoder (a,en,y);

input [2:0]a;

input en;

output [7:0]y;

reg[7:0]y;

always @ (a or en)

begin

if(!en)

y=4‟b0000;

else

case(a)

3‟b000 : y = 8‟b00000001;

3‟b001 : y = 8‟b00000010;

3‟b010 : y = 8‟b00000100;

3‟b011 : y = 8‟b00001000;

3‟b100 : y = 8‟b00010000;

3‟b101 : y = 8‟b00100000;

3‟b110 : y = 8‟b01000000;

3‟b111 : y = 8‟b10000000;

Result:

Thus the study of simulation tools in XILINX ISE 9.1i was completed

P a g e | 8

Expt.no: STUDY OF SYNTHESIS TOOLS

Date :

Aim:

To study the synthesis tools in XILINX ISE 9.1i Simulator

Apparatus Required:


Theory:

Synthesis describes the process of transformation of the model of the design from

one level of abstract in one domain(HDL) to a lower level of abstraction in same or other

domain.Synthesis is the process of constructing a gate level net list from a register

transfer level blocks.The Synthesis methodology checker is needed to ensure that the

model being written is Synthesizable.Some case of functional mismatches between the

design model and its synthesized net list that may possibly occur, describe their cause and

provide recommendations for using them.When synthesizing an synchronous circuit

preset and clear the flip flop the recommendations is to design only constant values under

the asynchronous conditions.

Procedure:










7) Assign the required points in this window and click „Next‟ to write the Verilog

code

P a g e | 9

8) Check syntax by process window -> Synthesize -> check syntax and remove

errors if present

9) Translate your design into gates and optimize it for the target architecture.This

is synthesize phase.

10) Highlight file in the source and run the synthesize process

11) Synthesize will run a green tick will appear,when synthesize is completed

successfully.Red cross indicates error.Then it should be corrected.Exclamation indicates

warning.

12) Now running process can be done

4 to 1 MUX:

P a g e | 10

4 to 1 MUX Truth table:

C1 C0 M

0 0 X0

0 1 X1

1 0 X2

1 1 X3

Program:

module multi(y,c0,c1,x0,x1,x2,x3);

input a,b,x0,x1,x2,x3;

output y;

wire z0,z1,z2,z3,c,d;

not n1(c,c0);

not n2(d,c1);

and g1(z0,x0,c,d);

and g2(z1,x1,c,c1);

and g3(z1,x1,c0,d);

and g4(z3,x3,c0,c1);

or g5(y,z0,z1,z2,z3);

end module;

Result:

Thus the study of synthesis tools in XILINX ISE 9.1i was completed

P a g e | 11

Ex.pt no: STUDY OF DEVELOPMENT TOOL FOR FPGA

Date : USING SCHEMATIC ENTRY AND VERILOG

Aim:

To study about the development tool for FPGA using schematic entry and verilog.

Apparatus Required:

System with XILINX software

Theory:

A typical design flow for creating VLSI circuits consists of a sequence of steps

beginning with design entry some CAD system include an editing program for creating

and modifying the schematic.This process is called as schematic entry. The verification is

performed by applying inputs to the circuit and using a logic simulator to determine the

output.An important development in the design system is HDL.HDL represents logic

diagram and other digital information in textual form.

Procedure:

1) Select schematic from new source and assign name to the file

2) From the sources select logic and from symbols pick and drop gates as

required

3) Once the component is selected, use “Add wire” option to provide connection

of other components or external input

4) Use “Add I/O mark” to assign parts.

5) Complete the schematic diagram

6) After the schematic is completed.synthesize the design

7) After the synthesize implement or simulate the same using XILINX

procedure.

P a g e | 12

FULL SUBTRACTOR LOGIC DIAGRAM:

TRUTH TABLE

a b c D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Result:

Thus the study of development tool for FPGA schematic entry was completed.

P a g e | 13

Expt.no: STUDY OF FPGA BOARD AND TESTING ON

Date : BOARD LEDS AND SWITCHES

Aim:

To study and test the board LED‟s and switches using verilog codes.

Apparatus Required:

1. FPGA universal kit

2. Adapter

3. FRC cables – 2

4. JTAG cables – 1

Connections:

1) Connect FRC1 of main board connector to switch

2) Connect FRC2 of main board connector to LED

Procedure:

1) Download the program to the FPGA kit

2) Then switch on the switches and verify the corresponding LED‟s glow or not

P a g e | 14

Program:

module buffer(a,y);

input [7:0]a;

output[7:0]y;

reg[7:0]y;

always @ (a)

begin

y=a;

end

end module

User Constraint File:

NET “a[0]” LOC = “P83”;

NET “a[1]” LOC = “P80”;

NET “a[2]” LOC = “P82”;

NET “a[3]” LOC = “P78”;

NET “a[4]” LOC = “P79”;

NET “a[5]” LOC = “P77”;

NET “a[6]” LOC = “P76”;

NET “a[7]” LOC = “P74”;

NET “y[0]” LOC = “P96”;

NET “y[1]” LOC = “P92”;

NET “y[2]” LOC = “P90”;

NET “y[3]” LOC = “P89”;

NET “y[4]” LOC = “P87”;

NET “y[5]” LOC = “P86”;

NET “y[6]” LOC = “P85”;

NET “y[7]” LOC = “P84”;

Result:

Thus the testing of FPGA on board LEDS and switches was performed by using

verilog codes.

P a g e | 15

Expt.no: SIMULATION OF PARALLEL ADDER Date :

Aim: Write a program using Verilog code to simulate a parallel adder of 48 numbers

with 12 bits each.

Apparatus Required:


Procedure:











code








P a g e | 16



Block diagram of parallel adder

program:

module paralleladder(sum,carry);

output[11:0] sum;

output[3:0] carry;

reg[11:0] sum;

reg[3:0] carry;

reg in1=12'b111100101100;

reg in2=12'b110111000101;

reg in3=12'b000100110011;

reg in4=12'b010101101001;

reg in5=12'b101001000111;

reg in6=12'b011010001101;

reg in7=12'b100111001111;

reg in8=12'b111101110110;

reg[12:0] temp=13'b1000000000000;

reg[11:0] a1,a2,a3,a4,a5,a6,a7,a8;

reg[14:0] c=15'b000000000000000;

reg[15:0] res=16'b0000000000000000;

reg[15:0] temp1=16'b1000000000000000;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp,

c,res)

P a g e | 17

begin

a1<=temp-in1;

a2<=temp-in2;

a3<=temp-in3;

a4<=temp-in4;

a5<=temp-in5;

a6<=temp-in6;

a7<=temp-in7;

a8<=temp-in8;

c<=a1+a2+a3+a4+a5+a6+a7+a8;

res<=temp1-c;

sum<=res[11:0];

carry<=res[15:12];

end

endmodule

Result:

Simulation of parallel adder was done successfully.

P a g e | 18

Expt no: SIMULATION OF SERIAL ADDER Date :

Aim:

Write a program using Verilog code to simulate a serial adder of 8 numbers with

12 bits each.

Apparatus Required:


Procedure:











code







P a g e | 19




Block diagram of serial Adder

P a g e | 20

program:

module sadd(sum,carry);

output[11:0]sum;

output[3:0]carry;

reg[11:0]sum;

reg[3:0]carry;

reg[11:0]in1=12'b111100101100;//F2C

reg[11:0]in2=12'b110111000101;//DC5

reg[11:0]in3=12'b000100110011;//133

reg[11:0]in4=12'b010101101001;//569

reg[11:0]in5=12'b101001000111;//A47

reg[11:0]in6=12'b011010001101;//68D

reg[11:0]in7=12'b100111001111;//9CF

reg[11:0]in8=12'b111001110110;//E76

reg[12:0]temp=13'b1000000000000;

reg[15:0]temp1=16'b1000000000000000;

wire[11:0]sum1;

reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8;

reg[2:0]car0=3'b000;

wire[2:0]car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12;

reg[14:0]c=15'b000000000000000;

reg[15:0]res=16'b0000000000000000;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8)

begin

a1<=temp-in1;

a2<=temp-in2;

a3<=temp-in3;

a4<=temp-in4;

a5<=temp-in5;

a6<=temp-in6;

a7<=temp-in7;

a8<=temp-in8;

end

fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1);









P a g e | 21


fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],

car11);

fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],

car12);

always@(car12,sum1,temp1,c,res)

begin

c<={car12,sum1};

res<=temp1-c;

sum<=res[11:0];

carry<=res[15:12];

end

endmodule

//fhadd(8 bit addition)

module fhadd(i1,i2,i3,i4,i5,i6,i7,i8,cp,s,c);

input i1,i2,i3,i4,i5,i6,i7,i8;

input [2:0]cp;

output s;

output [2:0]c;

reg s;

reg [2:0]c;

reg [3:0]s2;

wire [3:0]s1;

wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18;

wire ca1,ca2,ca3,ca4,ca5,ca6,ca7,ca8,ca9,ca10,ca11,ca12;

wire ca13,ca14,ca15,ca16,ca17,ca18,ca19,ca20,ca21,ca22;

hala ha1(i1,i2,x1,ca1);

hala ha2(x1,i3,x2,ca2);





hala ha7(x6,i8,s1[0],ca7);

hala ha8(ca1,ca2,x7,ca8);

hala ha9(ca3,x7,x8,ca9);

hala hal0(ca4,x8,x9,ca10);



hala hal3(ca7,x11,s1[1],ca13);

hala hal4(ca8,ca9,x12,ca14);




hala hal8(ca13,x15,s1[2],ca18);

P a g e | 22

hala hal9(ca14,ca15,x16,ca19);



hala ha22(ca18,x18,s1[3],ca22);

always@(s1,cp,s2)

begin

s2<=s1+cp;

s<=s2[0];

c<=s2[3:1];

end

endmodule

// hala(2 bit addition)

module hala(a,b,s,c);

input a,b;

output s,c;

reg s,c;

always@(a,b)

begin

s=a^b;

c=a&b;

end

endmodule

Result: Simulation of serial adder was done successfully.

P a g e | 23

Expt. no: SIMULATION OF TRAFFIC LIGHT CONTROLLER Date :

Aim : Write a program in Verilog HDL for 4-way traffic light control and simulate it

using Xilinx ISE9.2i si mulator.

Apparatus Required:


Procedure:











code








P a g e | 24

15) Double click on Simulate behavioral model for simulation view the output

according to the input

Block diagram – 4way traffic light controller

P a g e | 25

Program:

module tlc(clk,reset,p1,p2,p3,p4,pl);

input clk;

input reset;

output[4:0]p1;

output[4:0]p2;

output[4:0]p3;

output[4:0]p4;

output[3:0]pl;

reg[4:0]p1;

reg[4:0]p2;

reg[4:0]p3;

reg[4:0]p4;

reg[3:0]pl;

reg[5:0]sig;

always @(posedge clk or negedge reset)

begin

if(reset==1'b0)

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

sig<=6'b000000;

end

else

begin

sig<=sig+1;

case(sig[5:0])

6'b000000:

begin

p1<=5'b10011;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b000100:

begin

p1<=5'b01000;

p2<=5'b00100;

p3<=5'b00100;

P a g e | 26

p4<=5'b00100;

pl<=4'b1111;

end

6'b001000:

begin

p1<=5'b00100;

p2<=5'b10011;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b001100:

begin

p1<=5'b00100;

p2<=5'b01000;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b1111;

end

6'b010000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b10011;

p4<=5'b00100;

pl<=4'b1111;

end

6'b010100:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b01000;

p4<=5'b00100;

pl<=4'b1111;

end

6'b011000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b10011;

pl<=4'b1111;

end

6'b011100:

begin

p1<=5'b00100;

P a g e | 27

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b01000;

pl<=4'b1111;

end

6'b100000:

begin

p1<=5'b00100;

p2<=5'b00100;

p3<=5'b00100;

p4<=5'b00100;

pl<=4'b0000;

end

6'b100100:sig<=6'b000000;

default:begin

end

endcase

end

end

endmodule

Result:

Thus the simulation of 4-way traffic light controller was completed successfully

using Xilinx ISE9.2i

P a g e | 28

Expt.no: SIMULATION OF 8- BIT MULTIPLIER Date :

Aim :

Write a program in verilog HDL to mutliply two 8 bit numbers & simulate it on

Xilinx ISE 9.2i.

Apparatus Required:


Procedure:











code








P a g e | 29

15) Double click on Simulate behavioral model for simulation view the output

according to the input

BLOCK DIAGRAM OF MULTIPLIER

PROGRAM:

module mul_new_verilog(clk,addr,load,clear,data_in,calc,result);

input clk,clear,calc,load;

input addr;

input [7:0]data_in;

output reg [15:0]result;

reg [7:0]ram[1:0];

always@(posedge clk)

begin

if(~clear)

begin

ram[0]=8'b0;

ram[1]=8'b0;

end

else if(~load)

P a g e | 30

ram[addr]=data_in;

end


begin

if(~load)

result={8'b0,data_in};

else if(~calc)

result=multiply_8x8_2sC(ram[0],ram[1]);

else

result={8'b0,ram[addr]};

end

function[15:0] multiply_8x8_2sC;

input[7:0] a,b;

reg[7:0] a_mag,b_mag;

reg[14:0] y_mag;

reg[14:0] y_neg;

begin

case(a[7])

0:a_mag=a[6:0];

1:a_mag=128-a[6:0];

endcase

case(b[7])

0:b_mag=b[6:0];

1:b_mag=128-b[6:0];

endcase

y_mag=a_mag*b_mag;

if((a[7]^b[7])&(y_mag!=0))

begin

y_neg=32768-y_mag[13:0];

multiply_8x8_2sC={1'b1,y_neg};

end

else

multiply_8x8_2sC=y_mag;

end

endfunction

endmodule

RESULT:

Verilog program for 8 – bit multiplication was written & it was succcessfully

simulated usng xilinx ise 9.2i simulator

P a g e | 31

Ex.pt no: DESIGN AND IMPLEMENTATION OF REAL

Date : TIME CLOCK WITH FPGA BOARD

Aim: Write a program in Verilog HDL to implement Real Time Clock

Apparatus required: pc with xilinx software

FPGA kit

Anna university card 1

FRC cables

JTAG cable

Connections: 1) connect FRC 5 of main board to CN2of card 1

2) connect FRC 10 of main board to CN1 of card 1


4) connect FRC 4 of main board to CN4of card 1



procedure: 1) connections are made as above and implement the design into

FPGA device.

2) Real time clock is on , all 7 Segment displays will be in on position

and starts counting .

3) The time can be set by the switches & reset pin resets the clock

Program:

module

real_time_clk_verilog(clk,clear,hour1,hour2,minute1,minute2,second1,second2,hour_A2,

min_A1,sec_A0,load,data_in);

input clk,clear;

output reg[6:0]hour1,hour2,minute1,minute2,second1,second2;

input load;

input hour_A2,min_A1,sec_A0;

input [7:0]data_in;

reg clk_sec,clk,clk_msec;

reg[7:0]sec,min,hr;

integer timer_count1=0,timer_counter2=0;


begin

if(timer_counter1==3999)

begin

timer_counter1=0;

clk_msec=1'b1;

P a g e | 32

end

else

begin

timer_count1=timer_count1+1;

clk_msec=1'b0;

end

end

always@(posedge clk_msec)

begin

if(timer_count2==999)

begin

timer_count2=0;

clk_sec=1'b1;

end else

begin

timer_counter2=timer_counter2+1;

clk_sec=1'b0;

end

end

always@(negedge clk_sec)

begin

if(~clear)

begin

sec=0;

min=0;

hr=0;

end

else

if(~load)

begin

if(hour_A2)

begin

if(hr[7:4]==4'b0010)

begin

if(hr[3:0]<4'b0100)

hr=data_in;

end

else if(hr[7:4]<4'b0010)

hr=data_in;

else

hr=8'b0;

P a g e | 33

end

if(min_A1)

begin

if(min[7:4]<4'b0110)

min=data_in;

else

min=8'b0;

end

if(sec_A0)

begin

if(sec[7:4]<4'b0110)

sec=data_in;

else

sec=8'b0;

end

end

else

begin

if(sec[3:0]==4'b1001)

begin

sec[3:0]=4'b0;

if(sec[7:4]==4'b0101)

begin

sec[7:4]=4'b0;

if(min[3:0]==4'b1001)

begin

min[3:0]=4'b0;

if(min[7:4]==4'b0101)

begin

min[7:4]=4'b0;

if(hr==8'b00100100)

hr=0;

else if(hr[3:0]==4'b1001)

begin

hr[3:0]=4'b0;

hr[7:4]=hr[7:4]+1;

end

else

hr[3:0]=hr[3:0]+1;

P a g e | 34

end

else

min[7:4]=min[7:4]+1;

end

else

in[3:0]=min[3:0]+1;

end

else

sec[7:4]=sec[7:4]+1;

end

else

sec[3:0]=sec[3:0]+1;

end

end

always@(sec)

begin

case(sec[3:0])

4'b0000:second1=7'b1111110;

4'b0001:second1=7'b0110000;

4'b0010:second1=7'b1101101;

4'b0011:second1=7'b1111001;

4'b0100:second1=7'b0110011;

4'b0101:second1=7'b1011011;

4'b0110:second1=7'b1011111;

4'b0111:second1=7'b1110000;

4'b1000:second1=7'b1111111;

4'b1001:second1=7'b1111011;

default:second1=7'b0;

endcase

end

always@(sec)

begin

case(sec[7:4])

4'b0000:second2=7'b1111110;

4'b0001:second2=7'b0110000;

4'b0010:second2=7'b1101101;

4'b0011:second2=7'b1111001;

4'b0100:second2=7'b0110011;

4'b0101:second2=7'b1011011;

4'b0110:second2=7'b1011111;

P a g e | 35

4'b0111:second2=7'b1110000;

4'b1000:second2=7'b1111111;

4'b1001:second2=7'b1111011;

default:second2=7'b0;

endcase

end

always@(min)

begin

case(min[3:0])

4'b0000:minute1=7'b1111110;

4'b0001:minute1=7'b0110000;

4'b0010:minute1=7'b1101101;

4'b0011:minute1=7'b1111001;

4'b0100:minute1=7'b0110011;

4'b0101:minute1=7'b1011011;

4'b0110:minute1=7'b1011111;

4'b0111:minute1=7'b1110000;

4'b1000:minute1=7'b1111111;

4'b1001:minute1=7'b1111011;

default:minute1=7'b0;

endcase

end

always@(min)

begin

case(min[7:4])

4'b0000:minute2=7'b1111110;

4'b0001:minute2=7'b0110000;

4'b0010:minute2=7'b1101101;

4'b0011:minute2=7'b1111001;

4'b0100:minute2=7'b0110011;

4'b0101:minute2=7'b1011011;

4'b0110:minute2=7'b1011111;

4'b0111:minute2=7'b1110000;

4'b1000:minute2=7'b1111111;

4'b1001:minute2=7'b1111011;

default:minute2=7'b0;

endcase

end

always@(hr)

begin

P a g e | 36

case(hr[3:0])

4'b0000:hour1=7'b1111110;

4'b0001:hour1=7'b0110000;

4'b0010:hour1=7'b1101101;

4'b0011:hour1=7'b1111001;

4'b0100:hour1=7'b0110011;

4'b0101:hour1=7'b1011011;

4'b0110:hour1=7'b1011111;

4'b0111:hour1=7'b1110000;

4'b1000:hour1=7'b1111111;

4'b1001:hour1=7'b1111011;

default:hour1=7'b0;

endcase

end

always@(hr)

begin

case(hr[7:4])

4'b0000:hour2=7'b1111110;

4'b0001:hour2=7'b0110000;

4'b0010:hour2=7'b1101101;

4'b0011:hour2=7'b1111001;

4'b0100:hour2=7'b0110011;

4'b0101:hour2=7'b1011011;

4'b0110:hour2=7'b1011111;

4'b0111:hour2=7'b1110000;

4'b1000:hour2=7'b1111111;

4'b1001:hour2=7'b1111011;

default:hour2=7'b0;

endcase

end

endmodule

P a g e | 37

UCF file(User Constraint File)

NET”clear”LOC=”p137”;

NET”clk”LOC=”p52”;

NET”data_in<0>”LOC=”p92”;








NET”hour1<0>”LOC=”p95”;














NET”hour_A2”LOC=”p78”;

NET”load”LOC=”p83”;

NET”min_A1”LOC=”p82”;

NET”minute1<0>”LOC=”p14”;














NET”sec_A0”LOC=”p80”;

NET”second1<0>”LOC=”p32”;


P a g e | 38












NET”second2<6>”LOC=”p10”

RESULT:

Real Time Clock is designed with Verilog HDL code & it was implented

with FPGA kit

P a g e | 39

Expt no: DESIGN &IMPLEMENTATION OF TRAFFIC LIGHT

Date : CONTROL WITH FPGA BOARD

Aim : Write Verilog Code for 4 way traffic light control and implement the

same with FPGA Board

Apparatus Required:

pc with xilinx software

FPGA kit

Anna university card 2

FRC cables

JTAG cable.

Connections:

1) connect FRC 5 of main board to CN1of card2

2) connect FRC 1 of main board to CN2of card2

3)connect FRC 8 of main board to CN3 of card2

Procedure:

1) Download the program into FPGA kit.

2) Connect FRC connections as specified.

3) On card 2 ,load the timer count signals.

4) Set the clock, state of signals and output was verified.

P a g e | 40

Block diagram of four way traffic light controller

P a g e | 41

PROGRAM:

module traffic_verilog(seg_1,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst);

output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG;

output reg[13:0]seg_1;

input clk,rst;

integer timer_count1=0,timer_count2=0;

reg clk_msec,clk_sec:

reg[4:0]count;

reg[1:0]state=2'b0;


begin

if(timer_count1++3999)

begin

timer_count1=0;

clk-msec=1'b1;

end

else

begin


clk_msec=1'b0;

end

end

always@(posedge clk_msec)

begin

if(timer_count2==999)

begin

if(timer_count2=0;

clk_sec=1'b1;

end

else

begin

P a g e | 42


clk_sec=1'b0;

end

end

always@(poedge clk_sec)

begin

if(~rst)

begin

R1=1'b1;G1=1'b0;Y1=1'b0;

R2=1'b1;G2=1'b0;Y2=1'b0;

R3=1'b1;G3=1'b0;Y3=1'b0;

state=2'b00;

end

else

begin

case(state)

2'b00://SIGNAL AT SIGNAL LIGHTS ONE

begin

if(count==5'b11100)

begin

G1=1'b0;

R1=1'b0;

Y1=1'b1;

Y3=1'b0;

G3=1'b0;

end

if(count==5'b11111)

begin

G1=1'b1;

y1=1'b0;

state=2'b01;

P a g e | 43

end

else

state=2'b00;

end

2'b01://SIGNAL AT SIGNAL LIGHTS TWO

begin

if(count==5'b 11100)

begin

Y1=1'b1;

G1=1'b0;

R2=1'b0;

Y2=1'b1;

G2=1'b0;

end

if(count==5'b11111)

begin

R1=1'b1;

Y1=1'b0;

Y2=1'b0;

G2=1'b1;

state=2'b10;

end

else

state=2'b01;

end

2'b10://SIGNAL AT SIGNAL LIGHTS THREE

begin

if(count==5'b 11100)

begin

Y2=1'b1;

G2=1'b0;

P a g e | 44

R3=1'b0;

Y3=1'b1;

G3=1'b0;

end

if(count==5'b11111)

begin

R2=1'b1;

Y2=1'b0;

Y3=1'b0;

G3=1b1;

state=2'b11;

end

else

state=2'b10;

end

2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS

begin

if(count==5'b11100)

begin

Y1=1'b0;

Y3=1'b1;

G3=1'b0;

end

if(count==5'b11111)

begin

Y1=1'b0;

R3=1'b1;

Y3=1'b0;

state=2'b00;

end

else

P a g e | 45

state=2b11;

end

endcase

end

end

always@(count.state)

begin

if((state==2'b00)&&(count<=5'b11100))

begin

PR=1'b0;

PG=1'b1;

end

else

begin

PR=1'b1;

PG=1'b0;

end

end

always@(posedge clk_sec)

begin

if((clk_sec)

begin

count[4:0]=count[4:0]+1;

//if(count[4:0==8'b10011)

//count[4:0]=4'b00000;

end

end

always@(count)

begin

case(count[40])

5'b00001:seg_1=14'b11111100110000;//01

P a g e | 46

5”b00010:seg_1=14'b11111101101101;//02

5'b00010:seg_1=14'b11111101111001;//03

5'b00100:seg_1=14'b11111100110011;//04

5'b00101:seg_1=14'b11111101011011;//05

5'b00110:seg_1=14'b11111101011111;//06

5'b00111:seg_1=14'b11111101110000;//07

5'b01000:seg_1=14'b11111101111111;//08

5'b01001:seg_1=14'b11111101111011;//09

5'b01010:seg_1=14'b01100001111110;//10

5'b01011:seg_1=14'b01100000110000;//11

5'b01100:seg_1=14'b01100001101101;//12

5'b01101:seg_1=14'b01100001111001;//13

5'b01110:seg_1=14'b01100000110011;//14

5'b01111:seg_1=14'b01100001011011;//15

5'b10000:seg_1=14'b01100001011111;//16

5'b10001:seg_1=14'b01100001110000;//17

5'b10010:seg_1=14'b01100001111111;//18

5'b10011:seg_1=14'b01100001111011;//19

5'b10100:seg_1=14'b11011011111110;//20

5'b10101:seg_1=14'b11011010110000;//21

5'b10110:seg_1=14'b11011011101101;//22

5'b10111:seg_1=14'b11011011111001;//23

5'b11000:seg_1=14'b11011010110011;//24

5'b11001:seg_1=14'b11011011011011;//25

5'b11010:seg_1=14'b11011011011111;//26

5'b11011:seg_1=14'b11011011110000;//27

5'b11100:seg_1=14'b11011011111111;//28

5'b11101:seg_1=14'b11011011111011;//29

5'b11110:seg_1=14'b11110011111110;//30

5'b11111:seg_1=14'b11110010110000;//31

//default:seg_1=14'b000000000000000;//off

P a g e | 47

endcase

end

endmodule

UCF file(use constraint file)

NET “clk” LOC =”p52”;

NET “G1” LOC =”p97”;

NET “G2” LOC =”p98”;

NET “G3” LOC =”p125”;

NET “PG” LOC =”p132”;

NET “PR” LOC =”p135”;

NET “R1” LOC =”p93”;

NET “R2” LOC =”104”;

NET “R3” LOC =”p129”;

NET “rst” LOC =”p78”;

NET “seg_1<6>” LOC =”p27”;

NET “seg_1<5>” LOC =”p26”;

NET “seg_1<4>” LOC =”p24”;

NET “seg_1<3>” LOC=”P23”;



NET “seg_1<0>” LOC=”p17”;








NET Y1 LOC =P95;

NET Y2 LOC =P99;

NET Y3 LOC=P122;

RESULT:

Thus the Verilog code for 4 way traffic controller was written and it was

implemented on FPGA.

Date post:	17-Oct-2014
Category:	Documents
Upload:	qwertyuiop
View:	164 times
Download:	6 times

VLSI Design Lab

Documents