VLSI DesignLecture 3: Parasitics of CMOS Wires

Mohammad Arjomand

CE DepartmentSharif Univ. of Tech.

Adapted with modifications from Harris’s lecture notes

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Topics

Wire and via structures. Wire parasitics. Transistor parasitics. Fabrication theory and practice.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Wires and vias

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Metal interconnect

Many layers of metal interconnect are possible.– 12 layers of metal are common.

Lower layers have smaller features, higher layers have larger features.

Can’t directly go from a layer to any other layer.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Copper interconnect

Much better electrical characteristics. Copper is poisonous to semiconductors---

must be isolated from silicon.– Bottom layer of interconnect is aluminum.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Metal migration

Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit.

Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Metal migration problems and solutions

Marginal wires will fail after a small operating period—infant mortality.

Normal wires must be sized to accomodate maximum current flow:Imax = 1.5 mA/m of metal width.

Mainly applies to VDD/VSS lines.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Diffusion wire capacitance

Capacitances formed by p-n junctions:

n+ (ND)

depletion region

substrate (NA)bottomwallcapacitance

sidewallcapacitances

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Depletion region capacitance

Zero-bias depletion capacitance:– Cj0 = si/xd.

Depletion region width:– xd0 = sqrt[(1/NA + 1/ND)2siVbi/q].

Junction capacitance is function of voltage across junction:– Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Poly/metal wire capacitance

Two components:– parallel plate;– fringe.

plate

fringe

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Metal coupling capacitances

Can couple to adjacent wires on same layer, wires on above/below layers:

metal 2

metal 1 metal 1

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Example: parasitic capacitance measurement

n-diffusion: bottomwall=2 fF, sidewall=2 fF.

metal: plate=0.15 fF, fringe=0.72 fF.

3 m

0.75 m 1 m

1.5 m

2.5 m

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Wire resistance

Resistance of any size square is constant:

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Skin effect

At low frequencies, most of copper conductor’s cross section carries current.

As frequency increases, current moves to skin of conductor.– Back EMF induces counter-current in body of

conductor. Skin effect most important at gigahertz

frequencies.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Skin effect, cont’d

Isolated conductor: Conductor and ground:

Low frequency

High frequency

Low frequency

High frequency

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Skin depth

Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: = 1/sqrt(f)– f = signal frequency = magnetic permeability = wire conducitvity

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Effect on resistance

Low frequency resistance of wire:– Rdc = 1/ wt

High frequency resistance with skin effect:– Rhf = 1/2 (w + t)

Resistance per unit length:– Rac = sqrt(Rdc 2 + Rhf2

Typically = 1.2.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Transistor gate parasitics

Gate-source/drain overlap capacitance:

gate

source drain

overlap

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Transistor source/drain parasitics

Source/drain have significant capacitance, resistance.

Measured same way as for wires. Source/drain R, C may be included in Spice

model rather than as separate parasitics.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Why we need design rules

Masks are tooling for manufacturing. Manufacturing processes have inherent

limitations in accuracy. Design rules specify geometry of masks

which will provide reasonable yields. Design rules are determined by experience.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Design rules and yield

Design rules are determined by manufacturing process characteristics.

Design rules should provide adequate yield if followed.

Types of design rules:– Spacing.– Separation.– Composition.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Yield

Gamma distribution for yield of a single type of structure:– Yi = [1/(1+Ai)]i.

Total yield for the process is the product of all yield components:– Y = Yi.

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Manufacturing problems

Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Transistor problems

Varaiations in threshold voltage:– oxide thickness;– ion implanatation;– poly variations.

Changes in source/drain diffusion overlap. Variations in substrate.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Wiring problems

Diffusion: changes in doping -> variations in resistance, capacitance.

Poly, metal: variations in height, width -> variations in resistance, capacitance.

Shorts and opens:

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Oxide problems

Variations in height. Lack of planarity -> step coverage.

metal 1metal 2

metal 2

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Via problems

Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Scaling theory

Chips get better as features shrink in classical scaling theory:– Capacitive load goes down faster than current.

Classical scaling theory runs into complications at nanometer features.– Leakage.– Smaller supply voltage.

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Scaling model

/x. W W/x, L L/x. tox tox /x.

Nd Nd/x.

VDD VSS (VDD VSS)/x.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Current and capacitance scaling

Saturation drain current scales as 1/x. Capacitance scales as 1/x. Total performance over scaling:

– [C’V’/l’]/[CV/l] = 1/x.– Circuit speeds up by factor x.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Interconnect scaling

Two varieties of interconnect scaling:– Ideal scaling reduces vertical and horizontal

dimensions equally.– Constant dimension does not change wiring

sizes.– Higher levels of interconnect are constant

dimension---same as older technologies.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Interconnect scaling trends

Ideal scaling Constant dimension

Line width/spacing S 1

Wire thickness S 1

Interlevel dielectric S 1

Wire length 1/sqrt(S) 1/sqrt(S)

Resistance/unit length 1/S2 1

Capacitance/unit length 1 1

RC delay 1/S3 1/S

Current density 1/S S

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ITRS roadmap

Semiconductor industry projects fabrication trends.– Helps plan future technologies.

Roadmap describes features, technology required to get to those goals.

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

ITRS roadmap 2005-2012

2005 2006 2007 2008 2009 2010 2011 2012

CPU metal pitch

90 75 68 59 52 45 40 36

CPU gate length

32 28 25 23 20 18 16 14

ASIC gate length

45 38 32 28 25 23 20 18