VLSI DesignVLSI DesignLecture 3: Transistor

CharacteristicsShaahin Hessabi

Department of Computer EngineeringDepartment of Computer EngineeringSharif University of Technology

Adapted, with modifications, from lecture notes prepared by the author (from Prentice Hall PTR)

Topics

Derivation of transistor characteristics. Simulation

Modern VLSI Design 4e: Chapter 2 Slide 2 of 25Sharif University of Technology

MOSFET gate as capacitor

Basic structure of gate is parallel-plate capacitor:

gate

x+

b t t

SiO2xoxVg

-

substrate

Modern VLSI Design 4e: Chapter 2 Slide 3 of 25Sharif University of Technology

Parallel plate capacitance

Formula for parallel plate capacitance:p p pCox = ox / xox

Permittivity of silicon: ox = 3.46 x 10-13 F/cmy ox /

Gate capacitance helps determine charge in channel which forms inversion regionwhich forms inversion region.

Mobile electrons move if voltage applied between Source and Drainand Drain

Qchannel = CV C = Cg = oxWL/xox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt

Modern VLSI Design 4e: Chapter 2 Slide 4 of 25Sharif University of Technology

gc t ( gs ds/ ) t

Carrier Velocityy Charge is carried by e- Carrier velocity v proportional to lateral E --field

between source and drain v = E called mobility E = V /L E = Vds/L Time for carrier to cross channel: t = L / v

t

Vgd

gate

+ +source Vgs drain

Vg

CgW

polysilicongate

n+ n+

p-type body

+--

Vds

channel-Vs Vd

n+ n+

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

Modern VLSI Design 4e: Chapter 2 Slide 5 of 25Sharif University of Technology

p-type body

nMOS Linear I-V Now we knowHow much charge Qchannel is in the channel (slide 4)How much time t each carrier takes to cross (slide 5)

c h a n n e ld s

QIt

k’ = Cox Process transconductanceo x 2d s

g s t d s

tW VC V V VL

= CoxWL

C (V V ) i i h b f i i h h l

Device transconductance2d s

g s t d sVV V V

Current (Vgs-Vt) since it sets the number of carriers in the channelCurrent Cox 1/xox

Current W/L -- Resistance L/W

Modern VLSI Design 4e: Chapter 2 Slide 6 of 25Sharif University of Technology

/ /

nMOS Saturation I-V

If V < V h l i h ff d i If Vgd < Vt, channel pinches off near drainWhen Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

2dsat

d t d tVI V V V

2

2ds gs t dsatI V V V

V V

2 gs tV V

Modern VLSI Design 4e: Chapter 2 Slide 7 of 25Sharif University of Technology

nMOS I-V Summary

Shockley 1st order transistor modelsy

cutoff0 gs tV V

linear2

gs t

dsds gs t ds ds dsat

VI V V V V V

2saturatio

2

n

g

d dV V V V

saturatio2

ngs t ds dsatV V V V

Modern VLSI Design 4e: Chapter 2 Slide 8 of 25Sharif University of Technology

Threshold voltage

Components of threshold voltage Vt:p g t

Vfb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surfacefunction between gate and substrate and on fixed surface charge.

= surface potential (about 2 ) s = surface potential (about 2f). Voltage on paralell plate capacitor. Additional ion implantation.

Modern VLSI Design 4e: Chapter 2 Slide 9 of 25Sharif University of Technology

Body effect

Reorganize threshold voltage equation:g g qVt = Vt0 + Vt

Threshold voltage is a function of source/substrate Threshold voltage is a function of source/substrate voltage Vsb. B d ff i h ffi i f h V d d Body effect is the coefficient for the Vsb dependence factor. n = sqrt(2qSiNA)/Cox

Vt = Vt0 + n(sqrt(S + Vsb) - sqrt(S))

Modern VLSI Design 4e: Chapter 2 Slide 10 of 25Sharif University of Technology

Example: threshold voltage of a transistor

Vt0 = Vfb + s + Qb/Cox + VIIt0 fb s Qb/ ox II

= -0.83 V + 0.58 V + (1.4E-8/8.6E-7) + 0.93 V= 0 7 V= 0.7 V

Body effect n = sqrt(2qSiNA/Cox) = 0.1 Vt = n[sqrt(s + Vsb) - sqrt(Vs)]

= 0.05 V

Modern VLSI Design 4e: Chapter 2 Slide 11 of 25Sharif University of Technology

Channel length modulation length parameterg g p

describes small dependence of drain current on Vds in p dssaturation. Factor is measured empirically.p y

New drain current equation: I = 0 5k’ (W/L)(V V ) 2(l + V ) Id = 0.5k (W/L)(Vgs - Vt) (l + Vds)

Equation has a discontinuity between linear and saturation regions small enough to be ignoredsaturation regions---small enough to be ignored.

Modern VLSI Design 4e: Chapter 2 Slide 12 of 25Sharif University of Technology

Ideal Quadratic NMOS I-V CurveQ

Ids Vgs=2.5VSaturation starts here

ds

Vgs=2V

Vgs=1VVgs=1.5V

Vds

Modern VLSI Design 4e: Chapter 2 Slide 13 of 25Sharif University of Technology

Real NMOS I-V Curve

Transistor, when conducting, may be modeled as voltage-, g, y gcontrolled resistor

Ids

VgsVgs

Vds

Modern VLSI Design 4e: Chapter 2 Slide 14 of 25Sharif University of Technology

Vds

Examplep Using a 0.6 m process from AMI Semiconductorxox = 100 Å = 350 cm2/V*s 2.5

Vgs = 5

Vt = 0.7 V

Plot Ids vs. Vds1.5

2

mA

) Vgs = 4ds ds

Vgs = 0, 1, 2, 3, 4, 5Use W/L = 4/2 0.5

1I ds (m

Vgs = 3

Vgs = 2Use W/L 4/2 0 1 2 3 4 5

0

Vds

Vgs 2Vgs = 1

14

28

3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

Modern VLSI Design 4e: Chapter 2 Slide 15 of 25Sharif University of Technology

100 10L L L

pMOS I-V

All dopings and voltages are inverted for pMOS All dopings and voltages are inverted for pMOS Mobility p is determined by holesTypically 2-3 times lower than that of electrons n

120 cm2/V*s in AMI 0.6 m process

Thus pMOS must be wider to provide same currentAssume n / p = 2 (depends on technology)

Modern VLSI Design 4e: Chapter 2 Slide 16 of 25Sharif University of Technology

Gate voltage and the channel

gate

d icurrent

Vgs > VtV < V Vdrainsource

Id

Vds < Vgs - Vt

gate

drainsourcecurrent Vgs > Vt

V V VId

t

Vds = Vgs - Vt

gate

drainsource

I

Vgs > VtVds > Vgs - Vt

Modern VLSI Design 4e: Chapter 2 Slide 17 of 25Sharif University of Technology

Idds gs t

Leakage and subthreshold current

A variety of leakage currents draw current away from the y g ymain logic path.

Leakage currents cause static power dissipation Leakage currents cause static power dissipation. The subthreshold current is one particularly important

type of leakage currenttype of leakage current.

Modern VLSI Design 4e: Chapter 2 Slide 18 of 25Sharif University of Technology

Types of leakage current

Weak inversion current (a.k.a. subthreshold current).( ) Gate oxide tunneling. Reverse biased pn junctions Reverse-biased pn junctions.Follows diode law: Il = Ilo(eqVd/kT -1) I i ll f h f Ilo typically a few tenths of nanoamp.

Drain-induced barrier lowering. Gate-induced drain leakage; Punchthrough currents.g Hot carriers.

Modern VLSI Design 4e: Chapter 2 Slide 19 of 25Sharif University of Technology

Sub-threshold current

Sub-threshold current: Isub = ke[(Vgs - Vt)/(S/ln 10)][1-e-qVds/kT] Sub-threshold slope S characterizes

weak inversion current. Subthreshold current is an

exponential function of gateexponential function of gate voltage

S b threshold c rrent is a f nction Sub-threshold current is a function of Vt.C dj V b h i hCan adjust Vt by changing the

substrate bias to control leakage.

Modern VLSI Design 4e: Chapter 2 Slide 20 of 25Sharif University of Technology

Thermal effects

Vicious cycle:yLeakage current causes heating.Heating increases leakage current.g g

Thermal runaway: chip overheats due to leakage. S bthreshold leakage c rrent is the most important Subthreshold leakage current is the most important

temperature-dependent current.8 12 100°C8x-12x per 100°C.

Modern VLSI Design 4e: Chapter 2 Slide 21 of 25Sharif University of Technology

The modern MOSFET

Features of deep submicron MOSFETs:p epitaxial layer for heavily-doped channel; reduced area source/drain contacts for lower capacitance;/ p ; lightly-doped drains to reduce hot electron effects; silicided poly, diffusion to reduce resistance. silicided poly, diffusion to reduce resistance.

Modern VLSI Design 4e: Chapter 2 Slide 22 of 25Sharif University of Technology

Circuit simulation

Circuit simulators like Spice numerically solve device p ymodels and Kirchoff’s laws to determine time-domain circuit behavior.

Numerical solution allows more sophisticated models, non-functional (table-driven) models etc.non functional (table driven) models, etc.

Modern VLSI Design 4e: Chapter 2 Slide 23 of 25Sharif University of Technology

Spice MOSFET models

Level 1: basic transistor equations of Section 2.2; not very q ; yaccurate.

Level 2: more accurate model (effective channel length Level 2: more accurate model (effective channel length, etc.).

Level 3: empirical model Level 3: empirical model. Level 4 (BSIM): efficient empirical model. New models: level 28 (BSIM2), level 47 (BSIM3).

Modern VLSI Design 4e: Chapter 2 Slide 24 of 25Sharif University of Technology

Some Spice model parameters

L, W: transistor length, width., g , KP: transconductance. GAMMA: body bias factor GAMMA: body bias factor. AS, AD: source/drain areas. CJSW: zero-bias sidewall capacitance. CGBO: zero-bias gate/bulk overlap capacitance.g p p

Modern VLSI Design 4e: Chapter 2 Slide 25 of 25Sharif University of Technology