VLSI for 3D Integration: Modeling, Design and

PrototypingNeil Goldsman

Bruce Jacob

George Metze

Omar Ramahi

Mike Khbeis, Akin Akturk, Zeynep Dilli, Xi Shao, Latise Parker

Problems with Conventional 2D Multi-Chip Integration

Bond PadBond Wire

Transmission Line

Pins

Transmission Line

Input OutputIC 1 IC 2

Chip-to-chip PCB integration is limiting:

The parasitics of the bond pads, wires and board buses limit speed, driving capability and functionality

3-D Integration3-D Integration3-D Chip Stacking (die stacking): Bringing bare dies together in a vertical structure.

Advantages:-Enable more mixed signal integration -Increased ratio of active Si substrate area to chip footprint area-Reduction of delay, faster clock speeds and higher bandwidths, through

-Less use of pads, smaller pads-Shorter interconnects-Less parasitic impedance

Disadvantages:-Potential increase in heat dissipation problems-Increased (geometric, computational, routing) design complexity.Research Goals:-Develop prototypes and design tools to understand limits of 2D integration and exploit benefits of 3D integration.

Outline

• Task I: Modeling and Prototyping Device and Chip Heating for 2D & 3D Integration

• Task 2: Modeling and Prototyping for on Chip Electromagnetic Effects

• Task 3: Prototyping and Modeling Passive 3D Structures

Task I: Coupled Modeling of Time-Dependent Full-Chip IC and Quantum Non-Isothermal Device Operation

Pentium III Pentium III Temperature

Motivation :

• As devices get smaller on-chip thermal effects become increasingly important.

• Predictions indicate that chip temperatures will increase exponentially beyond acceptable values.

• Thus modeling of full-chip heating is essential for the design of fail-safe architectures in both 2D and 3D.

Objective :

• Develop heating models for 2D and 3D IC’s.

• Predict circuit and chip performance variations due to chip heating.

• Test the model and develop temperature sensors by fabricating specially designed chips.

% Area % Power0 Bus Interface Unit 4.25 6.2 1 Clock 1.00 5.22 L1 Data Cache 12.5 9.83 Memory Order Buffer 3.25 4.74 Execute 9.45 135 L2 Data Cache 29.75 8.56 Register Alias Table 3.25 4.77 Issue 9.45 14.1 8 Fetch 12.5 16.89 Decode 14.6 17.2Source: www.intel.com

Functional Blocks in Pentium III

MOSFET devices and their thermal connections

KCL-type lumped thermal networkPentium has 40 million nodes

Thermal Network Containing Millions of Nodes

2 2

* 2

( )( ) ( , ) ( )

2

d yE y q x y y

m dy

2

1.

1.

n n n

p p p

qp n D

nJ R G

t q

pJ R G

t q

. n p

TC T J J

t

Schrödinger Eqn.

Poisson Eqn.

Electron Current Continuity Eqn.

Hole Current Continuity Eqn.

Heat flow Eqn.

Device Equations

1 1 1

, , , , 1 , 1, ,, , ,

, 1/ 2 1/ 2, ,

k k k k k k ki j i j i j i j i j i j i jth th k

i j i j i jth th thi j i j i j

T T T T T T TC I T

t R R R

V S V

TC dV TdS HdV

t

i

ij ij ijii i i j i

j ij V

x yTC T T HdV

t z

th zR

x y

thC C

Integrated Circuit Heat Flow Equation

Coupled Flowchart

Flowchart

MOSFET IV Curves for T=300K and 400K; VGS=0.4, 0.7, 1.0V

Temperature profile in the channel of a MOSFET; Far left and right corners are source and drain sides, respectively. Far side is parallel

to gate terminal.

Device Simulations

Maximum chip temperature as a function of uniformly distributed thermal contacts.

Maximum chip temperature for different device counts with constant power density.Temperature profile for a 0.5cm IC with uniform

device activity throughout the chip: Temperature Isotherms range from 300K at the chip edges to 360K inside chip.

Chip Simulations & Cooling with Thermal Contacts

Thermal contacts cool chip

Calculated Pentium III Temperature Profile with non-uniform device activity throughout the chip but with uniform device activity within each functional block: • Temperature Isotherms range from 300K at the chip edges to 340K inside the clock.• Clock and L2 Cache are the hottest and coolest regions, respectively.

Calculated Temperature Profile for Pentium III

Prototyping Temperature Sensor Array (10x10)

Diodes are used as temperature sensors:

Diode current increases exponentially with temperature.

SiO2

metalTask II: Modeling and Measuring the Effects of EM Parasitics and Coupling in 2D and 3D

Microelectronic Circuits

Problems with Conventional 2D Multi-Chip Integration

Bond PadBond Wire

Transmission Line

Pins

Transmission Line

Input OutputIC 1 IC 2

Chip-to-chip PCB integration is limiting:

The parasitics of the bond pads, wires and board buses limit speed, driving capability and functionality

Effect of PadsEffect of PadsDesigned chips with two different ring-oscillators: 1. “External”: Uses bonding pads for stage-to-stage connection 2. “Internal”: Stages directly connected to each other

Effect of Pads: Results SummaryEffect of Pads: Results Summary

Internal Osc.Internal Osc. External Osc.External Osc. One-stage delayOne-stage delay

112 MHz (31-stage)(equivalent to 1.16 GHz for 3 stages)

398 KHz (11-stage)(equivalent to 1.46 MHz for 3 stages)

~330 ps for internal, ~330 ns for external devices

0.6 m chip, measurements taken by Tektronix oscilloscope with 1 pF-capacitance active probe on the breadboard

Speed ratio: 794.5Load ratio: ~1000

Expecting similar results on a PCB

Factor of ~ 800 Faster without Pads & PCB Connections

Effects of EM Coupling in IC

n+ n+

dbCsbC heR

Noise Injection:• Capacitive Injection• Hot Electron Injection

n+ n+

dbCsbC thV

Noise Reception• Capacitive Reception• Threshold Voltage Modulation

Noise Coupling• Resistive Coupling• Inductance Coupling

subR

IC Chip Layout

12-B

it C

oun

ter Ou

tpu

tD

rive

r

Ou

tpu

tD

rive

r

OutputDriver

PF

DVCO VCO VCO

Digital Switching Noise Testing Circuit 1

Coupling Measurement

50MHz 100MHz 500MHzFrequency:

-2.2dBc/Hz-1.5dBc/Hz -1.8dBc/HzPhaseNoise:

12.8dBc/Hz35.4dBc/Hz 29.1dBc/Hz

Modeling Interconnects and Coupling:

Metal

SubstrateInsulator

(3)

(2)

(1)

2

EJ

Jt

E

cB

t

BE

r

Challenges:• Skin depth effect in the metal layer. • Substrate current.• How to couple large EM wavelength (mm to cm)

scale with fine material structure (of um scale)?• Ans. Develop new EM ADI Maxwell Solver

Maxwell’s Equation

500um

500um

1.8 um

2 um

x

y

z

555 um555 um 6 um

6um

20um

Lossy Silicon Substrate

Activemetal line

SiO2

VacuumPassivemetal line

500um

500um

1.8 um

2 um

x

y

z

555 um555 um 6 um

6um

20um

Lossy Silicon Substrate

Activemetal line

SiO2

VacuumPassivemetal line

Simulating EM Coupling between Interconnect Lines inMetal-Insulator-Silicon-Substrate (MISS) Structure

Adjacent Interconnects X-section Voltage Pulse Coupling Results

Results: New simulator allows for resolving large variations in grid points

Induced voltage 20% of applied signal even at 20μm apart.

500um

500um

1.8 um

2 um

x

y

z

555 um555 um 6 um

6um

20um

Lossy Silicon Substrate

Activemetal line

SiO2

VacuumPassivemetal line

500um

500um

1.8 um

2 um

x

y

z

555 um555 um 6 um

6um

20um

Lossy Silicon Substrate

Activemetal line

SiO2

VacuumPassivemetal line

Simulations show extensive coupling through substrate currents.

Substrate Current: Horizontal x-section

Substrate Current: Vertical x-section

Task 3: Prototyping and Modeling 3D Structures

3-D Connections3-D ConnectionsChip-to-chip communication between different chips with vertical vias that require 12m x 12m metal pads

Cadence-extracted capacitance for a pad 9.23 fF: Same order of magnitude as inverter load cap

To be investigated: Extra capacitive effects of the vertical via

in2 out2

out1 in1

3-D Connections: “Symmetric” Chip3-D Connections: “Symmetric” Chip

New chip in fab with structures that can be connected in 3D and planar counterparts for comparison

Planar inductor vs. Multilayer inductor

Layouts for planar inductor (left) and multilayer inductor (right), in fabrication for probe-station measurements. The total length of the inductors are the same, and the two pictures are of the same scale. Note the much smaller footprint of the multilayer inductor.

Modeling Inductance

I

I

I

s

LLL

LLL

LLL

V

V

V

NNNmNm

Nmm

Nmm

N

2,1,

1,2221,

1,12,11

2

1Net inductance represented by inductance matrix:

•Diagonal elements: self-inductances of segments

•Off-diagonal elements: mutual inductances between segments

j

i j

a jj

i a jij aij

jij

iijm

daJ

ldldr

dadaJ

aL

1

4,

Mutual inductance calculation: The vector potential approach

Planar Inductor vs. Multilayer Inductor

Same net length same net resistance, but higher inductance.(four-level multilayer)

Conclusion:

• A methodology was developed to model full-chip heating.• Predictions show thermal coupling between devices causes the chip heating. • Excessive heating will render circuits inoperable.• Careful placement of micron-scale thermal contacts should relieve the problem.•To test our methodology and develop new technology, we designed a chip and submitted it to MOSIS for fabrication.

Conclusion:

• Prototyped chips show 30dBm in 2D EM noise coupling• An Electromagnetic Solver was developed that is tailored to

IC’s• The method can be used to resolve the coupling between large

EM wave length and fine material structure, e.g. IC on-chip interconnects.

• Show the dispersion and decaying of the signal propagating along the Metal Insulator Semiconductor Substrate (MISS) structure.

• Show the detailed structure of the electric and magnetic field inside the metal and substrate. The substrate current can lead to cross-talk and losses.

• In the skin-effect mode region, enhancing the silicon substrate doping conforms the shape of propagating signal better.

Conclusion:

• Prototyping shows bonding pads and I/0 ESD protection circuits can cause 800 times decrease in circuit operation speed.

• 3D integration will obviate need for most I/0 circuits reducing delays.

• Chip modules for 3D integration developed.

• 3D inductors designed and under fabrication.

• Modeling indicates 3D inductors yield superior performance to 2D counterparts.

Future Work

• Incorporate heat sensor into 3D structures and calibrate heat model.

• Incorporate heat conduits into 3D structures.

• Expand EM calculations to 3D interconnects and more passive structures.

• Test fabricated inductor structures to experimentally to verify advantages of 3D.

• Perform 3D stacking of 2D MOSIS chips.

• Develop state-of-the-art mixed signal 3D IC.