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EE 577a VLSI DESIGN I

FALL 2013

INSTRUCTOR: M. PEDRAM

LAB ASSIGNMENT 1

Submitted by

KARTHIK RAMASAMY5539 4733 38

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SPECIFICATION:

Supply Vdd = 1.8V. Data and Clock transitions are 10ps. Clock signal has 50% duty cycle. Both true and the complement signals are available.

SRAM CELL DESIGN:

1. 256 bit SRAM DESIGN:

a)

Read Delay (ns) Write Delay (ns)i. All 6T of 4/2 0.33 0.065ii. 6/2 Inverter Nmos

4/2 Nmos Access4/3 Inverter Pmos

0.28 0.06

I have chosen the case ii.

The area for the 6T SRAM cell of Case ii: 4.6 * 5.05 = 22.725

b) Comparison of Architectures:

The following observations are from the schematic simulations mimicking the load capacitances of thedifferent Architectures.

Read Delay (ns) Write Delay (ns)i. One 644 Bit 0.33 0.225ii. Two 324 Bit (2-1 Mux) 0.33 0.203iii. Four 164 Bit (4-1 Mux) 0.328 0.22

Model:

= 50.14

= 225.78 fF

The elmore delay = 0.69 /2 = 3.9 ps

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c)

The Architecture chosen is 32 8 with 4 (2-1) Mux.

i. The BIT BIT line bar time is 226 ps.ii. Sense Amplifier delay is 58 ps.iii. The write delay is less than the read delay.

Sizing:

Sense Amplifier (Optimized)

= 3um

= 800nm

= 800nm

= 600nm

= 600nm

= 1um

= 1um

Mux: (Read,Write)

Mux has the sizing of

W = 4um

L = 200nm

The write and the Precharge circuitry has the default sizing.

2. DECODER DESIGN:

The pre decoding implementation is done with the 3 input NAND, 2 input NAND and 3 input NOR gateswith a enable signal.

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3. OUTPUT REGISTER:

The D-FLIP FLOP (4 FF) using Transmission Gate is used at the output of the Sense Amplifier with theClock Period of 3ns.

4. SRAM LAYOUT:

The 256 bit SRAM Layout is done using the optimized 6T SRAM cell, Row Decoder, Write Circuitry, ReadCircuitry, Column Muxes and the output Registers. Metal 1,2,3 are used for routing.

DELAY OF SRAM:

READ DELAY OF SRAM 256bits = 3ns

AREA = 13,348.68

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LVS OUTPUT:

@(#)$CDS: LVS version 6.1.4-64b 09/21/2011 03:25 (sjfdl054) $

Command line: /usr/local/cadence/IC610/tools.lnx86/dfII/bin/64bit/LVS -dir /home/scf-13/kramasam/cds/LVS -l -s -t /home/scf-13/kramasam/cds/LVS/layout /home/scf-13/kramasam/cds/LVS/schematicLike matching is enabled.Net swapping is enabled.Using terminal names as correspondence points.Compiling Diva LVS rules...

Net-list summary for /home/scf-13/kramasam/cds/LVS/layout/netlistcount

808 nets36 terminals864 pmos

1412 nmos

Net-list summary for /home/scf-13/kramasam/cds/LVS/schematic/netlistcount

808 nets36 terminals840 pmos1340 nmos

Terminal correspondence points

N778 N33 A0N799 N94 A0_bN776 N87 A1N785 N91 A1_bN775 N83 A2N800 N101 A2_bN774 N98 A3N786 N105 A3_bN773 N97 A4N801 N104 A4_bN772 N38 A5N787 N100 A5_bN805 N14 D0N804 N99 D1N803 N26 D2N802 N103 D3N784 N92 D_b0N783 N86 D_b1N782 N52 D_b2N780 N74 D_b3

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N806 N50 PrechargeN792 N22 Read_enN795 N27 Write_enN791 N82 Z0N797 N79 Z0_bN790 N13 Z1N777 N96 Z1_bN789 N12 Z2N798 N95 Z2_bN788 N15 Z3N779 N20 Z3_bN796 N49 clkN807 N19 clk_bN793 N17 enN781 N1 gnd!N794 N0 vdd!

Devices in the netlist but not in the rules:pcapacitor

Devices in the rules but not in the netlist:cap nfet pfet nmos4 pmos4

The net-lists match.

layout schematicinstances

un-matched 0 0rewired 0 0

size errors 0 0pruned 0 0active 2276 2180total 2276 2180

netsun-matched 0 0merged 0 0pruned 0 0active 808 808total 808 808

terminalsun-matched 0 0matched butdifferent type 0 0total 36 36

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Probe files from /home/scf-13/kramasam/cds/LVS/schematicdevbad.out:netbad.out:mergenet.out:termbad.out:prunenet.out:prunedev.out:audit.out:

Probe files from /home/scf-13/kramasam/cds/LVS/layoutdevbad.out:netbad.out:mergenet.out:termbad.out:prunenet.out:prunedev.out:audit.out:

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WAVEFORMS:SCHEMATIC:

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LAYOUT WAVEFORMS:

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