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SEMINAR ON VLSI PHYSICAL DESIGN

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Department of Information TechnologySchool Of Technology, Assam University Silchar

Presented ByDeepak Gupta (31320025)B.Tech (IT) 6th SemAssam University , Silchar

Guided By Mr. A. K. Khan Assistant Professor Dept. of Information Technology

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VLSI PHYSICAL DESIGN

CONTENTS

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1. Introduction2. VLSI Design Cycle3. Physical Design4. Physical Design Style5. Physical Packaging Style6. Physical Design Cycle

(A). Partitioning(B). Floor Plan And Placement(C). Routing(D). Layout Optimization(E). Extraction And Verification

7. Summary8. Bibliography

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VLSI PHYSICAL DESIGN

The VLSI ( Very Large Scale Integration ) Circuits is

The Collection of More Over 1 Million Small Chips Integrated on it.

INTRODUCTION

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They are Initially Partitioned or Designed in Small Scale or as Independent Module .

After Designing and Testing Each Modules They are Fabricated in a Single Chip To Form A Large Chip.

That Large Chip is Known as VLSI Circuits.

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VLSI PHYSICAL DESIGN

VLSI Design Cycle

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System Specification

Architectural design

Functional Design Logic Design Circuit

DesignPhysical Design Fabrication Packing and

Testing

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VLSI PHYSICAL DESIGN

Physical Design

Input :- A Net List of Gates (or blocks) and Their interconnections .

Output :- A Geometrical Layout of the Net List Within an Area Constraint .

Goals :- Minimize Signal Delays, interconnection Area, Power

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In The Physical Design of VLSI ( Very Large Scale Integrated ) Circuits , The Logical Structure of a Circuit is Transformed into its Physical Layout.

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VLSI PHYSICAL DESIGN

Physical Design Style

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VLSI PHYSICAL DESIGN

Physical Design Style

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VLSI PHYSICAL DESIGN

Physical Design Style

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VLSI PHYSICAL DESIGN

Comparison of Design Style

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VLSI PHYSICAL DESIGN

Physical Packaging Style

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VLSI PHYSICAL DESIGN

Physical Packaging Style

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VLSI PHYSICAL DESIGN

Physical Design

Cycle Circuit Partitioning

Floor Planning And Placement

Routing

Layout Optimization

Extraction And Verificationwww.i-world-tech.blogspot.in

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VLSI PHYSICAL DESIGN

Partitioni

ng

The Process of Decomposing a Circuit into Smaller Sub-Circuits, Which are Called block, is Known as Partitioning.

Objective : 1. The Size of Each Component is Within

Prescribed Ranges2. The Number of Connections between The

Components is Minimized .

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Good Partitioning : 1. Improve Circuit Performance ( Speeds up The

Design Process )2. Reduce Layout Costs.

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VLSI PHYSICAL DESIGN

Partitioning

Levels Three Types of Partitioning Levels. 1. System Level Partitioning 2. Board Level Partitioning 3. Chip Level Partitioning

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System Level Partitioning

A System is Partitioned into a Set of Sub Systems Where by Each Sub System can be Designed and Fabricated Independently on a PCB or MCM.

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VLSI PHYSICAL DESIGN

Broad Level Partitioning

If PCB is Too Large

The Circuit Assigned To a PCB is Partitioned into Sub Circuits Such That Each Sub Circuit Can be Fabricated as a VLSI Chip.

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If Chip is Too Large

Chip Level Partitioning The Circuit assigned to a Chip is Partitioned into Smaller Sub Circuits.

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VLSI PHYSICAL DESIGN

Partitioning Algorithm

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VLSI PHYSICAL DESIGN

Group Migration Algorithm

Among All Algorithms , Group Migration Algorithm has been The Most Successful heuristics For Partitioning Problems.

Group Migration Algorithms belong To Class of Iterative Improvement Algorithms.

1. These Algorithms Start With Some Initial Partitions Usually Generated Randomly.2. Local Changes are Then Applied To The Partition to Reduce The Cut Size.3. This Process is Repeated until no Further Improvement is Achieved.

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VLSI PHYSICAL DESIGN

Kernighan-Lin (K-L) Algorithm

Time Complexity :

The Partition Sizes have To be Specified before Partitioning.

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Let G(V,E) be a Graph Where , V=Set of Nodes and E=Set of Edges

This Algorithm Attempts To Find a Partition of V into Two Disjoint Subsets A and B of Equal Size, Such That The Sum T of The Weights of The Edges between Nodes in A and B is minimized .

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VLSI PHYSICAL DESIGN

Kernighan-Lin (K-L) Algorithm

Let L(a) be The Internal Cost of a ( The Sum of The Costs of Edges between a and other Nodes in A ).

Let E(a) be The External Cost of a ( The Sum of The Costs of Edges between a and Nodes in B ).

D(a)=E(a)-L(a) Difference b/w External and Internal costs of a.

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If a and b are Interchanged , Then The Reduction in Cost isT(old)-T(new)=D(a)-D(b)-2C(a,b)

Where , C(a,b)=Cost of The Possible Edge between a and b.

The Algorithm Attempts To Find an Optimal Series of Interchange Operations between Elements of A and B Which Maximizes T(old)-T(new) and Then Executes The Operations , Producing a Partition of The Graph To A and B

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VLSI PHYSICAL DESIGN

Kernighan-Lin (K-L) Algorithm

Step-1. Function Kernighan-Lin (G(V,E))Step-2. Determine a balanced initial Partition of The Nodes into Sets A and B Step-3. do Step-4. A1 := A; B1 := B Step-5. Compute D Values For All a in A1 and b in B1 Step-6. For (i := 1 to |V|/2) Step-7. Find a[i] From A1 and b[i] From B1, Such That g[i] = D[a[i]] + D[b[i]] - 2*c[a[i]][b[i]] is Maximal Step-8. Move a[i] to B1 and b[i] to A1

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VLSI PHYSICAL DESIGN

Kernighan-Lin (K-L) Algorithm

Step-9. Remove a[i] and b[i] From Further Consideration in This Pass Step-10. Update D Values For The Elements of A1 = A1 / a[i] and B1 = B1 / b[i] Step-11. End for Step-12. Find k Which Maximizes g_max, The Sum of

g[1],...,g[k] Step-13. if (g_max > 0) Then Step-14. Exchange a[1],a[2],...,a[k] With b[1],b[2],...,b[k] Step-15. Until (g_max <= 0) Step-16. Return G(V,E) www.i-world-tech.blogspot.in

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VLSI PHYSICAL DESIGN

Kernighan-Lin (K-L) Algorithm

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VLSI PHYSICAL DESIGN

Floor Planning and Placement

Floor Planning : Determination of The Approximate Location

of Each Module in a Rectangular Chip Area.

Placement : When Each Module is Fixed , That is , has

Fixed Shape and Fixed Terminals , is The Determination of The best Position For Each Module.

Good Floor Planning and Placement Algorithm :1. Making The Subsequent Routing Phase

Easy 2. Minimizing The Total Chip Area3. Reducing Signal Delays.www.i-world-tech.blogspot.in

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VLSI PHYSICAL DESIGN

Floor Planning and Placement Input : 1. A Set of blocks , both Fixed and Flexible

2. Pin Location of Fixed blocks 3. A Net List

Requirement : 1. Find Location For Each block so That no Two blocks Overlap

2. Determine Shapes of Flexible blocks

Objectives : 1. Minimize Area 2. Reduce Net-Length For Critical Nets

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VLSI PHYSICAL DESIGN

Non-Slicing Floor Plan

Slicing Floor Plan Hierarchical Floor Plan

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VLSI PHYSICAL DESIGN

Floor Planning Algorithm

Rectangular Dual-Graph Approach Hierarchical Approach Simulated Annealing

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VLSI PHYSICAL DESIGN

Rectangular Dual-Graph Approach

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Output of The Partitioning Algorithm Represented by a Graph.

Floor Plan can be obtained by Converting The Graph into its Rectangular dual.

The Rectangular dual of a Graph satisfies The Following Properties :

1. Each Vertex Corresponds To a distinct Rectangle.2. For Every Edge, The Corresponding Rectangles are Adjacent.

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VLSI PHYSICAL DESIGN

Rectangular Dual-Graph Approach

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VLSI PHYSICAL DESIGN

Routing

The Process of Finding The Geometric Layouts (horizontal and vertical) of all The Nets is Called Routing. Routing :

1. Global Routing2. Detailed Routing

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Minimize :Area (Channel Width) Wire Delays Number of LayersCost of Implementation

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VLSI PHYSICAL DESIGN

Routing

Global Routing :Decomposes a Large Routing Problem into

Small , Manageable Problems For Detailed Routing . Method :

First Partitions The Routing Region into a

Collection of Disjoint Rectilinear Sub Regions.

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Detailed Routing : Follows The Global Routing To Effectively Realize Interconnections in VLSI Circuits.

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VLSI PHYSICAL DESIGN

Channel Routing

Problem

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Input Two Vectors of The same Length to represent The

Pins on Two sides of the Channel. One horizontal Layer and one Vertical Layer.

Output Connect Pins of The Same net Together such That

There is no Overlap Among horizontal Wires and There is no overlap Among Vertical Wires.

Minimize the channel width..

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VLSI PHYSICAL DESIGN

Channel Routing Problem

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Given a channel instance

Solution

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VLSI PHYSICAL DESIGN

Vertical Constraint

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Vertical Constraints determine The order in Which The intervals Should be Assigned From Top to bottom Across The height of The Channel.

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VLSI PHYSICAL DESIGN

Horizontal Constraint

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The horizontal Constraints Determines Whether Two intervals Ii

and Ij of Two Different nets ni and nj respectively, are Assignable to The Same Track.

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VLSI PHYSICAL DESIGN

Basic Left-Edge Algorithm

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Problem : Given a Set of Segments (intervals) [ximin , ximax], Put non-Overlapping Segments on The Same Track Such That The Number of Tracks is Minimal.

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VLSI PHYSICAL DESIGN

Basic Left-Edge Algorithm

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Example

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VLSI PHYSICAL DESIGN

Layout Optimization

Layout Optimization is a Post-Processing Step. In This Stage The Layout is Optimized.Ex. by Compacting The Area.

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Compaction is done by Three Ways :(A). By Reducing space between blocks Without Violating design space rule.(B). By Reducing Size of Each block Without Violating Design Size Rule.(C). By Reducing Shape of blocks Without Violating Electrical Characteristics of blocks.

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VLSI PHYSICAL DESIGN

Optimization Techiques

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VLSI PHYSICAL DESIGN

2 Dimensional Approach

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In This Method Compaction is done in both Dimension x-dimension as Well as in y-dimension.

2-D compaction is in General Much better Than Performing 1-D Compaction.

If 2-D Compaction, Solved Optimally, Produces Minimum Area Layouts.

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VLSI PHYSICAL DESIGN

2 Dimensional Approach

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Example

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VLSI PHYSICAL DESIGN

Extraction And Verification

Layout Verification is The Testing of a Layout To Determine if It Satisfies Design and Layout Rules.

This includes Verifying That The Layout

1. Complies With All Technology Requirement.

2. is Consistent With The Original Net List.3. Complies With All Electrical Requirementwww.i-world-tech.blogspot.in

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VLSI PHYSICAL DESIGN

Summa

ry

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Physical design is one of the Steps in the VLSI design Cycle. Physical design is Further divided into

Partitioning , Floor Plan and Placement , Routing , Compaction , Extraction and Verification. There are Four Major design Style :

Full Custom, Standard Cell , Gate Array , and FPGAs. There are Three Alternative For Packing of Chips :

PCB , MCM , and WSI.

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VLSI PHYSICAL DESIGN

Bibliograp

hy

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Comparison of Compaction Techniques in VLSI Physical Design.By : Chetan Sharma and Shobhit Jaiswal

VLSI Physical Design Automation Introduction ,Partitioning , Floor-planningBy : Arnab Sarkar IIT Kharagpur

A Genetic Algorithm for Channel Routing in VLSI CircuitsBy:Jens Lienigt and K. Thulasiraman

Simulated Annealing-Based Channel Routing on Hypercube Computers By: R Mall, L.M. Patnaik, and Srilata Raman

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VLSI PHYSICAL DESIGN

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THANK YOU