MicroLab, VLSI-1 (1/28) JMM v1.4 VLSI System Design VLSI System Design VLSI System Design VLSI System Design Overview of VLSI Design Issues Overview of VLSI Design Issues Overview of VLSI Design Issues Overview of VLSI Design Issues Overview Overview Overview Overview Microelectronic history Microelectronic history Microelectronic history Microelectronic history the complexity of microelectronics the complexity of microelectronics the complexity of microelectronics the complexity of microelectronics design steps design steps design steps design steps Goal: Goal: Goal: Goal: You are familiar with the microelectronics history, You are familiar with the microelectronics history, You are familiar with the microelectronics history, You are familiar with the microelectronics history, have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and you have an overview of the VLSI design steps. you have an overview of the VLSI design steps. you have an overview of the VLSI design steps. you have an overview of the VLSI design steps. Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed by by by by Chris Chris Chris Chris Terman Terman Terman Terman at MIT, completely updated and adapted at at MIT, completely updated and adapted at at MIT, completely updated and adapted at at MIT, completely updated and adapted at MicroLab MicroLab MicroLab MicroLab-I3S) I3S) I3S) I3S)
Transcript
MicroLab, VLSI-1 (1/28)
JMM v1.4
VLSI System DesignVLSI System DesignVLSI System DesignVLSI System DesignOverview of VLSI Design IssuesOverview of VLSI Design IssuesOverview of VLSI Design IssuesOverview of VLSI Design Issues
OverviewOverviewOverviewOverviewMicroelectronic historyMicroelectronic historyMicroelectronic historyMicroelectronic historythe complexity of microelectronicsthe complexity of microelectronicsthe complexity of microelectronicsthe complexity of microelectronicsdesign stepsdesign stepsdesign stepsdesign steps
Goal: Goal: Goal: Goal: You are familiar with the microelectronics history,You are familiar with the microelectronics history,You are familiar with the microelectronics history,You are familiar with the microelectronics history,have an idea about the microelectronics complexity andhave an idea about the microelectronics complexity andhave an idea about the microelectronics complexity andhave an idea about the microelectronics complexity andyou have an overview of the VLSI design steps.you have an overview of the VLSI design steps.you have an overview of the VLSI design steps.you have an overview of the VLSI design steps.
Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed by by by by Chris Chris Chris Chris TermanTermanTermanTerman at MIT, completely updated and adapted at at MIT, completely updated and adapted at at MIT, completely updated and adapted at at MIT, completely updated and adapted at MicroLabMicroLabMicroLabMicroLab----I3S)I3S)I3S)I3S)
MicroLab, VLSI-1 (2/28)
JMM v1.4
What’s expected of youWhat’s expected of youWhat’s expected of youWhat’s expected of you
Readings from a Starter Guide to Readings from a Starter Guide to Readings from a Starter Guide to Readings from a Starter Guide to VHDL and some articles. Some VHDL and some articles. Some VHDL and some articles. Some VHDL and some articles. Some problems to be worked at home. Selfproblems to be worked at home. Selfproblems to be worked at home. Selfproblems to be worked at home. Self----study of the VHDL language with help study of the VHDL language with help study of the VHDL language with help study of the VHDL language with help of the CBT CD from of the CBT CD from of the CBT CD from of the CBT CD from DoulouseDoulouseDoulouseDoulouse....
Some design exercises to be done in Some design exercises to be done in Some design exercises to be done in Some design exercises to be done in the lab. Specify, design and simulate the lab. Specify, design and simulate the lab. Specify, design and simulate the lab. Specify, design and simulate a small VHDL design project using a a small VHDL design project using a a small VHDL design project using a a small VHDL design project using a datadatadatadata----path / path / path / path / finitfinitfinitfinit state machine. state machine. state machine. state machine. Place & route it on a FPGA target Place & route it on a FPGA target Place & route it on a FPGA target Place & route it on a FPGA target technology (due date: July 19technology (due date: July 19technology (due date: July 19technology (due date: July 19thththth at at at at 13h00, 2002)13h00, 2002)13h00, 2002)13h00, 2002)
One 70 minute inOne 70 minute inOne 70 minute inOne 70 minute in----class test. Meant class test. Meant class test. Meant class test. Meant to be duck soup if you’ve been to be duck soup if you’ve been to be duck soup if you’ve been to be duck soup if you’ve been coming to lectures and doing the lab coming to lectures and doing the lab coming to lectures and doing the lab coming to lectures and doing the lab and homework (date: Friday July 12and homework (date: Friday July 12and homework (date: Friday July 12and homework (date: Friday July 12thththth, , , , 2002).2002).2002).2002).
50% in class50% in class50% in class50% in class50% homework50% homework50% homework50% homework
ProjectProjectProjectProject
40% of final grade40% of final grade40% of final grade40% of final grade
TestTestTestTest
60% of final grade60% of final grade60% of final grade60% of final grade
MicroLab, VLSI-1 (3/28)
JMM v1.4
Timetable 4th Semester: Timetable 4th Semester: Timetable 4th Semester: Timetable 4th Semester: Introduction to VLSI System DesignIntroduction to VLSI System DesignIntroduction to VLSI System DesignIntroduction to VLSI System Design
DateDateDateDate TopicTopicTopicTopic SelfSelfSelfSelf----StudyStudyStudyStudy11111111----15.3.15.3.15.3.15.3. vlsi1: history & complexityvlsi1: history & complexityvlsi1: history & complexityvlsi1: history & complexity A VLSI A VLSI A VLSI A VLSI tutorialtutorialtutorialtutorial18181818----22.3.22.3.22.3.22.3. vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies HowHowHowHow a a a a silicon silicon silicon silicon int.int.int.int.25252525----29.3.29.3.29.3.29.3. --------11111111----19.4.19.4.19.4.19.4. vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies article Hoffarticle Hoffarticle Hoffarticle Hoff22222222----26.4.26.4.26.4.26.4. vlsi21: topvlsi21: topvlsi21: topvlsi21: top----down design, VHDLdown design, VHDLdown design, VHDLdown design, VHDL VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT29.429.429.429.4----3.5.3.5.3.5.3.5. Ex400, 401Ex400, 401Ex400, 401Ex400, 401 VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT6666----10.5.10.5.10.5.10.5. -------- VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT13131313----17.5.17.5.17.5.17.5. vlsi21 & Ex402vlsi21 & Ex402vlsi21 & Ex402vlsi21 & Ex402 VHDLVHDLVHDLVHDL20202020----24.5.24.5.24.5.24.5. vlsi21 & Ex404,405 vlsi21 & Ex404,405 vlsi21 & Ex404,405 vlsi21 & Ex404,405 VHDLVHDLVHDLVHDL27272727----31.5.31.5.31.5.31.5. vlsi21 & Ex406vlsi21 & Ex406vlsi21 & Ex406vlsi21 & Ex406----408 408 408 408 VHDLVHDLVHDLVHDL3333----7.6.7.6.7.6.7.6. vlsi21 & Ex409vlsi21 & Ex409vlsi21 & Ex409vlsi21 & Ex409 chapter 5chapter 5chapter 5chapter 510101010----14.6.14.6.14.6.14.6. vlsi21: & Ex410vlsi21: & Ex410vlsi21: & Ex410vlsi21: & Ex410 VHDL finishVHDL finishVHDL finishVHDL finish17171717----21.6. 21.6. 21.6. 21.6. Ex450Ex450Ex450Ex450 projectprojectprojectproject24242424----28.628.628.628.6 Ex451Ex451Ex451Ex451 projectprojectprojectproject1111----5.7.5.7.5.7.5.7. Ex452Ex452Ex452Ex452 projectprojectprojectproject8888----12.6.12.6.12.6.12.6. TestTestTestTest projectprojectprojectproject15151515----19. 619. 619. 619. 6 test discussion and outlooktest discussion and outlooktest discussion and outlooktest discussion and outlook projectprojectprojectproject
19.6. 19.6. 19.6. 19.6. at 13h00 project dueat 13h00 project dueat 13h00 project dueat 13h00 project due
MicroLab, VLSI-1 (4/28)
JMM v1.4
So, what’s VLSI Systems DesignSo, what’s VLSI Systems DesignSo, what’s VLSI Systems DesignSo, what’s VLSI Systems Designall about?all about?all about?all about?
You’ll get a bottomYou’ll get a bottomYou’ll get a bottomYou’ll get a bottom----up tour of how integrated up tour of how integrated up tour of how integrated up tour of how integrated circuits are engineered. We’ll talk aboutcircuits are engineered. We’ll talk aboutcircuits are engineered. We’ll talk aboutcircuits are engineered. We’ll talk aboutfieldfieldfieldfield----effect transistors: how they work, how they’re effect transistors: how they work, how they’re effect transistors: how they work, how they’re effect transistors: how they work, how they’re built, effects of new technologiesbuilt, effects of new technologiesbuilt, effects of new technologiesbuilt, effects of new technologiesvarious design and layout techniques, from the various design and layout techniques, from the various design and layout techniques, from the various design and layout techniques, from the ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational and sequential circuits, and sequential circuits, and sequential circuits, and sequential circuits, datapathsdatapathsdatapathsdatapaths, memories, , memories, , memories, , memories, buffers, regular logic structures, …buffers, regular logic structures, …buffers, regular logic structures, …buffers, regular logic structures, …how you tackle the problem of designing circuits how you tackle the problem of designing circuits how you tackle the problem of designing circuits how you tackle the problem of designing circuits with 1,000,000 gates with 1,000,000 gates with 1,000,000 gates with 1,000,000 gates -------- you’re not in Digital you’re not in Digital you’re not in Digital you’re not in Digital Technique anymore!Technique anymore!Technique anymore!Technique anymore!
microelectronics is a key technology of the world microelectronics is a key technology of the world microelectronics is a key technology of the world microelectronics is a key technology of the world economyeconomyeconomyeconomytechnology development is extremely aggressivetechnology development is extremely aggressivetechnology development is extremely aggressivetechnology development is extremely aggressivepostpostpostpost----grade engineering education is importantgrade engineering education is importantgrade engineering education is importantgrade engineering education is importantinfluence of other technologies like software influence of other technologies like software influence of other technologies like software influence of other technologies like software engineeringengineeringengineeringengineeringkey technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 Japan hold 80% share of the world production of Japan hold 80% share of the world production of Japan hold 80% share of the world production of Japan hold 80% share of the world production of 4MB 4MB 4MB 4MB DRAMsDRAMsDRAMsDRAMs. Artificial raw material shortage are . Artificial raw material shortage are . Artificial raw material shortage are . Artificial raw material shortage are disastrous.disastrous.disastrous.disastrous.very few Swiss chip very few Swiss chip very few Swiss chip very few Swiss chip fabsfabsfabsfabs. Our raw material is the . Our raw material is the . Our raw material is the . Our raw material is the high education standard, that means high education standard, that means high education standard, that means high education standard, that means YOUYOUYOUYOU
MicroLab, VLSI-1 (6/28)
JMM v1.4
What is a VLSI Circuit?What is a VLSI Circuit?What is a VLSI Circuit?What is a VLSI Circuit?
VERY LARGE SCALE INTEGRATED CIRCUITVERY LARGE SCALE INTEGRATED CIRCUITVERY LARGE SCALE INTEGRATED CIRCUITVERY LARGE SCALE INTEGRATED CIRCUIT
Technique where many circuit components and Technique where many circuit components and Technique where many circuit components and Technique where many circuit components and the wiring that connects them are manufactured the wiring that connects them are manufactured the wiring that connects them are manufactured the wiring that connects them are manufactured simultaneously into a compact, reliable and simultaneously into a compact, reliable and simultaneously into a compact, reliable and simultaneously into a compact, reliable and inexpensive chip.inexpensive chip.inexpensive chip.inexpensive chip.
Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit “size” before people realized that the number of “size” before people realized that the number of “size” before people realized that the number of “size” before people realized that the number of components per chip was quadrupling every 24 components per chip was quadrupling every 24 components per chip was quadrupling every 24 components per chip was quadrupling every 24 months (months (months (months (Moore’sMoore’sMoore’sMoore’s Law)! This growth rate has Law)! This growth rate has Law)! This growth rate has Law)! This growth rate has slowed in recent years… can you guess why?slowed in recent years… can you guess why?slowed in recent years… can you guess why?slowed in recent years… can you guess why?
MicroLab, VLSI-1 (7/28)
JMM v1.4
Course Outline/Brief historyCourse Outline/Brief historyCourse Outline/Brief historyCourse Outline/Brief history
Bell Labs lays the groundwork:Bell Labs lays the groundwork:Bell Labs lays the groundwork:Bell Labs lays the groundwork:1940: 1940: 1940: 1940: OhlOhlOhlOhl develops PN junctiondevelops PN junctiondevelops PN junctiondevelops PN junction1945: Shockley’s lab established1945: Shockley’s lab established1945: Shockley’s lab established1945: Shockley’s lab established1947: 1947: 1947: 1947: BardeenBardeenBardeenBardeen and and and and BrattainBrattainBrattainBrattain createcreatecreatecreate
pointpointpointpoint----contact transistor withcontact transistor withcontact transistor withcontact transistor withtwo PN junctions. Gain = 18.two PN junctions. Gain = 18.two PN junctions. Gain = 18.two PN junctions. Gain = 18.
1951: Shockley develops junction1951: Shockley develops junction1951: Shockley develops junction1951: Shockley develops junctiontransistor which can betransistor which can betransistor which can betransistor which can bemanufactured in quantity.manufactured in quantity.manufactured in quantity.manufactured in quantity.
1954: The first transistor radio!1954: The first transistor radio!1954: The first transistor radio!1954: The first transistor radio!Also, TI makes first siliconAlso, TI makes first siliconAlso, TI makes first siliconAlso, TI makes first silicontransistor (price $2.50)transistor (price $2.50)transistor (price $2.50)transistor (price $2.50)
MicroLab, VLSI-1 (8/28)
JMM v1.4
Early integrationEarly integrationEarly integrationEarly integration
Jack Jack Jack Jack KilbyKilbyKilbyKilby, working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea of a monolithic “integrated circuit” in July 1959. By the end oof a monolithic “integrated circuit” in July 1959. By the end oof a monolithic “integrated circuit” in July 1959. By the end oof a monolithic “integrated circuit” in July 1959. By the end of the f the f the f the year, he had constructed several examples, including the flipyear, he had constructed several examples, including the flipyear, he had constructed several examples, including the flipyear, he had constructed several examples, including the flip----flop flop flop flop shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by handhandhandhand----soldered wires and isolated by “shaping” and soldered wires and isolated by “shaping” and soldered wires and isolated by “shaping” and soldered wires and isolated by “shaping” and pnpnpnpn diodes used as diodes used as diodes used as diodes used as resistors.resistors.resistors.resistors.
Robert Robert Robert Robert NoyceNoyceNoyceNoyce experimented in the late 40’s withexperimented in the late 40’s withexperimented in the late 40’s withexperimented in the late 40’s withtransistors while a physics major at college. He went to MIT whtransistors while a physics major at college. He went to MIT whtransistors while a physics major at college. He went to MIT whtransistors while a physics major at college. He went to MIT where ere ere ere “much to his surprise, few people had even heard about the “much to his surprise, few people had even heard about the “much to his surprise, few people had even heard about the “much to his surprise, few people had even heard about the transistor.” After getting his PhD in 1953, he worked in industtransistor.” After getting his PhD in 1953, he worked in industtransistor.” After getting his PhD in 1953, he worked in industtransistor.” After getting his PhD in 1953, he worked in industry, ry, ry, ry, finally arriving at Mountain View, CA and Shockley Semiconductorfinally arriving at Mountain View, CA and Shockley Semiconductorfinally arriving at Mountain View, CA and Shockley Semiconductorfinally arriving at Mountain View, CA and Shockley SemiconductorLabs in 1955.Labs in 1955.Labs in 1955.Labs in 1955.
MicroLab, VLSI-1 (9/28)
JMM v1.4
“ ““ ““ ““ “
In 1957, In 1957, In 1957, In 1957, NoyceNoyceNoyceNoyce left Shockley’sleft Shockley’sleft Shockley’sleft Shockley’slab to form Fairchild Semilab to form Fairchild Semilab to form Fairchild Semilab to form Fairchild Semi----conductor with Jean conductor with Jean conductor with Jean conductor with Jean HoerniHoerniHoerniHoerni....Gordon Moore is anotherGordon Moore is anotherGordon Moore is anotherGordon Moore is anotherfounder.founder.founder.founder.
In early 1958, In early 1958, In early 1958, In early 1958, HoerniHoerniHoerniHoerni invents invents invents invents technique for diffusing impurities technique for diffusing impurities technique for diffusing impurities technique for diffusing impurities intointointointothe silicon to build planar transistors the silicon to build planar transistors the silicon to build planar transistors the silicon to build planar transistors and then using a SiO2 insulator. and then using a SiO2 insulator. and then using a SiO2 insulator. and then using a SiO2 insulator.
In mid 1959, In mid 1959, In mid 1959, In mid 1959, NoyceNoyceNoyceNoyce developsdevelopsdevelopsdevelopsfirst true IC using planar transistors, first true IC using planar transistors, first true IC using planar transistors, first true IC using planar transistors, backbackbackback----totototo----back back back back pnpnpnpn junctions for junctions for junctions for junctions for isolation, diodeisolation, diodeisolation, diodeisolation, diode----isolated silicon isolated silicon isolated silicon isolated silicon resistors and SiO2 insulation with resistors and SiO2 insulation with resistors and SiO2 insulation with resistors and SiO2 insulation with evaporated metal wiring on top.evaporated metal wiring on top.evaporated metal wiring on top.evaporated metal wiring on top.
MicroLab, VLSI-1 (10/28)
JMM v1.4
Practice makes perfect...Practice makes perfect...Practice makes perfect...Practice makes perfect...
1968: 1968: 1968: 1968: NoyceNoyceNoyceNoyce and Moore leaveand Moore leaveand Moore leaveand Moore leaveFairchild and found Intel. NoFairchild and found Intel. NoFairchild and found Intel. NoFairchild and found Intel. Nobusiness plan, just a promisebusiness plan, just a promisebusiness plan, just a promisebusiness plan, just a promiseto specialize in memory chips.to specialize in memory chips.to specialize in memory chips.to specialize in memory chips.They raise $3M in two daysThey raise $3M in two daysThey raise $3M in two daysThey raise $3M in two daysand move to Santa Clara. Byand move to Santa Clara. Byand move to Santa Clara. Byand move to Santa Clara. By1971 Intel had 500 employees;1971 Intel had 500 employees;1971 Intel had 500 employees;1971 Intel had 500 employees;by 1983 it had 21,500by 1983 it had 21,500by 1983 it had 21,500by 1983 it had 21,500employees and $1100M in sales.employees and $1100M in sales.employees and $1100M in sales.employees and $1100M in sales.
1961: TI and Fairchild introduced1961: TI and Fairchild introduced1961: TI and Fairchild introduced1961: TI and Fairchild introducedthe first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in quantity!). This is a dual flipquantity!). This is a dual flipquantity!). This is a dual flipquantity!). This is a dual flip----flop with 4 flop with 4 flop with 4 flop with 4 transistors.transistors.transistors.transistors.
1963: Densities and yields are improving. 1963: Densities and yields are improving. 1963: Densities and yields are improving. 1963: Densities and yields are improving. This circuit has four flip flops. This circuit has four flip flops. This circuit has four flip flops. This circuit has four flip flops.
1.5 mm1.5 mm1.5 mm1.5 mm
0.97 mm0.97 mm0.97 mm0.97 mm
3.81 mm3.81 mm3.81 mm3.81 mm
1967: Fairchild markets the semi1967: Fairchild markets the semi1967: Fairchild markets the semi1967: Fairchild markets the semi----custom custom custom custom chip shown below. Transistors (organized in chip shown below. Transistors (organized in chip shown below. Transistors (organized in chip shown below. Transistors (organized in columns) could be easily rewired using a columns) could be easily rewired using a columns) could be easily rewired using a columns) could be easily rewired using a twotwotwotwo----layer interconnect to create different layer interconnect to create different layer interconnect to create different layer interconnect to create different circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic gates.gates.gates.gates.
MicroLab, VLSI-1 (11/28)
JMM v1.4
The Big BangThe Big BangThe Big BangThe Big Bang
In 1971 Intel introduces the first In 1971 Intel introduces the first In 1971 Intel introduces the first In 1971 Intel introduces the first microprocessor, designed by Ted microprocessor, designed by Ted microprocessor, designed by Ted microprocessor, designed by Ted Hoff. The 4004 had 4Hoff. The 4004 had 4Hoff. The 4004 had 4Hoff. The 4004 had 4----bit buses and bit buses and bit buses and bit buses and a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 transistors and was built in a 10um transistors and was built in a 10um transistors and was built in a 10um transistors and was built in a 10um process. It never captured much process. It never captured much process. It never captured much process. It never captured much interest in the market and was soon interest in the market and was soon interest in the market and was soon interest in the market and was soon eclipsed by its more capable brothers.eclipsed by its more capable brothers.eclipsed by its more capable brothers.eclipsed by its more capable brothers.
2.87 mm2.87 mm2.87 mm2.87 mm
In 1970, making good onIn 1970, making good onIn 1970, making good onIn 1970, making good onits promise to its investors Intel its promise to its investors Intel its promise to its investors Intel its promise to its investors Intel starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the
1103. It was a bear to interface to, 1103. It was a bear to interface to, 1103. It was a bear to interface to, 1103. It was a bear to interface to, but its density and cost make it the but its density and cost make it the but its density and cost make it the but its density and cost make it the
only game it town.only game it town.only game it town.only game it town.
Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 transistors supporting a bytetransistors supporting a bytetransistors supporting a bytetransistors supporting a byte----wide data path. wide data path. wide data path. wide data path. Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first microprocessor capable of playing the role of microprocessor capable of playing the role of microprocessor capable of playing the role of microprocessor capable of playing the role of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of the July ‘74 issue of the July ‘74 issue of the July ‘74 issue of the July ‘74 issue of RadioRadioRadioRadio----ElectronicsElectronicsElectronicsElectronics....
Last, but not least, on our tour is the Last, but not least, on our tour is the Last, but not least, on our tour is the Last, but not least, on our tour is the 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 had 6,000 transistors had 6,000 transistors had 6,000 transistors had 6,000 transistors fab’edfab’edfab’edfab’ed in a 6um in a 6um in a 6um in a 6um
process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more than enough to ignite the personal than enough to ignite the personal than enough to ignite the personal than enough to ignite the personal
computer industry. At least Paul Allen computer industry. At least Paul Allen computer industry. At least Paul Allen computer industry. At least Paul Allen and his partner thought so when they and his partner thought so when they and his partner thought so when they and his partner thought so when they
wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 in 1975. They would later collaborate in in 1975. They would later collaborate in in 1975. They would later collaborate in in 1975. They would later collaborate in
another, more profitable, venture...another, more profitable, venture...another, more profitable, venture...another, more profitable, venture...
MicroLab, VLSI-1 (13/28)
JMM v1.4
TodayTodayTodayToday
Many disciplines have contributed to the current state of the arMany disciplines have contributed to the current state of the arMany disciplines have contributed to the current state of the arMany disciplines have contributed to the current state of the art t t t in VLSI design:in VLSI design:in VLSI design:in VLSI design:
solidsolidsolidsolid----state physicsstate physicsstate physicsstate physicsmaterials sciencematerials sciencematerials sciencematerials sciencelithography and lithography and lithography and lithography and fabfabfabfab
AVPAVPAVPAVP----III Video III Video III Video III Video CodecCodecCodecCodec from Lucent Technologiesfrom Lucent Technologiesfrom Lucent Technologiesfrom Lucent Technologies
We’ll be concentrating on the rightWe’ll be concentrating on the rightWe’ll be concentrating on the rightWe’ll be concentrating on the right----hand columnhand columnhand columnhand column
Tools to do the tedious, repetitive work such asTools to do the tedious, repetitive work such asTools to do the tedious, repetitive work such asTools to do the tedious, repetitive work such asrouting,“tiling” a mosaic of buildingrouting,“tiling” a mosaic of buildingrouting,“tiling” a mosaic of buildingrouting,“tiling” a mosaic of building----block cells, orblock cells, orblock cells, orblock cells, orverifying that the layout and schematic match.verifying that the layout and schematic match.verifying that the layout and schematic match.verifying that the layout and schematic match.
Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at all the process corners. Gateall the process corners. Gateall the process corners. Gateall the process corners. Gate----level and behavioral level and behavioral level and behavioral level and behavioral simulators help you get it right the first time!simulators help you get it right the first time!simulators help you get it right the first time!simulators help you get it right the first time!
Symbolic layout tools toSymbolic layout tools toSymbolic layout tools toSymbolic layout tools toease the task of physicalease the task of physicalease the task of physicalease the task of physicaldesign; mask verificationdesign; mask verificationdesign; mask verificationdesign; mask verificationto ensure manufacturability.to ensure manufacturability.to ensure manufacturability.to ensure manufacturability.
StandardStandardStandardStandard----cell placecell placecell placecell placeand route for “random”and route for “random”and route for “random”and route for “random”logic.logic.logic.logic.
Problem:Problem:Problem:Problem:designing highly complex VLSI circuits designing highly complex VLSI circuits designing highly complex VLSI circuits designing highly complex VLSI circuits (100K to (100K to (100K to (100K to xM fetsxM fetsxM fetsxM fets))))classical, iterative procedures are unsuitableclassical, iterative procedures are unsuitableclassical, iterative procedures are unsuitableclassical, iterative procedures are unsuitableprecise transistor models are necessary for precise transistor models are necessary for precise transistor models are necessary for precise transistor models are necessary for reliable predictions reliable predictions reliable predictions reliable predictions data inflationdata inflationdata inflationdata inflation
Solution:Solution:Solution:Solution:new design methodologiesnew design methodologiesnew design methodologiesnew design methodologiespowerful design toolspowerful design toolspowerful design toolspowerful design toolshigh level design languageshigh level design languageshigh level design languageshigh level design languagessilicon compiler would be usefulsilicon compiler would be usefulsilicon compiler would be usefulsilicon compiler would be useful
Goal:Goal:Goal:Goal:designing circuits with increasing complexity in designing circuits with increasing complexity in designing circuits with increasing complexity in designing circuits with increasing complexity in always shorter timesalways shorter timesalways shorter timesalways shorter times
computer has to take over routine workcomputer has to take over routine workcomputer has to take over routine workcomputer has to take over routine workdeliberate the designer from unnecessary low deliberate the designer from unnecessary low deliberate the designer from unnecessary low deliberate the designer from unnecessary low qualification workqualification workqualification workqualification workshift of design activities to higher level abstract shift of design activities to higher level abstract shift of design activities to higher level abstract shift of design activities to higher level abstract workworkworkworkcomputer has to support new design methodscomputer has to support new design methodscomputer has to support new design methodscomputer has to support new design methods
Chip classification according to number of active Chip classification according to number of active Chip classification according to number of active Chip classification according to number of active elements and minimal feature size:elements and minimal feature size:elements and minimal feature size:elements and minimal feature size:
classificationclassificationclassificationclassification #transistors#transistors#transistors#transistors exampleexampleexampleexampleSSISSISSISSI 1 1 1 1 ---- 100100100100 gatesgatesgatesgatesMSIMSIMSIMSI 100 100 100 100 ---- 1k1k1k1k registersregistersregistersregistersLSILSILSILSI 1k 1k 1k 1k ---- 100k100k100k100k uPuPuPuPVLSIVLSIVLSIVLSI 100K 100K 100K 100K ---- RAM, sig. proc.RAM, sig. proc.RAM, sig. proc.RAM, sig. proc.ULSIULSIULSIULSI ????
can you really imagine the chip complexity of can you really imagine the chip complexity of can you really imagine the chip complexity of can you really imagine the chip complexity of today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere numbernumbernumbernumber
(Multiple choice) (Multiple choice) (Multiple choice) (Multiple choice) This is a picture ofThis is a picture ofThis is a picture ofThis is a picture of
(A) a programmable general purpose ASIC with 1/4 million(A) a programmable general purpose ASIC with 1/4 million(A) a programmable general purpose ASIC with 1/4 million(A) a programmable general purpose ASIC with 1/4 milliontransistors on a 40mmtransistors on a 40mmtransistors on a 40mmtransistors on a 40mm2222 designed in a 0.7designed in a 0.7designed in a 0.7designed in a 0.7µµµµm CMOSm CMOSm CMOSm CMOSfull custom technology. full custom technology. full custom technology. full custom technology.
(B) a processor able to execute 64 knowledge based rules(B) a processor able to execute 64 knowledge based rules(B) a processor able to execute 64 knowledge based rules(B) a processor able to execute 64 knowledge based rulesin parallel due to a 3 stage pipelined architecture within parallel due to a 3 stage pipelined architecture within parallel due to a 3 stage pipelined architecture within parallel due to a 3 stage pipelined architecture withhardhardhardhard----coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture.
(C) the fastest fuzzy processor in the world, designed(C) the fastest fuzzy processor in the world, designed(C) the fastest fuzzy processor in the world, designed(C) the fastest fuzzy processor in the world, designedby by by by MicroLabMicroLabMicroLabMicroLab----I3S and presented at the international I3S and presented at the international I3S and presented at the international I3S and presented at the international FUZZ‘98 conference in New OrleansFUZZ‘98 conference in New OrleansFUZZ‘98 conference in New OrleansFUZZ‘98 conference in New Orleans
Q: Which engineer drew the most Q: Which engineer drew the most Q: Which engineer drew the most Q: Which engineer drew the most fetsfetsfetsfets? ______? ______? ______? ______
MicroLab, VLSI-1 (21/28)
JMM v1.4
VLSI: The Ideal Implementation VLSI: The Ideal Implementation VLSI: The Ideal Implementation VLSI: The Ideal Implementation Medium?Medium?Medium?Medium?
VLSIVLSIVLSIVLSIgives the designer control over almost everything: gives the designer control over almost everything: gives the designer control over almost everything: gives the designer control over almost everything: architecture, logic design, speed, area, power, …architecture, logic design, speed, area, power, …architecture, logic design, speed, area, power, …architecture, logic design, speed, area, power, …densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each passing yearpassing yearpassing yearpassing yearis used by almost everyone: is used by almost everyone: is used by almost everyone: is used by almost everyone: “No one gets fired for “No one gets fired for “No one gets fired for “No one gets fired for building an ASIC”building an ASIC”building an ASIC”building an ASIC”was the enabling technology for much of the was the enabling technology for much of the was the enabling technology for much of the was the enabling technology for much of the economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no doubt continue in its starring role for some time doubt continue in its starring role for some time doubt continue in its starring role for some time doubt continue in its starring role for some time come.come.come.come.
Is life really a bowl of cherries?Is life really a bowl of cherries?Is life really a bowl of cherries?Is life really a bowl of cherries?
MicroLab, VLSI-1 (22/28)
JMM v1.4
VLSI FactVLSI FactVLSI FactVLSI Fact----ofofofof----Life #1:Life #1:Life #1:Life #1:“So much to do, so little time”“So much to do, so little time”“So much to do, so little time”“So much to do, so little time”
lowlowlowlow----level building blocks,level building blocks,level building blocks,level building blocks,highhighhighhigh----level architecturelevel architecturelevel architecturelevel architecture
You need a You need a You need a You need a design methodology design methodology design methodology design methodology ::::
MicroLab, VLSI-1 (23/28)
JMM v1.4
VLSI FactVLSI FactVLSI FactVLSI Fact----ofofofof----Life #2:Life #2:Life #2:Life #2:“You can’t reach in and fix it”“You can’t reach in and fix it”“You can’t reach in and fix it”“You can’t reach in and fix it”
Notice that the word Notice that the word Notice that the word Notice that the word ““““verificationverificationverificationverification”””” kept appearing in kept appearing in kept appearing in kept appearing in the previous slide. the previous slide. the previous slide. the previous slide. Mistakes can be costly:Mistakes can be costly:Mistakes can be costly:Mistakes can be costly:
There’s a lot that needs checking:There’s a lot that needs checking:There’s a lot that needs checking:There’s a lot that needs checking:circuit must operate at all “corners”circuit must operate at all “corners”circuit must operate at all “corners”circuit must operate at all “corners”
verified at building block levelverified at building block levelverified at building block levelverified at building block levellogic must be correct, operate reliablylogic must be correct, operate reliablylogic must be correct, operate reliablylogic must be correct, operate reliably
verified at RTL/gate levelverified at RTL/gate levelverified at RTL/gate levelverified at RTL/gate levelchip has to interoperate with systemchip has to interoperate with systemchip has to interoperate with systemchip has to interoperate with system
verified at behavioral levelverified at behavioral levelverified at behavioral levelverified at behavioral levelchip has to be chip has to be chip has to be chip has to be manufacturabmanufacturabmanufacturabmanufacturable le le le
verified at mask level, at testerverified at mask level, at testerverified at mask level, at testerverified at mask level, at tester
MicroLab, VLSI-1 (24/28)
JMM v1.4
VLSI FactVLSI FactVLSI FactVLSI Fact----ofofofof----Life #3:Life #3:Life #3:Life #3:“Verification is a tedious task”“Verification is a tedious task”“Verification is a tedious task”“Verification is a tedious task”
MicroLab, VLSI-1 (25/28)
JMM v1.4
VLSI FactVLSI FactVLSI FactVLSI Fact----ofofofof----Life #4:Life #4:Life #4:Life #4:“You can’t “You can’t “You can’t “You can’t findfindfindfind all the bugs”all the bugs”all the bugs”all the bugs”
The key word here is “find”:The key word here is “find”:The key word here is “find”:The key word here is “find”:one can’t explore the one can’t explore the one can’t explore the one can’t explore the behaviourbehaviourbehaviourbehaviour of the circuit under all of the circuit under all of the circuit under all of the circuit under all possible conditionspossible conditionspossible conditionspossible conditionssome of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions which, by definition, one never thinks of testingwhich, by definition, one never thinks of testingwhich, by definition, one never thinks of testingwhich, by definition, one never thinks of testingit’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! Time pressures mean that most searches stop too soon.Time pressures mean that most searches stop too soon.Time pressures mean that most searches stop too soon.Time pressures mean that most searches stop too soon.
The trick is to choose some implementation rules that The trick is to choose some implementation rules that The trick is to choose some implementation rules that The trick is to choose some implementation rules that result in a circuit that is result in a circuit that is result in a circuit that is result in a circuit that is correct by construction*correct by construction*correct by construction*correct by construction*. For . For . For . For example:example:example:example:
choose a simple clocking schemechoose a simple clocking schemechoose a simple clocking schemechoose a simple clocking schememodule inputs must go only to module inputs must go only to module inputs must go only to module inputs must go only to fetfetfetfet gatesgatesgatesgatesdisallow disallow disallow disallow unclockedunclockedunclockedunclocked feedbackfeedbackfeedbackfeedbackmake register t(make register t(make register t(make register t(clkclkclkclk----totototo----Q) > t(hold)+skewQ) > t(hold)+skewQ) > t(hold)+skewQ) > t(hold)+skewuse poly only for local interconnectuse poly only for local interconnectuse poly only for local interconnectuse poly only for local interconnectno diffusion wiresno diffusion wiresno diffusion wiresno diffusion wiresetc., etc., etc.etc., etc., etc.etc., etc., etc.etc., etc., etc.
* or at least avoid as many problems as possible!* or at least avoid as many problems as possible!* or at least avoid as many problems as possible!* or at least avoid as many problems as possible!
Plan for what happens after you turn it on and Plan for what happens after you turn it on and Plan for what happens after you turn it on and Plan for what happens after you turn it on and nothing happens.nothing happens.nothing happens.nothing happens.
provide lot’s of provide lot’s of provide lot’s of provide lot’s of observabilityobservabilityobservabilityobservability and and and and controlabilitycontrolabilitycontrolabilitycontrolability. . . . You’ll need to localize and then find the bug.You’ll need to localize and then find the bug.You’ll need to localize and then find the bug.You’ll need to localize and then find the bug.
have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it without it burning up or loosing bits.without it burning up or loosing bits.without it burning up or loosing bits.without it burning up or loosing bits.
figure out how to track down performance figure out how to track down performance figure out how to track down performance figure out how to track down performance problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins are slow!)are slow!)are slow!)are slow!)
leave room in the budgetleave room in the budgetleave room in the budgetleave room in the budget(time, (time, (time, (time, EcuEcuEcuEcu) for debugging.) for debugging.) for debugging.) for debugging.
write and run yourwrite and run yourwrite and run yourwrite and run yourmanufacturing testsmanufacturing testsmanufacturing testsmanufacturing testsbeforebeforebeforebefore tape out.tape out.tape out.tape out.
MicroLab, VLSI-1 (27/28)
JMM v1.4
Microelectronics in 4th SemesterMicroelectronics in 4th SemesterMicroelectronics in 4th SemesterMicroelectronics in 4th Semester
history &history &history &history &complexitycomplexitycomplexitycomplexity
EXPERIENCEEXPERIENCEEXPERIENCEEXPERIENCEdata path / data path / data path / data path / fsmfsmfsmfsm
projectprojectprojectproject
synthesissynthesissynthesissynthesis
Course materialCourse materialCourse materialCourse materialTextbook fromTextbook fromTextbook fromTextbook from WesteWesteWesteWeste & & & & EshraghianEshraghianEshraghianEshraghian for for for for 4th and 5th semester (voluntary) 4th and 5th semester (voluntary) 4th and 5th semester (voluntary) 4th and 5th semester (voluntary) Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes)VHDL VHDL VHDL VHDL StarterStarterStarterStarter (recommended)(recommended)(recommended)(recommended)CAD Exercises on the CAD Exercises on the CAD Exercises on the CAD Exercises on the MicroLabMicroLabMicroLabMicroLab web pagesweb pagesweb pagesweb pagesCBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending from from from from MicroLabMicroLabMicroLabMicroLab in 4th semester)in 4th semester)in 4th semester)in 4th semester)different small articlesdifferent small articlesdifferent small articlesdifferent small articles
MicroLab, VLSI-1 (28/28)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
We’ll be traveling topWe’ll be traveling topWe’ll be traveling topWe’ll be traveling top----down in 4th semester and down in 4th semester and down in 4th semester and down in 4th semester and bottombottombottombottom----up in 5 & 6 semester:up in 5 & 6 semester:up in 5 & 6 semester:up in 5 & 6 semester:
Next topic…Next topic…Next topic…Next topic…Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, gate array, seagate array, seagate array, seagate array, sea----ofofofof----gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny micromicromicromicro----controllers.controllers.controllers.controllers.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…web CBT tutorials see on web CBT tutorials see on web CBT tutorials see on web CBT tutorials see on
http://www.http://www.http://www.http://www.microlabmicrolabmicrolabmicrolab....chchchch/academics/courses/academics/courses/academics/courses/academics/coursesHow a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT)A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR (web CBT from(web CBT from(web CBT from(web CBT from UniUniUniUni Manchester)Manchester)Manchester)Manchester)T. HoffT. HoffT. HoffT. Hoff: Article about the : Article about the : Article about the : Article about the µµµµPPPP History (GHistory (GHistory (GHistory (Germanermanermanerman))))To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle some die photos of oldiesome die photos of oldiesome die photos of oldiesome die photos of oldie----butbutbutbut----goodie chips browse goodie chips browse goodie chips browse goodie chips browse at the Intel link of the at the Intel link of the at the Intel link of the at the Intel link of the MicroLabMicroLabMicroLabMicroLab VLSI course web VLSI course web VLSI course web VLSI course web page.page.page.page.
Are device models asAre device models asAre device models asAre device models asnice as Cindy ?nice as Cindy ?nice as Cindy ?nice as Cindy ?
OverviewOverviewOverviewOverviewThe large signal MOSFET model and second order The large signal MOSFET model and second order The large signal MOSFET model and second order The large signal MOSFET model and second order
effects. MOSFET capacitances.effects. MOSFET capacitances.effects. MOSFET capacitances.effects. MOSFET capacitances.Introduction in Introduction in Introduction in Introduction in fet fet fet fet process technologyprocess technologyprocess technologyprocess technology
Goal: Goal: Goal: Goal: You can use the large signal equivalent MOS You can use the large signal equivalent MOS You can use the large signal equivalent MOS You can use the large signal equivalent MOS device equation. You are familiar with second order device equation. You are familiar with second order device equation. You are familiar with second order device equation. You are familiar with second order effects like body effect, channel length modulation. effects like body effect, channel length modulation. effects like body effect, channel length modulation. effects like body effect, channel length modulation. You know the MOS capacitances. You know the You know the MOS capacitances. You know the You know the MOS capacitances. You know the You know the MOS capacitances. You know the basic steps in MOS fabrication.basic steps in MOS fabrication.basic steps in MOS fabrication.basic steps in MOS fabrication.
MicroLab, VLSI-2 (2/24)
JMM v1.4
Let’s build a MOSFETLet’s build a MOSFETLet’s build a MOSFETLet’s build a MOSFETThere are lots of different recipes to choose from. There are lots of different recipes to choose from. There are lots of different recipes to choose from. There are lots of different recipes to choose from. Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation hardness, reduced latchhardness, reduced latchhardness, reduced latchhardness, reduced latch----up and substrate noise, … up and substrate noise, … up and substrate noise, … up and substrate noise, … are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general process: bulk CMOS with a pprocess: bulk CMOS with a pprocess: bulk CMOS with a pprocess: bulk CMOS with a p----type substrate:type substrate:type substrate:type substrate:
pppp----typetypetypetype
500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to increase the concentration of holes to 10increase the concentration of holes to 10increase the concentration of holes to 10increase the concentration of holes to 1014141414/cm/cm/cm/cm3333
---- 1010101018181818/cm/cm/cm/cm3333....
Back is metaBack is metaBack is metaBack is metalllllilililizzzzed to provideed to provideed to provideed to providea good ground connection.a good ground connection.a good ground connection.a good ground connection.
Good for nGood for nGood for nGood for n----channel channel channel channel fetsfetsfetsfets, but p, but p, but p, but p----channelchannelchannelchannelfetsfetsfetsfets will need a nwill need a nwill need a nwill need a n----type “well” (or tub) totype “well” (or tub) totype “well” (or tub) totype “well” (or tub) tolive in!live in!live in!live in!
Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called field oxidefield oxidefield oxidefield oxide, is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we want to make a want to make a want to make a want to make a mosfetmosfetmosfetmosfet::::
pppp
Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen. wafer to dry oxygen. wafer to dry oxygen. wafer to dry oxygen.
pppp
The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the more oomph the more oomph the more oomph the more oomph the fetfetfetfet will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the harder it is to make it defect free. harder it is to make it defect free. harder it is to make it defect free. harder it is to make it defect free.
MicroLab, VLSI-2 (4/24)
JMM v1.4
On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polycrystalline silicon, called polycrystalline silicon, called polycrystalline silicon, called polysiliconpolysiliconpolysiliconpolysilicon or or or or polypolypolypoly for for for for short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and drain junctions will be formed:drain junctions will be formed:drain junctions will be formed:drain junctions will be formed:
pppp
field oxidefield oxidefield oxidefield oxidepoly wirespoly wirespoly wirespoly wiresgate oxidegate oxidegate oxidegate oxide(only under poly)(only under poly)(only under poly)(only under poly)
exposed surface for sourceexposed surface for sourceexposed surface for sourceexposed surface for sourceand drain junctionsand drain junctionsand drain junctionsand drain junctions
Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a can be reduced by adding a layer of a can be reduced by adding a layer of a can be reduced by adding a layer of a silicidedsilicidedsilicidedsilicided refractory refractory refractory refractory metal such titanium (TiSimetal such titanium (TiSimetal such titanium (TiSimetal such titanium (TiSi2222), tantalum (TaSi), tantalum (TaSi), tantalum (TaSi), tantalum (TaSi2222) or ) or ) or ) or molybdenum (MoSimolybdenum (MoSimolybdenum (MoSimolybdenum (MoSi2222). These have sheet resistances of 1, ). These have sheet resistances of 1, ). These have sheet resistances of 1, ). These have sheet resistances of 1, 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for memory structures that have lots of poly wiring. memory structures that have lots of poly wiring. memory structures that have lots of poly wiring. memory structures that have lots of poly wiring.
MicroLab, VLSI-2 (5/24)
JMM v1.4
The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron implantation, with phosphorus (an electron implantation, with phosphorus (an electron implantation, with phosphorus (an electron donordonordonordonor) which ) which ) which ) which creates two ncreates two ncreates two ncreates two n----type regions in the substrate. The type regions in the substrate. The type regions in the substrate. The type regions in the substrate. The phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance and affecting the and affecting the and affecting the and affecting the nfet’snfet’snfet’snfet’s threshold.threshold.threshold.threshold.
Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then reflowedreflowedreflowedreflowed to to to to flattenflattenflattenflatten its surface. Holes are etched in the its surface. Holes are etched in the its surface. Holes are etched in the its surface. Holes are etched in the oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and alumialumialumialuminnnnum deposited, patterned and etched.um deposited, patterned and etched.um deposited, patterned and etched.um deposited, patterned and etched.
diffusions are “selfdiffusions are “selfdiffusions are “selfdiffusions are “self----aligned”aligned”aligned”aligned”with polywith polywith polywith poly
mobile electrons,mobile electrons,mobile electrons,mobile electrons,fixed positive ionsfixed positive ionsfixed positive ionsfixed positive ions(n+ means heavily(n+ means heavily(n+ means heavily(n+ means heavilydoped with donors,doped with donors,doped with donors,doped with donors,doesn’t implydoesn’t implydoesn’t implydoesn’t implypositive charge!)positive charge!)positive charge!)positive charge!)
depletion layerdepletion layerdepletion layerdepletion layerno mobile carriers,no mobile carriers,no mobile carriers,no mobile carriers,but fixed negative ionsbut fixed negative ionsbut fixed negative ionsbut fixed negative ions(slight intrusion into n+,(slight intrusion into n+,(slight intrusion into n+,(slight intrusion into n+,but mostly in p area)but mostly in p area)but mostly in p area)but mostly in p area)
Picture shows configuration when Picture shows configuration when Picture shows configuration when Picture shows configuration when VgsVgsVgsVgs < < < < VtoVtoVtoVto
BBBB
SSSS DDDD
GGGGTerminal with higher Terminal with higher Terminal with higher Terminal with higher voltage is labelled D,voltage is labelled D,voltage is labelled D,voltage is labelled D,the other is labelled Sthe other is labelled Sthe other is labelled Sthe other is labelled Sso Ids >= 0.so Ids >= 0.so Ids >= 0.so Ids >= 0.
IIIIdsdsdsds = 0= 0= 0= 0
Other symbols:Other symbols:Other symbols:Other symbols:
almost always groundalmost always groundalmost always groundalmost always ground
MicroLab, VLSI-2 (7/24)
JMM v1.4
FET = field effect transistorFET = field effect transistorFET = field effect transistorFET = field effect transistorThe four terminals of a The four terminals of a The four terminals of a The four terminals of a fetfetfetfet (gate, source, drain and bulk) (gate, source, drain and bulk) (gate, source, drain and bulk) (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on the relative voltages of each terminal. the relative voltages of each terminal. the relative voltages of each terminal. the relative voltages of each terminal.
EEEEhhhh EEEEvvvv
sourcesourcesourcesource draindraindraindrain
gategategategate
bulkbulkbulkbulk
INVERSION:INVERSION:INVERSION:INVERSION:A sufficiently A sufficiently A sufficiently A sufficiently ststststrrrronononongggg verticalverticalverticalverticalfield will attract enoughfield will attract enoughfield will attract enoughfield will attract enoughelectrons to the surface toelectrons to the surface toelectrons to the surface toelectrons to the surface tocreate a conducting ncreate a conducting ncreate a conducting ncreate a conducting n----type channel type channel type channel type channel between the source and drain.between the source and drain.between the source and drain.between the source and drain.
CONDUCTION:CONDUCTION:CONDUCTION:CONDUCTION:If a channel exists, aIf a channel exists, aIf a channel exists, aIf a channel exists, ahorizontal field will causehorizontal field will causehorizontal field will causehorizontal field will causea drift current from thea drift current from thea drift current from thea drift current from thedrain to the source.drain to the source.drain to the source.drain to the source.Expect Ids proportionalExpect Ids proportionalExpect Ids proportionalExpect Ids proportionalto to to to VdsVdsVdsVds*(W/L)?*(W/L)?*(W/L)?*(W/L)?
inversioninversioninversioninversionhappens herehappens herehappens herehappens here
Picture shows configuration Picture shows configuration Picture shows configuration Picture shows configuration when when when when VgbVgbVgbVgb > > > > VtoVtoVtoVto
MicroLab, VLSI-2 (8/24)
JMM v1.4
Threshold voltageThreshold voltageThreshold voltageThreshold voltageThe gate voltage required to form the channel is called the The gate voltage required to form the channel is called the The gate voltage required to form the channel is called the The gate voltage required to form the channel is called the threshold threshold threshold threshold voltagevoltagevoltagevoltage. Many factors affect the gate. Many factors affect the gate. Many factors affect the gate. Many factors affect the gate----source voltage at which the source voltage at which the source voltage at which the source voltage at which the channel becomes conductive. Threshold voltage for sourcechannel becomes conductive. Threshold voltage for sourcechannel becomes conductive. Threshold voltage for sourcechannel becomes conductive. Threshold voltage for source----bulk voltage bulk voltage bulk voltage bulk voltage zero:zero:zero:zero:
0.61V for n0.61V for n0.61V for n0.61V for n----channelchannelchannelchannel----0.61V for p0.61V for p0.61V for p0.61V for p----channelchannelchannelchannel
iiii
AAAA
nnnnNNNN
lnlnlnlnqqqqkTkTkTkT2
εεεε oxoxoxox
oxoxoxoxtttt
FAsi Nq φε 22
VVVV VVVV VVVVTOTOTOTO tttt msmsmsms fbfbfbfb= +−
2222iiii
AAAADDDD
nnnnNNNNNNNN
lnlnlnlnqqqqkTkTkTkT
ox
fcms
ox
bFTO C
QCQ
V −++= φφ2
MicroLab, VLSI-2 (9/24)
JMM v1.4
Body effect (second order)Body effect (second order)Body effect (second order)Body effect (second order)As As As As VVVVsbsbsbsb increases, the depth of the depletion region increases, the depth of the depletion region increases, the depth of the depletion region increases, the depth of the depletion region increases, exposing more of the fixed acceptor (i.e. increases, exposing more of the fixed acceptor (i.e. increases, exposing more of the fixed acceptor (i.e. increases, exposing more of the fixed acceptor (i.e. negative) ions in the substrate.negative) ions in the substrate.negative) ions in the substrate.negative) ions in the substrate.Thus the second term in the threshold voltage equation on Thus the second term in the threshold voltage equation on Thus the second term in the threshold voltage equation on Thus the second term in the threshold voltage equation on the previous slide increases fromthe previous slide increases fromthe previous slide increases fromthe previous slide increases from
totototo
the threshold voltage of the nthe threshold voltage of the nthe threshold voltage of the nthe threshold voltage of the n----channel transistor is now:channel transistor is now:channel transistor is now:channel transistor is now:
( )FFFFsbsbsbsbAAAAsisisisi
FFFFAAAAsisisisi
2222VVVVNNNNqqqq2222
2222NNNNqqqq2222
Φ+
Φ
εε
As we’ll see, this effect As we’ll see, this effect As we’ll see, this effect As we’ll see, this effect comes into play in comes into play in comes into play in comes into play in seriesseriesseriesseries----connected connected connected connected fetsfetsfetsfetswhere only one of the where only one of the where only one of the where only one of the fetsfetsfetsfets will have will have will have will have VVVVsbsbsbsb = 0 = 0 = 0 = 0 and the other and the other and the other and the other fetsfetsfetsfets will will will will have have have have VVVVsbsbsbsb > 0 and a > 0 and a > 0 and a > 0 and a higher threshold voltage.higher threshold voltage.higher threshold voltage.higher threshold voltage.
Basic DC equationsBasic DC equationsBasic DC equationsBasic DC equations
MOS transistors have 3 regions of operation:MOS transistors have 3 regions of operation:MOS transistors have 3 regions of operation:MOS transistors have 3 regions of operation:cutoffcutoffcutoffcutoff region (region (region (region (subthresholdsubthresholdsubthresholdsubthreshold))))linear region (triode region)linear region (triode region)linear region (triode region)linear region (triode region)saturated region (active region)saturated region (active region)saturated region (active region)saturated region (active region)
CutoffCutoffCutoffCutoff or or or or subthresholdsubthresholdsubthresholdsubthreshold region:region:region:region:VVVVgsgsgsgs <=<=<=<=VVVVtttt
IIIIdsdsdsds = 0= 0= 0= 0There is still a small current described in the There is still a small current described in the There is still a small current described in the There is still a small current described in the second order effects (weak inversion). Important to second order effects (weak inversion). Important to second order effects (weak inversion). Important to second order effects (weak inversion). Important to model for model for model for model for analoganaloganaloganalog circuits:circuits:circuits:circuits: IIII VVVVdsdsdsds dsdsdsds∝∝∝∝
Larger Larger Larger Larger VdsVdsVdsVds increases drift current but increases drift current but increases drift current but increases drift current but also reduces vertical field component also reduces vertical field component also reduces vertical field component also reduces vertical field component which in turn makes channel less deep. which in turn makes channel less deep. which in turn makes channel less deep. which in turn makes channel less deep. Channel will pinchChannel will pinchChannel will pinchChannel will pinch----off, whenoff, whenoff, whenoff, when
only linear when only linear when only linear when only linear when VVVVdsdsdsds is small,is small,is small,is small,otherwise parabolicotherwise parabolicotherwise parabolicotherwise parabolic
max value at max value at max value at max value at VVVVdsdsdsds = = = = VVVVdsatdsatdsatdsat,,,,but then channel isbut then channel isbut then channel isbut then channel ispinched off (see next slide)pinched off (see next slide)pinched off (see next slide)pinched off (see next slide)
Voltage at channel endVoltage at channel endVoltage at channel endVoltage at channel endremains essentiallyremains essentiallyremains essentiallyremains essentiallyconstant at constant at constant at constant at VVVVdsatdsatdsatdsat sosososodrift current also remainsdrift current also remainsdrift current also remainsdrift current also remainsconstant: device is inconstant: device is inconstant: device is inconstant: device is insaturationsaturationsaturationsaturation....
Electrons arriving from source are Electrons arriving from source are Electrons arriving from source are Electrons arriving from source are injected into drain depletion region injected into drain depletion region injected into drain depletion region injected into drain depletion region and accelerated towards drain by field and accelerated towards drain by field and accelerated towards drain by field and accelerated towards drain by field proportional to proportional to proportional to proportional to VVVVdsdsdsds ---- VVVVdsatdsatdsatdsat usually usually usually usually reaching the drift velocity limit.reaching the drift velocity limit.reaching the drift velocity limit.reaching the drift velocity limit.
this is just Ithis is just Ithis is just Ithis is just Idsdsdsds from previous slidefrom previous slidefrom previous slidefrom previous slideevaluated at evaluated at evaluated at evaluated at VVVVdsdsdsds = = = = VVVVdsatdsatdsatdsat
As As As As VVVVdsdsdsds increases,increases,increases,increases,dLdLdLdL get largerget largerget largerget larger
This looks just like aThis looks just like aThis looks just like aThis looks just like afetfetfetfet with a channel lengthwith a channel lengthwith a channel lengthwith a channel lengthof L’ < L. Shorter L’ impliesof L’ < L. Shorter L’ impliesof L’ < L. Shorter L’ impliesof L’ < L. Shorter L’ impliesgreater Igreater Igreater Igreater Idsdsdsds............
As As As As VVVVdsdsdsds increases the effective channel length gets increases the effective channel length gets increases the effective channel length gets increases the effective channel length gets shorter so Ishorter so Ishorter so Ishorter so Idsdsdsds(sat) increases. (sat) increases. (sat) increases. (sat) increases. dLdLdLdL is proportional tois proportional tois proportional tois proportional to
but most people approximate channel but most people approximate channel but most people approximate channel but most people approximate channel length modulation as a linear effect:length modulation as a linear effect:length modulation as a linear effect:length modulation as a linear effect:
“Put it together and what have you got?”“Put it together and what have you got?”“Put it together and what have you got?”“Put it together and what have you got?”
plot of Ids vs. plot of Ids vs. plot of Ids vs. plot of Ids vs. VdsVdsVdsVds for for for for VgsVgsVgsVgs = 0 ,1, 2, 3, 4 and 5V= 0 ,1, 2, 3, 4 and 5V= 0 ,1, 2, 3, 4 and 5V= 0 ,1, 2, 3, 4 and 5V
Can you find the following in the plot?Can you find the following in the plot?Can you find the following in the plot?Can you find the following in the plot?IIIIdsdsdsds vs. vs. vs. vs. VVVVdsdsdsds when when when when VVVVgsgsgsgs = 0V= 0V= 0V= 0VIIIIdsdsdsds vs. vs. vs. vs. VVVVdsdsdsds when when when when VVVVgsgsgsgs = 5V= 5V= 5V= 5Vvalue of value of value of value of VVVVttttvalue of value of value of value of VVVVdsatdsatdsatdsatevidence of body effectevidence of body effectevidence of body effectevidence of body effectevidence of channel length modulationevidence of channel length modulationevidence of channel length modulationevidence of channel length modulation
MicroLab, VLSI-2 (15/24)
JMM v1.4
SPICE ModelsSPICE ModelsSPICE ModelsSPICE ModelsThere are different models used in circuit simulators:There are different models used in circuit simulators:There are different models used in circuit simulators:There are different models used in circuit simulators:
level 1 is our simple model including the most level 1 is our simple model including the most level 1 is our simple model including the most level 1 is our simple model including the most important second order effects describedimportant second order effects describedimportant second order effects describedimportant second order effects describedlevel 2 model is based on device physicslevel 2 model is based on device physicslevel 2 model is based on device physicslevel 2 model is based on device physicslevel 3 is a semilevel 3 is a semilevel 3 is a semilevel 3 is a semi----empirical model allowing to match empirical model allowing to match empirical model allowing to match empirical model allowing to match equations to the real circuitequations to the real circuitequations to the real circuitequations to the real circuit: example BSIM model : example BSIM model : example BSIM model : example BSIM model from Berkeley models from Berkeley models from Berkeley models from Berkeley models subthreshold subthreshold subthreshold subthreshold characteristicscharacteristicscharacteristicscharacteristics
summary of the main SPICE DC parameters used in summary of the main SPICE DC parameters used in summary of the main SPICE DC parameters used in summary of the main SPICE DC parameters used in all three models at the end of this chapterall three models at the end of this chapterall three models at the end of this chapterall three models at the end of this chapter
the dynamic response of MOS systems strongly the dynamic response of MOS systems strongly the dynamic response of MOS systems strongly the dynamic response of MOS systems strongly depends on the parasitic capacitances associated with depends on the parasitic capacitances associated with depends on the parasitic capacitances associated with depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the the MOS device. The total load capacitance on the the MOS device. The total load capacitance on the the MOS device. The total load capacitance on the output of a CMOS gate is the sum of:output of a CMOS gate is the sum of:output of a CMOS gate is the sum of:output of a CMOS gate is the sum of:
gate capacitance (of other inputs connected to out)gate capacitance (of other inputs connected to out)gate capacitance (of other inputs connected to out)gate capacitance (of other inputs connected to out)diffusion capacitance (of drain/source regions)diffusion capacitance (of drain/source regions)diffusion capacitance (of drain/source regions)diffusion capacitance (of drain/source regions)routing capacitances (output to other inputs)routing capacitances (output to other inputs)routing capacitances (output to other inputs)routing capacitances (output to other inputs)
Cg = Cg = Cg = Cg = CgdCgdCgdCgd + + + + CgsCgsCgsCgs + + + + CgbCgbCgbCgbOxideOxideOxideOxide----related capacitances come in two forms: related capacitances come in two forms: related capacitances come in two forms: related capacitances come in two forms:
overlap capacitance (extrinsic) since gate slightlyoverlap capacitance (extrinsic) since gate slightlyoverlap capacitance (extrinsic) since gate slightlyoverlap capacitance (extrinsic) since gate slightlyoverhangs diffusions and bulk:overhangs diffusions and bulk:overhangs diffusions and bulk:overhangs diffusions and bulk:
C(overlap) = W LC(overlap) = W LC(overlap) = W LC(overlap) = W LD D D D CCCCoxoxoxox
channelchannelchannelchannel----charge related capacitances (intrinsic):charge related capacitances (intrinsic):charge related capacitances (intrinsic):charge related capacitances (intrinsic):
saturation:saturation:saturation:saturation: CgbCgbCgbCgb = 0= 0= 0= 0CgdCgdCgdCgd = 0= 0= 0= 0CgsCgsCgsCgs = 0.67 C= 0.67 C= 0.67 C= 0.67 Cox ox ox ox W L W L W L W L
amount of overlapamount of overlapamount of overlapamount of overlap
for Cgbfor Cgbfor Cgbfor Cgb
shielded by channelshielded by channelshielded by channelshielded by channel
equally shared between S and Dequally shared between S and Dequally shared between S and Dequally shared between S and Dnote capacitive coupling of gate and drain/sourcenote capacitive coupling of gate and drain/sourcenote capacitive coupling of gate and drain/sourcenote capacitive coupling of gate and drain/source
Junction capacitances Junction capacitances Junction capacitances Junction capacitances CCCCdbdbdbdb and and and and CCCCsbsbsbsb are a function of theare a function of theare a function of theare a function of theapplied terminal voltages and diffusion dimensions:applied terminal voltages and diffusion dimensions:applied terminal voltages and diffusion dimensions:applied terminal voltages and diffusion dimensions:
zerozerozerozero----bias C/unit area of bottom junctionbias C/unit area of bottom junctionbias C/unit area of bottom junctionbias C/unit area of bottom junction
perimeter of diffusionperimeter of diffusionperimeter of diffusionperimeter of diffusion
nnnn----well always connectedwell always connectedwell always connectedwell always connectedto to to to VddVddVddVdd to keep to keep to keep to keep pnpnpnpnjunction backjunction backjunction backjunction back----biasedbiasedbiasedbiased
threshold voltage isthreshold voltage isthreshold voltage isthreshold voltage isnegative since we neednegative since we neednegative since we neednegative since we needattract holes to formattract holes to formattract holes to formattract holes to forminversion layerinversion layerinversion layerinversion layer
PFET is built inside itsPFET is built inside itsPFET is built inside itsPFET is built inside itsown “substrate”: a nown “substrate”: a nown “substrate”: a nown “substrate”: a n----typetypetypetypewell or tub diffused intowell or tub diffused intowell or tub diffused intowell or tub diffused intopppp----type bulk substrate.type bulk substrate.type bulk substrate.type bulk substrate.Don’t forget well contacts!Don’t forget well contacts!Don’t forget well contacts!Don’t forget well contacts!
Terminal with Terminal with Terminal with Terminal with lowerlowerlowerlowervoltage is labelled D,voltage is labelled D,voltage is labelled D,voltage is labelled D,the other is labelled Sthe other is labelled Sthe other is labelled Sthe other is labelled S
This This This This mosfetmosfetmosfetmosfet is always conducting but, like ordinary is always conducting but, like ordinary is always conducting but, like ordinary is always conducting but, like ordinary enhancement enhancement enhancement enhancement fetsfetsfetsfets, it will conduct more current as , it will conduct more current as , it will conduct more current as , it will conduct more current as VVVVgsgsgsgsincreases. One can build logic circuits with only nincreases. One can build logic circuits with only nincreases. One can build logic circuits with only nincreases. One can build logic circuits with only n----channel devices (NMOS): enhancement channel devices (NMOS): enhancement channel devices (NMOS): enhancement channel devices (NMOS): enhancement fetsfetsfetsfets for for for for pulldownspulldownspulldownspulldownsand depletion and depletion and depletion and depletion fetsfetsfetsfets as static as static as static as static pullupspullupspullupspullups. Since NMOS logic . Since NMOS logic . Since NMOS logic . Since NMOS logic dissipates DC power it’s been largely replaced by CMOS.dissipates DC power it’s been largely replaced by CMOS.dissipates DC power it’s been largely replaced by CMOS.dissipates DC power it’s been largely replaced by CMOS.
SSSS DDDDGGGG
n+n+n+n+ n+n+n+n+
pppp
BBBBchannel doped with donorschannel doped with donorschannel doped with donorschannel doped with donorsto give negative thresholdto give negative thresholdto give negative thresholdto give negative thresholdvoltage, i.e., depletion voltage, i.e., depletion voltage, i.e., depletion voltage, i.e., depletion fetsfetsfetsfetsare always on.are always on.are always on.are always on.
MicroLab, VLSI-2 (21/24)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Static characteristics of MOS inverters: inputStatic characteristics of MOS inverters: inputStatic characteristics of MOS inverters: inputStatic characteristics of MOS inverters: inputand output voltages, noise margins, powerand output voltages, noise margins, powerand output voltages, noise margins, powerand output voltages, noise margins, powerdissipation.dissipation.dissipation.dissipation.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WestWestWestWesteeee: : : :
sections 2 thru 2.23 except 2.2.2.4 sections 2 thru 2.23 except 2.2.2.4 sections 2 thru 2.23 except 2.2.2.4 sections 2 thru 2.23 except 2.2.2.4 ---- 2.2.2.7 (2.2.2.7 (2.2.2.7 (2.2.2.7 (fetfetfetfetmodels),models),models),models),3 thru 3.2.2 (process technology) and 3 thru 3.2.2 (process technology) and 3 thru 3.2.2 (process technology) and 3 thru 3.2.2 (process technology) and 4.3 through 4.3.4 (capacitances)4.3 through 4.3.4 (capacitances)4.3 through 4.3.4 (capacitances)4.3 through 4.3.4 (capacitances)
CBT:CBT:CBT:CBT:Study the chip fabrication text of the university of Study the chip fabrication text of the university of Study the chip fabrication text of the university of Study the chip fabrication text of the university of Manchester at the Manchester at the Manchester at the Manchester at the MicroLabMicroLabMicroLabMicroLab VLSI course web link.VLSI course web link.VLSI course web link.VLSI course web link.
symsymsymsym value value value value units units units units descriptiondescriptiondescriptiondescriptionεεεε0000 8.8542E8.8542E8.8542E8.8542E----12 12 12 12 F/mF/mF/mF/m permittivitypermittivitypermittivitypermittivityεεεεoxoxoxox 3.9 3.9 3.9 3.9 εεεε0000 F/mF/mF/mF/m permittivitypermittivitypermittivitypermittivity of SiOof SiOof SiOof SiO2222
εεεεSiSiSiSi 11.7 11.7 11.7 11.7 εεεε0000 F/mF/mF/mF/m permittivitypermittivitypermittivitypermittivity of siliconof siliconof siliconof siliconVVVVTTTT 25.825.825.825.8 mVmVmVmV kTkTkTkT/q (@300°K)/q (@300°K)/q (@300°K)/q (@300°K)qqqq 1.6022E1.6022E1.6022E1.6022E----19191919 CCCC charge of electroncharge of electroncharge of electroncharge of electronkkkk 1.381E1.381E1.381E1.381E----23232323 J/°KJ/°KJ/°KJ/°K BoltzmannBoltzmannBoltzmannBoltzmann‘s constant‘s constant‘s constant‘s constantnnnniiii 1.45E101.45E101.45E101.45E10 cmcmcmcm----3333 intrinsic carrier concentrationintrinsic carrier concentrationintrinsic carrier concentrationintrinsic carrier concentration
MicroLab, VLSI-2 (23/24)
JMM v1.4
AlcatelAlcatelAlcatelAlcatel 0,5um Process Parameters0,5um Process Parameters0,5um Process Parameters0,5um Process Parameterssymsymsymsym paramparamparamparam nmosnmosnmosnmos pmospmospmospmos unitsunitsunitsunits descriptiondescriptiondescriptiondescriptionVVVVt0t0t0t0 VTOVTOVTOVTO 0.610.610.610.61 ----0.610.610.610.61 VVVV threshold voltagethreshold voltagethreshold voltagethreshold voltagettttoxoxoxox TOXTOXTOXTOX 1E1E1E1E----8888 1E1E1E1E----8888 mmmm thin oxide thicknessthin oxide thicknessthin oxide thicknessthin oxide thicknessNNNNAAAA NSUBNSUBNSUBNSUB 4E164E164E164E16 4E164E164E164E16 cmcmcmcm----3333 substrate doping densitysubstrate doping densitysubstrate doping densitysubstrate doping densityµµµµ U0U0U0U0 290290290290 77772222 cmcmcmcm2222/Vs charge mobility/Vs charge mobility/Vs charge mobility/Vs charge mobilitykkkk KPKPKPKP A/VA/VA/VA/V2222 fet fet fet fet gain factorgain factorgain factorgain factorγγγγ GAMMA GAMMA GAMMA GAMMA VVVV0.50.50.50.5 bulk threshold bulk threshold bulk threshold bulk threshold paramparamparamparam....CCCCoxoxoxox COXCOXCOXCOX F/mF/mF/mF/m2222 oxide oxide oxide oxide capacitanccapacitanccapacitanccapacitance e e e λ αααα/L/L/L/L VVVV----1111 channel lengthchannel lengthchannel lengthchannel lengthαααα modulatmodulatmodulatmodulat....1e1e1e1e----8888 2e2e2e2e----8888 VVVV----1111mmmm----1111 channel length mod fact.channel length mod fact.channel length mod fact.channel length mod fact.φφφφ0000 PBPBPBPB 0.75560.75560.75560.7556 0.784690.784690.784690.78469 VVVV built in junction potent.built in junction potent.built in junction potent.built in junction potent.2222φφφφFFFF PHIPHIPHIPHI 0.770.770.770.77 0.770.770.770.77 VVVV surface inversion pot.surface inversion pot.surface inversion pot.surface inversion pot.
CCCCgb0gb0gb0gb0 CGB0CGB0CGB0CGB0 3.45E3.45E3.45E3.45E----10 10 10 10 ditoditoditodito F/mF/mF/mF/m overlapping cap per 2Loverlapping cap per 2Loverlapping cap per 2Loverlapping cap per 2LCCCCgs0gs0gs0gs0 CGS0CGS0CGS0CGS0 1.38E1.38E1.38E1.38E----10 10 10 10 ditoditoditodito F/mF/mF/mF/m overlapping cap per Woverlapping cap per Woverlapping cap per Woverlapping cap per WCCCCgd0gd0gd0gd0 CGD0CGD0CGD0CGD0 1.38E1.38E1.38E1.38E----10 10 10 10 ditoditoditodito F/mF/mF/mF/m overlapping cap per Woverlapping cap per Woverlapping cap per Woverlapping cap per WCCCCjjjj CJCJCJCJ 7.75E7.75E7.75E7.75E----4 8.15E4 8.15E4 8.15E4 8.15E----4 F/m4 F/m4 F/m4 F/m2222 zerozerozerozero----bias cap / unit Abias cap / unit Abias cap / unit Abias cap / unit ACCCCjswjswjswjsw CJSWCJSWCJSWCJSW 3.44E3.44E3.44E3.44E----10 3.54E10 3.54E10 3.54E10 3.54E----10 F/m10 F/m10 F/m10 F/m zerozerozerozero----bias cap per unit Pbias cap per unit Pbias cap per unit Pbias cap per unit PMMMMjjjj MJ MJ MJ MJ 0.350.350.350.35 0.360.360.360.36 grading grading grading grading coeffcoeffcoeffcoeff for bottomfor bottomfor bottomfor bottomMMMMjsw jsw jsw jsw MJSW MJSW MJSW MJSW 0.260.260.260.26 0.270.270.270.27 grading grading grading grading coeffcoeffcoeffcoeff sidewallsidewallsidewallsidewall
MicroLab, VLSI-2 (24/24)
JMM v1.4
Exercises: VLSIExercises: VLSIExercises: VLSIExercises: VLSI----2222Ex vlsi2.1 (difficulty: easy):Ex vlsi2.1 (difficulty: easy):Ex vlsi2.1 (difficulty: easy):Ex vlsi2.1 (difficulty: easy): Calculate the missing Calculate the missing Calculate the missing Calculate the missing
parameters on the previous transparency like intrinsic parameters on the previous transparency like intrinsic parameters on the previous transparency like intrinsic parameters on the previous transparency like intrinsic transconductancetransconductancetransconductancetransconductance k, bulk threshold parameter k, bulk threshold parameter k, bulk threshold parameter k, bulk threshold parameter γ and and and and oxide capacitance Coxide capacitance Coxide capacitance Coxide capacitance Coxoxoxox of an of an of an of an nfetnfetnfetnfet ((((AlatelAlatelAlatelAlatel 0.50.50.50.5µµµµm processm processm processm process))))
Result: Result: Result: Result: kkkknnnn=100=100=100=100µµµµA/VA/VA/VA/V2222, , , , kkkkpppp=24.9=24.9=24.9=24.9µµµµA/VA/VA/VA/V2222, , , , γγγγ=0.334V=0.334V=0.334V=0.334V0.50.50.50.5, , , , CCCCoxoxoxox=3.45E=3.45E=3.45E=3.45E----7 F/cm7 F/cm7 F/cm7 F/cm2222 (see (see (see (see WesteWesteWesteWeste pp48ff)pp48ff)pp48ff)pp48ff)
Ex vlsi2.2 (difficulty: easy):Ex vlsi2.2 (difficulty: easy):Ex vlsi2.2 (difficulty: easy):Ex vlsi2.2 (difficulty: easy): Calculate the threshold Calculate the threshold Calculate the threshold Calculate the threshold voltage shift due to the body effect of an voltage shift due to the body effect of an voltage shift due to the body effect of an voltage shift due to the body effect of an nfetnfetnfetnfet at at at at VVVVsbsbsbsb = = = = 2.2V (2.2V (2.2V (2.2V (AlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm process)m process)m process)m process)
Result: Result: Result: Result: dVdVdVdVtntntntn = 0.282V (see = 0.282V (see = 0.282V (see = 0.282V (see WesteWesteWesteWeste pp55)pp55)pp55)pp55)Ex vlsi2.3 (difficulty: easy):Ex vlsi2.3 (difficulty: easy):Ex vlsi2.3 (difficulty: easy):Ex vlsi2.3 (difficulty: easy): Calculate the Calculate the Calculate the Calculate the
transconductance transconductance transconductance transconductance ββββnnnn of an of an of an of an nfetnfetnfetnfet ((((AlatelAlatelAlatelAlatel 0.50.50.50.5µµµµm process), m process), m process), m process), W=1 W=1 W=1 W=1 µµµµm, L= 0.5 m, L= 0.5 m, L= 0.5 m, L= 0.5 µµµµmmmm
Result: Result: Result: Result: ββββnnnn=200 =200 =200 =200 µΑµΑµΑµΑ////VVVV2 2 2 2 (see (see (see (see WesteWesteWesteWeste pp53) pp53) pp53) pp53) Ex vlsi2.4 (difficulty: easy):Ex vlsi2.4 (difficulty: easy):Ex vlsi2.4 (difficulty: easy):Ex vlsi2.4 (difficulty: easy): Calculate the capacitances of Calculate the capacitances of Calculate the capacitances of Calculate the capacitances of
an an an an nfetnfetnfetnfet with with with with VsbVsbVsbVsb====VdbVdbVdbVdb=3V, W=1=3V, W=1=3V, W=1=3V, W=1µµµµm, L=0.5m, L=0.5m, L=0.5m, L=0.5µµµµm, m, m, m, A=1A=1A=1A=1µµµµmmmm2222, P=3, P=3, P=3, P=3µµµµm (m (m (m (AlatelAlatelAlatelAlatel 0.50.50.50.5µµµµm process)m process)m process)m process)
Result: Result: Result: Result: CCCCgategategategate=2.35fF, =2.35fF, =2.35fF, =2.35fF, CCCCdraindraindraindrain====CCCCsourcesourcesourcesource=1.2fF (see =1.2fF (see =1.2fF (see =1.2fF (see WesteWesteWesteWestepp183pp183pp183pp183----191)191)191)191)
WesteWesteWesteWeste pp99: 2.10: pp99: 2.10: pp99: 2.10: pp99: 2.10: Have a look at ex 8, 9Have a look at ex 8, 9Have a look at ex 8, 9Have a look at ex 8, 9
MicroLab, VLSI-3 (1/14)
JMM v1.4
VLSI Design IVLSI Design IVLSI Design IVLSI Design IStatic characteristics of MOS inverterStatic characteristics of MOS inverterStatic characteristics of MOS inverterStatic characteristics of MOS inverter
Static characteristics?Static characteristics?Static characteristics?Static characteristics?Does that mean it’s notDoes that mean it’s notDoes that mean it’s notDoes that mean it’s notgoing to move?going to move?going to move?going to move?
OverviewOverviewOverviewOverviewStatic transfer characteristic of CMOS gatesStatic transfer characteristic of CMOS gatesStatic transfer characteristic of CMOS gatesStatic transfer characteristic of CMOS gates
Goal: Goal: Goal: Goal: You You You You know the transfer characteristic of CMOS know the transfer characteristic of CMOS know the transfer characteristic of CMOS know the transfer characteristic of CMOS gates and know how to calculate noise marginsgates and know how to calculate noise marginsgates and know how to calculate noise marginsgates and know how to calculate noise margins
““““Bipolar” LogicBipolar” LogicBipolar” LogicBipolar” LogicIsn’t this aIsn’t this aIsn’t this aIsn’t this aCMOS course?CMOS course?CMOS course?CMOS course?
Bipolar = two signal levelsBipolar = two signal levelsBipolar = two signal levelsBipolar = two signal levels‘0’ when V near 0‘0’ when V near 0‘0’ when V near 0‘0’ when V near 0‘1’ when V near ‘1’ when V near ‘1’ when V near ‘1’ when V near VVVVdddddddd
VVVVdddddddd
VVVVinininin VVVVoutoutoutout
pulluppulluppulluppullup: make this connection: make this connection: make this connection: make this connectionwhen when when when VVVVinininin near 0 so that near 0 so that near 0 so that near 0 so that VVVVoutoutoutout = = = = VVVVdddddddd
pulldownpulldownpulldownpulldown: make this connection: make this connection: make this connection: make this connectionwhen when when when VVVVinininin near near near near VVVVdddddddd so that so that so that so that VVVVoutoutoutout = 0= 0= 0= 0
one power supply => low impedance source for 2 levelsone power supply => low impedance source for 2 levelsone power supply => low impedance source for 2 levelsone power supply => low impedance source for 2 levelsreceivers have a simple job => only make one decisionreceivers have a simple job => only make one decisionreceivers have a simple job => only make one decisionreceivers have a simple job => only make one decisionno DC power if connections not “made” at same timeno DC power if connections not “made” at same timeno DC power if connections not “made” at same timeno DC power if connections not “made” at same timeBoolean logic has been around a long timeBoolean logic has been around a long timeBoolean logic has been around a long timeBoolean logic has been around a long time
What goals do we want to achieve with our inverter What goals do we want to achieve with our inverter What goals do we want to achieve with our inverter What goals do we want to achieve with our inverter implementation (and, more generally, other functions)?implementation (and, more generally, other functions)?implementation (and, more generally, other functions)?implementation (and, more generally, other functions)?
fast propagation delay (next lecture!)fast propagation delay (next lecture!)fast propagation delay (next lecture!)fast propagation delay (next lecture!)low power dissipationlow power dissipationlow power dissipationlow power dissipationcompact layoutcompact layoutcompact layoutcompact layoutnoise immunitynoise immunitynoise immunitynoise immunity
VVVVIHIHIHIHVVVVILILILIL
VVVVOLOLOLOL
VVVVOHOHOHOH
Draw voltageDraw voltageDraw voltageDraw voltage----transfertransfertransfertransfercurve (VTC) for inverter.curve (VTC) for inverter.curve (VTC) for inverter.curve (VTC) for inverter.ShadeShadeShadeShade----in areas thatin areas thatin areas thatin areas thatVTC can’t enter.VTC can’t enter.VTC can’t enter.VTC can’t enter.What can we say aboutWhat can we say aboutWhat can we say aboutWhat can we say aboutgain?gain?gain?gain?What is “ideal” inv. VTC?What is “ideal” inv. VTC?What is “ideal” inv. VTC?What is “ideal” inv. VTC?
VVVVinininin
VVVVoutoutoutout
MicroLab, VLSI-3 (6/14)
JMM v1.4
Noise MarginNoise MarginNoise MarginNoise Margin
noise immunity. Since we’re signalling values using noise immunity. Since we’re signalling values using noise immunity. Since we’re signalling values using noise immunity. Since we’re signalling values using voltages, we want good voltages, we want good voltages, we want good voltages, we want good noise marginsnoise marginsnoise marginsnoise margins. This means . This means . This means . This means that we need to make an allowance for noise when that we need to make an allowance for noise when that we need to make an allowance for noise when that we need to make an allowance for noise when assigning voltage levels for valid inputs and outputsassigning voltage levels for valid inputs and outputsassigning voltage levels for valid inputs and outputsassigning voltage levels for valid inputs and outputsdefinition:definition:definition:definition: NMNMNMNM VVVV VVVV
don’t want to amplify noisedon’t want to amplify noisedon’t want to amplify noisedon’t want to amplify noiseso find values of so find values of so find values of so find values of VinVinVinVin wherewherewherewhereVTC gain = 1 or VTC gain = 1 or VTC gain = 1 or VTC gain = 1 or ----1. Choose1. Choose1. Choose1. Choosesmallest Vsmallest Vsmallest Vsmallest VILILILIL and largest Vand largest Vand largest Vand largest VIHIHIHIH
merged VTC for allmerged VTC for allmerged VTC for allmerged VTC for allprocess corners &process corners &process corners &process corners &
choose values so thatchoose values so thatchoose values so thatchoose values so that(1) VTC is in legal territory(1) VTC is in legal territory(1) VTC is in legal territory(1) VTC is in legal territory(2) leave desired noise(2) leave desired noise(2) leave desired noise(2) leave desired noise
marginsmarginsmarginsmargins
This is a subject on which reasonable peopleThis is a subject on which reasonable peopleThis is a subject on which reasonable peopleThis is a subject on which reasonable peoplecan disagree! One possible line of attack:can disagree! One possible line of attack:can disagree! One possible line of attack:can disagree! One possible line of attack:
NMNMNMNMLLLL NMNMNMNMHHHH
MicroLab, VLSI-3 (8/14)
JMM v1.4
Inverter Inverter Inverter Inverter pulldownpulldownpulldownpulldown devicesdevicesdevicesdevicesThe NFET makes an ideal The NFET makes an ideal The NFET makes an ideal The NFET makes an ideal pulldownpulldownpulldownpulldown device:device:device:device:
IIIIpdpdpdpd
if if if if pulluppulluppulluppullup is off, Vis off, Vis off, Vis off, VOLOLOLOL = ______= ______= ______= ______no DC connection when no DC connection when no DC connection when no DC connection when VVVVinininin < ______< ______< ______< ______increase width to increase increase width to increase increase width to increase increase width to increase IIIIpdpdpdpdcompact layoutcompact layoutcompact layoutcompact layout
Inverter Inverter Inverter Inverter pulluppulluppulluppullup devicesdevicesdevicesdevicesResistor. No load on input, VResistor. No load on input, VResistor. No load on input, VResistor. No load on input, VOHOHOHOH====VVVVddddddddWill dissipate static power; increasing R will reduce Will dissipate static power; increasing R will reduce Will dissipate static power; increasing R will reduce Will dissipate static power; increasing R will reduce power and increase noise margin, but lowpower and increase noise margin, but lowpower and increase noise margin, but lowpower and increase noise margin, but low----totototo----high high high high transition gets slower. Only practical if process transition gets slower. Only practical if process transition gets slower. Only practical if process transition gets slower. Only practical if process supports supports supports supports unununundodododopppped poly which has sheet resistance of 10M ed poly which has sheet resistance of 10M ed poly which has sheet resistance of 10M ed poly which has sheet resistance of 10M Ohm/square.Ohm/square.Ohm/square.Ohm/square.
DepletionDepletionDepletionDepletion----mode NFET. No load on input, Vmode NFET. No load on input, Vmode NFET. No load on input, Vmode NFET. No load on input, VOHOHOHOH====VVVVdddddddd....Connecting gate to source sets Connecting gate to source sets Connecting gate to source sets Connecting gate to source sets VVVVgsgsgsgs = 0 so = 0 so = 0 so = 0 so IIIIpupupupu is is is is determined only by determined only by determined only by determined only by VVVVoutoutoutout. Layout can be compact since . Layout can be compact since . Layout can be compact since . Layout can be compact since pulluppulluppulluppullup is in same well as is in same well as is in same well as is in same well as pulldownpulldownpulldownpulldown; buried contact can be ; buried contact can be ; buried contact can be ; buried contact can be used to connect gate to source. Only found in NMOS used to connect gate to source. Only found in NMOS used to connect gate to source. Only found in NMOS used to connect gate to source. Only found in NMOS processes.processes.processes.processes.
EnhancementEnhancementEnhancementEnhancement----mode NFET. Vmode NFET. Vmode NFET. Vmode NFET. VOHOHOHOH= = = = VVVVdddddddd---- VVVVtttt unless gate of unless gate of unless gate of unless gate of pulluppulluppulluppullup is driven above is driven above is driven above is driven above VVVVdddddddd. If gate is not switched off, . If gate is not switched off, . If gate is not switched off, . If gate is not switched off, pulluppulluppulluppullup needs to be weak to avoid excessive power needs to be weak to avoid excessive power needs to be weak to avoid excessive power needs to be weak to avoid excessive power dissipation, but this may entail larger layouts. Useful dissipation, but this may entail larger layouts. Useful dissipation, but this may entail larger layouts. Useful dissipation, but this may entail larger layouts. Useful where where where where PFETsPFETsPFETsPFETs not wanted (e.g., some I/O structures). not wanted (e.g., some I/O structures). not wanted (e.g., some I/O structures). not wanted (e.g., some I/O structures).
PseudoPseudoPseudoPseudo----NMOS using saturated PFET as loadNMOS using saturated PFET as loadNMOS using saturated PFET as loadNMOS using saturated PFET as loaddevice. Vdevice. Vdevice. Vdevice. VOHOHOHOH= = = = VVVVdddddddd. Useful for building large fan. Useful for building large fan. Useful for building large fan. Useful for building large fan----in NOR in NOR in NOR in NOR gates found in static ROMs and gates found in static ROMs and gates found in static ROMs and gates found in static ROMs and PLAsPLAsPLAsPLAs where static power where static power where static power where static power dissipation is okay. dissipation is okay. dissipation is okay. dissipation is okay.
MicroLab, VLSI-3 (10/14)
JMM v1.4
Inverter with PFET Inverter with PFET Inverter with PFET Inverter with PFET pulluppulluppulluppullup
VVVVinininin VVVVoutoutoutout
negligible steadynegligible steadynegligible steadynegligible steady----statestatestatestatepower dissipationpower dissipationpower dissipationpower dissipationVVVVOLOLOLOL = 0V, V= 0V, V= 0V, V= 0V, VOHOHOHOH = = = = VVVVddddddddVTC transition very sharpVTC transition very sharpVTC transition very sharpVTC transition very sharpswitching point can beswitching point can beswitching point can beswitching point can beadjusted by adjusted by adjusted by adjusted by fetfetfetfet sizingsizingsizingsizing
nonnonnonnon----vertical only becausevertical only becausevertical only becausevertical only becauseof channelof channelof channelof channel----length modulationlength modulationlength modulationlength modulation
Build your own VTCBuild your own VTCBuild your own VTCBuild your own VTCIn the steady state:In the steady state:In the steady state:In the steady state:
When both When both When both When both fetsfetsfetsfets arearearearesaturated, small changessaturated, small changessaturated, small changessaturated, small changesin in in in VVVVinininin produce largeproduce largeproduce largeproduce largechanges in changes in changes in changes in VVVVoutoutoutout
How many would you buy?How many would you buy?How many would you buy?How many would you buy?
MicroLab, VLSI-3 (13/14)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Dynamic characteristics of MOS inverters: Dynamic characteristics of MOS inverters: Dynamic characteristics of MOS inverters: Dynamic characteristics of MOS inverters: propagation delay, effects of rise and fall times. propagation delay, effects of rise and fall times. propagation delay, effects of rise and fall times. propagation delay, effects of rise and fall times. Transistor sizing, interconnect issues, estimating Transistor sizing, interconnect issues, estimating Transistor sizing, interconnect issues, estimating Transistor sizing, interconnect issues, estimating performance.performance.performance.performance.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WestWestWestWesteeee: : : :
Exercises: VLSIExercises: VLSIExercises: VLSIExercises: VLSI----3333Ex vlsi3.1 (difficulty: easy):Ex vlsi3.1 (difficulty: easy):Ex vlsi3.1 (difficulty: easy):Ex vlsi3.1 (difficulty: easy): Calculate the CMOS Calculate the CMOS Calculate the CMOS Calculate the CMOS
inverter threshold values for the following inverter threshold values for the following inverter threshold values for the following inverter threshold values for the following conficonficonficonfi----gurationsgurationsgurationsgurations ((((AlcatelAlcatelAlcatelAlcatel 0,50,50,50,5µµµµm process,Vm process,Vm process,Vm process,VDDDDDDDD=3,3V)=3,3V)=3,3V)=3,3V)a) a) a) a) WWWWnnnn = = = = LLLLnnnn, , , , WWWWpppp = = = = LLLLpppp
b) b) b) b) WWWWnnnn = 10 = 10 = 10 = 10 LLLLnnnn, , , , WWWWpppp = = = = LLLLpppp
c) c) c) c) WWWWnnnn = = = = LLLLnnnn, , , , WWWWpppp = 10 = 10 = 10 = 10 LLLLpppp
Result: a) Result: a) Result: a) Result: a) VVVVinvinvinvinv = 1.30V, b) = 1.30V, b) = 1.30V, b) = 1.30V, b) VVVVinvinvinvinv = 0.893, c) = 0.893, c) = 0.893, c) = 0.893, c) VVVVinvinvinvinv = = = = 1.88V (see 1.88V (see 1.88V (see 1.88V (see WesteWesteWesteWeste pp66)pp66)pp66)pp66)
Ex vlsi3.2 (difficulty: medium, time consuming):Ex vlsi3.2 (difficulty: medium, time consuming):Ex vlsi3.2 (difficulty: medium, time consuming):Ex vlsi3.2 (difficulty: medium, time consuming):Calculate the noise margin and VCalculate the noise margin and VCalculate the noise margin and VCalculate the noise margin and VILILILIL, V, V, V, VIHIHIHIH, V, V, V, VOLOLOLOL, V, V, V, VOHOHOHOH, , , , for a CMOS inverter operating at 3.3V with for a CMOS inverter operating at 3.3V with for a CMOS inverter operating at 3.3V with for a CMOS inverter operating at 3.3V with ββββnnnn= = = = ββββpppp, , , , UUUUtntntntn= = = = ----UUUUtptptptp=0.61V.=0.61V.=0.61V.=0.61V.
WesteWesteWesteWeste pp99: 2.10 ex 5 (difficulty: medium, time pp99: 2.10 ex 5 (difficulty: medium, time pp99: 2.10 ex 5 (difficulty: medium, time pp99: 2.10 ex 5 (difficulty: medium, time consuming):consuming):consuming):consuming): Design an input buffer that may be Design an input buffer that may be Design an input buffer that may be Design an input buffer that may be used to interface with a TTL driver (used to interface with a TTL driver (used to interface with a TTL driver (used to interface with a TTL driver (VVVVdddddddd=3.3V, =3.3V, =3.3V, =3.3V, VVVVOLOLOLOL=0.8V, V=0.8V, V=0.8V, V=0.8V, VOHOHOHOH=2.0V). Show full derivations of =2.0V). Show full derivations of =2.0V). Show full derivations of =2.0V). Show full derivations of DC conditions. Assume DC conditions. Assume DC conditions. Assume DC conditions. Assume WWWWnnnn =1=1=1=1µµµµm and m and m and m and LLLLnnnn = = = = LLLLpppp = = = = 0.50.50.50.5µµµµm m m m
VLSI Design IVLSI Design IVLSI Design IVLSI Design IDynamic characteristics of MOS invertersDynamic characteristics of MOS invertersDynamic characteristics of MOS invertersDynamic characteristics of MOS inverters
Wow! 0 to 3.3 volts in 300ps!Wow! 0 to 3.3 volts in 300ps!Wow! 0 to 3.3 volts in 300ps!Wow! 0 to 3.3 volts in 300ps!
Goal: Goal: Goal: Goal: You are familiar with CMOS gate delay models You are familiar with CMOS gate delay models You are familiar with CMOS gate delay models You are familiar with CMOS gate delay models like Penfieldlike Penfieldlike Penfieldlike Penfield----RubensteinRubensteinRubensteinRubenstein and wire models. You and wire models. You and wire models. You and wire models. You know the influence of body effect and large loads to know the influence of body effect and large loads to know the influence of body effect and large loads to know the influence of body effect and large loads to gate delay. You know why ground bounce gate delay. You know why ground bounce gate delay. You know why ground bounce gate delay. You know why ground bounce occurresoccurresoccurresoccurres. . . . You know the different factors in power dissipation.You know the different factors in power dissipation.You know the different factors in power dissipation.You know the different factors in power dissipation.
sharp transition:sharp transition:sharp transition:sharp transition:inverter goodinverter goodinverter goodinverter goodreceiver for voltagereceiver for voltagereceiver for voltagereceiver for voltage----based signallingbased signallingbased signallingbased signalling
VVVVOHOHOHOH====VVVVdddddddd, V, V, V, VOLOLOLOL=0, sharp transition => good noise margins=0, sharp transition => good noise margins=0, sharp transition => good noise margins=0, sharp transition => good noise marginsVVVVOHOHOHOH====VVVVdddddddd => => => => pfetpfetpfetpfet off when off when off when off when VVVVinininin=V=V=V=VOHOHOHOH => no static power=> no static power=> no static power=> no static powerVVVVOLOLOLOL=0 => =0 => =0 => =0 => nfetnfetnfetnfet off when off when off when off when VVVVinininin=V=V=V=VOLOLOLOL => no static power=> no static power=> no static power=> no static power
Define Define Define Define thesholdthesholdthesholdtheshold voltagevoltagevoltagevoltageVVVVinvinvinvinv as voltage whereas voltage whereas voltage whereas voltage whereVVVVinininin = = = = VVVVoutoutoutout on VTC.on VTC.on VTC.on VTC.
VTC describes static behaviour. When VTC describes static behaviour. When VTC describes static behaviour. When VTC describes static behaviour. When VVVVinininin changes, changes, changes, changes, VVVVoutoutoutout“lags behind” because it takes time for capacitors to “lags behind” because it takes time for capacitors to “lags behind” because it takes time for capacitors to “lags behind” because it takes time for capacitors to charge/discharge. So, in real, life charge/discharge. So, in real, life charge/discharge. So, in real, life charge/discharge. So, in real, life VVVVinininin reaches reaches reaches reaches VVVVthththth beforebeforebeforebeforeVVVVoutoutoutout does.does.does.does.
MicroLab, VLSI-4 (3/29)
JMM v1.3
Choosing what to measureChoosing what to measureChoosing what to measureChoosing what to measure
Rise time, Rise time, Rise time, Rise time, ttttrrrr = time for a waveform to rise from 10% to = time for a waveform to rise from 10% to = time for a waveform to rise from 10% to = time for a waveform to rise from 10% to 90% of its steady90% of its steady90% of its steady90% of its steady----state valuestate valuestate valuestate value
Fall time, Fall time, Fall time, Fall time, ttttffff = time for a waveform to fall from 90% to = time for a waveform to fall from 90% to = time for a waveform to fall from 90% to = time for a waveform to fall from 90% to 10% of its steady10% of its steady10% of its steady10% of its steady----state valuestate valuestate valuestate value
Delay time, tDelay time, tDelay time, tDelay time, tdddd = time between input transition (when = time between input transition (when = time between input transition (when = time between input transition (when VVVVinininin= ???) and output transition (when = ???) and output transition (when = ???) and output transition (when = ???) and output transition (when VVVVoutoutoutout = ???).= ???).= ???).= ???).
If ??? = If ??? = If ??? = If ??? = VVVVinvinvinvinv, can delay be negative?, can delay be negative?, can delay be negative?, can delay be negative?does does does does VVVVinvinvinvinv differ for each gate?differ for each gate?differ for each gate?differ for each gate?so does tso does tso does tso does tdddd(seq. of gates) = sum(t(seq. of gates) = sum(t(seq. of gates) = sum(t(seq. of gates) = sum(tdddd)?)?)?)?should we choose 50% instead of should we choose 50% instead of should we choose 50% instead of should we choose 50% instead of VVVVinvinvinvinv????
VVVVinininin VVVVoutoutoutout
VVVV
tttt
VVVVinininin
VVVVoutoutoutout
90%90%90%90%
10%10%10%10%
????????????
ttttffff
ttttrrrr
ttttdddd
MicroLab, VLSI-4 (4/29)
JMM v1.3
Signal delay timeSignal delay timeSignal delay timeSignal delay time
Signal delay time is composed as followsSignal delay time is composed as followsSignal delay time is composed as followsSignal delay time is composed as followsgate delay timegate delay timegate delay timegate delay timeinterconnection delay timeinterconnection delay timeinterconnection delay timeinterconnection delay time
due to minimization the delay times decreasesdue to minimization the delay times decreasesdue to minimization the delay times decreasesdue to minimization the delay times decreasesthe output impedance of buffers increases, thus the the output impedance of buffers increases, thus the the output impedance of buffers increases, thus the the output impedance of buffers increases, thus the importance of interconnection delays increasesimportance of interconnection delays increasesimportance of interconnection delays increasesimportance of interconnection delays increases
due to continuing miniaturization, signal delay time due to continuing miniaturization, signal delay time due to continuing miniaturization, signal delay time due to continuing miniaturization, signal delay time becomes less dependent on gate delay but more becomes less dependent on gate delay but more becomes less dependent on gate delay but more becomes less dependent on gate delay but more dependent on interconnection delay timedependent on interconnection delay timedependent on interconnection delay timedependent on interconnection delay time
CCCCinininin RRRRnnnn
RRRRpppp
UUUUoutoutoutoutUUUUinininin
UUUUCCCCCCCC
CCCCRRRR
UUUUdsdsdsdsUUUUgsgsgsgs
switch level mode of switch level mode of switch level mode of switch level mode of fetfetfetfet switch level modeswitch level modeswitch level modeswitch level modeof inverterof inverterof inverterof inverter
MicroLab, VLSI-4 (5/29)
JMM v1.3
Fall time analysis #1Fall time analysis #1Fall time analysis #1Fall time analysis #1
the switching speed is limited by the time taken to the switching speed is limited by the time taken to the switching speed is limited by the time taken to the switching speed is limited by the time taken to discharge the capacitance Cdischarge the capacitance Cdischarge the capacitance Cdischarge the capacitance CLLLL
the static transition curve moves to the right if the the static transition curve moves to the right if the the static transition curve moves to the right if the the static transition curve moves to the right if the input transition is fastinput transition is fastinput transition is fastinput transition is fastpppp----fetfetfetfet gets cutgets cutgets cutgets cut----off during the whole falling output timeoff during the whole falling output timeoff during the whole falling output timeoff during the whole falling output timennnn----fetfetfetfet immediately gets saturated, later on linearimmediately gets saturated, later on linearimmediately gets saturated, later on linearimmediately gets saturated, later on linear
So, time to fall from 0.9VSo, time to fall from 0.9VSo, time to fall from 0.9VSo, time to fall from 0.9Vdddddddd totototoVVVVdddddddd ---- VVVVtttt,n,n,n,n is given byis given byis given byis given by
So, time to fall from So, time to fall from So, time to fall from So, time to fall from VVVVdddddddd ---- VVVVtttt,n,n,n,n totototo0.1V0.1V0.1V0.1Vdddddddd is given byis given byis given byis given by
functionfunctionfunctionfunctionof of of of VVVVoutoutoutout
Adding to get total fall time (Adding to get total fall time (Adding to get total fall time (Adding to get total fall time (WesteWesteWesteWeste, , , , EqEqEqEq 4.37):4.37):4.37):4.37):VVVVtttt,n,n,n,n////VVVVdddddddd
ttttrrrr isisisissimilarsimilarsimilarsimilar equals 3 to 4 for equals 3 to 4 for equals 3 to 4 for equals 3 to 4 for VVVVdddddddd=3V=3V=3V=3V----5V and 5V and 5V and 5V and VVVVtttt,n,n,n,n=.5V=.5V=.5V=.5V----1V1V1V1V
equals 3.6 for C05Mequals 3.6 for C05Mequals 3.6 for C05Mequals 3.6 for C05M
Having found a general form for approximate rise and fall Having found a general form for approximate rise and fall Having found a general form for approximate rise and fall Having found a general form for approximate rise and fall times, one might estimate all delays using the same general times, one might estimate all delays using the same general times, one might estimate all delays using the same general times, one might estimate all delays using the same general form:form:form:form:
Where Where Where Where AAAAdelaydelaydelaydelay is a constant that depends on the power supply is a constant that depends on the power supply is a constant that depends on the power supply is a constant that depends on the power supply and transition voltages, the process and the minimum and transition voltages, the process and the minimum and transition voltages, the process and the minimum and transition voltages, the process and the minimum mosfetmosfetmosfetmosfet dimensions. This last dependency might strike one dimensions. This last dependency might strike one dimensions. This last dependency might strike one dimensions. This last dependency might strike one as odd, but usually all as odd, but usually all as odd, but usually all as odd, but usually all mosfetsmosfetsmosfetsmosfets are built using the minimum are built using the minimum are built using the minimum are built using the minimum allowable allowable allowable allowable mosfetmosfetmosfetmosfet length for the process.length for the process.length for the process.length for the process.Rather than solve the equations analytically, one can use Rather than solve the equations analytically, one can use Rather than solve the equations analytically, one can use Rather than solve the equations analytically, one can use Spice to determine the value of various useful constants: Spice to determine the value of various useful constants: Spice to determine the value of various useful constants: Spice to determine the value of various useful constants: AAAArrrr, , , , AAAAffff, , , , AAAAdrdrdrdr, , , , AAAAdfdfdfdf. These can be used in quick&dirty . These can be used in quick&dirty . These can be used in quick&dirty . These can be used in quick&dirty calculations for sizing transistors during the design calculations for sizing transistors during the design calculations for sizing transistors during the design calculations for sizing transistors during the design process.process.process.process.
In most CMOS circuits, the delay of a single gate is In most CMOS circuits, the delay of a single gate is In most CMOS circuits, the delay of a single gate is In most CMOS circuits, the delay of a single gate is dominated by the output raise and fall time. Thus:dominated by the output raise and fall time. Thus:dominated by the output raise and fall time. Thus:dominated by the output raise and fall time. Thus:
How do input rise and fall times affect delay?How do input rise and fall times affect delay?How do input rise and fall times affect delay?How do input rise and fall times affect delay?fast inputs will quickly turn off one fast inputs will quickly turn off one fast inputs will quickly turn off one fast inputs will quickly turn off one mosfetmosfetmosfetmosfet and provide and provide and provide and provide maximum maximum maximum maximum VVVVgsgsgsgs to the driving to the driving to the driving to the driving mosfetmosfetmosfetmosfet for most of the output for most of the output for most of the output for most of the output transitiontransitiontransitiontransitionslow inputs will leave both slow inputs will leave both slow inputs will leave both slow inputs will leave both mosfetsmosfetsmosfetsmosfets on longer, reducing on longer, reducing on longer, reducing on longer, reducing effective current to/from load capacitance and effective current to/from load capacitance and effective current to/from load capacitance and effective current to/from load capacitance and VVVVgsgsgsgs will be will be will be will be lower than above.lower than above.lower than above.lower than above.
So we might expect slower input transitions to lead to So we might expect slower input transitions to lead to So we might expect slower input transitions to lead to So we might expect slower input transitions to lead to longer output delay times.longer output delay times.longer output delay times.longer output delay times.One rule of thumb (One rule of thumb (One rule of thumb (One rule of thumb (WesteWesteWesteWeste, p. 216ff), p. 216ff), p. 216ff), p. 216ff)
valid for input transitions that aren’t “too” longvalid for input transitions that aren’t “too” longvalid for input transitions that aren’t “too” longvalid for input transitions that aren’t “too” long
When the input starts to rise, the output, which was When the input starts to rise, the output, which was When the input starts to rise, the output, which was When the input starts to rise, the output, which was high, starts to fall. Thus the voltage across Chigh, starts to fall. Thus the voltage across Chigh, starts to fall. Thus the voltage across Chigh, starts to fall. Thus the voltage across CGDGDGDGDchanges requiring the input to supply more current to changes requiring the input to supply more current to changes requiring the input to supply more current to changes requiring the input to supply more current to charge Ccharge Ccharge Ccharge CGDGDGDGD, slowing the input transition., slowing the input transition., slowing the input transition., slowing the input transition.Since CSince CSince CSince CGDGDGDGD is small, this is usually a small effect.is small, this is usually a small effect.is small, this is usually a small effect.is small, this is usually a small effect.When inverter is biased into its linear region, CWhen inverter is biased into its linear region, CWhen inverter is biased into its linear region, CWhen inverter is biased into its linear region, CGDGDGDGD may may may may appear multiplied by the gain of the inverter (appear multiplied by the gain of the inverter (appear multiplied by the gain of the inverter (appear multiplied by the gain of the inverter (Miller Miller Miller Miller effecteffecteffecteffect). This doesn’t usually matter in digital circuits ). This doesn’t usually matter in digital circuits ). This doesn’t usually matter in digital circuits ). This doesn’t usually matter in digital circuits since the input passes rapidly through linear region. since the input passes rapidly through linear region. since the input passes rapidly through linear region. since the input passes rapidly through linear region. Useful in Useful in Useful in Useful in analoganaloganaloganalog circuits...circuits...circuits...circuits...
How should we model delays when we have multiple How should we model delays when we have multiple How should we model delays when we have multiple How should we model delays when we have multiple inputs? When A, B, C and D are logic 1:inputs? When A, B, C and D are logic 1:inputs? When A, B, C and D are logic 1:inputs? When A, B, C and D are logic 1:
treat series treat series treat series treat series mosfetsmosfetsmosfetsmosfets as resistances in series. Lump intermediate as resistances in series. Lump intermediate as resistances in series. Lump intermediate as resistances in series. Lump intermediate node capacitance with load capacitance.node capacitance with load capacitance.node capacitance with load capacitance.node capacitance with load capacitance.
use Penfielduse Penfielduse Penfielduse Penfield----RubensteinRubensteinRubensteinRubenstein model which predictsmodel which predictsmodel which predictsmodel which predicts
where where where where RRRRiiii is the summed resistance from point i to ground and is the summed resistance from point i to ground and is the summed resistance from point i to ground and is the summed resistance from point i to ground and CCCCiiiiis the capacitance at point i.is the capacitance at point i.is the capacitance at point i.is the capacitance at point i.PenfieldPenfieldPenfieldPenfield----RubensteinRubensteinRubensteinRubenstein Slope Model uses effective Slope Model uses effective Slope Model uses effective Slope Model uses effective resistance simulated by Spice:resistance simulated by Spice:resistance simulated by Spice:resistance simulated by Spice:
If A goes from 0 to 1 while B, C and D are 1,If A goes from 0 to 1 while B, C and D are 1,If A goes from 0 to 1 while B, C and D are 1,If A goes from 0 to 1 while B, C and D are 1,then all the intermediate nodes in the then all the intermediate nodes in the then all the intermediate nodes in the then all the intermediate nodes in the pulldownpulldownpulldownpulldown chain have chain have chain have chain have already been discharged and the top already been discharged and the top already been discharged and the top already been discharged and the top mosfetmosfetmosfetmosfet sees only a sees only a sees only a sees only a small body effect.small body effect.small body effect.small body effect.If D goes from 0 to 1 while A, B and C are 1,If D goes from 0 to 1 while A, B and C are 1,If D goes from 0 to 1 while A, B and C are 1,If D goes from 0 to 1 while A, B and C are 1,then the intermediate nodes are all one then the intermediate nodes are all one then the intermediate nodes are all one then the intermediate nodes are all one VVVVtttt below below below below VVVVdddddddd and and and and the upper the upper the upper the upper mosfetsmosfetsmosfetsmosfets see a larger body effect.see a larger body effect.see a larger body effect.see a larger body effect.
Thus A is the “faster” input!Thus A is the “faster” input!Thus A is the “faster” input!Thus A is the “faster” input!
AAAA
BBBB
CCCC
DDDD
MicroLab, VLSI-4 (12/29)
JMM v1.3
Driving large loads #1Driving large loads #1Driving large loads #1Driving large loads #1If large loads have to be driven, the delay may increase If large loads have to be driven, the delay may increase If large loads have to be driven, the delay may increase If large loads have to be driven, the delay may increase drastically. Large loads are output capacitances, clock trees, drastically. Large loads are output capacitances, clock trees, drastically. Large loads are output capacitances, clock trees, drastically. Large loads are output capacitances, clock trees, etc.etc.etc.etc.
CCCCLLLL=1000 C=1000 C=1000 C=1000 CGGGG
CCCCGGGG
CCCCGGGG
1111invinvinvinv
GGGG
LLLLinvinvinvinvdddd tttt1000100010001000
CCCCCCCC
tttttttt ⋅⋅⋅⋅========
A possibility to reduce the delay, but probably not the A possibility to reduce the delay, but probably not the A possibility to reduce the delay, but probably not the A possibility to reduce the delay, but probably not the optimum:optimum:optimum:optimum:
Driving large loads #2Driving large loads #2Driving large loads #2Driving large loads #2To drive a large load capacitance one mightTo drive a large load capacitance one mightTo drive a large load capacitance one mightTo drive a large load capacitance one mightemploy a sequence of n inverters, each a factor “a” larger employ a sequence of n inverters, each a factor “a” larger employ a sequence of n inverters, each a factor “a” larger employ a sequence of n inverters, each a factor “a” larger than the previous one:than the previous one:than the previous one:than the previous one:
The delay through each stage is The delay through each stage is The delay through each stage is The delay through each stage is atatatatdddd where where where where ttttdddd is the average is the average is the average is the average delay of a minimumdelay of a minimumdelay of a minimumdelay of a minimum----sized inverter driving another minimumsized inverter driving another minimumsized inverter driving another minimumsized inverter driving another minimum----sized inverter. We want sized inverter. We want sized inverter. We want sized inverter. We want aaaannnn = (C= (C= (C= (CLLLL/C/C/C/CGGGG)))), so, so, so, so
Thus, total delay is minimized when a = e = 2.7 Thus, total delay is minimized when a = e = 2.7 Thus, total delay is minimized when a = e = 2.7 Thus, total delay is minimized when a = e = 2.7
in practice in practice in practice in practice a=3...5 a=3...5 a=3...5 a=3...5
MicroLab, VLSI-4 (14/29)
JMM v1.3
Power dissipation #1Power dissipation #1Power dissipation #1Power dissipation #1
the power consumption is low compared to other the power consumption is low compared to other the power consumption is low compared to other the power consumption is low compared to other technologiestechnologiestechnologiestechnologiesscaling down increases the power dissipation scaling down increases the power dissipation scaling down increases the power dissipation scaling down increases the power dissipation density with respect to chip areadensity with respect to chip areadensity with respect to chip areadensity with respect to chip areapower dissipation produces heat on the chip, which power dissipation produces heat on the chip, which power dissipation produces heat on the chip, which power dissipation produces heat on the chip, which has to be carried off through the chip sockethas to be carried off through the chip sockethas to be carried off through the chip sockethas to be carried off through the chip socketpower dissipation is one of the limiting factors in power dissipation is one of the limiting factors in power dissipation is one of the limiting factors in power dissipation is one of the limiting factors in todaystodaystodaystodays CMOS VLSI chipsCMOS VLSI chipsCMOS VLSI chipsCMOS VLSI chipslow power applications is a speciality of EM low power applications is a speciality of EM low power applications is a speciality of EM low power applications is a speciality of EM ((((NeuenburgNeuenburgNeuenburgNeuenburg, watches, battery applications, etc), watches, battery applications, etc), watches, battery applications, etc), watches, battery applications, etc)
MicroLab, VLSI-4 (15/29)
JMM v1.3
Power dissipation #2Power dissipation #2Power dissipation #2Power dissipation #2
sources of power dissipation:sources of power dissipation:sources of power dissipation:sources of power dissipation:static power dissipation (quiescent current)static power dissipation (quiescent current)static power dissipation (quiescent current)static power dissipation (quiescent current)dynamic power dissipationdynamic power dissipationdynamic power dissipationdynamic power dissipation
dc power dc power dc power dc power dissipadissipadissipadissipattttion: short circuit current (power to ion: short circuit current (power to ion: short circuit current (power to ion: short circuit current (power to ground) due to switchingground) due to switchingground) due to switchingground) due to switchingac power dissipation: capacitor current (charging, reac power dissipation: capacitor current (charging, reac power dissipation: capacitor current (charging, reac power dissipation: capacitor current (charging, re----charging) due to switchingcharging) due to switchingcharging) due to switchingcharging) due to switching
static power dissipationstatic power dissipationstatic power dissipationstatic power dissipationthere is always one there is always one there is always one there is always one fetfetfetfet off, so only leakage current is off, so only leakage current is off, so only leakage current is off, so only leakage current is presentpresentpresentpresent
(((( ))))
∑∑∑∑ ⋅⋅⋅⋅====
−−−−====
DDDDDDDD0000SSSS
kTkTkTkT////qVqVqVqVSSSS0000
VVVVIIIIPPPP
1111eeeeIIIIIIII
MicroLab, VLSI-4 (16/29)
JMM v1.3
Dynamic power dissipation #1Dynamic power dissipation #1Dynamic power dissipation #1Dynamic power dissipation #1
Comparison of dynamic short circuit current vs. Comparison of dynamic short circuit current vs. Comparison of dynamic short circuit current vs. Comparison of dynamic short circuit current vs. capacitive current.capacitive current.capacitive current.capacitive current.As expected, the short circuit current have a less As expected, the short circuit current have a less As expected, the short circuit current have a less As expected, the short circuit current have a less important contribution when the load gets large. important contribution when the load gets large. important contribution when the load gets large. important contribution when the load gets large. Slower input transition would increase short circuit Slower input transition would increase short circuit Slower input transition would increase short circuit Slower input transition would increase short circuit current.current.current.current.
W/L=4W/L=4W/L=4W/L=4
W/L=2W/L=2W/L=2W/L=2
UUUUinininin UUUUoutoutoutout----AAAA
W/L=4W/L=4W/L=4W/L=4
W/L=2W/L=2W/L=2W/L=2 50fF50fF50fF50fF
UUUUinininin UUUUoutoutoutout----BBBB
W/L=4W/L=4W/L=4W/L=4
W/L=2W/L=2W/L=2W/L=2 200fF200fF200fF200fF
UUUUinininin UUUUoutoutoutout----CCCC
IIIIdsndsndsndsn
IIIIdspdspdspdsp
IIIIdsndsndsndsn
IIIIdspdspdspdsp
IIIIdsndsndsndsn
IIIIdspdspdspdsp
UUUUinininin UUUUoutoutoutout
MicroLab, VLSI-4 (17/29)
JMM v1.3
Dynamic power dissipation #2Dynamic power dissipation #2Dynamic power dissipation #2Dynamic power dissipation #2Average dynamic power for switching a squareAverage dynamic power for switching a squareAverage dynamic power for switching a squareAverage dynamic power for switching a square----wave input wave input wave input wave input with a repetition frequency of with a repetition frequency of with a repetition frequency of with a repetition frequency of ffffpppp = 1/= 1/= 1/= 1/ttttpppp is (capacitor is (capacitor is (capacitor is (capacitor current)current)current)current)
Assuming a step input and taking iAssuming a step input and taking iAssuming a step input and taking iAssuming a step input and taking innnn(t) = (t) = (t) = (t) = CCCCLLLLdVdVdVdVoutoutoutout////dtdtdtdt, , , , i.e.i.e.i.e.i.e., the capacitive current, we get:, the capacitive current, we get:, the capacitive current, we get:, the capacitive current, we get:
proportional to switchingproportional to switchingproportional to switchingproportional to switchingfrequency but independentfrequency but independentfrequency but independentfrequency but independentof device parametersof device parametersof device parametersof device parameters
Aha! Now one can see why everybody Aha! Now one can see why everybody Aha! Now one can see why everybody Aha! Now one can see why everybody changes from 5V to 3.3V and to 2.5V!changes from 5V to 3.3V and to 2.5V!changes from 5V to 3.3V and to 2.5V!changes from 5V to 3.3V and to 2.5V!
Dynamic power dissipation #3Dynamic power dissipation #3Dynamic power dissipation #3Dynamic power dissipation #3
Short circuit power dissipation is given byShort circuit power dissipation is given byShort circuit power dissipation is given byShort circuit power dissipation is given by
The above waveform shows the short circuit currentThe above waveform shows the short circuit currentThe above waveform shows the short circuit currentThe above waveform shows the short circuit current
tttt1111 tttt3333tttt2222
IIIImeanmeanmeanmean
IIIImaxmaxmaxmax
(((( ))))3333ttttDDDDDDDD
pppp
rfrfrfrfscscscsc VVVV2222VVVV
tttttttt
12121212PPPP −−−−⋅⋅⋅⋅ββββ====
MicroLab, VLSI-4 (19/29)
JMM v1.3
Total power Total power Total power Total power dissipationdissipationdissipationdissipation
Total power dissipation is:Total power dissipation is:Total power dissipation is:Total power dissipation is:
dynamic power dissipation is dominantdynamic power dissipation is dominantdynamic power dissipation is dominantdynamic power dissipation is dominantuse switching activity to estimate power use switching activity to estimate power use switching activity to estimate power use switching activity to estimate power dissipation:dissipation:dissipation:dissipation:
switching activity:switching activity:switching activity:switching activity:nnnnswitchingswitchingswitchingswitching = percentage of switching gates= percentage of switching gates= percentage of switching gates= percentage of switching gatesthere exist simulators estimating power dissipation there exist simulators estimating power dissipation there exist simulators estimating power dissipation there exist simulators estimating power dissipation using the switching activityusing the switching activityusing the switching activityusing the switching activity
Build your own power meterBuild your own power meterBuild your own power meterBuild your own power meter
If one choosesIf one choosesIf one choosesIf one chooses
andandandandRRRRyyyyCCCCyyyy >> T>> T>> T>> T
Then Then Then Then VVVVyyyy(T) in volts will equal the average dynamic (T) in volts will equal the average dynamic (T) in volts will equal the average dynamic (T) in volts will equal the average dynamic power in watts drawn from the power supply over power in watts drawn from the power supply over power in watts drawn from the power supply over power in watts drawn from the power supply over one period.one period.one period.one period.
linear currentlinear currentlinear currentlinear current----controlledcontrolledcontrolledcontrolledcurrent sourcecurrent sourcecurrent sourcecurrent source
ggggVVVV CCCC
TTTTdddddddd yyyy====
MicroLab, VLSI-4 (21/29)
JMM v1.3
Power and ground bouncePower and ground bouncePower and ground bouncePower and ground bounce
Metal powerMetal powerMetal powerMetal power----carrying conductors have to be sized carrying conductors have to be sized carrying conductors have to be sized carrying conductors have to be sized for three reasons:for three reasons:for three reasons:for three reasons:
general rule:general rule:general rule:general rule:limit current density limit current density limit current density limit current density contact replicationcontact replicationcontact replicationcontact replication
“It’s the wires, stupid”“It’s the wires, stupid”“It’s the wires, stupid”“It’s the wires, stupid”As process dimensions shrink, As process dimensions shrink, As process dimensions shrink, As process dimensions shrink, wiring capacitanceswiring capacitanceswiring capacitanceswiring capacitancesstart to dominate the start to dominate the start to dominate the start to dominate the mosfetmosfetmosfetmosfet capacitances.capacitances.capacitances.capacitances.To estimate wiring capacitances, consider the To estimate wiring capacitances, consider the To estimate wiring capacitances, consider the To estimate wiring capacitances, consider the following figure:following figure:following figure:following figure:
ParallelParallelParallelParallel----plate capacitance given in processplate capacitance given in processplate capacitance given in processplate capacitance given in processfiles. Fringing capacitance is significantfiles. Fringing capacitance is significantfiles. Fringing capacitance is significantfiles. Fringing capacitance is significantwhen t is comparable to h.when t is comparable to h.when t is comparable to h.when t is comparable to h.
CppCppCppCpp
MicroLab, VLSI-4 (23/29)
JMM v1.3
Fringing CapacitanceFringing CapacitanceFringing CapacitanceFringing CapacitanceFigure 6.11 from Figure 6.11 from Figure 6.11 from Figure 6.11 from CMOS Digital Integrated Circuits: CMOS Digital Integrated Circuits: CMOS Digital Integrated Circuits: CMOS Digital Integrated Circuits: Analysis and DesignAnalysis and DesignAnalysis and DesignAnalysis and Design, by Kang and , by Kang and , by Kang and , by Kang and LeblebiciLeblebiciLeblebiciLeblebici::::
For a long conductor where (t/h)=0.4,For a long conductor where (t/h)=0.4,For a long conductor where (t/h)=0.4,For a long conductor where (t/h)=0.4,(w/h)=0.25, (w/l)=0, the total capacitance(w/h)=0.25, (w/l)=0, the total capacitance(w/h)=0.25, (w/l)=0, the total capacitance(w/h)=0.25, (w/l)=0, the total capacitancemay be 10x the parallel plate capacitance.may be 10x the parallel plate capacitance.may be 10x the parallel plate capacitance.may be 10x the parallel plate capacitance.
MicroLab, VLSI-4 (24/29)
JMM v1.3
Wire model?Wire model?Wire model?Wire model?
Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm which has “time of flight” of ~130ps assuming which has “time of flight” of ~130ps assuming which has “time of flight” of ~130ps assuming which has “time of flight” of ~130ps assuming εεεεSiOSiOSiOSiO2222= 3.9 = 3.9 = 3.9 = 3.9 εεεε0000
If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of flight we can model wires as a distributed RC network. flight we can model wires as a distributed RC network. flight we can model wires as a distributed RC network. flight we can model wires as a distributed RC network. Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire to be modelled as a to be modelled as a to be modelled as a to be modelled as a transmission linetransmission linetransmission linetransmission line....For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where signal propagation can be shown to obey the signal propagation can be shown to obey the signal propagation can be shown to obey the signal propagation can be shown to obey the diffusion diffusion diffusion diffusion equationequationequationequation::::
C/unit lengthC/unit lengthC/unit lengthC/unit length distance from driverdistance from driverdistance from driverdistance from driver
Which means the prop time Which means the prop time Which means the prop time Which means the prop time ttttxxxx = kx= kx= kx= kx2 2 2 2 with thewith thewith thewith thesignal “edge” becoming dispersed withsignal “edge” becoming dispersed withsignal “edge” becoming dispersed withsignal “edge” becoming dispersed withincreasing x.increasing x.increasing x.increasing x.
rrrr ccccdVdVdVdVdtdtdtdt
dddd VVVVdxdxdxdx
====2222
2222
MicroLab, VLSI-4 (25/29)
JMM v1.3
Diffusion Diffusion Diffusion Diffusion EqEqEqEq. in “real life”. in “real life”. in “real life”. in “real life”WesteWesteWesteWeste, , , , EqEqEqEq. 4.28, . 4.28, . 4.28, . 4.28, but 10% to 90% rise/fall timebut 10% to 90% rise/fall timebut 10% to 90% rise/fall timebut 10% to 90% rise/fall time
Ex vlsi4.3:Ex vlsi4.3:Ex vlsi4.3:Ex vlsi4.3: clock with 50pf load distributedclock with 50pf load distributedclock with 50pf load distributedclock with 50pf load distributedby 1by 1by 1by 1µµµµ----wide metal wire running from clockwide metal wire running from clockwide metal wire running from clockwide metal wire running from clockbuffer in corner of 10mm x 10mm chip.buffer in corner of 10mm x 10mm chip.buffer in corner of 10mm x 10mm chip.buffer in corner of 10mm x 10mm chip.
Fix: drive clock from central location toFix: drive clock from central location toFix: drive clock from central location toFix: drive clock from central location todecrease l and widen clock wire to 20decrease l and widen clock wire to 20decrease l and widen clock wire to 20decrease l and widen clock wire to 20µµµµ::::
a) t = ?a) t = ?a) t = ?a) t = ? b) t = ?b) t = ?b) t = ?b) t = ?
bufferbufferbufferbuffer
MicroLab, VLSI-4 (26/29)
JMM v1.3
InductanceInductanceInductanceInductanceBondBondBondBond----wire inductance can cause deleterious effects wire inductance can cause deleterious effects wire inductance can cause deleterious effects wire inductance can cause deleterious effects in large, high speed I/O buffersin large, high speed I/O buffersin large, high speed I/O buffersin large, high speed I/O buffers
with process shrinking onwith process shrinking onwith process shrinking onwith process shrinking on----chip inductance has to be chip inductance has to be chip inductance has to be chip inductance has to be taken into accounttaken into accounttaken into accounttaken into account
design techniques:design techniques:design techniques:design techniques:separate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip coremultiple power and ground pinsmultiple power and ground pinsmultiple power and ground pinsmultiple power and ground pinscareful selection of the position of the power and careful selection of the position of the power and careful selection of the position of the power and careful selection of the position of the power and ground pins on the packageground pins on the packageground pins on the packageground pins on the packageadding decoupling capacitances on the boardadding decoupling capacitances on the boardadding decoupling capacitances on the boardadding decoupling capacitances on the boardincrease the rise and fall timesincrease the rise and fall timesincrease the rise and fall timesincrease the rise and fall timesuse advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc)
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WWWWesteesteesteeste: : : :
4.4 (inductance)4.4 (inductance)4.4 (inductance)4.4 (inductance)4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.5.4.4, and 4.6.3 (delay modelling)4.5.4.4, and 4.6.3 (delay modelling)4.5.4.4, and 4.6.3 (delay modelling)4.5.4.4, and 4.6.3 (delay modelling)4.7 (power consumption)4.7 (power consumption)4.7 (power consumption)4.7 (power consumption)4.8 (sizing routing conductors)4.8 (sizing routing conductors)4.8 (sizing routing conductors)4.8 (sizing routing conductors)
You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get the chance ...the chance ...the chance ...the chance ...
Ex vlsi4.1 (difficulty: easy):Ex vlsi4.1 (difficulty: easy):Ex vlsi4.1 (difficulty: easy):Ex vlsi4.1 (difficulty: easy): Calculate the inductive spike Calculate the inductive spike Calculate the inductive spike Calculate the inductive spike at the power supply provoked by 8 output buffers, each at the power supply provoked by 8 output buffers, each at the power supply provoked by 8 output buffers, each at the power supply provoked by 8 output buffers, each driving 50pF in 4ns, driving 50pF in 4ns, driving 50pF in 4ns, driving 50pF in 4ns, VVVVdddddddd=3.3V, total bonding =3.3V, total bonding =3.3V, total bonding =3.3V, total bonding inductance 15nHinductance 15nHinductance 15nHinductance 15nH
Result: Result: Result: Result: dVdVdVdVtottottottot = 1.24V (see = 1.24V (see = 1.24V (see = 1.24V (see WesteWesteWesteWeste pp 205)pp 205)pp 205)pp 205)
Ex vlsi4.2 (difficulty: easy):Ex vlsi4.2 (difficulty: easy):Ex vlsi4.2 (difficulty: easy):Ex vlsi4.2 (difficulty: easy): a) Calculate the power a) Calculate the power a) Calculate the power a) Calculate the power supply width supply width supply width supply width WWWWpowerpowerpowerpower necessary for feeding a clock buffer necessary for feeding a clock buffer necessary for feeding a clock buffer necessary for feeding a clock buffer running at 50MHz driving 100pF. b) What is the ground running at 50MHz driving 100pF. b) What is the ground running at 50MHz driving 100pF. b) What is the ground running at 50MHz driving 100pF. b) What is the ground bounce with the chosen conductor? (Jbounce with the chosen conductor? (Jbounce with the chosen conductor? (Jbounce with the chosen conductor? (JALALALAL=0.5mA/=0.5mA/=0.5mA/=0.5mA/µµµµm, m, m, m, power supply distance l = 1mm, power supply distance l = 1mm, power supply distance l = 1mm, power supply distance l = 1mm, VVVVdddddddd=3.3V, R=3.3V, R=3.3V, R=3.3V, Rmetal1metal1metal1metal1 = = = = 72m72m72m72mΩΩΩΩ/sq, /sq, /sq, /sq, ttttrrrr= = = = ttttffff=1ns)=1ns)=1ns)=1ns)
Result: a) Result: a) Result: a) Result: a) WWWWpowerpowerpowerpower=33 =33 =33 =33 µµµµm, m, m, m, b) b) b) b) dVdVdVdV = 0.72V (see = 0.72V (see = 0.72V (see = 0.72V (see WesteWesteWesteWeste pp 239)pp 239)pp 239)pp 239)
Ex vlsi4.3 (difficulty: easy):Ex vlsi4.3 (difficulty: easy):Ex vlsi4.3 (difficulty: easy):Ex vlsi4.3 (difficulty: easy): Calculate the clock Calculate the clock Calculate the clock Calculate the clock distribution delay for the example on transparency 25distribution delay for the example on transparency 25distribution delay for the example on transparency 25distribution delay for the example on transparency 25
Result: a) tResult: a) tResult: a) tResult: a) tdddd=55 ns, b) t=55 ns, b) t=55 ns, b) t=55 ns, b) tdddd=27.5 ns, =27.5 ns, =27.5 ns, =27.5 ns, b) tb) tb) tb) tdddd=1.38 ns (see =1.38 ns (see =1.38 ns (see =1.38 ns (see WesteWesteWesteWeste pp 200)pp 200)pp 200)pp 200)
Ex vlsi4.4 (difficulty: easy):Ex vlsi4.4 (difficulty: easy):Ex vlsi4.4 (difficulty: easy):Ex vlsi4.4 (difficulty: easy): Calculate Calculate Calculate Calculate AAAArrrr and and and and AAAAffff for for for for a CMOS inverter (a CMOS inverter (a CMOS inverter (a CMOS inverter (VddVddVddVdd=3.3V, =3.3V, =3.3V, =3.3V, AlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm m m m process)process)process)process)
Result: Result: Result: Result: AAAArrrr =43.9 k=43.9 k=43.9 k=43.9 kΩΩΩΩ, , , , AAAAffff =10.9 k=10.9 k=10.9 k=10.9 kΩ Ω Ω Ω (see (see (see (see WesteWesteWesteWestepp208ff and transparency 7)pp208ff and transparency 7)pp208ff and transparency 7)pp208ff and transparency 7)
WesteWesteWesteWeste pp370: 5.9 ex 14 (difficulty: easy):pp370: 5.9 ex 14 (difficulty: easy):pp370: 5.9 ex 14 (difficulty: easy):pp370: 5.9 ex 14 (difficulty: easy): A low A low A low A low power 3.3V chip has a clock of 12MHz. In the power 3.3V chip has a clock of 12MHz. In the power 3.3V chip has a clock of 12MHz. In the power 3.3V chip has a clock of 12MHz. In the power downpower downpower downpower down----mode, the clock driver drives 5mm of a mode, the clock driver drives 5mm of a mode, the clock driver drives 5mm of a mode, the clock driver drives 5mm of a 2222µµµµm wide metal1 wire. If the area capacitance of m wide metal1 wire. If the area capacitance of m wide metal1 wire. If the area capacitance of m wide metal1 wire. If the area capacitance of metal is Ca=2.37pF/metal is Ca=2.37pF/metal is Ca=2.37pF/metal is Ca=2.37pF/µµµµmmmm2222 and the sidewall and the sidewall and the sidewall and the sidewall capacitance is Cf0= 2.37pF/capacitance is Cf0= 2.37pF/capacitance is Cf0= 2.37pF/capacitance is Cf0= 2.37pF/µµµµm what is the m what is the m what is the m what is the powerpowerpowerpower----down dissipation, assuming this is the down dissipation, assuming this is the down dissipation, assuming this is the down dissipation, assuming this is the dominant term? What is the dissipation if the wire dominant term? What is the dissipation if the wire dominant term? What is the dissipation if the wire dominant term? What is the dissipation if the wire is reduced to 50is reduced to 50is reduced to 50is reduced to 50µµµµm length?m length?m length?m length?
Result: PResult: PResult: PResult: Pdddd = 85= 85= 85= 85µµµµW, 0.85W, 0.85W, 0.85W, 0.85µµµµW (see W (see W (see W (see WesteWesteWesteWeste pp 235)pp 235)pp 235)pp 235)
OverviewOverviewOverviewOverviewEuler Euler Euler Euler rules for complex CMOS gatesrules for complex CMOS gatesrules for complex CMOS gatesrules for complex CMOS gatesLayout and stick diagram Layout and stick diagram Layout and stick diagram Layout and stick diagram
Goal: Goal: Goal: Goal: You know how to design compact layout of You know how to design compact layout of You know how to design compact layout of You know how to design compact layout of complex CMOS logic gates with the complex CMOS logic gates with the complex CMOS logic gates with the complex CMOS logic gates with the Euler Euler Euler Euler rules. rules. rules. rules. You are familiar with transmission gates and its You are familiar with transmission gates and its You are familiar with transmission gates and its You are familiar with transmission gates and its limitations.limitations.limitations.limitations.
MicroLab, VLSI-5 (2/34)
JMM v1.4
How ‘bout more than 1 input?How ‘bout more than 1 input?How ‘bout more than 1 input?How ‘bout more than 1 input?
Finally! I wasFinally! I wasFinally! I wasFinally! I wasgetting tiredgetting tiredgetting tiredgetting tiredof inverters...of inverters...of inverters...of inverters...
VVVVdddddddd
AAAA1111F(AF(AF(AF(A1111,…,A,…,A,…,A,…,Annnn))))
pulluppulluppulluppullup: make this connection: make this connection: make this connection: make this connectionwhen we want F(Awhen we want F(Awhen we want F(Awhen we want F(A1111,…,A,…,A,…,A,…,Annnn) = 1) = 1) = 1) = 1
pulldownpulldownpulldownpulldown: make this connection: make this connection: make this connection: make this connectionwhen we want F(Awhen we want F(Awhen we want F(Awhen we want F(A1111,…,A,…,A,…,A,…,Annnn) = 0) = 0) = 0) = 0
we want Vwe want Vwe want Vwe want VOHOHOHOH = = = = VVVVdddddddd, better use only, better use only, better use only, better use onlypfetspfetspfetspfets in the in the in the in the pulluppulluppulluppullup pathpathpathpathsimilarly, since we want Vsimilarly, since we want Vsimilarly, since we want Vsimilarly, since we want VOLOLOLOL = 0, better= 0, better= 0, better= 0, betteruse only use only use only use only nfetsnfetsnfetsnfets in the in the in the in the pulldownpulldownpulldownpulldown pathpathpathpathlooking at looking at looking at looking at pulldownpulldownpulldownpulldown path: since path: since path: since path: since nfetsnfetsnfetsnfets areareareareon when Von when Von when Von when VGSGSGSGS > V> V> V> VTHTHTHTH, output will be pulled, output will be pulled, output will be pulled, output will be pulledlow when right combination of inputs arelow when right combination of inputs arelow when right combination of inputs arelow when right combination of inputs arehigh…high…high…high…
CMOS gates are naturally invertingCMOS gates are naturally invertingCMOS gates are naturally invertingCMOS gates are naturally inverting
We want We want We want We want complementarycomplementarycomplementarycomplementary pulluppulluppulluppullup and and and and pulldownpulldownpulldownpulldownlogic, i.e., the logic, i.e., the logic, i.e., the logic, i.e., the pulldownpulldownpulldownpulldown should be “on” whenshould be “on” whenshould be “on” whenshould be “on” whenthe the the the pulluppulluppulluppullup is “off” and vice versa.is “off” and vice versa.is “off” and vice versa.is “off” and vice versa.
Since there’s plenty of capacitance on the outputSince there’s plenty of capacitance on the outputSince there’s plenty of capacitance on the outputSince there’s plenty of capacitance on the outputnode, when the output becomes disconnected itnode, when the output becomes disconnected itnode, when the output becomes disconnected itnode, when the output becomes disconnected it“remembers” its previous voltage “remembers” its previous voltage “remembers” its previous voltage “remembers” its previous voltage -------- at least for a at least for a at least for a at least for a while. The “memory” is the load capacitor’s charge.while. The “memory” is the load capacitor’s charge.while. The “memory” is the load capacitor’s charge.while. The “memory” is the load capacitor’s charge.Leakage currents will cause eventual decay of theLeakage currents will cause eventual decay of theLeakage currents will cause eventual decay of theLeakage currents will cause eventual decay of thecharge (that’s why charge (that’s why charge (that’s why charge (that’s why DRAMsDRAMsDRAMsDRAMs need to be refreshed!).need to be refreshed!).need to be refreshed!).need to be refreshed!).
“No connection” is also useful for constructing“No connection” is also useful for constructing“No connection” is also useful for constructing“No connection” is also useful for constructingtristatetristatetristatetristate drivers! In this case, we call this statedrivers! In this case, we call this statedrivers! In this case, we call this statedrivers! In this case, we call this state“Z” which is short for “high“Z” which is short for “high“Z” which is short for “high“Z” which is short for “high----Z” which is short forZ” which is short forZ” which is short forZ” which is short for“high impedance” which is how engineers say“high impedance” which is how engineers say“high impedance” which is how engineers say“high impedance” which is how engineers say“no connection”. Isn’t jargon wonderful?“no connection”. Isn’t jargon wonderful?“no connection”. Isn’t jargon wonderful?“no connection”. Isn’t jargon wonderful?
Now you know what the “C”Now you know what the “C”Now you know what the “C”Now you know what the “C”in CMOS stands for!in CMOS stands for!in CMOS stands for!in CMOS stands for!
MicroLab, VLSI-5 (4/34)
JMM v1.4
CMOS complementsCMOS complementsCMOS complementsCMOS complementsWhat a niceWhat a niceWhat a niceWhat a niceVVVVOHOHOHOH you have...you have...you have...you have...
Thanks. It runsThanks. It runsThanks. It runsThanks. It runsin the family...in the family...in the family...in the family...
conducts when Vconducts when Vconducts when Vconducts when VGSGSGSGS is highis highis highis high conducts when Vconducts when Vconducts when Vconducts when VGSGSGSGS is lowis lowis lowis low
conducts when A is highconducts when A is highconducts when A is highconducts when A is highandandandand B is high: AB is high: AB is high: AB is high: A....BBBB
AAAA
BBBBAAAA BBBB
conducts when A is lowconducts when A is lowconducts when A is lowconducts when A is loworororor B is low: A+B = AB is low: A+B = AB is low: A+B = AB is low: A+B = A....BBBB
conducts when A is highconducts when A is highconducts when A is highconducts when A is highorororor B is high: A+BB is high: A+BB is high: A+BB is high: A+B
AAAA
BBBBAAAA BBBB
conducts when A is lowconducts when A is lowconducts when A is lowconducts when A is lowandandandand B is low: AB is low: AB is low: AB is low: A....B = A+BB = A+BB = A+BB = A+B
Development of CMOS gates /1Development of CMOS gates /1Development of CMOS gates /1Development of CMOS gates /1
Example: CMOS NAND gate F = A*BExample: CMOS NAND gate F = A*BExample: CMOS NAND gate F = A*BExample: CMOS NAND gate F = A*B
Step 1: development of Step 1: development of Step 1: development of Step 1: development of nfetnfetnfetnfetblock. Logic miniblock. Logic miniblock. Logic miniblock. Logic mini----mizationmizationmizationmization of “0” in of “0” in of “0” in of “0” in KarnaughKarnaughKarnaughKarnaugh diagramdiagramdiagramdiagram
1111
1111
1111
0000
AAAABBBB 1111
1111
0000
0000
F = A * BF = A * BF = A * BF = A * B
AAAA
BBBB
MicroLab, VLSI-5 (6/34)
JMM v1.4
Development of CMOS gates /2Development of CMOS gates /2Development of CMOS gates /2Development of CMOS gates /2
Step 2: development of Step 2: development of Step 2: development of Step 2: development of pfetpfetpfetpfetblock. Logic miniblock. Logic miniblock. Logic miniblock. Logic mini----mizationmizationmizationmization of “1” in of “1” in of “1” in of “1” in KarnaughKarnaughKarnaughKarnaugh diagramdiagramdiagramdiagram
1111
1111
1111
0000
AAAABBBB 1111
1111
0000
0000
F = A + BF = A + BF = A + BF = A + B
AAAA BBBB
MicroLab, VLSI-5 (7/34)
JMM v1.4
Development of CMOS gates /2Development of CMOS gates /2Development of CMOS gates /2Development of CMOS gates /2
Step 3: put Step 3: put Step 3: put Step 3: put nfetnfetnfetnfet and and and and pfetpfetpfetpfetblock togetherblock togetherblock togetherblock together 1111
1111
1111
0000
AAAABBBB 1111
1111
0000
0000
F = A * BF = A * BF = A * BF = A * B
BBBB
AAAA
FFFF
MicroLab, VLSI-5 (8/34)
JMM v1.4
NAND & NORNAND & NORNAND & NORNAND & NOR2222----input NAND. When output is low,input NAND. When output is low,input NAND. When output is low,input NAND. When output is low,two two two two nfetsnfetsnfetsnfets are in series. So to keepare in series. So to keepare in series. So to keepare in series. So to keepoutput fall time equivalent to thatoutput fall time equivalent to thatoutput fall time equivalent to thatoutput fall time equivalent to thatof an inverter, the of an inverter, the of an inverter, the of an inverter, the nfetsnfetsnfetsnfets have to behave to behave to behave to betwice as wide. twice as wide. twice as wide. twice as wide. PfetPfetPfetPfet widths can bewidths can bewidths can bewidths can besame as those in the inverter (butsame as those in the inverter (butsame as those in the inverter (butsame as those in the inverter (butremember there were already 2x remember there were already 2x remember there were already 2x remember there were already 2x nfetnfetnfetnfetwidths!). Can be extended to largewidths!). Can be extended to largewidths!). Can be extended to largewidths!). Can be extended to largefanfanfanfan----in but practical limit is 4 inputs.in but practical limit is 4 inputs.in but practical limit is 4 inputs.in but practical limit is 4 inputs.Why?Why?Why?Why?
AAAA
BBBB
2222----input NOR. When output is high,input NOR. When output is high,input NOR. When output is high,input NOR. When output is high,two two two two pfetspfetspfetspfets are in series. So to keepare in series. So to keepare in series. So to keepare in series. So to keepoutput rise time equivalent to thatoutput rise time equivalent to thatoutput rise time equivalent to thatoutput rise time equivalent to thatof an inverter, the of an inverter, the of an inverter, the of an inverter, the pfetspfetspfetspfets have to behave to behave to behave to betwice as wide. twice as wide. twice as wide. twice as wide. NfetNfetNfetNfet widths can bewidths can bewidths can bewidths can besame as those in the inverter. Cansame as those in the inverter. Cansame as those in the inverter. Cansame as those in the inverter. Canbe extended to large fanbe extended to large fanbe extended to large fanbe extended to large fan----in butin butin butin butpractical limit is 4 inputs. NOR gatespractical limit is 4 inputs. NOR gatespractical limit is 4 inputs. NOR gatespractical limit is 4 inputs. NOR gatesare considered less good than NANDare considered less good than NANDare considered less good than NANDare considered less good than NANDgates. Why?gates. Why?gates. Why?gates. Why?
AAAA
BBBB
AAAA1111 … A… A… A… Annnn
PseudoPseudoPseudoPseudo----NMOS NOR gates areNMOS NOR gates areNMOS NOR gates areNMOS NOR gates areused to build high fanused to build high fanused to build high fanused to build high fan----in NORin NORin NORin NORgates for gates for gates for gates for PLA’sPLA’sPLA’sPLA’s to save areato save areato save areato save area(at some cost in static power).(at some cost in static power).(at some cost in static power).(at some cost in static power).
MicroLab, VLSI-5 (9/34)
JMM v1.4
Layout of simple gatesLayout of simple gatesLayout of simple gatesLayout of simple gates
layout rules are the common language between layout rules are the common language between layout rules are the common language between layout rules are the common language between design and process engineersdesign and process engineersdesign and process engineersdesign and process engineersconservative rules absorb process disturbances and conservative rules absorb process disturbances and conservative rules absorb process disturbances and conservative rules absorb process disturbances and variationsvariationsvariationsvariationslayout rules must be respected by the designerlayout rules must be respected by the designerlayout rules must be respected by the designerlayout rules must be respected by the designerlayout rules reflect the limits of a process, they layout rules reflect the limits of a process, they layout rules reflect the limits of a process, they layout rules reflect the limits of a process, they describe:describe:describe:describe:
layout readability is improved using colours:layout readability is improved using colours:layout readability is improved using colours:layout readability is improved using colours:metalmetalmetalmetal bluebluebluebluepolysiliciumpolysiliciumpolysiliciumpolysilicium redredredrednnnn----diffusiondiffusiondiffusiondiffusion greengreengreengreenpppp----diffusiondiffusiondiffusiondiffusion yellowyellowyellowyellownnnn----wellwellwellwell brownbrownbrownbrowncontact, viacontact, viacontact, viacontact, via blackblackblackblack
symbol and mask layout of a CMOS invertersymbol and mask layout of a CMOS invertersymbol and mask layout of a CMOS invertersymbol and mask layout of a CMOS inverter
stick diagrams are technology independentstick diagrams are technology independentstick diagrams are technology independentstick diagrams are technology independentno layout rules need to be knownno layout rules need to be knownno layout rules need to be knownno layout rules need to be knownmask layout may be generated automaticallymask layout may be generated automaticallymask layout may be generated automaticallymask layout may be generated automatically
MicroLab, VLSI-5 (13/34)
JMM v1.4
NAND & NOR (NAND & NOR (NAND & NOR (NAND & NOR (againagainagainagain))))
CMOS gates with large fanCMOS gates with large fanCMOS gates with large fanCMOS gates with large fan----in suffer from:in suffer from:in suffer from:in suffer from:body effectbody effectbody effectbody effectunsymmetrical delayunsymmetrical delayunsymmetrical delayunsymmetrical delaylarge delaylarge delaylarge delaylarge delay
⇒ never use more than 4 or 5 never use more than 4 or 5 never use more than 4 or 5 never use more than 4 or 5 fetsfetsfetsfets in seriesin seriesin seriesin series⇒ increment logic depthincrement logic depthincrement logic depthincrement logic depth
Step 1. Figure out Step 1. Figure out Step 1. Figure out Step 1. Figure out pulldownpulldownpulldownpulldownnetwork that does what younetwork that does what younetwork that does what younetwork that does what youwant, want, want, want, e.g.e.g.e.g.e.g., F = A*(B+C), F = A*(B+C), F = A*(B+C), F = A*(B+C)
AAAA
BBBB CCCC
Step 2. Walk the hierarchyStep 2. Walk the hierarchyStep 2. Walk the hierarchyStep 2. Walk the hierarchyreplacing replacing replacing replacing nfetsnfetsnfetsnfets with with with with pfetspfetspfetspfets,,,,series subnets with parallelseries subnets with parallelseries subnets with parallelseries subnets with parallelsubnets, and parallelsubnets, and parallelsubnets, and parallelsubnets, and parallelsubnets with series subnetssubnets with series subnetssubnets with series subnetssubnets with series subnets
AAAABBBB
CCCC
AAAABBBB
CCCC
AAAA
BBBB CCCC
Step 3. Combine Step 3. Combine Step 3. Combine Step 3. Combine pfetpfetpfetpfetpulluppulluppulluppullup network from Stepnetwork from Stepnetwork from Stepnetwork from Step2 with 2 with 2 with 2 with nfet nfet nfet nfet pulldownpulldownpulldownpulldownnetwork from Step 1 tonetwork from Step 1 tonetwork from Step 1 tonetwork from Step 1 toform fullyform fullyform fullyform fully----complementarycomplementarycomplementarycomplementaryCMOS gate.CMOS gate.CMOS gate.CMOS gate.
But isn’t itBut isn’t itBut isn’t itBut isn’t ithard to wirehard to wirehard to wirehard to wireit all up?it all up?it all up?it all up?
classical CMOS logic gates are always inverting classical CMOS logic gates are always inverting classical CMOS logic gates are always inverting classical CMOS logic gates are always inverting logic gateslogic gateslogic gateslogic gatescomplex CMOS logic gates are a mixture of AND complex CMOS logic gates are a mixture of AND complex CMOS logic gates are a mixture of AND complex CMOS logic gates are a mixture of AND and OR structures with a final inversionand OR structures with a final inversionand OR structures with a final inversionand OR structures with a final inversion
Example: F = A * B + C * DExample: F = A * B + C * DExample: F = A * B + C * DExample: F = A * B + C * D
Step 1: Step 1: Step 1: Step 1: generation of generation of generation of generation of nfet nfet nfet nfet block (logic “0”)block (logic “0”)block (logic “0”)block (logic “0”)
F = A * B + C * DF = A * B + C * DF = A * B + C * DF = A * B + C * D
Step 2: Step 2: Step 2: Step 2: generation of generation of generation of generation of pfet pfet pfet pfet block (logic “1”)block (logic “1”)block (logic “1”)block (logic “1”)
F = (A + B) * (C + D)F = (A + B) * (C + D)F = (A + B) * (C + D)F = (A + B) * (C + D)
Step 3: Step 3: Step 3: Step 3: put everything put everything put everything put everything together. What together. What together. What together. What about the layout ?about the layout ?about the layout ?about the layout ?
AAAA
BBBB
&&&&
CCCC
DDDD
&&&&
≥≥≥≥ 1
where is this signalwhere is this signalwhere is this signalwhere is this signalin the transistor schema ?in the transistor schema ?in the transistor schema ?in the transistor schema ?
Goal: compact layout. All complex gates may be Goal: compact layout. All complex gates may be Goal: compact layout. All complex gates may be Goal: compact layout. All complex gates may be designed using a single row of designed using a single row of designed using a single row of designed using a single row of nfetsnfetsnfetsnfets and a single and a single and a single and a single line of line of line of line of pfetspfetspfetspfets, thus adjacent drain/source diffusions , thus adjacent drain/source diffusions , thus adjacent drain/source diffusions , thus adjacent drain/source diffusions of of of of fetsfetsfetsfets are very close.are very close.are very close.are very close.
EulerEulerEulerEuler rule:rule:rule:rule:generate an ngenerate an ngenerate an ngenerate an n----graph by replacing the graph by replacing the graph by replacing the graph by replacing the nfetnfetnfetnfet block with block with block with block with vertices for nodes and edges for vertices for nodes and edges for vertices for nodes and edges for vertices for nodes and edges for fetsfetsfetsfetsgenerate a dual pgenerate a dual pgenerate a dual pgenerate a dual p----graphgraphgraphgraphfind a sequence find a sequence find a sequence find a sequence containingcontainingcontainingcontaining all edges in the nall edges in the nall edges in the nall edges in the n----graph. graph. graph. graph. This sequence is called This sequence is called This sequence is called This sequence is called EulerEulerEulerEuler nnnn----path.path.path.path.generate an generate an generate an generate an EulerEulerEulerEuler pppp----path with the same labelling as path with the same labelling as path with the same labelling as path with the same labelling as the the the the EulerEulerEulerEuler nnnn----path. If not possible start again.path. If not possible start again.path. If not possible start again.path. If not possible start again.the labelling sequence of the 2 the labelling sequence of the 2 the labelling sequence of the 2 the labelling sequence of the 2 EulerEulerEulerEuler paths are the paths are the paths are the paths are the gate sequence of the single row gate sequence of the single row gate sequence of the single row gate sequence of the single row nfetnfetnfetnfet////pfetpfetpfetpfet CMOS CMOS CMOS CMOS gate.gate.gate.gate.
Find the minimal transistor circuit (2 * 4 Find the minimal transistor circuit (2 * 4 Find the minimal transistor circuit (2 * 4 Find the minimal transistor circuit (2 * 4 fetsfetsfetsfets) and ) and ) and ) and the most compact layout using the most compact layout using the most compact layout using the most compact layout using EulersEulersEulersEulers rule.rule.rule.rule.
F = A * B + B * C * D F = A * B + B * C * D F = A * B + B * C * D F = A * B + B * C * D
F = B * ( A + C * D) equation ready for pF = B * ( A + C * D) equation ready for pF = B * ( A + C * D) equation ready for pF = B * ( A + C * D) equation ready for p----blockblockblockblock
VDDVDDVDDVDD
N1N1N1N1VSSVSSVSSVSS P1P1P1P1
P2P2P2P2
FFFF
CCCC
DDDDAAAA
BBBB
FFFF
startstartstartstart
startstartstartstart
D D D D ----> C > C > C > C ----> A > A > A > A ----> B> B> B> B
If VIf VIf VIf VAAAA = V= V= V= VDDDDDDDD then current will flow fromthen current will flow fromthen current will flow fromthen current will flow fromA to B until VA to B until VA to B until VA to B until VBBBB = _____= _____= _____= _____
If VIf VIf VIf VAAAA = 0 then current will flow from= 0 then current will flow from= 0 then current will flow from= 0 then current will flow fromB to A until VB to A until VB to A until VB to A until VB = _____= _____= _____= _____
Assuming S and Assuming S and Assuming S and Assuming S and ----S are complementary signals, the CMOS S are complementary signals, the CMOS S are complementary signals, the CMOS S are complementary signals, the CMOS transmission gate (TG) acts as a switch, controlled by S, transmission gate (TG) acts as a switch, controlled by S, transmission gate (TG) acts as a switch, controlled by S, transmission gate (TG) acts as a switch, controlled by S, that has no inherent voltage drop (unlike a switch that has no inherent voltage drop (unlike a switch that has no inherent voltage drop (unlike a switch that has no inherent voltage drop (unlike a switch constructed from a single constructed from a single constructed from a single constructed from a single nfetnfetnfetnfet or or or or pfetpfetpfetpfet which exhibits at which exhibits at which exhibits at which exhibits at VVVVTTTT drop at one rail or the other).drop at one rail or the other).drop at one rail or the other).drop at one rail or the other).
Y = A * S + B * SY = A * S + B * SY = A * S + B * SY = A * S + B * S
Is this nodeIs this nodeIs this nodeIs this nodealways the “output”always the “output”always the “output”always the “output”of this gate?of this gate?of this gate?of this gate?
TG Circuits: 4 to 1 MUXTG Circuits: 4 to 1 MUXTG Circuits: 4 to 1 MUXTG Circuits: 4 to 1 MUX
multiplexersmultiplexersmultiplexersmultiplexers can easily be done with TGcan easily be done with TGcan easily be done with TGcan easily be done with TGnever forget that TG are binever forget that TG are binever forget that TG are binever forget that TG are bi----directionaldirectionaldirectionaldirectionalcompact layout by combining identical gatescompact layout by combining identical gatescompact layout by combining identical gatescompact layout by combining identical gates
AAAA
BBBB
CCCC
DDDD
SSSS1111
FFFF
SSSS2222
MicroLab, VLSI-5 (29/34)
JMM v1.4
Best XOR in TownBest XOR in TownBest XOR in TownBest XOR in Town
AAAA
BBBB
A * B + A * BA * B + A * BA * B + A * BA * B + A * B
Is this nodeIs this nodeIs this nodeIs this nodealways the “output”always the “output”always the “output”always the “output”of this gate?of this gate?of this gate?of this gate?8 transistors8 transistors8 transistors8 transistors
A * B + A * BA * B + A * BA * B + A * BA * B + A * B
Is this nodeIs this nodeIs this nodeIs this nodealways the “output”always the “output”always the “output”always the “output”of this gate?of this gate?of this gate?of this gate?
Find the function of the following 4 transistor circuit:Find the function of the following 4 transistor circuit:Find the function of the following 4 transistor circuit:Find the function of the following 4 transistor circuit:
difficult to get compact layoutdifficult to get compact layoutdifficult to get compact layoutdifficult to get compact layoutoutputs behave like bioutputs behave like bioutputs behave like bioutputs behave like bi----directional signalsdirectional signalsdirectional signalsdirectional signalsmany TG in series provoke large delaysmany TG in series provoke large delaysmany TG in series provoke large delaysmany TG in series provoke large delays
Ex vlsi5.1 (difficulty: easy): Ex vlsi5.1 (difficulty: easy): Ex vlsi5.1 (difficulty: easy): Ex vlsi5.1 (difficulty: easy): Design a CMOS gate that Design a CMOS gate that Design a CMOS gate that Design a CMOS gate that implements the functionimplements the functionimplements the functionimplements the function
Ex vlsi5.2 (difficulty: easy): Ex vlsi5.2 (difficulty: easy): Ex vlsi5.2 (difficulty: easy): Ex vlsi5.2 (difficulty: easy): What is the Boolean What is the Boolean What is the Boolean What is the Boolean equation of the following CMOS gate.equation of the following CMOS gate.equation of the following CMOS gate.equation of the following CMOS gate.
WesteWesteWesteWeste pp371: 5.9ex7 (difficulty: easy): pp371: 5.9ex7 (difficulty: easy): pp371: 5.9ex7 (difficulty: easy): pp371: 5.9ex7 (difficulty: easy): Design a pass Design a pass Design a pass Design a pass transistor network that implements the sum transistor network that implements the sum transistor network that implements the sum transistor network that implements the sum function for an adderfunction for an adderfunction for an adderfunction for an adder
Goal: Goal: Goal: Goal: You are familiar with dynamic logic gates and its You are familiar with dynamic logic gates and its You are familiar with dynamic logic gates and its You are familiar with dynamic logic gates and its different families. You can handle the dynamic different families. You can handle the dynamic different families. You can handle the dynamic different families. You can handle the dynamic logic problems like charge sharing and timing.logic problems like charge sharing and timing.logic problems like charge sharing and timing.logic problems like charge sharing and timing.
MicroLab, VLSI-6 (2/28)
JMM v1.3
Tinkering with Logic GatesTinkering with Logic GatesTinkering with Logic GatesTinkering with Logic Gates
Things to like about CMOS gates:Things to like about CMOS gates:Things to like about CMOS gates:Things to like about CMOS gates:easy to translate logic to fetseasy to translate logic to fetseasy to translate logic to fetseasy to translate logic to fetsrailrailrailrail----totototo----rail switchingrail switchingrail switchingrail switching
good noise marginsgood noise marginsgood noise marginsgood noise marginsno static power since fets are in no static power since fets are in no static power since fets are in no static power since fets are in cutoffcutoffcutoffcutoff
sizing not critical to correct operationsizing not critical to correct operationsizing not critical to correct operationsizing not critical to correct operation
Things not to like about CMOS gates:Things not to like about CMOS gates:Things not to like about CMOS gates:Things not to like about CMOS gates:N inputs N inputs N inputs N inputs 2N fets (i.e., one 2N fets (i.e., one 2N fets (i.e., one 2N fets (i.e., one nfetnfetnfetnfet and one and one and one and one pfetpfetpfetpfet))))
large circuit area, especially for large circuit area, especially for large circuit area, especially for large circuit area, especially for pfetspfetspfetspfets“heavy” loading of inputs“heavy” loading of inputs“heavy” loading of inputs“heavy” loading of inputs
pfetspfetspfetspfets are either large or slow relative to are either large or slow relative to are either large or slow relative to are either large or slow relative to nfetsnfetsnfetsnfetsseries connections can get very slowseries connections can get very slowseries connections can get very slowseries connections can get very slow
We can replace We can replace We can replace We can replace pfet pulluppfet pulluppfet pulluppfet pullup network with pseudonetwork with pseudonetwork with pseudonetwork with pseudo----NMOS NMOS NMOS NMOS load (load (load (load (pfetpfetpfetpfet with grounded gate) butwith grounded gate) butwith grounded gate) butwith grounded gate) but
dissipate static power when output is lowdissipate static power when output is lowdissipate static power when output is lowdissipate static power when output is lowhave to make load have to make load have to make load have to make load fetfetfetfet small to ensure thatsmall to ensure thatsmall to ensure thatsmall to ensure thatVVVVOL OL OL OL is low enough to cut offis low enough to cut offis low enough to cut offis low enough to cut off nfetsnfetsnfetsnfets in next stagein next stagein next stagein next stage
reduces static power consumption (good!)reduces static power consumption (good!)reduces static power consumption (good!)reduces static power consumption (good!)increases output rise time (bad!)increases output rise time (bad!)increases output rise time (bad!)increases output rise time (bad!)
One alternative: One alternative: One alternative: One alternative: dynamic CMOS gatesdynamic CMOS gatesdynamic CMOS gatesdynamic CMOS gates
inputs must be stable before CLK goes high because inputs must be stable before CLK goes high because inputs must be stable before CLK goes high because inputs must be stable before CLK goes high because once output has once output has once output has once output has been discharged it won’t go high again until next cyclebeen discharged it won’t go high again until next cyclebeen discharged it won’t go high again until next cyclebeen discharged it won’t go high again until next cycle
for same reason, noise/glitches on inputs cannot exceed for same reason, noise/glitches on inputs cannot exceed for same reason, noise/glitches on inputs cannot exceed for same reason, noise/glitches on inputs cannot exceed nfetnfetnfetnfetthreshold, a much more stringent requirement than for static CMOthreshold, a much more stringent requirement than for static CMOthreshold, a much more stringent requirement than for static CMOthreshold, a much more stringent requirement than for static CMOS S S S gates.gates.gates.gates.
There’s good news & bad newsThere’s good news & bad newsThere’s good news & bad newsThere’s good news & bad newsThe good news:The good news:The good news:The good news:
Dynamic gates are faster than static gates despite the extra Dynamic gates are faster than static gates despite the extra Dynamic gates are faster than static gates despite the extra Dynamic gates are faster than static gates despite the extra “evaluate” “evaluate” “evaluate” “evaluate” fetfetfetfet in the in the in the in the pulldownpulldownpulldownpulldown path because of the reduction in selfpath because of the reduction in selfpath because of the reduction in selfpath because of the reduction in self----loading and the elimination of the loading and the elimination of the loading and the elimination of the loading and the elimination of the pulluppulluppulluppullup shortshortshortshort----circuit current during circuit current during circuit current during circuit current during the first part of the output transition.the first part of the output transition.the first part of the output transition.the first part of the output transition.
The bad news:The bad news:The bad news:The bad news:Dynamic gates cannot be cascaded.Dynamic gates cannot be cascaded.Dynamic gates cannot be cascaded.Dynamic gates cannot be cascaded.
Because of finite Because of finite Because of finite Because of finite pulldownpulldownpulldownpulldowntime for node , node time for node , node time for node , node time for node , node starts to discharge!starts to discharge!starts to discharge!starts to discharge!
Solution: develop techniques that avoid racesSolution: develop techniques that avoid racesSolution: develop techniques that avoid racesSolution: develop techniques that avoid racesCMOS Domino logicCMOS Domino logicCMOS Domino logicCMOS Domino logicCMOS NORA (no race) logicCMOS NORA (no race) logicCMOS NORA (no race) logicCMOS NORA (no race) logic
When CLK is low, dynamic node is preWhen CLK is low, dynamic node is preWhen CLK is low, dynamic node is preWhen CLK is low, dynamic node is preeeeecharged high and buffer inverter charged high and buffer inverter charged high and buffer inverter charged high and buffer inverter output is low. output is low. output is low. output is low. NfetsNfetsNfetsNfets in the next logic block will be off.in the next logic block will be off.in the next logic block will be off.in the next logic block will be off.
When CLK goes high, dynamic node is conditionally discharged anWhen CLK goes high, dynamic node is conditionally discharged anWhen CLK goes high, dynamic node is conditionally discharged anWhen CLK goes high, dynamic node is conditionally discharged and the d the d the d the buffer output will conditionally go high. Since discharge can obuffer output will conditionally go high. Since discharge can obuffer output will conditionally go high. Since discharge can obuffer output will conditionally go high. Since discharge can only nly nly nly happen once, buffer output can only make one lowhappen once, buffer output can only make one lowhappen once, buffer output can only make one lowhappen once, buffer output can only make one low----totototo----high transition.high transition.high transition.high transition.
When domino gates are cascaded, as each gate “evaluates”, if itsWhen domino gates are cascaded, as each gate “evaluates”, if itsWhen domino gates are cascaded, as each gate “evaluates”, if itsWhen domino gates are cascaded, as each gate “evaluates”, if itsoutput rises, it will trigger the evaluation of the next stage, output rises, it will trigger the evaluation of the next stage, output rises, it will trigger the evaluation of the next stage, output rises, it will trigger the evaluation of the next stage, and so and so and so and so on… like a line of dominos falling. Like dominos, once the inteon… like a line of dominos falling. Like dominos, once the inteon… like a line of dominos falling. Like dominos, once the inteon… like a line of dominos falling. Like dominos, once the internal rnal rnal rnal node in a gate “falls”, it stays “fallen” until it is “picked upnode in a gate “falls”, it stays “fallen” until it is “picked upnode in a gate “falls”, it stays “fallen” until it is “picked upnode in a gate “falls”, it stays “fallen” until it is “picked up” by the ” by the ” by the ” by the prepreprepreeeeecharge phase of the next cycle.charge phase of the next cycle.charge phase of the next cycle.charge phase of the next cycle.Thus many gates may evaluate in one Thus many gates may evaluate in one Thus many gates may evaluate in one Thus many gates may evaluate in one evalevalevaleval cycle.cycle.cycle.cycle.
buffer mightbuffer mightbuffer mightbuffer mightbe neededbe neededbe neededbe neededin any casein any casein any casein any casefor high fanfor high fanfor high fanfor high fan----outoutoutoutcircuits.circuits.circuits.circuits.
MicroLab, VLSI-6 (6/28)
JMM v1.3
More DominoMore DominoMore DominoMore Domino----style Circuitsstyle Circuitsstyle Circuitsstyle Circuits
nfetsnfetsnfetsnfets
CLKCLKCLKCLK
weak weak weak weak pfetpfetpfetpfet “keeper” keeps dynamic node pulled high during “keeper” keeps dynamic node pulled high during “keeper” keeps dynamic node pulled high during “keeper” keeps dynamic node pulled high during evaluate phase if it’s not being pulled down through evaluate phase if it’s not being pulled down through evaluate phase if it’s not being pulled down through evaluate phase if it’s not being pulled down through nfetsnfetsnfetsnfetsgate is static in both clock phases.gate is static in both clock phases.gate is static in both clock phases.gate is static in both clock phases.
nfetsnfetsnfetsnfets
“latching” “latching” “latching” “latching” pfetpfetpfetpfet acts like keeper above unless dynamic node acts like keeper above unless dynamic node acts like keeper above unless dynamic node acts like keeper above unless dynamic node gets pulled down during evaluate phase. When buffer output gets pulled down during evaluate phase. When buffer output gets pulled down during evaluate phase. When buffer output gets pulled down during evaluate phase. When buffer output goes high it switches keeper off saving static power. Good goes high it switches keeper off saving static power. Good goes high it switches keeper off saving static power. Good goes high it switches keeper off saving static power. Good for leakage current problems...for leakage current problems...for leakage current problems...for leakage current problems...
CLKCLKCLKCLK
Use NOR gate instead of inverter as the Use NOR gate instead of inverter as the Use NOR gate instead of inverter as the Use NOR gate instead of inverter as the buffer to make a faster high fanbuffer to make a faster high fanbuffer to make a faster high fanbuffer to make a faster high fan----in AND in AND in AND in AND gate. Same trick works for high fangate. Same trick works for high fangate. Same trick works for high fangate. Same trick works for high fan----in OR in OR in OR in OR or MUX functions. or MUX functions. or MUX functions. or MUX functions. CLKCLKCLKCLK
Note that you can put an Note that you can put an Note that you can put an Note that you can put an evenevenevenevennumber of static gates afternumber of static gates afternumber of static gates afternumber of static gates afterthe inverter and before thethe inverter and before thethe inverter and before thethe inverter and before thenext domino gate.next domino gate.next domino gate.next domino gate.
!!!! Be careful of cap.Be careful of cap.Be careful of cap.Be careful of cap.coupling to dynamiccoupling to dynamiccoupling to dynamiccoupling to dynamicnode (see later slide).node (see later slide).node (see later slide).node (see later slide).
Since domino gate outputs are low during the prSince domino gate outputs are low during the prSince domino gate outputs are low during the prSince domino gate outputs are low during the preeeecharge charge charge charge phase, gates which have only domino output nodes as phase, gates which have only domino output nodes as phase, gates which have only domino output nodes as phase, gates which have only domino output nodes as inputs don’t need the “evaluate” inputs don’t need the “evaluate” inputs don’t need the “evaluate” inputs don’t need the “evaluate” nfetnfetnfetnfet since all the since all the since all the since all the nfetsnfetsnfetsnfetsin the in the in the in the pulldownpulldownpulldownpulldown will be off anyway.will be off anyway.will be off anyway.will be off anyway.
But remember: if evaluate But remember: if evaluate But remember: if evaluate But remember: if evaluate nfetnfetnfetnfet is removed, precharge is removed, precharge is removed, precharge is removed, precharge will “ripple” through cascaded gates just like evaluates will “ripple” through cascaded gates just like evaluates will “ripple” through cascaded gates just like evaluates will “ripple” through cascaded gates just like evaluates do. Maybe only remove for gates where do. Maybe only remove for gates where do. Maybe only remove for gates where do. Maybe only remove for gates where nfetnfetnfetnfet stack is stack is stack is stack is tall (i.e. resistive) enough that tall (i.e. resistive) enough that tall (i.e. resistive) enough that tall (i.e. resistive) enough that pulluppulluppulluppullup will start to will start to will start to will start to “win” anyway before ripple reaches gates and turns off “win” anyway before ripple reaches gates and turns off “win” anyway before ripple reaches gates and turns off “win” anyway before ripple reaches gates and turns off pulldownspulldownspulldownspulldowns....
In domino logic circuits we want evaluateIn domino logic circuits we want evaluateIn domino logic circuits we want evaluateIn domino logic circuits we want evaluateto happen as quickly as possible. We canto happen as quickly as possible. We canto happen as quickly as possible. We canto happen as quickly as possible. We cansize fets to optimise evaluate speed.size fets to optimise evaluate speed.size fets to optimise evaluate speed.size fets to optimise evaluate speed.
If we make the If we make the If we make the If we make the nfetnfetnfetnfet in the output inverterin the output inverterin the output inverterin the output invertermuch smaller than the much smaller than the much smaller than the much smaller than the pfetpfetpfetpfet thenthenthenthen
the load on the internal node decreases, andthe load on the internal node decreases, andthe load on the internal node decreases, andthe load on the internal node decreases, andthe switching threshold of the inverter increasesthe switching threshold of the inverter increasesthe switching threshold of the inverter increasesthe switching threshold of the inverter increases
Both effects make the gate evaluate sooner. If large >> Both effects make the gate evaluate sooner. If large >> Both effects make the gate evaluate sooner. If large >> Both effects make the gate evaluate sooner. If large >> small, the gate delay can be cut almost in small, the gate delay can be cut almost in small, the gate delay can be cut almost in small, the gate delay can be cut almost in halfhalfhalfhalf! However, ! However, ! However, ! However, the other edge is very slow, so ripple prethe other edge is very slow, so ripple prethe other edge is very slow, so ripple prethe other edge is very slow, so ripple preeeeecharge is a charge is a charge is a charge is a problem.problem.problem.problem.
Some designers also “grade” the sizes of the Some designers also “grade” the sizes of the Some designers also “grade” the sizes of the Some designers also “grade” the sizes of the nfetsnfetsnfetsnfets, , , , smallest at the top (increase in R offset by decrease smallest at the top (increase in R offset by decrease smallest at the top (increase in R offset by decrease smallest at the top (increase in R offset by decrease in C)in C)in C)in C)
MicroLab, VLSI-6 (9/28)
JMM v1.3
“it is not everything gold which is “it is not everything gold which is “it is not everything gold which is “it is not everything gold which is glittering“glittering“glittering“glittering“
There are a few “little” difficulties:There are a few “little” difficulties:There are a few “little” difficulties:There are a few “little” difficulties:““““charge sharingcharge sharingcharge sharingcharge sharing” between nodes in the ” between nodes in the ” between nodes in the ” between nodes in the pulldownpulldownpulldownpulldownnetwork and the dynamic node can unintentionally network and the dynamic node can unintentionally network and the dynamic node can unintentionally network and the dynamic node can unintentionally reduce the voltage of the dynamic node enough to reduce the voltage of the dynamic node enough to reduce the voltage of the dynamic node enough to reduce the voltage of the dynamic node enough to switch output bufferswitch output bufferswitch output bufferswitch output bufferthe addition of the output inverter makes domino the addition of the output inverter makes domino the addition of the output inverter makes domino the addition of the output inverter makes domino gates nongates nongates nongates non----inverting. One can often design around inverting. One can often design around inverting. One can often design around inverting. One can often design around this limitation, but this limitation, but this limitation, but this limitation, but some circuits cannot be some circuits cannot be some circuits cannot be some circuits cannot be implemented solely using domino logicimplemented solely using domino logicimplemented solely using domino logicimplemented solely using domino logic unless both unless both unless both unless both polarities (true and complement) of the inputs are polarities (true and complement) of the inputs are polarities (true and complement) of the inputs are polarities (true and complement) of the inputs are available. If both polarities of inputs are available available. If both polarities of inputs are available available. If both polarities of inputs are available available. If both polarities of inputs are available then we can generate both polarities of internal then we can generate both polarities of internal then we can generate both polarities of internal then we can generate both polarities of internal signals with two domino gates so subsequent signals with two domino gates so subsequent signals with two domino gates so subsequent signals with two domino gates so subsequent stages will have both polarities of their inputs stages will have both polarities of their inputs stages will have both polarities of their inputs stages will have both polarities of their inputs available too.available too.available too.available too.
3C3C3C3CSuppose the dynamic node has beenSuppose the dynamic node has beenSuppose the dynamic node has beenSuppose the dynamic node has beendischarged during the previous discharged during the previous discharged during the previous discharged during the previous evaluate cycle. Then during evaluate cycle. Then during evaluate cycle. Then during evaluate cycle. Then during precharge, all the intermediate nodes precharge, all the intermediate nodes precharge, all the intermediate nodes precharge, all the intermediate nodes in the in the in the in the pulldownpulldownpulldownpulldown chain will remain chain will remain chain will remain chain will remain discharged while the dynamic node is discharged while the dynamic node is discharged while the dynamic node is discharged while the dynamic node is prechargedprechargedprechargedprecharged. Calculate the voltage on . Calculate the voltage on . Calculate the voltage on . Calculate the voltage on the dynamic node when CLK goes the dynamic node when CLK goes the dynamic node when CLK goes the dynamic node when CLK goes high. When CLK goes high, the high. When CLK goes high, the high. When CLK goes high, the high. When CLK goes high, the voltage on the dynamic node goes tovoltage on the dynamic node goes tovoltage on the dynamic node goes tovoltage on the dynamic node goes to
which is low enough to switch the output which is low enough to switch the output which is low enough to switch the output which is low enough to switch the output inverter.inverter.inverter.inverter.
Fortunately this situation is easily detected by CAD tools and cFortunately this situation is easily detected by CAD tools and cFortunately this situation is easily detected by CAD tools and cFortunately this situation is easily detected by CAD tools and can be an be an be an be resolved by (1) adding additional preresolved by (1) adding additional preresolved by (1) adding additional preresolved by (1) adding additional preeeeecharge devices to intermediate charge devices to intermediate charge devices to intermediate charge devices to intermediate nodes or (2) increasing size of output buffer which will increasnodes or (2) increasing size of output buffer which will increasnodes or (2) increasing size of output buffer which will increasnodes or (2) increasing size of output buffer which will increase e e e capacitance of dynamic node (faster output buffer may compensatecapacitance of dynamic node (faster output buffer may compensatecapacitance of dynamic node (faster output buffer may compensatecapacitance of dynamic node (faster output buffer may compensatefor larger internal capacitance).for larger internal capacitance).for larger internal capacitance).for larger internal capacitance).
A=1 A=1 A=1 A=1 ---->0>0>0>0
B=1B=1B=1B=1
C=1C=1C=1C=1
D=1D=1D=1D=1
E=1E=1E=1E=1
F=0F=0F=0F=0---->1>1>1>1
for Vfor Vfor Vfor VDDDDDDDD=3.3V=3.3V=3.3V=3.3V
MicroLab, VLSI-6 (11/28)
JMM v1.3
Charge Sharing (II)Charge Sharing (II)Charge Sharing (II)Charge Sharing (II)
Coupling can also occur between other signal wires and long dynaCoupling can also occur between other signal wires and long dynaCoupling can also occur between other signal wires and long dynaCoupling can also occur between other signal wires and long dynamic mic mic mic nodes (e.g., ones that span multiple bits in a nodes (e.g., ones that span multiple bits in a nodes (e.g., ones that span multiple bits in a nodes (e.g., ones that span multiple bits in a datapathdatapathdatapathdatapath). Solutions: ). Solutions: ). Solutions: ). Solutions: on long routes add “twists” to avoid continuous routes or route on long routes add “twists” to avoid continuous routes or route on long routes add “twists” to avoid continuous routes or route on long routes add “twists” to avoid continuous routes or route dynamic signals between mutually exclusive or complementary dynamic signals between mutually exclusive or complementary dynamic signals between mutually exclusive or complementary dynamic signals between mutually exclusive or complementary signals.signals.signals.signals.
MicroLab, VLSI-6 (13/28)
JMM v1.3
Domino Logic DesignDomino Logic DesignDomino Logic DesignDomino Logic DesignTo convert to DominoTo convert to DominoTo convert to DominoTo convert to Domino----style design we need tostyle design we need tostyle design we need tostyle design we need tocreate schematic that uses noncreate schematic that uses noncreate schematic that uses noncreate schematic that uses non----inverting gates:inverting gates:inverting gates:inverting gates:
(1) look for CMOS gates followed by inverter(1) look for CMOS gates followed by inverter(1) look for CMOS gates followed by inverter(1) look for CMOS gates followed by inverter(2) use (2) use (2) use (2) use Demorgan’sDemorgan’sDemorgan’sDemorgan’s Law to create nonLaw to create nonLaw to create nonLaw to create non----inv gatesinv gatesinv gatesinv gates
use use use use Demorgan’sDemorgan’sDemorgan’sDemorgan’s lawlawlawlaw
Convert to Domino OR gateConvert to Domino OR gateConvert to Domino OR gateConvert to Domino OR gate
DualDualDualDual----rail Domino Logicrail Domino Logicrail Domino Logicrail Domino LogicDomino circuits that generate both polarities of outputDomino circuits that generate both polarities of outputDomino circuits that generate both polarities of outputDomino circuits that generate both polarities of output
CLKCLKCLKCLK
AAAA
BBBB
CLKCLKCLKCLK
AAAA BBBB
CLKCLKCLKCLK
AAAA
BBBB
CLKCLKCLKCLK
AAAA BBBB
CLKCLKCLKCLK
AAAA
BBBB
AAAA
AAAA
BBBB
CLKCLKCLKCLK
MicroLab, VLSI-6 (16/28)
JMM v1.3
MultipleMultipleMultipleMultiple----output Dominooutput Dominooutput Dominooutput DominoWhy stop at complementary outputs? There are interesting Why stop at complementary outputs? There are interesting Why stop at complementary outputs? There are interesting Why stop at complementary outputs? There are interesting multiplemultiplemultiplemultiple----output functions where there is a lot of output functions where there is a lot of output functions where there is a lot of output functions where there is a lot of sharing of sharing of sharing of sharing of nfetsnfetsnfetsnfets in in in in the the the the evaluevaluevaluevaluaaaatetetete logiclogiclogiclogic. For example, in a carry. For example, in a carry. For example, in a carry. For example, in a carry----lookaheadlookaheadlookaheadlookahead adderadderadderadder
The crossThe crossThe crossThe cross----coupled coupled coupled coupled pfetspfetspfetspfets serve as “keepers”serve as “keepers”serve as “keepers”serve as “keepers”for the output which is high making the gatefor the output which is high making the gatefor the output which is high making the gatefor the output which is high making the gatestatic rather than dynamic! During prechargestatic rather than dynamic! During prechargestatic rather than dynamic! During prechargestatic rather than dynamic! During prechargeboth keepers are off; during the evaluateboth keepers are off; during the evaluateboth keepers are off; during the evaluateboth keepers are off; during the evaluatephase, the output that goes low switchesphase, the output that goes low switchesphase, the output that goes low switchesphase, the output that goes low switcheson the keeper for the output that is stayingon the keeper for the output that is stayingon the keeper for the output that is stayingon the keeper for the output that is stayinghigh. Really solves capacitive couplinghigh. Really solves capacitive couplinghigh. Really solves capacitive couplinghigh. Really solves capacitive couplingproblems with dynamic logic in problems with dynamic logic in problems with dynamic logic in problems with dynamic logic in datapathsdatapathsdatapathsdatapaths....
MicroLab, VLSI-6 (18/28)
JMM v1.3
Cascade voltage switch logic (CVSL)Cascade voltage switch logic (CVSL)Cascade voltage switch logic (CVSL)Cascade voltage switch logic (CVSL)
The static version might be The static version might be The static version might be The static version might be quite slow due to the quite slow due to the quite slow due to the quite slow due to the nfet nfet nfet nfet pfetpfetpfetpfet “fight” during switching“fight” during switching“fight” during switching“fight” during switching
If we turn a dynamic gate “upside down” and use If we turn a dynamic gate “upside down” and use If we turn a dynamic gate “upside down” and use If we turn a dynamic gate “upside down” and use pfetspfetspfetspfets to build the to build the to build the to build the logic block, we get a logic gate that “prelogic block, we get a logic gate that “prelogic block, we get a logic gate that “prelogic block, we get a logic gate that “preeeeecharges” low and charges” low and charges” low and charges” low and “discharges” high. By using these gates in an alternating seque“discharges” high. By using these gates in an alternating seque“discharges” high. By using these gates in an alternating seque“discharges” high. By using these gates in an alternating sequence nce nce nce with regular with regular with regular with regular nfetnfetnfetnfet dynamic gates we can eliminate the race problem dynamic gates we can eliminate the race problem dynamic gates we can eliminate the race problem dynamic gates we can eliminate the race problem we had with we had with we had with we had with nfetnfetnfetnfet----only dynamic gate sequences and hence we don’t only dynamic gate sequences and hence we don’t only dynamic gate sequences and hence we don’t only dynamic gate sequences and hence we don’t need the buffer inverter present in domino gates.need the buffer inverter present in domino gates.need the buffer inverter present in domino gates.need the buffer inverter present in domino gates.
Removing the buffer is a mixed blessing since we may need it forRemoving the buffer is a mixed blessing since we may need it forRemoving the buffer is a mixed blessing since we may need it forRemoving the buffer is a mixed blessing since we may need it fordrive reasons and to keep compatibility with other domino gates.drive reasons and to keep compatibility with other domino gates.drive reasons and to keep compatibility with other domino gates.drive reasons and to keep compatibility with other domino gates. It It It It also makes NORA logic also makes NORA logic also makes NORA logic also makes NORA logic very susceptible to noisevery susceptible to noisevery susceptible to noisevery susceptible to noise since during the since during the since during the since during the evaluate phase allevaluate phase allevaluate phase allevaluate phase all
information is stored dynamically.information is stored dynamically.information is stored dynamically.information is stored dynamically.
CLKCLKCLKCLK
nfetsnfetsnfetsnfets
CLKCLKCLKCLK
pfetspfetspfetspfets
CLKCLKCLKCLK
nfetsnfetsnfetsnfets
p blocksp blocksp blocksp blocks n blocksn blocksn blocksn blocks
prepreprepre
evalevalevaleval
evalevalevaleval
evalevalevalevalprepreprepre
prepreprepre
p blocksp blocksp blocksp blocksn blocksn blocksn blocksn blocks
MicroLab, VLSI-6 (20/28)
JMM v1.3
Domino Life CycleDomino Life CycleDomino Life CycleDomino Life Cycle
Waiting for prechargeWaiting for prechargeWaiting for prechargeWaiting for precharge(holding output value)(holding output value)(holding output value)(holding output value)
The “9 O’clock” state is very interesting: once a Domino gate haThe “9 O’clock” state is very interesting: once a Domino gate haThe “9 O’clock” state is very interesting: once a Domino gate haThe “9 O’clock” state is very interesting: once a Domino gate has s s s finished evaluating, the gate’s immediate predecessors can startfinished evaluating, the gate’s immediate predecessors can startfinished evaluating, the gate’s immediate predecessors can startfinished evaluating, the gate’s immediate predecessors can start to to to to prprprpreeeeeargeeargeeargeearge (forcing the gate’s inputs low) without affecting the value of (forcing the gate’s inputs low) without affecting the value of (forcing the gate’s inputs low) without affecting the value of (forcing the gate’s inputs low) without affecting the value of the gate’s output. The gate is acting as the gate’s output. The gate is acting as the gate’s output. The gate is acting as the gate’s output. The gate is acting as latchlatchlatchlatch so long as its so long as its so long as its so long as its predecessors don’t start another evaluate cycle.predecessors don’t start another evaluate cycle.predecessors don’t start another evaluate cycle.predecessors don’t start another evaluate cycle.
Perhaps we can build a pipeline of domino stages where each stagPerhaps we can build a pipeline of domino stages where each stagPerhaps we can build a pipeline of domino stages where each stagPerhaps we can build a pipeline of domino stages where each stage e e e serves as both logic and latch depending on where it is in its cserves as both logic and latch depending on where it is in its cserves as both logic and latch depending on where it is in its cserves as both logic and latch depending on where it is in its cycle. ycle. ycle. ycle. Need to have each stage Need to have each stage Need to have each stage Need to have each stage supply its own prsupply its own prsupply its own prsupply its own preeeecharge/evaluate timingcharge/evaluate timingcharge/evaluate timingcharge/evaluate timingdependent on what its neighbours are doing...dependent on what its neighbours are doing...dependent on what its neighbours are doing...dependent on what its neighbours are doing...
might be several gatesmight be several gatesmight be several gatesmight be several gates
Simplest correctness rules:Simplest correctness rules:Simplest correctness rules:Simplest correctness rules:a stage only prea stage only prea stage only prea stage only precccchargeshargeshargesharges when bothwhen bothwhen bothwhen both
(a) its successor has finished evaluating(a) its successor has finished evaluating(a) its successor has finished evaluating(a) its successor has finished evaluating(it’s done with our values)(it’s done with our values)(it’s done with our values)(it’s done with our values)
(b) its predecessor has finished (b) its predecessor has finished (b) its predecessor has finished (b) its predecessor has finished prechargingprechargingprechargingprecharging(old values are gone so we can’t use ‘(old values are gone so we can’t use ‘(old values are gone so we can’t use ‘(old values are gone so we can’t use ‘emememem twice!)twice!)twice!)twice!)
a stage only evaluates when botha stage only evaluates when botha stage only evaluates when botha stage only evaluates when both(a) its successor has finished (a) its successor has finished (a) its successor has finished (a) its successor has finished prechargingprechargingprechargingprecharging
(our new output won’t affect its stored value)(our new output won’t affect its stored value)(our new output won’t affect its stored value)(our new output won’t affect its stored value)(b) its predecessor has finished (b) its predecessor has finished (b) its predecessor has finished (b) its predecessor has finished evalevalevalevaluuuuatingatingatingating
(there are new inputs for us to consider)(there are new inputs for us to consider)(there are new inputs for us to consider)(there are new inputs for us to consider)
P/EP/EP/EP/E P/EP/EP/EP/E P/EP/EP/EP/E
So, what logic goes in the clouds?So, what logic goes in the clouds?So, what logic goes in the clouds?So, what logic goes in the clouds?And how do we build the “done?” boxes?And how do we build the “done?” boxes?And how do we build the “done?” boxes?And how do we build the “done?” boxes?
Add weak feedbackAdd weak feedbackAdd weak feedbackAdd weak feedbackinverter if we’re worriedinverter if we’re worriedinverter if we’re worriedinverter if we’re worriedabout dynamic storageabout dynamic storageabout dynamic storageabout dynamic storagefor precharge/for precharge/for precharge/for precharge/evalevalevaleval signalsignalsignalsignal
The Muller CThe Muller CThe Muller CThe Muller C----Element is the “AND” gate for selfElement is the “AND” gate for selfElement is the “AND” gate for selfElement is the “AND” gate for self----timed timed timed timed logic because it changes its output only after both inputs logic because it changes its output only after both inputs logic because it changes its output only after both inputs logic because it changes its output only after both inputs have changed. As shown above, it’s an elegant have changed. As shown above, it’s an elegant have changed. As shown above, it’s an elegant have changed. As shown above, it’s an elegant implementation for both sets of rules on the previous implementation for both sets of rules on the previous implementation for both sets of rules on the previous implementation for both sets of rules on the previous slide.slide.slide.slide.
SelfSelfSelfSelf----timed logictimed logictimed logictimed logicuse dualuse dualuse dualuse dual----rail signalling (rail signalling (rail signalling (rail signalling (i.e.i.e.i.e.i.e., two wires) to encode, two wires) to encode, two wires) to encode, two wires) to encode
reset (not yet evaluated) reset (not yet evaluated) reset (not yet evaluated) reset (not yet evaluated) 00000000ready with value 0ready with value 0ready with value 0ready with value 0 01010101ready with value 1ready with value 1ready with value 1ready with value 1 10101010
and then build handshake logic that startsand then build handshake logic that startsand then build handshake logic that startsand then build handshake logic that startsnext stage when current stage is done and nextnext stage when current stage is done and nextnext stage when current stage is done and nextnext stage when current stage is done and nextstage has completed its previous computationstage has completed its previous computationstage has completed its previous computationstage has completed its previous computationand delivered its values...and delivered its values...and delivered its values...and delivered its values...
Propagation through selfPropagation through selfPropagation through selfPropagation through self----timed pipelinestimed pipelinestimed pipelinestimed pipelinesis constrained in both directions:is constrained in both directions:is constrained in both directions:is constrained in both directions:
In the forward direction by how long it takes for the evaluate In the forward direction by how long it takes for the evaluate In the forward direction by how long it takes for the evaluate In the forward direction by how long it takes for the evaluate edge in one stage to trigger the evaluate edge in the next stageedge in one stage to trigger the evaluate edge in the next stageedge in one stage to trigger the evaluate edge in the next stageedge in one stage to trigger the evaluate edge in the next stage::::
LLLLFFFF = = = = ttttFFFF + + + + ttttDDDD + + + + ttttCCCCIn the reverse direction by how long it takesIn the reverse direction by how long it takesIn the reverse direction by how long it takesIn the reverse direction by how long it takesfor the precharge in one stage to trigger a newfor the precharge in one stage to trigger a newfor the precharge in one stage to trigger a newfor the precharge in one stage to trigger a newevaluate in the stage after first evaluating the previous stage evaluate in the stage after first evaluating the previous stage evaluate in the stage after first evaluating the previous stage evaluate in the stage after first evaluating the previous stage (remember not double count!):(remember not double count!):(remember not double count!):(remember not double count!):
Further ImprovementsFurther ImprovementsFurther ImprovementsFurther Improvements
We don’t have to delay evaluation until successor has We don’t have to delay evaluation until successor has We don’t have to delay evaluation until successor has We don’t have to delay evaluation until successor has finishedfinishedfinishedfinishedits precharge (signalling that it’s finished with our values). its precharge (signalling that it’s finished with our values). its precharge (signalling that it’s finished with our values). its precharge (signalling that it’s finished with our values). We We We We can just check that successor has can just check that successor has can just check that successor has can just check that successor has startedstartedstartedstarted prechargingprechargingprechargingprecharging… Even … Even … Even … Even with this improvement, the correct sequencing will still happen with this improvement, the correct sequencing will still happen with this improvement, the correct sequencing will still happen with this improvement, the correct sequencing will still happen for any combination of precharge and evaluate times for all the for any combination of precharge and evaluate times for all the for any combination of precharge and evaluate times for all the for any combination of precharge and evaluate times for all the gates.gates.gates.gates.We can modify the control element like so:We can modify the control element like so:We can modify the control element like so:We can modify the control element like so:
PPPPdonedonedonedone
SSSSdonedonedonedone
P/EP/EP/EP/E
S S S S P/EP/EP/EP/E
Eliminate the “extra”Eliminate the “extra”Eliminate the “extra”Eliminate the “extra”inverter for good measureinverter for good measureinverter for good measureinverter for good measureand use dynamic storageand use dynamic storageand use dynamic storageand use dynamic storageas control element memoryas control element memoryas control element memoryas control element memory
We’re going to stop here, but there are otherWe’re going to stop here, but there are otherWe’re going to stop here, but there are otherWe’re going to stop here, but there are otherimprovements that can be made. Hint: do we haveimprovements that can be made. Hint: do we haveimprovements that can be made. Hint: do we haveimprovements that can be made. Hint: do we haveto wait until the predecessor is done computingto wait until the predecessor is done computingto wait until the predecessor is done computingto wait until the predecessor is done computingnew values before starting our new values before starting our new values before starting our new values before starting our evalevalevaleval? etc., etc., etc.? etc., etc., etc.? etc., etc., etc.? etc., etc., etc.
MicroLab, VLSI-6 (26/28)
JMM v1.3
Dynamic Logic SummaryDynamic Logic SummaryDynamic Logic SummaryDynamic Logic SummaryAdvantages of dynamic logic:Advantages of dynamic logic:Advantages of dynamic logic:Advantages of dynamic logic:
smaller area than fully static gatessmaller area than fully static gatessmaller area than fully static gatessmaller area than fully static gatessmaller parasitic capacitances hence higher smaller parasitic capacitances hence higher smaller parasitic capacitances hence higher smaller parasitic capacitances hence higher speedspeedspeedspeed
reliable operation if correctly designed. Concerns:reliable operation if correctly designed. Concerns:reliable operation if correctly designed. Concerns:reliable operation if correctly designed. Concerns:capacitive coupling to dynamic nodescapacitive coupling to dynamic nodescapacitive coupling to dynamic nodescapacitive coupling to dynamic nodescharge sharing with dynamic nodescharge sharing with dynamic nodescharge sharing with dynamic nodescharge sharing with dynamic nodessubthresholdsubthresholdsubthresholdsubthreshold leakage currents in leakage currents in leakage currents in leakage currents in evalevalevaleval logiclogiclogiclogicminority carrier injection and minority carrier injection and minority carrier injection and minority carrier injection and latchuplatchuplatchuplatchupalpha particle immunityalpha particle immunityalpha particle immunityalpha particle immunityvddvddvddvdd////gndgndgndgnd noise and resistancenoise and resistancenoise and resistancenoise and resistance
This makes dynamic logic a good choice for those parts of This makes dynamic logic a good choice for those parts of This makes dynamic logic a good choice for those parts of This makes dynamic logic a good choice for those parts of a circuit where the extra engineering investment is a circuit where the extra engineering investment is a circuit where the extra engineering investment is a circuit where the extra engineering investment is justified, e.g., along the critical timing paths.justified, e.g., along the critical timing paths.justified, e.g., along the critical timing paths.justified, e.g., along the critical timing paths.
Engineers who like this sortEngineers who like this sortEngineers who like this sortEngineers who like this sortof design will find this the sortof design will find this the sortof design will find this the sortof design will find this the sortof design they like!of design they like!of design they like!of design they like!
WesteWesteWesteWeste pp371: 5.9ex8 (difficulty: easy): pp371: 5.9ex8 (difficulty: easy): pp371: 5.9ex8 (difficulty: easy): pp371: 5.9ex8 (difficulty: easy): Design a Design a Design a Design a CVSL gate for the following fuCVSL gate for the following fuCVSL gate for the following fuCVSL gate for the following funnnnctionctionctionction::::
VLSI Systems DesignVLSI Systems DesignVLSI Systems DesignVLSI Systems DesignMicroelectronic TechnologiesMicroelectronic TechnologiesMicroelectronic TechnologiesMicroelectronic Technologies
Goal: Goal: Goal: Goal: You are familiar with the microelectronic You are familiar with the microelectronic You are familiar with the microelectronic You are familiar with the microelectronic technologies, and know their advantages and features.technologies, and know their advantages and features.technologies, and know their advantages and features.technologies, and know their advantages and features.
What is microelectronic ?What is microelectronic ?What is microelectronic ?What is microelectronic ?Has a microelectronic design engineer only to have Has a microelectronic design engineer only to have Has a microelectronic design engineer only to have Has a microelectronic design engineer only to have good knowledge about silicon, layout, etc. ?good knowledge about silicon, layout, etc. ?good knowledge about silicon, layout, etc. ?good knowledge about silicon, layout, etc. ?
featuresfeaturesfeaturesfeaturessize: 100 size: 100 size: 100 size: 100 ---- 1M gates1M gates1M gates1M gatesshort turn around timeshort turn around timeshort turn around timeshort turn around timecheap at medium quantitiescheap at medium quantitiescheap at medium quantitiescheap at medium quantitiesunsuitable for regular structures like RAM, PLA, ALUunsuitable for regular structures like RAM, PLA, ALUunsuitable for regular structures like RAM, PLA, ALUunsuitable for regular structures like RAM, PLA, ALU
3 cells of a gate array are illustrated3 cells of a gate array are illustrated3 cells of a gate array are illustrated3 cells of a gate array are illustrated1 cell corresponds to a 2 input1 cell corresponds to a 2 input1 cell corresponds to a 2 input1 cell corresponds to a 2 input nandnandnandnand gategategategate
I/O stages predefinedI/O stages predefinedI/O stages predefinedI/O stages predefinedregular array ofregular array ofregular array ofregular array of fetsfetsfetsfets, no reserved interconnection , no reserved interconnection , no reserved interconnection , no reserved interconnection channelschannelschannelschannelsinterconnection defines functionalityinterconnection defines functionalityinterconnection defines functionalityinterconnection defines functionality
featuresfeaturesfeaturesfeaturessize: 100 size: 100 size: 100 size: 100 ---- 1M gates1M gates1M gates1M gatesshort turn around timeshort turn around timeshort turn around timeshort turn around timecheap at medium quantitiescheap at medium quantitiescheap at medium quantitiescheap at medium quantitiesregular structures like RAM, PLA, ALU can be usedregular structures like RAM, PLA, ALU can be usedregular structures like RAM, PLA, ALU can be usedregular structures like RAM, PLA, ALU can be used
MicroLab, VLSI-8 (6/20)
JMM v1.4
SOG Example SOG Example SOG Example SOG Example INVINVINVINV NOR2NOR2NOR2NOR2
Standard Cell TechnologyStandard Cell TechnologyStandard Cell TechnologyStandard Cell Technologycomplete fabrication processcomplete fabrication processcomplete fabrication processcomplete fabrication process
predefined library of base functionspredefined library of base functionspredefined library of base functionspredefined library of base functionsmodular similar to TTL familiesmodular similar to TTL familiesmodular similar to TTL familiesmodular similar to TTL families
featuresfeaturesfeaturesfeatureschip size limits complexitychip size limits complexitychip size limits complexitychip size limits complexitylong turn around timelong turn around timelong turn around timelong turn around timecheap at high quantitiescheap at high quantitiescheap at high quantitiescheap at high quantitiesstandardized cell heightstandardized cell heightstandardized cell heightstandardized cell heightunsuitable for regular structuresunsuitable for regular structuresunsuitable for regular structuresunsuitable for regular structuresmore flexible and compact (1:4) than gate arraymore flexible and compact (1:4) than gate arraymore flexible and compact (1:4) than gate arraymore flexible and compact (1:4) than gate array
MicroLab, VLSI-8 (8/20)
JMM v1.4
Standard Cell ExampleStandard Cell ExampleStandard Cell ExampleStandard Cell Example
Quiz: what‘s the Quiz: what‘s the Quiz: what‘s the Quiz: what‘s the cells functioncells functioncells functioncells function
Create a Create a Create a Create a librarylibrarylibrarylibrary of preof preof preof pre----layedlayedlayedlayed----out cells, e.g,,out cells, e.g,,out cells, e.g,,out cells, e.g,, booleanbooleanbooleanboolean gates, gates, gates, gates, registers,registers,registers,registers, muxesmuxesmuxesmuxes, adders, I/O pads, … A data sheet for , adders, I/O pads, … A data sheet for , adders, I/O pads, … A data sheet for , adders, I/O pads, … A data sheet for each cell describes the cell’s function, area, power, each cell describes the cell’s function, area, power, each cell describes the cell’s function, area, power, each cell describes the cell’s function, area, power, propagation delay, output rise/fall time as function of propagation delay, output rise/fall time as function of propagation delay, output rise/fall time as function of propagation delay, output rise/fall time as function of load, etc.load, etc.load, etc.load, etc.
It’s just like designing with boardIt’s just like designing with boardIt’s just like designing with boardIt’s just like designing with board----level components. level components. level components. level components. CAD tools help with CAD tools help with CAD tools help with CAD tools help with placingplacingplacingplacing the cells to minimize area the cells to minimize area the cells to minimize area the cells to minimize area and to meet timing constraints (perhaps directed by aand to meet timing constraints (perhaps directed by aand to meet timing constraints (perhaps directed by aand to meet timing constraints (perhaps directed by afloorplanfloorplanfloorplanfloorplan created by the user); created by the user); created by the user); created by the user); routersroutersroutersrouters make the make the make the make the appropriate connections between the cells.appropriate connections between the cells.appropriate connections between the cells.appropriate connections between the cells.
MicroLab, VLSI-8 (9/20)
JMM v1.4
Full Custom TechnologyFull Custom TechnologyFull Custom TechnologyFull Custom Technology
complete fabrication processcomplete fabrication processcomplete fabrication processcomplete fabrication processtotal flexibility, only limited by layout rulestotal flexibility, only limited by layout rulestotal flexibility, only limited by layout rulestotal flexibility, only limited by layout rulesmanual designmanual designmanual designmanual design
featuresfeaturesfeaturesfeatureschip size limits complexitychip size limits complexitychip size limits complexitychip size limits complexitylong design and fabrication timelong design and fabrication timelong design and fabrication timelong design and fabrication timeefficient use of silicon areaefficient use of silicon areaefficient use of silicon areaefficient use of silicon areacheap only at highest quantities (ex.cheap only at highest quantities (ex.cheap only at highest quantities (ex.cheap only at highest quantities (ex. uPuPuPuP, memories, ...), memories, ...), memories, ...), memories, ...)
complete fabrication processcomplete fabrication processcomplete fabrication processcomplete fabrication processcombines semicombines semicombines semicombines semi---- and full custom technologiesand full custom technologiesand full custom technologiesand full custom technologiespredefined library of base functionspredefined library of base functionspredefined library of base functionspredefined library of base functionsgenerators for regular structuresgenerators for regular structuresgenerators for regular structuresgenerators for regular structures
featuresfeaturesfeaturesfeatureschip size limits complexitychip size limits complexitychip size limits complexitychip size limits complexityshort design, long fabrication timeshort design, long fabrication timeshort design, long fabrication timeshort design, long fabrication timecheap at high quantitiescheap at high quantitiescheap at high quantitiescheap at high quantitieshigh flexibility, high flexibility, high flexibility, high flexibility, compact layoutscompact layoutscompact layoutscompact layouts
field programmable devicefield programmable devicefield programmable devicefield programmable deviceno fabrication needed for customizingno fabrication needed for customizingno fabrication needed for customizingno fabrication needed for customizingpredefined logic blockspredefined logic blockspredefined logic blockspredefined logic blocksunsuitable for regular structuresunsuitable for regular structuresunsuitable for regular structuresunsuitable for regular structures
featuresfeaturesfeaturesfeaturessize: up to 2‘000’000 logic gates (seesize: up to 2‘000’000 logic gates (seesize: up to 2‘000’000 logic gates (seesize: up to 2‘000’000 logic gates (see VirtexVirtexVirtexVirtex fromfromfromfrom XilinxXilinxXilinxXilinx))))large silicon area necessary (72 millionlarge silicon area necessary (72 millionlarge silicon area necessary (72 millionlarge silicon area necessary (72 million fetsfetsfetsfets, 10x Pentium2), 10x Pentium2), 10x Pentium2), 10x Pentium2)short design and customize timeshort design and customize timeshort design and customize timeshort design and customize timecheap for small quantitiescheap for small quantitiescheap for small quantitiescheap for small quantitiescompared tocompared tocompared tocompared to ASICsASICsASICsASICs,,,, FPGAsFPGAsFPGAsFPGAs have a reduced clock speedhave a reduced clock speedhave a reduced clock speedhave a reduced clock speedcircuit configuration downloadable (RAM or PROM)circuit configuration downloadable (RAM or PROM)circuit configuration downloadable (RAM or PROM)circuit configuration downloadable (RAM or PROM)
configurationconfigurationconfigurationconfiguration---- mask programmablemask programmablemask programmablemask programmable---- one time programmableone time programmableone time programmableone time programmable---- downloading of configuration from host into internal RAMdownloading of configuration from host into internal RAMdownloading of configuration from host into internal RAMdownloading of configuration from host into internal RAM---- downloading of configuration from on board serial ROMdownloading of configuration from on board serial ROMdownloading of configuration from on board serial ROMdownloading of configuration from on board serial ROM
Switching matrix withSwitching matrix withSwitching matrix withSwitching matrix with CLBsCLBsCLBsCLBs
MicroLab, VLSI-8 (16/20)
JMM v1.4
uCuCuCuC TechnologyTechnologyTechnologyTechnology
field programmable devicefield programmable devicefield programmable devicefield programmable deviceno fabrication needed for customizingno fabrication needed for customizingno fabrication needed for customizingno fabrication needed for customizingsimple C software compilerssimple C software compilerssimple C software compilerssimple C software compilerssoftware vs. hardware solutionssoftware vs. hardware solutionssoftware vs. hardware solutionssoftware vs. hardware solutions
featuresfeaturesfeaturesfeatures4 or 8 bit CPU, size: 512 bytes or more4 or 8 bit CPU, size: 512 bytes or more4 or 8 bit CPU, size: 512 bytes or more4 or 8 bit CPU, size: 512 bytes or moredown to 8 pinsdown to 8 pinsdown to 8 pinsdown to 8 pinsAD,AD,AD,AD, usartusartusartusart, timer, etc. included, timer, etc. included, timer, etc. included, timer, etc. includedvery slow compared to hardware solutionsvery slow compared to hardware solutionsvery slow compared to hardware solutionsvery slow compared to hardware solutionscheap (<$2)cheap (<$2)cheap (<$2)cheap (<$2)
PICPICPICPIC
36 mm36 mm36 mm36 mm
MicroLab, VLSI-8 (17/20)
JMM v1.4
How to select a technologyHow to select a technologyHow to select a technologyHow to select a technology
Selection argumentsSelection argumentsSelection argumentsSelection arguments---- costcostcostcost---- speedspeedspeedspeed---- sizesizesizesize---- time to markettime to markettime to markettime to market
quantityquantityquantityquantity
costcostcostcost
designdesigndesigndesign
unitsunitsunitsunitsdesigndesigndesigndesign
NRENRENRENRE
unitsunitsunitsunits ASICASICASICASIC
break evenbreak evenbreak evenbreak even
FPGAFPGAFPGAFPGA
MicroLab, VLSI-8 (18/20)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Hardware description language VHDL, topHardware description language VHDL, topHardware description language VHDL, topHardware description language VHDL, top----down down down down design. design. design. design.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…XilinxXilinxXilinxXilinx articlearticlearticlearticle: The total cost of ownership: The total cost of ownership: The total cost of ownership: The total cost of ownership
Ex vlsi08.1 (difficulty: easy): Ex vlsi08.1 (difficulty: easy): Ex vlsi08.1 (difficulty: easy): Ex vlsi08.1 (difficulty: easy): Calculate the breakeven Calculate the breakeven Calculate the breakeven Calculate the breakeven point between an FPGA and ASIC design. Assume a point between an FPGA and ASIC design. Assume a point between an FPGA and ASIC design. Assume a point between an FPGA and ASIC design. Assume a design time of 6 months and an additional backdesign time of 6 months and an additional backdesign time of 6 months and an additional backdesign time of 6 months and an additional back----end end end end design time of 1 month for the ASIC. The NRE design time of 1 month for the ASIC. The NRE design time of 1 month for the ASIC. The NRE design time of 1 month for the ASIC. The NRE costs of the ASIC are 75kEuro, the cost per unit costs of the ASIC are 75kEuro, the cost per unit costs of the ASIC are 75kEuro, the cost per unit costs of the ASIC are 75kEuro, the cost per unit are 150Euro for the FPGA and 3 Euro for the ASIC. are 150Euro for the FPGA and 3 Euro for the ASIC. are 150Euro for the FPGA and 3 Euro for the ASIC. are 150Euro for the FPGA and 3 Euro for the ASIC. The cost of 1 engineer per month are 10kEuro. The cost of 1 engineer per month are 10kEuro. The cost of 1 engineer per month are 10kEuro. The cost of 1 engineer per month are 10kEuro.
Result: breakeven at 578Result: breakeven at 578Result: breakeven at 578Result: breakeven at 578
Ex vlsi08.2 (difficulty: medium): Ex vlsi08.2 (difficulty: medium): Ex vlsi08.2 (difficulty: medium): Ex vlsi08.2 (difficulty: medium): Calculate the Calculate the Calculate the Calculate the breakeven point between an FPGA and ASIC design. breakeven point between an FPGA and ASIC design. breakeven point between an FPGA and ASIC design. breakeven point between an FPGA and ASIC design. Assume the design costs from exercise vlsi08.2 Assume the design costs from exercise vlsi08.2 Assume the design costs from exercise vlsi08.2 Assume the design costs from exercise vlsi08.2 and a fabrication time of 3 months for the ASIC. and a fabrication time of 3 months for the ASIC. and a fabrication time of 3 months for the ASIC. and a fabrication time of 3 months for the ASIC. The revenue per sold system at a product lifetime The revenue per sold system at a product lifetime The revenue per sold system at a product lifetime The revenue per sold system at a product lifetime of 4 years is 600Euro without taking into account of 4 years is 600Euro without taking into account of 4 years is 600Euro without taking into account of 4 years is 600Euro without taking into account the FPGA/ASIC chip costs. Use the triangular the FPGA/ASIC chip costs. Use the triangular the FPGA/ASIC chip costs. Use the triangular the FPGA/ASIC chip costs. Use the triangular timetimetimetime----totototo----market model frommarket model frommarket model frommarket model from SynopsysSynopsysSynopsysSynopsys (see(see(see(see XilinxXilinxXilinxXilinxarticle “The total cost of ownership). article “The total cost of ownership). article “The total cost of ownership). article “The total cost of ownership).
Result: breakeven at 14068 FPGA solutionsResult: breakeven at 14068 FPGA solutionsResult: breakeven at 14068 FPGA solutionsResult: breakeven at 14068 FPGA solutions
Look for a systematic physical structure:w get handle on layout for “random” logicw automate layout task once schematic is donew may have several structures to choose from, each optimized
along a different design dimensionstandard cells, gate arrays
But we still have to draw the schematic! So look for systematic logical structures:w may lead to additional systematic physical layoutsw find canonical logic representations that can be automatically
turned into compact physical structures (automate, automate,automate…)
w would like to be able to make changes in the logic without having to redo entire layout -- look for “ECO-tolerant” structures (engineering change orders)
muxes, ROMs, PLAs
MicroLab, VLSI-9 (3/12)
JMM v1.2
Useful Logic Forms
Truth tablesw direct implementation as muxes, ROMsw good when you have many outputs and few inputs since cost of
“decoding” inputs is fixedw ECO-tolerant but often not efficient use of logic
Minimum Sum-of-Products (SOP, AND-OR)w minimize no. of literals (small fan-in ANDs) or no. of products
(small fan-in ORs)w maximum sharing of product terms for multiple-output functionsw if fan-ins are small: direct implementation as complex gates or
as 2-levels of ANDs then ORsw if fan-ins aren’t small: multiple levels of gates (e.g., parity,
“Achilles heel” = 2n-1 minterms) w efficient use of logic, but not very ECO-tolerant
But how do we minimize the number of literals or minterms? Yeah, we know about Karnaugh maps, but they aren’t so good for more than 4 inputs or for maximizing minterm sharing.
MicroLab, VLSI-9 (4/12)
JMM v1.2
Logic Manipulation
Start with two-level minimizationw by inspection searching for terms that are logically
adjacent:
w Karnaugh maps for simple situationsw Quine-McCluskey otherwise
Then try to generate multiple levels:w factoring. Choose literal that appears in most product
terms (>1) and factor it out.
w factor again with or-terms that appear in multiple places
w find common subexpressions (multiple output decomposition)
ppxxpxpxp =⋅=+⋅=⋅+⋅ 1)(
F a c a d b c b d a ea c d b c d ae
= ⋅ + ⋅ + ⋅ + ⋅ + ⋅= ⋅ + + ⋅ + +( ) ( )
F a b c d ae= + ⋅ + +( ) ( )
MicroLab, VLSI-9 (5/12)
JMM v1.2
Muxes as “lookup tables”A00001111
B00110011
C01010101
F00010111
A,B,C
A,B
0CC1
Easy to implement but not necessarilycompact even when implemented with TGs.But you can make a nice Boolean Unit:
A,B
OP0OP1OP2OP3
F
OP<3:0> F0110
0011
0011
0000
ZEROANDORXOR
Vcc
gnd
out
B
A
MicroLab, VLSI-9 (6/12)
JMM v1.2
Read-only Memories
7
6
5
4
3
2
1
0
A B C F1 F0
Address decoderimplemented asAND (= NOR).Note: all but onerow pulled downfor given input.
For each Fi,OR togetherall rows forwhich outputis 1 (actuallyuse NOR theninvert).
Like muxes, but share decoding logic amongall outputs. Potential optimizations:w delete rows with no output pulldownsw look for “adjacent” rows with identical
output pulldown configurations andmerge into single row.
Are these worth doing?
if connection ormosfet is present,blank otherwise
if connection ormosfet is present,blank otherwise
MicroLab, VLSI-9 (7/12)
JMM v1.2
PLAs
4,5,6,7
2,3
1
A B C F1 F0
In fact, the optimizations from the previousslide are so worthwhile that we have aname for the resulting “optimized” ROM:Programmed Logic Array, or PLA for short.
PLAs are usually constructed directly from minimizedSOP logic equations: the rows represent the minterms ofthe equations, the “input” columns form the minterms and the “output” columns form the sums.Note that with multiple output columns,minterm sharing between the outputs happens naturally...
What are the logicequations for F1and F0?
Hint: for greaterECO-tolerance, adda few extra emptyrows!
“AND” plane “OR” plane
MicroLab, VLSI-9 (8/12)
JMM v1.2
PLA Folding
3456
21
A A B B C C D D F1 F2
F1A A B B
D D C C
345
6
21
F2
PLAs can be sparse, i.e., only a few of thepossible connections in either plane may be made. (AND plane can only have 50%!)
If we allow input and outputs to come fromboth above and below then we may be ableto fold two columns into one if the rowsthey use don’t overlap. This may requirerearranging the rows to minimize overlapand hence maximize folding possibilities.
Row foldingis anotherpossibleoptimization(but not in thisexample).
MicroLab, VLSI-9 (9/12)
JMM v1.2
Multiple-input encodingOn the previous slide, it was noted thatthe AND plane can have at most 50% ofits connections programmed. Why?
To improve the utilization of the inputcolumns, consider encoding the 4 columnsused to transmit the two input literals andtheir complements with some more usefulfunctions of the two literals. For example:
AIN
AB
BIN
AB AB AB
AIN
AA
BIN
BB
You get extra computing oomph: for example, it’s now possible to compute (A xor B) usinga single row rather than the two rows it tookwith the old encoding.
MicroLab, VLSI-9 (10/12)
JMM v1.2
Datapath OperatorsMost digital functions can be divided into the following categories:
u datapath operatorsu memory elementsu control structuresu I/O cells
Datapath operators form an important subclass ofVLSI design that benefit from the structured design principles of hierarchy, regularity, modularity and locality.
u N-bit Data is generally processed by the use of n identical subcircuits.
u Data operations may be sequenced in time or space.
u data may be arranged to flow in one directionu control signals are introduced in an orthogonal direction
to the dataflow
- =0
m
m
m
A
B
Z
less than or equal
- =0 ifA0B0
- =0 ifA1B1
- =0 ifAm-1Bm-1
- =0 ifAmBm
m bit
s
Z0
Z1
Zm-1
Zm
ctrl
subtractor equal-zero mux
If (A<=B) then Z=A else Z=B
metal
1 con
trol f
low
metal2 data flow
MicroLab, VLSI-9 (12/12)
JMM v1.2
Coming Up...
Next topic…Sequential logic: state elements, latches and registers. Static vs. dynamic storage. Single and multiphase clocking strategies. Setup and holdtimes; propagation delays.
Readings for next time…Weste:u Sections 8.1 thru 8.2 (data operators)u 8.3.2, 8.4.2 (just read, don‘t study)
OverviewOverviewOverviewOverviewsingle and double phase clock systemssingle and double phase clock systemssingle and double phase clock systemssingle and double phase clock systemsLatch and FF timingLatch and FF timingLatch and FF timingLatch and FF timing
Goal: Goal: Goal: Goal: You are familiar with static and dynamic You are familiar with static and dynamic You are familiar with static and dynamic You are familiar with static and dynamic latches/latches/latches/latches/FFs FFs FFs FFs as well as with single, double phase as well as with single, double phase as well as with single, double phase as well as with single, double phase clock, clock redistribution, clock skew and PLL clock, clock redistribution, clock skew and PLL clock, clock redistribution, clock skew and PLL clock, clock redistribution, clock skew and PLL clocking techniques.clocking techniques.clocking techniques.clocking techniques.
MicroLab, VLSI-10 (2/23)
JMM v1.4
Sequential LogicSequential LogicSequential LogicSequential LogicUse #1:Use #1:Use #1:Use #1: Get better utilization from Get better utilization from Get better utilization from Get better utilization from idle combinational logic blocks. idle combinational logic blocks. idle combinational logic blocks. idle combinational logic blocks. PipelinePipelinePipelinePipeline the system so that new the system so that new the system so that new the system so that new computations start before the old ones computations start before the old ones computations start before the old ones computations start before the old ones complete. Add registers to keep complete. Add registers to keep complete. Add registers to keep complete. Add registers to keep computations separate.computations separate.computations separate.computations separate.
Use #2:Use #2:Use #2:Use #2: Convert parallel operations Convert parallel operations Convert parallel operations Convert parallel operations to a sequence of (faster, smaller) to a sequence of (faster, smaller) to a sequence of (faster, smaller) to a sequence of (faster, smaller) serial operationsserial operationsserial operationsserial operations....
8888AAAA
BBBBCCCC
8888
8888
AAAA
BBBB
CCCC
1111
8888
1111
Use #3:Use #3:Use #3:Use #3: Need to Need to Need to Need to process aprocess aprocess aprocess asequence of inputssequence of inputssequence of inputssequence of inputs and want to and want to and want to and want to reuse the same hardware (finite reuse the same hardware (finite reuse the same hardware (finite reuse the same hardware (finite state machine).state machine).state machine).state machine).
++++
xxxx
8888
MicroLab, VLSI-10 (3/23)
JMM v1.4
Latches and FlipLatches and FlipLatches and FlipLatches and Flip----FlopsFlopsFlopsFlops
A A A A staticstaticstaticstatic latch will hold data while G is inactive, however long latch will hold data while G is inactive, however long latch will hold data while G is inactive, however long latch will hold data while G is inactive, however long that may be. A that may be. A that may be. A that may be. A dynamicdynamicdynamicdynamic latch will hold data while G is latch will hold data while G is latch will hold data while G is latch will hold data while G is inactive, but only “for a while”, after which the saved value inactive, but only “for a while”, after which the saved value inactive, but only “for a while”, after which the saved value inactive, but only “for a while”, after which the saved value may decay.may decay.may decay.may decay.
Do static latches dissipate static power?Do static latches dissipate static power?Do static latches dissipate static power?Do static latches dissipate static power?How long is “for a while”?How long is “for a while”?How long is “for a while”?How long is “for a while”?Which one should I use?Which one should I use?Which one should I use?Which one should I use?
Do I have toDo I have toDo I have toDo I have tocheck ALL thesecheck ALL thesecheck ALL thesecheck ALL theseconstraints?constraints?constraints?constraints?
= hold time= hold time= hold time= hold time= = = = setupsetupsetupsetup timetimetimetime= min delay from invalid input to invalid output= min delay from invalid input to invalid output= min delay from invalid input to invalid output= min delay from invalid input to invalid output= max delay from valid input to valid output = max delay from valid input to valid output = max delay from valid input to valid output = max delay from valid input to valid output = delay for combinatorial logic from input to output= delay for combinatorial logic from input to output= delay for combinatorial logic from input to output= delay for combinatorial logic from input to output= delay for memory element from G to Q= delay for memory element from G to Q= delay for memory element from G to Q= delay for memory element from G to Q
= low period of clock cycle= low period of clock cycle= low period of clock cycle= low period of clock cycle
tttthhhh
ttttllll
ttttc0c0c0c0
HHHH SSSSSSSSHHHH
ttttqqqq
ttttssss
ttttnnnn
GGGG
DDDD QQQQ
GGGG
DDDD QQQQ
GGGG
DDDD QQQQ
CLKCLKCLKCLK
CLCLCLCLaaaa CLCLCLCLbbbb
latch alatch alatch alatch a latch blatch blatch blatch b
Questions for latchQuestions for latchQuestions for latchQuestions for latch----based designs:based designs:based designs:based designs:how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic delay)?delay)?delay)?delay)?
ttttxlaxlaxlaxla + + + + ttttxlbxlbxlbxlb < < < < ttttcccc ---- 2(2(2(2(ttttssss + + + + ttttxqxqxqxq))))what is the maximal clock frequencywhat is the maximal clock frequencywhat is the maximal clock frequencywhat is the maximal clock frequency
does it help to guarantee a minimum does it help to guarantee a minimum does it help to guarantee a minimum does it help to guarantee a minimum ttttnnnn, for example, by requiring , for example, by requiring , for example, by requiring , for example, by requiring a minimum number of gates in each cloud?a minimum number of gates in each cloud?a minimum number of gates in each cloud?a minimum number of gates in each cloud?Suppose the maximum clock skew is Suppose the maximum clock skew is Suppose the maximum clock skew is Suppose the maximum clock skew is ttttSKEWSKEWSKEWSKEW. How does that affect . How does that affect . How does that affect . How does that affect the equations above? Clock skew measures the difference in the equations above? Clock skew measures the difference in the equations above? Clock skew measures the difference in the equations above? Clock skew measures the difference in arrival of CLK at two cascaded latches (not necessarily any two arrival of CLK at two cascaded latches (not necessarily any two arrival of CLK at two cascaded latches (not necessarily any two arrival of CLK at two cascaded latches (not necessarily any two latches!).latches!).latches!).latches!).
Basic idea:Basic idea:Basic idea:Basic idea: Want storage node toWant storage node toWant storage node toWant storage node tobe isolated from whatever be isolated from whatever be isolated from whatever be isolated from whatever user does to Q.user does to Q.user does to Q.user does to Q.
Would like fast CLKWould like fast CLKWould like fast CLKWould like fast CLK----totototo----Q,Q,Q,Q,small small small small setupsetupsetupsetup and zero holdand zero holdand zero holdand zero holdtimes.times.times.times.
Need gain aroundNeed gain aroundNeed gain aroundNeed gain aroundthis loop to makethis loop to makethis loop to makethis loop to makelatch static.latch static.latch static.latch static.
Should we buffer CLKShould we buffer CLKShould we buffer CLKShould we buffer CLK0, 1 or 2 times?0, 1 or 2 times?0, 1 or 2 times?0, 1 or 2 times?
Oops… feedback notOops… feedback notOops… feedback notOops… feedback notisolated from Q. Couldisolated from Q. Couldisolated from Q. Couldisolated from Q. Couldadd additionaladd additionaladd additionaladd additionaloutput inverters...output inverters...output inverters...output inverters...
Good! Input goesGood! Input goesGood! Input goesGood! Input goesonly to only to only to only to fetfetfetfet gatesgatesgatesgates
CLKNCLKNCLKNCLKN
CLKCLKCLKCLK
DDDD
MicroLab, VLSI-10 (7/23)
JMM v1.4
Latch TimingLatch TimingLatch TimingLatch Timing
setupsetupsetupsetup time = how long D input has to be stable time = how long D input has to be stable time = how long D input has to be stable time = how long D input has to be stable beforebeforebeforebefore CLK transition.CLK transition.CLK transition.CLK transition.hold time = how long D input has to be stable hold time = how long D input has to be stable hold time = how long D input has to be stable hold time = how long D input has to be stable afterafterafterafter CLK transition.CLK transition.CLK transition.CLK transition.
DDDD
CLKCLKCLKCLK
QQQQ
1111 2222
So, what node should we use to measureSo, what node should we use to measureSo, what node should we use to measureSo, what node should we use to measuresetupsetupsetupsetup and hold times? And what should we measure?and hold times? And what should we measure?and hold times? And what should we measure?and hold times? And what should we measure?
Other time of interest: CLKOther time of interest: CLKOther time of interest: CLKOther time of interest: CLK----totototo----QQQQ
Suppose in the interest of speed we wereSuppose in the interest of speed we wereSuppose in the interest of speed we wereSuppose in the interest of speed we werewilling to give up the “static guarantee”willing to give up the “static guarantee”willing to give up the “static guarantee”willing to give up the “static guarantee”and take our chances with dynamic latches,and take our chances with dynamic latches,and take our chances with dynamic latches,and take our chances with dynamic latches,i.e., remove feedback path...i.e., remove feedback path...i.e., remove feedback path...i.e., remove feedback path...
Can we do without the CLK inverter too?Can we do without the CLK inverter too?Can we do without the CLK inverter too?Can we do without the CLK inverter too?DEC did without on 21064 but put in back in for 21164DEC did without on 21064 but put in back in for 21164DEC did without on 21064 but put in back in for 21164DEC did without on 21064 but put in back in for 21164
DDDD
CLKCLKCLKCLK
QQQQDDDD
CLKCLKCLKCLK
QQQQ
CLKNCLKNCLKNCLKN
Delete the PFET driven by CLKN and then addDelete the PFET driven by CLKN and then addDelete the PFET driven by CLKN and then addDelete the PFET driven by CLKN and then addNFET driven by CLK in Q’s NFET driven by CLK in Q’s NFET driven by CLK in Q’s NFET driven by CLK in Q’s pulldownpulldownpulldownpulldown path topath topath topath tohandle what happens when D goes from 1 to 0.handle what happens when D goes from 1 to 0.handle what happens when D goes from 1 to 0.handle what happens when D goes from 1 to 0.
local or globallocal or globallocal or globallocal or globalclock inverter?clock inverter?clock inverter?clock inverter?
Eliminate whenEliminate whenEliminate whenEliminate whenQ Q Q Q fanoutfanoutfanoutfanout is small (1)is small (1)is small (1)is small (1)
MicroLab, VLSI-10 (9/23)
JMM v1.4
FlipFlipFlipFlip----flops (registers)flops (registers)flops (registers)flops (registers)Using alternating positive and negative dynamic latches with Using alternating positive and negative dynamic latches with Using alternating positive and negative dynamic latches with Using alternating positive and negative dynamic latches with a single clock gives great speed and small area, but…a single clock gives great speed and small area, but…a single clock gives great speed and small area, but…a single clock gives great speed and small area, but…
lots of worries about clock skewlots of worries about clock skewlots of worries about clock skewlots of worries about clock skewmust balance logic delays to minimize wastagemust balance logic delays to minimize wastagemust balance logic delays to minimize wastagemust balance logic delays to minimize wastageneed latch size checks (check optimisations!)need latch size checks (check optimisations!)need latch size checks (check optimisations!)need latch size checks (check optimisations!)
What about those of us who don’t have buildings full of What about those of us who don’t have buildings full of What about those of us who don’t have buildings full of What about those of us who don’t have buildings full of engineers to sweat the details? Use engineers to sweat the details? Use engineers to sweat the details? Use engineers to sweat the details? Use DDDD----flipflipflipflip----flopsflopsflopsflops and and and and address all the problems once!address all the problems once!address all the problems once!address all the problems once!
Use “jamb” latches to lighten CLK load:Use “jamb” latches to lighten CLK load:Use “jamb” latches to lighten CLK load:Use “jamb” latches to lighten CLK load:
DDDD
CLKCLKCLKCLK
QQQQ
“Weak” feedback inverters“Weak” feedback inverters“Weak” feedback inverters“Weak” feedback inverters(long n and p) get overridden(long n and p) get overridden(long n and p) get overridden(long n and p) get overridden
Questions for registerQuestions for registerQuestions for registerQuestions for register----based designs:based designs:based designs:based designs:how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic how much time for useful work (i.e. for combinational logic delay)?delay)?delay)?delay)?does it help to guarantee a minimum does it help to guarantee a minimum does it help to guarantee a minimum does it help to guarantee a minimum ttttnnnn? How about designing ? How about designing ? How about designing ? How about designing registers so thatregisters so thatregisters so thatregisters so that
ttttxqxqxqxq > > > > tttthhhh????SupSupSupSuppppposeoseoseose the maximum clock skew is the maximum clock skew is the maximum clock skew is the maximum clock skew is ttttSKEWSKEWSKEWSKEW. How does that affect . How does that affect . How does that affect . How does that affect the equations above?the equations above?the equations above?the equations above?
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQCLCLCLCL
MicroLab, VLSI-10 (12/23)
JMM v1.4
Dynamic FlipDynamic FlipDynamic FlipDynamic Flip----FlopsFlopsFlopsFlopsI’ll have the I’ll have the I’ll have the I’ll have the Christer SvenssonChrister SvenssonChrister SvenssonChrister Svenssonspecial please!special please!special please!special please!
DDDD
CLKCLKCLKCLK QNQNQNQN
1111
2222
CLK is low:CLK is low:CLK is low:CLK is low:node 1 follows not(D)node 1 follows not(D)node 1 follows not(D)node 1 follows not(D)node 2 pulled upnode 2 pulled upnode 2 pulled upnode 2 pulled upQN is “floating” with it’s old valueQN is “floating” with it’s old valueQN is “floating” with it’s old valueQN is “floating” with it’s old value
CLK is highCLK is highCLK is highCLK is high::::node 2 = “0” if node 1 = “1”,node 2 = “0” if node 1 = “1”,node 2 = “0” if node 1 = “1”,node 2 = “0” if node 1 = “1”,
otherwise it stays “1”otherwise it stays “1”otherwise it stays “1”otherwise it stays “1”node 2 = not(node 1) shortly after node 2 = not(node 1) shortly after node 2 = not(node 1) shortly after node 2 = not(node 1) shortly after CLKCLKCLKCLK
QN = not(node 2) QN = not(node 2) QN = not(node 2) QN = not(node 2) stable soon after stable soon after stable soon after stable soon after CLKCLKCLKCLKnode 1 can be pulled down if D goes to “0” (capacitive node 1 can be pulled down if D goes to “0” (capacitive node 1 can be pulled down if D goes to “0” (capacitive node 1 can be pulled down if D goes to “0” (capacitive
coupling), but node 2 won’t change!coupling), but node 2 won’t change!coupling), but node 2 won’t change!coupling), but node 2 won’t change!
MicroLab, VLSI-10 (13/23)
JMM v1.4
SingleSingleSingleSingle----Phase Clocked SystemsPhase Clocked SystemsPhase Clocked SystemsPhase Clocked Systems
RTL #1:RTL #1:RTL #1:RTL #1:
GGGG
DDDD QQQQ
GGGG
DDDD QQQQ
GGGG
DDDD QQQQ
CLKCLKCLKCLK
latch #2:latch #2:latch #2:latch #2:
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
Simplest clocking methodology is to use a single clock in conjunSimplest clocking methodology is to use a single clock in conjunSimplest clocking methodology is to use a single clock in conjunSimplest clocking methodology is to use a single clock in conjunction ction ction ction with a register. Clocks are generated with global clock buffers.with a register. Clocks are generated with global clock buffers.with a register. Clocks are generated with global clock buffers.with a register. Clocks are generated with global clock buffers.CLK and CLK are generated locally.CLK and CLK are generated locally.CLK and CLK are generated locally.CLK and CLK are generated locally.
clkclkclkclk----inininin
buffers necessarybuffers necessarybuffers necessarybuffers necessaryfor large loadsfor large loadsfor large loadsfor large loads
clkclkclkclk
clkclkclkclk
MicroLab, VLSI-10 (14/23)
JMM v1.4
Clock SkewClock SkewClock SkewClock Skew
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
delaydelaydelaydelay delaydelaydelaydelay
if a clock net is heavily loaded, there might be a race if a clock net is heavily loaded, there might be a race if a clock net is heavily loaded, there might be a race if a clock net is heavily loaded, there might be a race between clock and data between clock and data between clock and data between clock and data ----> clock skew> clock skew> clock skew> clock skewspecial attention has be made by designing the clock special attention has be made by designing the clock special attention has be made by designing the clock special attention has be made by designing the clock tree. CAD tools are able to design balanced clock trees.tree. CAD tools are able to design balanced clock trees.tree. CAD tools are able to design balanced clock trees.tree. CAD tools are able to design balanced clock trees.two methods to avoid clock skew:two methods to avoid clock skew:two methods to avoid clock skew:two methods to avoid clock skew:
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
delaydelaydelaydelay
clkclkclkclk
DDDD QQQQ
latchlatchlatchlatch
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
delaydelaydelaydelay
clkclkclkclk
DDDD QQQQ
MicroLab, VLSI-10 (15/23)
JMM v1.4
TwoTwoTwoTwo----Phase Clocked SystemsPhase Clocked SystemsPhase Clocked SystemsPhase Clocked Systems (latch)(latch)(latch)(latch)
a problem in single phase clocked systems is the a problem in single phase clocked systems is the a problem in single phase clocked systems is the a problem in single phase clocked systems is the generation ageneration ageneration ageneration annnnd distribution of nearly perfect overlapping d distribution of nearly perfect overlapping d distribution of nearly perfect overlapping d distribution of nearly perfect overlapping clocks. clocks. clocks. clocks. in twoin twoin twoin two----phase clocked systems this is solved by nonphase clocked systems this is solved by nonphase clocked systems this is solved by nonphase clocked systems this is solved by non----overlapping clocksoverlapping clocksoverlapping clocksoverlapping clocksnonnonnonnon----overlapping clocks can be generated with latch overlapping clocks can be generated with latch overlapping clocks can be generated with latch overlapping clocks can be generated with latch structuresstructuresstructuresstructures
clkclkclkclk phi1phi1phi1phi1
phi2phi2phi2phi2
1≥≥≥≥
1≥≥≥≥
MicroLab, VLSI-10 (16/23)
JMM v1.4
TwoTwoTwoTwo----Phase Clocked SystemsPhase Clocked SystemsPhase Clocked SystemsPhase Clocked Systems (FF)(FF)(FF)(FF)
CLKCLKCLKCLK“non“non“non“non----overlappingoverlappingoverlappingoverlappingtwo two two two edgeedgeedgeedge clocks”clocks”clocks”clocks”
in properly designed twoin properly designed twoin properly designed twoin properly designed two----edge clocked systems clock edge clocked systems clock edge clocked systems clock edge clocked systems clock skew problems are drastically reduced skew problems are drastically reduced skew problems are drastically reduced skew problems are drastically reduced Disadvantage: 50% speed reductionDisadvantage: 50% speed reductionDisadvantage: 50% speed reductionDisadvantage: 50% speed reductiontypical application: FSM on rising edge, datatypical application: FSM on rising edge, datatypical application: FSM on rising edge, datatypical application: FSM on rising edge, data----path on path on path on path on falling edgefalling edgefalling edgefalling edgedesigns with several designs with several designs with several designs with several FSMsFSMsFSMsFSMs and dataand dataand dataand data----paths need thorough paths need thorough paths need thorough paths need thorough designdesigndesigndesign
CLKCLKCLKCLK
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
MicroLab, VLSI-10 (17/23)
JMM v1.4
Clock DistributionClock DistributionClock DistributionClock DistributionTwo main techniques for clock distribution exist:Two main techniques for clock distribution exist:Two main techniques for clock distribution exist:Two main techniques for clock distribution exist:
a single large buffer (see Alpha processor)a single large buffer (see Alpha processor)a single large buffer (see Alpha processor)a single large buffer (see Alpha processor)a distributed clock tree approacha distributed clock tree approacha distributed clock tree approacha distributed clock tree approach
there is no such thing as designthere is no such thing as designthere is no such thing as designthere is no such thing as design----free clocking free clocking free clocking free clocking strategy in today’s highstrategy in today’s highstrategy in today’s highstrategy in today’s high----performance processesperformance processesperformance processesperformance processesclock buffers should be surrounded by power pads clock buffers should be surrounded by power pads clock buffers should be surrounded by power pads clock buffers should be surrounded by power pads due to its large power consumptiondue to its large power consumptiondue to its large power consumptiondue to its large power consumption
delays have delays have delays have delays have to matchto matchto matchto matchbetweenbetweenbetweenbetweenstagesstagesstagesstages
nnnn----bit bit bit bit datapathdatapathdatapathdatapath
clkclkclkclk
nnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapathnnnn----bit bit bit bit datapathdatapathdatapathdatapath
Phase locked loops (PLL) are used to generate Phase locked loops (PLL) are used to generate Phase locked loops (PLL) are used to generate Phase locked loops (PLL) are used to generate internal clocks on chips for two main reasons:internal clocks on chips for two main reasons:internal clocks on chips for two main reasons:internal clocks on chips for two main reasons:to synchronize the internal clock of a chip with an to synchronize the internal clock of a chip with an to synchronize the internal clock of a chip with an to synchronize the internal clock of a chip with an external clockexternal clockexternal clockexternal clockto operate the internal clock at a higher rate than to operate the internal clock at a higher rate than to operate the internal clock at a higher rate than to operate the internal clock at a higher rate than the external clock inputthe external clock inputthe external clock inputthe external clock input
The phase detector produces a sequence of up/down The phase detector produces a sequence of up/down The phase detector produces a sequence of up/down The phase detector produces a sequence of up/down pulses, which are used to switch a charge pump.pulses, which are used to switch a charge pump.pulses, which are used to switch a charge pump.pulses, which are used to switch a charge pump.The charge pump charges/discharges a capacitor The charge pump charges/discharges a capacitor The charge pump charges/discharges a capacitor The charge pump charges/discharges a capacitor with voltage or current pulseswith voltage or current pulseswith voltage or current pulseswith voltage or current pulsesA filter is used to limit the rate of change of the A filter is used to limit the rate of change of the A filter is used to limit the rate of change of the A filter is used to limit the rate of change of the capacitor voltage. The result is a slowly changing capacitor voltage. The result is a slowly changing capacitor voltage. The result is a slowly changing capacitor voltage. The result is a slowly changing voltage that depends on the frequency difference voltage that depends on the frequency difference voltage that depends on the frequency difference voltage that depends on the frequency difference between the PLL and VCO.between the PLL and VCO.between the PLL and VCO.between the PLL and VCO.The VCO increases/decreases its frequency of The VCO increases/decreases its frequency of The VCO increases/decreases its frequency of The VCO increases/decreases its frequency of operation depending on its input operation depending on its input operation depending on its input operation depending on its input voltgaevoltgaevoltgaevoltgae
Static Timing AnalysisStatic Timing AnalysisStatic Timing AnalysisStatic Timing AnalysisDo I have toDo I have toDo I have toDo I have tocheck ALL thecheck ALL thecheck ALL thecheck ALL theconstraints?constraints?constraints?constraints?
Yup, for every pair of connectedYup, for every pair of connectedYup, for every pair of connectedYup, for every pair of connectedregister/latches AND for allregister/latches AND for allregister/latches AND for allregister/latches AND for allpossible data values!possible data values!possible data values!possible data values!
We need a CAD tool: We need a CAD tool: We need a CAD tool: We need a CAD tool: static timing analyser. static timing analyser. static timing analyser. static timing analyser. Here’s how Here’s how Here’s how Here’s how it works:it works:it works:it works:
Step 1: “LevelStep 1: “LevelStep 1: “LevelStep 1: “Level----izeizeizeize” all signal nodes.” all signal nodes.” all signal nodes.” all signal nodes.Start by assigning all register outputs and topStart by assigning all register outputs and topStart by assigning all register outputs and topStart by assigning all register outputs and top----level inputs a level inputs a level inputs a level inputs a level of 0. For all other gates: level of 0. For all other gates: level of 0. For all other gates: level of 0. For all other gates: levellevellevellevelOUTPUTOUTPUTOUTPUTOUTPUT = = = = max(max(max(max(levellevellevellevelINPUTINPUTINPUTINPUT)+1.)+1.)+1.)+1.
Step 2: Compute min/max signal delays.Step 2: Compute min/max signal delays.Step 2: Compute min/max signal delays.Step 2: Compute min/max signal delays.For each successive node level, compute min and max time for For each successive node level, compute min and max time for For each successive node level, compute min and max time for For each successive node level, compute min and max time for all nodes on that level (see next slide for details). This is aall nodes on that level (see next slide for details). This is aall nodes on that level (see next slide for details). This is aall nodes on that level (see next slide for details). This is a““““data independentdata independentdata independentdata independent” computation. Might need case analysis to ” computation. Might need case analysis to ” computation. Might need case analysis to ” computation. Might need case analysis to avoid avoid avoid avoid false pathsfalse pathsfalse pathsfalse paths....
Step 3: Check Step 3: Check Step 3: Check Step 3: Check setupsetupsetupsetup and hold constraintsand hold constraintsand hold constraintsand hold constraintsUse min times of register inputs to check hold time. Use max Use min times of register inputs to check hold time. Use max Use min times of register inputs to check hold time. Use max Use min times of register inputs to check hold time. Use max times and times and times and times and ttttCLKCLKCLKCLK to check to check to check to check setupsetupsetupsetup time or use max time + time or use max time + time or use max time + time or use max time + ttttSETUPSETUPSETUPSETUPto determine min to determine min to determine min to determine min ttttCLKCLKCLKCLK....
MicroLab, VLSI-10 (21/23)
JMM v1.4
Stage Delay ComputationStage Delay ComputationStage Delay ComputationStage Delay ComputationLook at each gate and use knowledge of input timing and rise/falLook at each gate and use knowledge of input timing and rise/falLook at each gate and use knowledge of input timing and rise/falLook at each gate and use knowledge of input timing and rise/fall l l l timing to compute earliest and latest time output could change ftiming to compute earliest and latest time output could change ftiming to compute earliest and latest time output could change ftiming to compute earliest and latest time output could change for or or or both rising and falling output transitions.both rising and falling output transitions.both rising and falling output transitions.both rising and falling output transitions.
ININININ
CLKCLKCLKCLK
CLKNCLKNCLKNCLKN
OUTOUTOUTOUT
CCCCOUTOUTOUTOUT
1111
CCCC1111
ININININ VVVVDDDDDDDD
ININININ OUTOUTOUTOUT
min min min min 1=OV, fast1=OV, fast1=OV, fast1=OV, fastmaxmaxmaxmax 1=V1=V1=V1=VDDDDDDDD, slow, slow, slow, slow
CCCCOUTOUTOUTOUTCCCC2222
ININININ OUTOUTOUTOUT
min min min min 2= V2= V2= V2= VDDDDDDDD , fast, fast, fast, fastmaxmaxmaxmax 2=0V, 2=0V, 2=0V, 2=0V, slowslowslowslow
ININININ GNDGNDGNDGND
2222
Use PenfieldUse PenfieldUse PenfieldUse Penfield----RubensteinRubensteinRubensteinRubenstein model to computemodel to computemodel to computemodel to computettttd,ind,ind,ind,in----outoutoutout = sum(= sum(= sum(= sum(RRRRiiii,,,,CCCCiiii) over all nodes “i” in the stage, where ) over all nodes “i” in the stage, where ) over all nodes “i” in the stage, where ) over all nodes “i” in the stage, where RRRRiiii is is is is total “effective resistance” to power rail and total “effective resistance” to power rail and total “effective resistance” to power rail and total “effective resistance” to power rail and CCCCiiii is nonis nonis nonis non----zero if node zero if node zero if node zero if node capacitor needs to be charged/discharged. Multiply by capacitor needs to be charged/discharged. Multiply by capacitor needs to be charged/discharged. Multiply by capacitor needs to be charged/discharged. Multiply by degradingdegradingdegradingdegradingfactor to account for rise/fall time of input.factor to account for rise/fall time of input.factor to account for rise/fall time of input.factor to account for rise/fall time of input.
Ex vlsi10.1 (difficulty: easy): Ex vlsi10.1 (difficulty: easy): Ex vlsi10.1 (difficulty: easy): Ex vlsi10.1 (difficulty: easy): calculate peak current calculate peak current calculate peak current calculate peak current and power and power and power and power consumption consumption consumption consumption of a 100MHz clock driver of a 100MHz clock driver of a 100MHz clock driver of a 100MHz clock driver with rise and fall times of 1ns driving 30k registers with rise and fall times of 1ns driving 30k registers with rise and fall times of 1ns driving 30k registers with rise and fall times of 1ns driving 30k registers bits at 100fF each with bits at 100fF each with bits at 100fF each with bits at 100fF each with VddVddVddVdd=3.3V=3.3V=3.3V=3.3V
Excuse me… Is there such a thing as unclockedsequential logic?
Wave pipeliningjust assert new inputs to logic after waiting “long enough” toensure that previous values won’t be corrupted. Requires verycareful design of each level of logic to ensure consistent propagation delay along all paths with all possible data values. Hard to do in the face of manufacturing variataions (“fast N, slowP” and vice versa)
Self-timed logicuse dual-rail signaling (i.e., two wires) to encode
reset (not yet evaluated) 00ready with value 0 01ready with value 1 10
and then build handshake logic that startsnext stage when current stage is done and nextstage has completed its previous computationand delivered its values. Dual-rail logic works wellwith precharge-evaluate gates… more on thisin a later lecture.
MicroLab, VLSI-11 (3/9)
JMM/ESA v1.0
Finite State Machines
Draw and check state transition diagram
merge equivalent states
perform state encoding
design logic implementation
MicroLab, VLSI-11 (4/9)
JMM/ESA v1.0
Correct State Diagrams
Arcs leaving a state must be:(1) mutually exclusive
can’t have two choices for a given input value
(2) collectively exhaustiveevery state must specify what happens for each possible input combination. “Nothing happens” means arc back toitself.
S1
S8S3
S5
S7
0/01/0
-/0
-/1
0/0
S2
S9 S4
S6
0/01/0
-/0
1/0
0/0
1/0
1/1 0/0
1/0
1/01/1
in/out
Is this a Mealy or Moore machine?
MicroLab, VLSI-11 (5/9)
JMM/ESA v1.0
Merge Equivalent States
Two states are equivalent if for eachpossible combination of inputs
(1) they have identical outputs(2) they transition to equivalent states
S2 S3 S4 S5S1
0/0
1/1
0/1
0/0 0/1 1/0 1/1
1/1 1/1 0/1
S2
S3
S4
S5
S1 S2 S3 S4
all but last state
all butfirststate
Compatibility table:start by putting “X”in square (Si,Sj) if Siproduces different outputfrom Sj for some input
XX
MicroLab, VLSI-11 (6/9)
JMM/ESA v1.0
S2 S3 S4 S5S1
0/0
1/1
0/1
0/0 0/1 1/0 1/1
1/1 1/1 0/1
S2
S3
S4
S5 XX
S1 S2 S3 S4
Next: for non-X square (Si,Sj) write in pairs of states that have to be equivalent in order for Si and Sj to be equivalent.
Finally: Look at an entry in (Si,Sj). If entry is “Sm,Sn”, and if(Sm,Sn) has an X, put an X in square (Si,Sj). Repeat until no more squares can be X’ed out.
S1,S5
Remaining squares indicate equivalent states.
MicroLab, VLSI-11 (7/9)
JMM/ESA v1.0
Perform State EncodingGiven a minimized symbolic state diagram,assign binary codes to the states. We need to predict the effects of logic minimization and find state encoding the produces smallest logic implementation.
This is hard when number of states is large!
input0101--
currentstateS1S1S2S2S3S4
newstateS1S2S1S3S4S1
output101101
S1=01 S3=10S2=00 S4=11
S1=00 S3=10S2=01 S4=11
0101--
010100001011
010001101101
101101
10--
000-1011
10011101
1101
0101--
000001011011
000100101100
101101
011--
0--00110-1
0001101100
10101
“Q-M”
“Q-M”
MicroLab, VLSI-11 (8/9)
JMM/ESA v1.0
FSM Logic Implementation
PLA
ROM
Multi-levelLogic
“One hot”Registers
“One hot” encoding uses a separate registerfor each possible state: register output is “1”if FSM is in that state. Hence only one stateregister is “hot” at a time. Makes for trivialdecoding of state, simple next state logic.Good for simple FSMs and when no multi-levelsynthesis is available. Often a good choicefor FPGA’s.
MicroLab, VLSI-11 (9/9)
JMM/ESA v1.0
Coming Up...
Next topic…Arithmetic circuits: adders and multipliers.
Readings for next time…Weste: 8.4
MicroLab, VLSI-12 (1/29)
JMM v1.4
VLSI Design IVLSI Design IVLSI Design IVLSI Design IDatapathDatapathDatapathDatapath Operators: Addition and MultiplicationOperators: Addition and MultiplicationOperators: Addition and MultiplicationOperators: Addition and Multiplication
01011+0010110000
Didn’t I learn howDidn’t I learn howDidn’t I learn howDidn’t I learn howto do addition into do addition into do addition into do addition inthe first year?the first year?the first year?the first year?First year courses First year courses First year courses First year courses arent’arent’arent’arent’ what they what they what they what they used to be...used to be...used to be...used to be...
Goal: Goal: Goal: Goal: You know serial and parallel addition and You know serial and parallel addition and You know serial and parallel addition and You know serial and parallel addition and multiplication architecturesmultiplication architecturesmultiplication architecturesmultiplication architectures
Most digital functions can be divided into the Most digital functions can be divided into the Most digital functions can be divided into the Most digital functions can be divided into the following categories:following categories:following categories:following categories:
Why can‘t we just add Why can‘t we just add Why can‘t we just add Why can‘t we just add
MicroLab, VLSI-12 (3/29)
JMM v1.4
Binary AdditionBinary AdditionBinary AdditionBinary AdditionHere’s an example of binary addition asHere’s an example of binary addition asHere’s an example of binary addition asHere’s an example of binary addition asone might do it by “hand”:one might do it by “hand”:one might do it by “hand”:one might do it by “hand”:
01101+0010110010
1111000011111111Carries from previousCarries from previousCarries from previousCarries from previouscolumncolumncolumncolumn
If we use a two’sIf we use a two’sIf we use a two’sIf we use a two’s----complement representationcomplement representationcomplement representationcomplement representationfor signed integers, the same procedure willfor signed integers, the same procedure willfor signed integers, the same procedure willfor signed integers, the same procedure willwork for adding both signed and unsignedwork for adding both signed and unsignedwork for adding both signed and unsignedwork for adding both signed and unsignednumbers.numbers.numbers.numbers.
Besides the sum, one often wants two otherBesides the sum, one often wants two otherBesides the sum, one often wants two otherBesides the sum, one often wants two otherbits of information from an adder:bits of information from an adder:bits of information from an adder:bits of information from an adder:
carrycarrycarrycarry----out:out:out:out: indicates that add in the most significant position indicates that add in the most significant position indicates that add in the most significant position indicates that add in the most significant position produced a carry; used when implementing multiproduced a carry; used when implementing multiproduced a carry; used when implementing multiproduced a carry; used when implementing multi----word arithmetic, word arithmetic, word arithmetic, word arithmetic, e.g, “1 + (e.g, “1 + (e.g, “1 + (e.g, “1 + (----1)”1)”1)”1)”
overflow:overflow:overflow:overflow: indicates that the answer has too many bits to be indicates that the answer has too many bits to be indicates that the answer has too many bits to be indicates that the answer has too many bits to be represented correctly by the result width (2‘s complement), represented correctly by the result width (2‘s complement), represented correctly by the result width (2‘s complement), represented correctly by the result width (2‘s complement), e.g., “(2e.g., “(2e.g., “(2e.g., “(2NNNN----1 1 1 1 ---- 1)+ (21)+ (21)+ (21)+ (2NNNN----1111---- 1)”1)”1)”1)”
)( 11111 −+−⋅−+−⋅−= nbnansnbnaC
111111 −⋅−⋅−+−⋅−⋅−= nsnbnansnbnaV
MicroLab, VLSI-12 (4/29)
JMM v1.4
Adder with “ripple” carry chainAdder with “ripple” carry chainAdder with “ripple” carry chainAdder with “ripple” carry chainTo convert the simple addition procedure to hardware, we’ll To convert the simple addition procedure to hardware, we’ll To convert the simple addition procedure to hardware, we’ll To convert the simple addition procedure to hardware, we’ll need “full adder” module:need “full adder” module:need “full adder” module:need “full adder” module:
CCCCOUTOUTOUTOUT
SSSS
AAAABBBBCCCCININININ
AAAA
00000000000000001111111111111111
BBBB
00000000111111110000000011111111
CCCCININININ
00001111000011110000111100001111
SSSS
00001111111100001111000000001111
CCCCOUTOUTOUTOUT
00000000000011110000111111111111
OneOneOneOne----bit adders are sometimesbit adders are sometimesbit adders are sometimesbit adders are sometimescalled “counters” since theycalled “counters” since theycalled “counters” since theycalled “counters” since theycount the number of 1’s on theircount the number of 1’s on theircount the number of 1’s on theircount the number of 1’s on theirinputs and encode the answerinputs and encode the answerinputs and encode the answerinputs and encode the answeron their outputs. Thus a fullon their outputs. Thus a fullon their outputs. Thus a fullon their outputs. Thus a fulladder is a 3:2 counter.adder is a 3:2 counter.adder is a 3:2 counter.adder is a 3:2 counter.
AAAA0000BBBB0000
AAAA1111BBBB1111
AAAA2222BBBB2222
AAAANNNN----1111BBBBNNNN----1111
............
SSSS0000
SSSS1111
SSSS2222
SSSSNNNN----1111
CCCCININININ
CCCCOUTOUTOUTOUT
Carry “ripples” fromCarry “ripples” fromCarry “ripples” fromCarry “ripples” fromone stage to the nextone stage to the nextone stage to the nextone stage to the next
Faster carry logic (CLA)Faster carry logic (CLA)Faster carry logic (CLA)Faster carry logic (CLA)Let’s see if we can improve the speed byLet’s see if we can improve the speed byLet’s see if we can improve the speed byLet’s see if we can improve the speed byrewriting the equations for Crewriting the equations for Crewriting the equations for Crewriting the equations for COUTOUTOUTOUT::::
CCCCOUTOUTOUTOUT = AB + AC= AB + AC= AB + AC= AB + ACININININ + BC+ BC+ BC+ BCININININ
= AB + (A + B)C= AB + (A + B)C= AB + (A + B)C= AB + (A + B)CININININ
= = = = GGGG + + + + P P P P CCCCININININ where G = AB and P = A + Bwhere G = AB and P = A + Bwhere G = AB and P = A + Bwhere G = AB and P = A + B
For adding two NFor adding two NFor adding two NFor adding two N----bit numbers:bit numbers:bit numbers:bit numbers:CCCCNNNN = G= G= G= GNNNN + P+ P+ P+ PNNNNCCCCNNNN----1111
= G= G= G= GNNNN + P+ P+ P+ PN N N N GGGGNNNN----1111 + P+ P+ P+ PN N N N PPPPNNNN----1111CCCCNNNN----2222
= G= G= G= GNNNN + P+ P+ P+ PN N N N GGGGNNNN----1111 + P+ P+ P+ PN N N N PPPPNNNN----1111GGGGNNNN----2 2 2 2 + … + P+ … + P+ … + P+ … + PN N N N ...P...P...P...P0000CCCCININININ
So So So So if we had (N+1)if we had (N+1)if we had (N+1)if we had (N+1)----input gates and didn’t mind a lot of input gates and didn’t mind a lot of input gates and didn’t mind a lot of input gates and didn’t mind a lot of loading on the P signalsloading on the P signalsloading on the P signalsloading on the P signals, the propagation delay of adder , the propagation delay of adder , the propagation delay of adder , the propagation delay of adder built using this equation for the carries would be (count built using this equation for the carries would be (count built using this equation for the carries would be (count built using this equation for the carries would be (count per fanper fanper fanper fan----in 1 delay unit: ripple carry: 5N delays):in 1 delay unit: ripple carry: 5N delays):in 1 delay unit: ripple carry: 5N delays):in 1 delay unit: ripple carry: 5N delays):
________________________________________________________________________________________________________________________________________________Of course, this is impractical but it does lead to some Of course, this is impractical but it does lead to some Of course, this is impractical but it does lead to some Of course, this is impractical but it does lead to some interesting ideas:interesting ideas:interesting ideas:interesting ideas:
Manchester carry chain (CLA)Manchester carry chain (CLA)Manchester carry chain (CLA)Manchester carry chain (CLA)The plan: first generate carryThe plan: first generate carryThe plan: first generate carryThe plan: first generate carry----in for each adder bit as fast in for each adder bit as fast in for each adder bit as fast in for each adder bit as fast as we can as we can as we can as we can thenthenthenthen compute the sum. Delay still proportional compute the sum. Delay still proportional compute the sum. Delay still proportional compute the sum. Delay still proportional to size of adder, but “constant” is pretty small.to size of adder, but “constant” is pretty small.to size of adder, but “constant” is pretty small.to size of adder, but “constant” is pretty small.
CLKCLKCLKCLK
CLKCLKCLKCLK
GGGGNNNNPPPPNNNN
CCCCNNNNCCCCNNNN----1111
When CLK is low, allWhen CLK is low, allWhen CLK is low, allWhen CLK is low, allC nodes C nodes C nodes C nodes prechargeprechargeprechargeprecharge....
When CLK is high, if GWhen CLK is high, if GWhen CLK is high, if GWhen CLK is high, if GNNNNis high, Cis high, Cis high, Cis high, CNNNN is asserted,is asserted,is asserted,is asserted,i.e., driven low.i.e., driven low.i.e., driven low.i.e., driven low.
To prevent GTo prevent GTo prevent GTo prevent GNNNN from affecting Cfrom affecting Cfrom affecting Cfrom affecting CNNNN----1111, P, P, P, PNNNN must be must be must be must be computed as Acomputed as Acomputed as Acomputed as ANNNN xorxorxorxor BBBBNNNN. But we needed the . But we needed the . But we needed the . But we needed the xorxorxorxoranyway… now Sanyway… now Sanyway… now Sanyway… now SNNNN = P= P= P= PNNNN xnorxnorxnorxnor CCCCNNNN
dynamic Manchester stagedynamic Manchester stagedynamic Manchester stagedynamic Manchester stage
static Manchester stagesstatic Manchester stagesstatic Manchester stagesstatic Manchester stages
The propagate logic in the Manchester carry chainThe propagate logic in the Manchester carry chainThe propagate logic in the Manchester carry chainThe propagate logic in the Manchester carry chainputs a lot of puts a lot of puts a lot of puts a lot of NFETsNFETsNFETsNFETs in series, so when CIN is highin series, so when CIN is highin series, so when CIN is highin series, so when CIN is highthe the the the pulldownpulldownpulldownpulldown path can get long if a lot of the Ppath can get long if a lot of the Ppath can get long if a lot of the Ppath can get long if a lot of the Psignals are true. For most technologies, thesignals are true. For most technologies, thesignals are true. For most technologies, thesignals are true. For most technologies, theperformance of this long performance of this long performance of this long performance of this long pulldownpulldownpulldownpulldown path limitspath limitspath limitspath limitsthe maximum length of the carry chain to aroundthe maximum length of the carry chain to aroundthe maximum length of the carry chain to aroundthe maximum length of the carry chain to aroundfour stages before it needs to split into four stages before it needs to split into four stages before it needs to split into four stages before it needs to split into subchainssubchainssubchainssubchains....
Adding a bypass path that Adding a bypass path that Adding a bypass path that Adding a bypass path that skipsskipsskipsskips over the blockover the blockover the blockover the blockwhen all P signals are true can improve maximum propagation delawhen all P signals are true can improve maximum propagation delawhen all P signals are true can improve maximum propagation delawhen all P signals are true can improve maximum propagation delay y y y when multiple Manchester carry chains are used in series.when multiple Manchester carry chains are used in series.when multiple Manchester carry chains are used in series.when multiple Manchester carry chains are used in series.
link in Manchesterlink in Manchesterlink in Manchesterlink in Manchestercarry chaincarry chaincarry chaincarry chain
CCCCinininin
CCCCinininin
MicroLab, VLSI-12 (8/29)
JMM v1.4
Hierarchical carryHierarchical carryHierarchical carryHierarchical carry----lookaheadlookaheadlookaheadlookahead addersaddersaddersaddersThe linear growth of adder carryThe linear growth of adder carryThe linear growth of adder carryThe linear growth of adder carry----delay with size of the input word maydelay with size of the input word maydelay with size of the input word maydelay with size of the input word maybe improved by calculating the carries to each stage in parallelbe improved by calculating the carries to each stage in parallelbe improved by calculating the carries to each stage in parallelbe improved by calculating the carries to each stage in parallel::::
GGGGIK IK IK IK = G= G= G= GJ+1,KJ+1,KJ+1,KJ+1,K + P+ P+ P+ PJ+1,K J+1,K J+1,K J+1,K GGGGIJIJIJIJ
PPPPIKIKIKIK = P= P= P= PIJ IJ IJ IJ PPPPJ+1,K J+1,K J+1,K J+1,K where I <= J and J+1 <=K where I <= J and J+1 <=K where I <= J and J+1 <=K where I <= J and J+1 <=K
“generate a carry from bits I thru“generate a carry from bits I thru“generate a carry from bits I thru“generate a carry from bits I thruK if it is generated in the highK if it is generated in the highK if it is generated in the highK if it is generated in the high----orderorderorderorder(J+1,K) part of the block or if it is(J+1,K) part of the block or if it is(J+1,K) part of the block or if it is(J+1,K) part of the block or if it is
generated in the lowgenerated in the lowgenerated in the lowgenerated in the low----order (I,J) partorder (I,J) partorder (I,J) partorder (I,J) partof the block and then propagatedof the block and then propagatedof the block and then propagatedof the block and then propagatedthru the high part”thru the high part”thru the high part”thru the high part”
CarryCarryCarryCarry----skip addersskip addersskip addersskip addersSince computing PSince computing PSince computing PSince computing PIKIKIKIK is simpler than computing Gis simpler than computing Gis simpler than computing Gis simpler than computing GIKIKIKIK, let’s try just , let’s try just , let’s try just , let’s try just computing Pcomputing Pcomputing Pcomputing PIKIKIKIK and apply the “skip” optimisation from Manchester and apply the “skip” optimisation from Manchester and apply the “skip” optimisation from Manchester and apply the “skip” optimisation from Manchester adders.adders.adders.adders.
SuSuSuSupppppppposeoseoseose it takes 1 time unit for a signal to pass thruit takes 1 time unit for a signal to pass thruit takes 1 time unit for a signal to pass thruit takes 1 time unit for a signal to pass thrutwo logic levels, thentwo logic levels, thentwo logic levels, thentwo logic levels, then
time to ripple thru block of k bits = k time unitstime to ripple thru block of k bits = k time unitstime to ripple thru block of k bits = k time unitstime to ripple thru block of k bits = k time unitstime to skip a block = 1 time unittime to skip a block = 1 time unittime to skip a block = 1 time unittime to skip a block = 1 time unit
Consider a 24Consider a 24Consider a 24Consider a 24----bit carrybit carrybit carrybit carry----skip adder organized asskip adder organized asskip adder organized asskip adder organized as6 blocks of four bits each. So the worst case propagation time 6 blocks of four bits each. So the worst case propagation time 6 blocks of four bits each. So the worst case propagation time 6 blocks of four bits each. So the worst case propagation time is is is is
But now reorganize the adder with the least significant 3 bits iBut now reorganize the adder with the least significant 3 bits iBut now reorganize the adder with the least significant 3 bits iBut now reorganize the adder with the least significant 3 bits in the n the n the n the first block, the next 4 bits in the second block, followed by blfirst block, the next 4 bits in the second block, followed by blfirst block, the next 4 bits in the second block, followed by blfirst block, the next 4 bits in the second block, followed by blocks of ocks of ocks of ocks of 5, 5, 4, and 3. Now the worst case propagation time is5, 5, 4, and 3. Now the worst case propagation time is5, 5, 4, and 3. Now the worst case propagation time is5, 5, 4, and 3. Now the worst case propagation time is
Is there a general way to reorganize aIs there a general way to reorganize aIs there a general way to reorganize aIs there a general way to reorganize alogic equation to accommodate a latelogic equation to accommodate a latelogic equation to accommodate a latelogic equation to accommodate a late----arriving input?arriving input?arriving input?arriving input?
Consider the following where XConsider the following where XConsider the following where XConsider the following where X1111 arrives late:arrives late:arrives late:arrives late:
If we want only one gate delay from XIf we want only one gate delay from XIf we want only one gate delay from XIf we want only one gate delay from X1111 totototothe output f, how do we do it?the output f, how do we do it?the output f, how do we do it?the output f, how do we do it?
543121 XXXXXXf ⋅+⋅+⋅=
MicroLab, VLSI-12 (11/29)
JMM v1.4
CarryCarryCarryCarry----select addersselect addersselect addersselect addersBuilding on the idea from the previous slide: perform two Building on the idea from the previous slide: perform two Building on the idea from the previous slide: perform two Building on the idea from the previous slide: perform two additions in parallel, one assuming the carryadditions in parallel, one assuming the carryadditions in parallel, one assuming the carryadditions in parallel, one assuming the carry----in is zero and in is zero and in is zero and in is zero and the other assuming the carrythe other assuming the carrythe other assuming the carrythe other assuming the carry----in is one. When the carryin is one. When the carryin is one. When the carryin is one. When the carry----in in in in is finally known, the correct result is selected from the two is finally known, the correct result is selected from the two is finally known, the correct result is selected from the two is finally known, the correct result is selected from the two precomputedprecomputedprecomputedprecomputed results.results.results.results.
............
0000
1111............
........................
0000
1111............
CINCINCINCIN
Is this a “Is this a “Is this a “Is this a “muxmuxmuxmux”?”?”?”?
If it takes k time units for a block to add kIf it takes k time units for a block to add kIf it takes k time units for a block to add kIf it takes k time units for a block to add k----bit numbers bit numbers bit numbers bit numbers and if it takes one time unit to compute and if it takes one time unit to compute and if it takes one time unit to compute and if it takes one time unit to compute muxmuxmuxmux select from select from select from select from the two carrythe two carrythe two carrythe two carry----out signals, then for optimal operation each out signals, then for optimal operation each out signals, then for optimal operation each out signals, then for optimal operation each block should be one bit wider than the next block, just as block should be one bit wider than the next block, just as block should be one bit wider than the next block, just as block should be one bit wider than the next block, just as in the carryin the carryin the carryin the carry----skip adder.skip adder.skip adder.skip adder.
EvenEvenEvenEven----Odd ArraysOdd ArraysOdd ArraysOdd ArraysAbstract carryAbstract carryAbstract carryAbstract carry----save picture from previous page:save picture from previous page:save picture from previous page:save picture from previous page:
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CPA
CPA
CPA
CPA
MMMM----2222
............
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CSA
CPA
CPA
CPA
CPA
MMMM----4444
............
CSA
CSA
CSA
CSA
2222
Rewire so that first two adders work in parallel.Rewire so that first two adders work in parallel.Rewire so that first two adders work in parallel.Rewire so that first two adders work in parallel.Feed results into third and fourth adders whichFeed results into third and fourth adders whichFeed results into third and fourth adders whichFeed results into third and fourth adders whichalso work in parallel, etc.also work in parallel, etc.also work in parallel, etc.also work in parallel, etc.
prop delay _____________ area _____prop delay _____________ area _____prop delay _____________ area _____prop delay _____________ area _____
EvenEvenEvenEven and and and and oddoddoddodd streams pass through half thestreams pass through half thestreams pass through half thestreams pass through half theadders so even/odd design runs at almost twiceadders so even/odd design runs at almost twiceadders so even/odd design runs at almost twiceadders so even/odd design runs at almost twicethe speed of simple CSA implementation.the speed of simple CSA implementation.the speed of simple CSA implementation.the speed of simple CSA implementation.
Wallace trees give asymptotically better behaviour than the earlWallace trees give asymptotically better behaviour than the earlWallace trees give asymptotically better behaviour than the earlWallace trees give asymptotically better behaviour than the earlier ier ier ier O(M) schemes, but they do not have a regular layout. Other O(M) schemes, but they do not have a regular layout. Other O(M) schemes, but they do not have a regular layout. Other O(M) schemes, but they do not have a regular layout. Other O(log(M)) schemes, e.g., O(log(M)) schemes, e.g., O(log(M)) schemes, e.g., O(log(M)) schemes, e.g., binarybinarybinarybinary----tree multiplierstree multiplierstree multiplierstree multipliers using signed using signed using signed using signed digit representations, have better layout properties but at a codigit representations, have better layout properties but at a codigit representations, have better layout properties but at a codigit representations, have better layout properties but at a cost of st of st of st of more complicated adder cells.more complicated adder cells.more complicated adder cells.more complicated adder cells.
We have been using fullWe have been using fullWe have been using fullWe have been using full----addersaddersaddersaddersor 3:2 counters in our arrayor 3:2 counters in our arrayor 3:2 counters in our arrayor 3:2 counters in our arrayadders. Higher adders. Higher adders. Higher adders. Higher faninfaninfaninfanin----counterscounterscounterscounterscan be used to further reducecan be used to further reducecan be used to further reducecan be used to further reducedelays for large M, e.g., delays for large M, e.g., delays for large M, e.g., delays for large M, e.g., WesteWesteWesteWesteshows a 5:3 counter in Fig. 8.41.shows a 5:3 counter in Fig. 8.41.shows a 5:3 counter in Fig. 8.41.shows a 5:3 counter in Fig. 8.41.
• bitbitbitbit----serial adders are very slow, have a high data serial adders are very slow, have a high data serial adders are very slow, have a high data serial adders are very slow, have a high data latency, but are extremely compactlatency, but are extremely compactlatency, but are extremely compactlatency, but are extremely compact
• applications are signal processingapplications are signal processingapplications are signal processingapplications are signal processing
CSA Adder (pipelining)CSA Adder (pipelining)CSA Adder (pipelining)CSA Adder (pipelining)• pipelining adders are extremely fast, but lack of pipelining adders are extremely fast, but lack of pipelining adders are extremely fast, but lack of pipelining adders are extremely fast, but lack of
high data latency (CSA structure of slide #13)high data latency (CSA structure of slide #13)high data latency (CSA structure of slide #13)high data latency (CSA structure of slide #13)
CPA Adder (pipelining)CPA Adder (pipelining)CPA Adder (pipelining)CPA Adder (pipelining)• the CPA structure on slide #13 can also be used in the CPA structure on slide #13 can also be used in the CPA structure on slide #13 can also be used in the CPA structure on slide #13 can also be used in
a pipeline structure. Useful in signal processing a pipeline structure. Useful in signal processing a pipeline structure. Useful in signal processing a pipeline structure. Useful in signal processing applications.applications.applications.applications.
Suppose we want to multiply two numbers:Suppose we want to multiply two numbers:Suppose we want to multiply two numbers:Suppose we want to multiply two numbers:
A = AA = AA = AA = ANNNN----1111, A, A, A, ANNNN----2222, …, A, …, A, …, A, …, A1111, A, A, A, A0000B = BB = BB = BB = BMMMM----1111, B, B, B, BMMMM----2222, …, B, …, B, …, B, …, B1111, B, B, B, B0000
to produce a (N*M)to produce a (N*M)to produce a (N*M)to produce a (N*M)----bit result. We can write the product bit result. We can write the product bit result. We can write the product bit result. We can write the product asasasas
Note that BNote that BNote that BNote that BKKKK*A can be accomplished with N AND gates *A can be accomplished with N AND gates *A can be accomplished with N AND gates *A can be accomplished with N AND gates since Bsince Bsince Bsince BKKKK = 0 or 1. The scaling by powers of two is a = 0 or 1. The scaling by powers of two is a = 0 or 1. The scaling by powers of two is a = 0 or 1. The scaling by powers of two is a simple shift.simple shift.simple shift.simple shift.
Thus multiplication of an NThus multiplication of an NThus multiplication of an NThus multiplication of an N----bit number by an Mbit number by an Mbit number by an Mbit number by an M----bit bit bit bit number boils down to the number boils down to the number boils down to the number boils down to the addition of M Naddition of M Naddition of M Naddition of M N----bit partial bit partial bit partial bit partial productsproductsproductsproducts each of which is formed by a simple Boolean each of which is formed by a simple Boolean each of which is formed by a simple Boolean each of which is formed by a simple Boolean operation. Any of the techniques from the previous slides operation. Any of the techniques from the previous slides operation. Any of the techniques from the previous slides operation. Any of the techniques from the previous slides can be used to accomplish the required additions.can be used to accomplish the required additions.can be used to accomplish the required additions.can be used to accomplish the required additions.
multipliermultipliermultipliermultiplier
multiplicandmultiplicandmultiplicandmultiplicand
MicroLab, VLSI-12 (20/29)
JMM v1.4
Array multipliersArray multipliersArray multipliersArray multipliersExample 3x3 array multiplierExample 3x3 array multiplierExample 3x3 array multiplierExample 3x3 array multiplierusing using using using CSAsCSAsCSAsCSAs to sum partialto sum partialto sum partialto sum partialproducts:products:products:products:
Actual layout is usually squished flat:Actual layout is usually squished flat:Actual layout is usually squished flat:Actual layout is usually squished flat:
Array multipliers are nice, but we get one column of adders (whiArray multipliers are nice, but we get one column of adders (whiArray multipliers are nice, but we get one column of adders (whiArray multipliers are nice, but we get one column of adders (which are ch are ch are ch are big/slow) for each partial product, i.e., one column for each bibig/slow) for each partial product, i.e., one column for each bibig/slow) for each partial product, i.e., one column for each bibig/slow) for each partial product, i.e., one column for each bit of the t of the t of the t of the multiplier. If we could use, say, 2 bits of the multiplier in gmultiplier. If we could use, say, 2 bits of the multiplier in gmultiplier. If we could use, say, 2 bits of the multiplier in gmultiplier. If we could use, say, 2 bits of the multiplier in generating enerating enerating enerating each partial product we would each partial product we would each partial product we would each partial product we would halve the number of columns and halve the number of columns and halve the number of columns and halve the number of columns and doubledoubledoubledoublethe speed of the multiplierthe speed of the multiplierthe speed of the multiplierthe speed of the multiplier!!!!
Let’s rewrite our equation for A*B:Let’s rewrite our equation for A*B:Let’s rewrite our equation for A*B:Let’s rewrite our equation for A*B:
This looks the same as before except we have half as many partiaThis looks the same as before except we have half as many partiaThis looks the same as before except we have half as many partiaThis looks the same as before except we have half as many partial l l l products to sum. Generating each partial product is now more products to sum. Generating each partial product is now more products to sum. Generating each partial product is now more products to sum. Generating each partial product is now more complicated since Bcomplicated since Bcomplicated since Bcomplicated since BK+1,KK+1,KK+1,KK+1,K can now be 0, 1, 2 or 3. The only can now be 0, 1, 2 or 3. The only can now be 0, 1, 2 or 3. The only can now be 0, 1, 2 or 3. The only troublesome value here is 3 since that would seem to require mortroublesome value here is 3 since that would seem to require mortroublesome value here is 3 since that would seem to require mortroublesome value here is 3 since that would seem to require more e e e adder inputs than we have (3*A = A + 2*A).adder inputs than we have (3*A = A + 2*A).adder inputs than we have (3*A = A + 2*A).adder inputs than we have (3*A = A + 2*A).
But… But… But… But… we can also write 3*A = 4*A we can also write 3*A = 4*A we can also write 3*A = 4*A we can also write 3*A = 4*A ---- A. We’ll do the A. We’ll do the A. We’ll do the A. We’ll do the ----A in this partial A in this partial A in this partial A in this partial product stage and signal the next stage that it needs to add 4*Aproduct stage and signal the next stage that it needs to add 4*Aproduct stage and signal the next stage that it needs to add 4*Aproduct stage and signal the next stage that it needs to add 4*A. To . To . To . To keep the signalling simple we’ll also rewrite 2*A = 4*A keep the signalling simple we’ll also rewrite 2*A = 4*A keep the signalling simple we’ll also rewrite 2*A = 4*A keep the signalling simple we’ll also rewrite 2*A = 4*A ---- 2*A2*A2*A2*A
Profs go crazy nowadays, why can‘t he just multiply as everybody does it
add 2*Aadd 2*Aadd 2*Aadd 2*Asub 2*Asub 2*Asub 2*Asub 2*Asub Asub Asub Asub Asub Asub Asub Asub Aadd 0add 0add 0add 0
NNNN
--------000000000000111111111111--------
x1x1x1x1
00001111111100000000111111110000
x2x2x2x2
00000000000011111111000000000000
AiAiAiAix1x1x1x1
Ai<<1Ai<<1Ai<<1Ai<<1x2x2x2x2
NNNN
PPiPPiPPiPPi
carrycarrycarrycarry----inininin
&&&&
&&&&>=1>=1>=1>=1
=1=1=1=1
NotNotNotNot cheaper than an ADD but all recodes cheaper than an ADD but all recodes cheaper than an ADD but all recodes cheaper than an ADD but all recodes can be done in parallel so we only pay can be done in parallel so we only pay can be done in parallel so we only pay can be done in parallel so we only pay time penalty once (for first column)!time penalty once (for first column)!time penalty once (for first column)!time penalty once (for first column)!
This multiplier only produces a 32This multiplier only produces a 32This multiplier only produces a 32This multiplier only produces a 32----bit result sobit result sobit result sobit result sotop 16top 16top 16top 16----bits of “rhombus” have been omitted:bits of “rhombus” have been omitted:bits of “rhombus” have been omitted:bits of “rhombus” have been omitted:
Serial MultiplicationSerial MultiplicationSerial MultiplicationSerial Multiplication
• bitbitbitbit----serial multipliers are very compact, but lack of serial multipliers are very compact, but lack of serial multipliers are very compact, but lack of serial multipliers are very compact, but lack of high data latency and are very slowhigh data latency and are very slowhigh data latency and are very slowhigh data latency and are very slow
• simplest form of serial multiplier: successive additionsimplest form of serial multiplier: successive additionsimplest form of serial multiplier: successive additionsimplest form of serial multiplier: successive addition
NNNN----1 bit register1 bit register1 bit register1 bit register
FFFFFFFF
clrclrclrclrclkclkclkclk
clkclkclkclk
coutcoutcoutcout
resultresultresultresultresetresetresetreset
AAAA
&&&&
&&&&BBBB
M+N bit product M+N bit product M+N bit product M+N bit product ----> t> t> t> tdddd=MN time intervals=MN time intervals=MN time intervals=MN time intervals
MicroLab, VLSI-12 (25/29)
JMM v1.4
Serial/parallel and Pipelined Serial/parallel and Pipelined Serial/parallel and Pipelined Serial/parallel and Pipelined MultiplicationMultiplicationMultiplicationMultiplication
• pipelined multiplication: 2 delay elements per cellpipelined multiplication: 2 delay elements per cellpipelined multiplication: 2 delay elements per cellpipelined multiplication: 2 delay elements per cell
YYYYnnnn
&&& &
XXXXjjjj+1+1+1+1XXXXjjjj
PPPPPPPPinininin PPPPPPPPoutoutoutout
• serial/parallel multiplier: very modular structureserial/parallel multiplier: very modular structureserial/parallel multiplier: very modular structureserial/parallel multiplier: very modular structureYYYY1111
&&& &
XXXX0000&&& & &&& &&&& &
YYYY2222 YYYY3333YYYY0000
XXXX1111 0000 0000
PPPP
M+N bit product M+N bit product M+N bit product M+N bit product ----> t> t> t> tdddd=M+N time intervals, but time intervals are larger=M+N time intervals, but time intervals are larger=M+N time intervals, but time intervals are larger=M+N time intervals, but time intervals are larger
MicroLab, VLSI-12 (26/29)
JMM v1.4
ShiftersShiftersShiftersShifters• Shifters are very important for microprocessor Shifters are very important for microprocessor Shifters are very important for microprocessor Shifters are very important for microprocessor
Operation: inputOperation: inputOperation: inputOperation: inputlogical right shift 0,0,0,A(3:0)logical right shift 0,0,0,A(3:0)logical right shift 0,0,0,A(3:0)logical right shift 0,0,0,A(3:0)logical left shift A(3:0),0,0,0logical left shift A(3:0),0,0,0logical left shift A(3:0),0,0,0logical left shift A(3:0),0,0,0right rotate A(2:0),A(3:0)right rotate A(2:0),A(3:0)right rotate A(2:0),A(3:0)right rotate A(2:0),A(3:0)left rotate A(3:0),A(2:0)left rotate A(3:0),A(2:0)left rotate A(3:0),A(2:0)left rotate A(3:0),A(2:0)arithmetic right shift Aarithmetic right shift Aarithmetic right shift Aarithmetic right shift A3333,A,A,A,A3333,A,A,A,A3333,A(3:0),A(3:0),A(3:0),A(3:0)arithmetic left shift A(3:0),Aarithmetic left shift A(3:0),Aarithmetic left shift A(3:0),Aarithmetic left shift A(3:0),A0000,A,A,A,A0000,A,A,A,A0000
MicroLab, VLSI-12 (27/29)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…VLSI fabrication: processing steps, basic VLSI fabrication: processing steps, basic VLSI fabrication: processing steps, basic VLSI fabrication: processing steps, basic structures, selfstructures, selfstructures, selfstructures, self----aligned processes, P and N devices.aligned processes, P and N devices.aligned processes, P and N devices.aligned processes, P and N devices.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WWWWesteesteesteeste: : : :
Sections 8 thru 8.2.1.6 and 8.2.7.3Sections 8 thru 8.2.1.6 and 8.2.7.3Sections 8 thru 8.2.1.6 and 8.2.7.3Sections 8 thru 8.2.1.6 and 8.2.7.38.2.7 thru 8.2.88.2.7 thru 8.2.88.2.7 thru 8.2.88.2.7 thru 8.2.8
Ex vlsi12.1 (difficulty: medium): Ex vlsi12.1 (difficulty: medium): Ex vlsi12.1 (difficulty: medium): Ex vlsi12.1 (difficulty: medium): Develop a 1 bit full Develop a 1 bit full Develop a 1 bit full Develop a 1 bit full adder with not more than 3 adder with not more than 3 adder with not more than 3 adder with not more than 3 fetsfetsfetsfets in series for the in series for the in series for the in series for the not(sum) and not more than 2 not(sum) and not more than 2 not(sum) and not more than 2 not(sum) and not more than 2 fetsfetsfetsfets in series for the in series for the in series for the in series for the not(carry) circuit. The not(carry) signal can be not(carry) circuit. The not(carry) signal can be not(carry) circuit. The not(carry) signal can be not(carry) circuit. The not(carry) signal can be used for the sum circuit.used for the sum circuit.used for the sum circuit.used for the sum circuit.
Result: Notice that the nResult: Notice that the nResult: Notice that the nResult: Notice that the n---- and and and and pfetpfetpfetpfet blocks are blocks are blocks are blocks are identical and not complementary.identical and not complementary.identical and not complementary.identical and not complementary.
Ex vlsi12.2 (difficulty: easy): Ex vlsi12.2 (difficulty: easy): Ex vlsi12.2 (difficulty: easy): Ex vlsi12.2 (difficulty: easy): A 32A 32A 32A 32----bit adder is built as a bit adder is built as a bit adder is built as a bit adder is built as a carrycarrycarrycarry----select adder. Each adder as well as the select adder. Each adder as well as the select adder. Each adder as well as the select adder. Each adder as well as the muxesmuxesmuxesmuxes have have have have one delay unit. Find the optimal structure in respect to one delay unit. Find the optimal structure in respect to one delay unit. Find the optimal structure in respect to one delay unit. Find the optimal structure in respect to speed. speed. speed. speed.
Result: The maximum speed is 9 time units for a structure Result: The maximum speed is 9 time units for a structure Result: The maximum speed is 9 time units for a structure Result: The maximum speed is 9 time units for a structure with stages 4with stages 4with stages 4with stages 4----4444----5555----6666----7777----6 (see 6 (see 6 (see 6 (see WesteWesteWesteWeste pp532)pp532)pp532)pp532)
Ex vlsi12.3 (difficulty: easy): Ex vlsi12.3 (difficulty: easy): Ex vlsi12.3 (difficulty: easy): Ex vlsi12.3 (difficulty: easy): A hierarchical carryA hierarchical carryA hierarchical carryA hierarchical carry----lookaheadlookaheadlookaheadlookahead adder (see slide 8) is given. Show adder (see slide 8) is given. Show adder (see slide 8) is given. Show adder (see slide 8) is given. Show algebraically that Calgebraically that Calgebraically that Calgebraically that C3333=G=G=G=G03030303+ P+ P+ P+ P03 03 03 03 CCCCinininin corresponds to the corresponds to the corresponds to the corresponds to the equation Cequation Cequation Cequation C3333=G=G=G=G3333+P+P+P+P3 3 3 3 GGGG2 2 2 2 +P+P+P+P3 3 3 3 PPPP2 2 2 2 GGGG1 1 1 1 +P+P+P+P3 3 3 3 PPPP2 2 2 2 PPPP1 1 1 1 GGGG0 0 0 0 +P+P+P+P3 3 3 3 PPPP2 2 2 2 PPPP1 1 1 1 PPPP0 0 0 0 CCCCinininin (note that (note that (note that (note that GGGGiiiiiiii= = = = GGGGiiii and and and and PPPPiiiiiiii= P= P= P= Piiii))))
Ex vlsi12.4 (difficulty: easy, time consuming): Ex vlsi12.4 (difficulty: easy, time consuming): Ex vlsi12.4 (difficulty: easy, time consuming): Ex vlsi12.4 (difficulty: easy, time consuming): Design a Design a Design a Design a VHDL code for a 32VHDL code for a 32VHDL code for a 32VHDL code for a 32----bit hierarchical carrybit hierarchical carrybit hierarchical carrybit hierarchical carry----lookaheadlookaheadlookaheadlookaheadadder (see slide 8). If one block has a delay of 1 time adder (see slide 8). If one block has a delay of 1 time adder (see slide 8). If one block has a delay of 1 time adder (see slide 8). If one block has a delay of 1 time unit, what is the overall delay.unit, what is the overall delay.unit, what is the overall delay.unit, what is the overall delay.
Result: The total delay is 9 time unitsResult: The total delay is 9 time unitsResult: The total delay is 9 time unitsResult: The total delay is 9 time unitsEx vlsi12.5 (difficulty: medium): Ex vlsi12.5 (difficulty: medium): Ex vlsi12.5 (difficulty: medium): Ex vlsi12.5 (difficulty: medium): Consider XConsider XConsider XConsider X1111 as a late as a late as a late as a late
arriving input which needs to be speed up. Develop the arriving input which needs to be speed up. Develop the arriving input which needs to be speed up. Develop the arriving input which needs to be speed up. Develop the circuit for the function: circuit for the function: circuit for the function: circuit for the function: 543121 XXXXXXf ⋅+⋅+⋅=
MicroLab, VLSI-13 (1/24)
JMM v1.4
VLSI Systems DesignVLSI Systems DesignVLSI Systems DesignVLSI Systems DesignDesign Project: Practical AspectsDesign Project: Practical AspectsDesign Project: Practical AspectsDesign Project: Practical Aspects
OverviewOverviewOverviewOverviewapplying the “descriptionapplying the “descriptionapplying the “descriptionapplying the “description----synthesis” design synthesis” design synthesis” design synthesis” design method in practicemethod in practicemethod in practicemethod in practice
Goal: Goal: Goal: Goal: You You You You are able to master your own VHDL projectare able to master your own VHDL projectare able to master your own VHDL projectare able to master your own VHDL project.... You You You You have basic notions about HW/SW cohave basic notions about HW/SW cohave basic notions about HW/SW cohave basic notions about HW/SW co----design.design.design.design.
I am a VHDL expert.I am a VHDL expert.I am a VHDL expert.I am a VHDL expert.But how applyingBut how applyingBut how applyingBut how applyingin real live in real live in real live in real live –––– for my MP3 player!for my MP3 player!for my MP3 player!for my MP3 player!
MicroLab, VLSI-13 (2/24)
JMM v1.4
Project GoalProject GoalProject GoalProject GoalGoal: Goal: Goal: Goal: design of adesign of adesign of adesign of annnn electronic system from specification electronic system from specification electronic system from specification electronic system from specification down to ASIC/FPGAdown to ASIC/FPGAdown to ASIC/FPGAdown to ASIC/FPGAProblem: Problem: Problem: Problem: one of the most difficult tasks in a VLSI project one of the most difficult tasks in a VLSI project one of the most difficult tasks in a VLSI project one of the most difficult tasks in a VLSI project design is to find the starting design pointdesign is to find the starting design pointdesign is to find the starting design pointdesign is to find the starting design pointBasic Steps:Basic Steps:Basic Steps:Basic Steps:in order to proceed in a structured manner, you in order to proceed in a structured manner, you in order to proceed in a structured manner, you in order to proceed in a structured manner, you should perform the following stepsshould perform the following stepsshould perform the following stepsshould perform the following steps
Initial System Design StepsInitial System Design StepsInitial System Design StepsInitial System Design StepsSystem design stepsSystem design stepsSystem design stepsSystem design steps1.1.1.1. identify your chip in the overall systemidentify your chip in the overall systemidentify your chip in the overall systemidentify your chip in the overall system2.2.2.2. define the chip IO and group them to blocks define the chip IO and group them to blocks define the chip IO and group them to blocks define the chip IO and group them to blocks 3.3.3.3. identify functional units of your chipidentify functional units of your chipidentify functional units of your chipidentify functional units of your chip4.4.4.4. identify the interconnection between your unitsidentify the interconnection between your unitsidentify the interconnection between your unitsidentify the interconnection between your units
5.5.5.5. identify speed sensitive (HW) and control sensitive (SW) identify speed sensitive (HW) and control sensitive (SW) identify speed sensitive (HW) and control sensitive (SW) identify speed sensitive (HW) and control sensitive (SW) taskstaskstaskstasks
6.6.6.6. define the “intelligence” of each functional unitdefine the “intelligence” of each functional unitdefine the “intelligence” of each functional unitdefine the “intelligence” of each functional unit
7.7.7.7. identify IP coresidentify IP coresidentify IP coresidentify IP cores8.8.8.8. organize as much as possible IP cores (tools, core organize as much as possible IP cores (tools, core organize as much as possible IP cores (tools, core organize as much as possible IP cores (tools, core
generators, old designs, internet)generators, old designs, internet)generators, old designs, internet)generators, old designs, internet)9.9.9.9. update design if necessary according to available IP coresupdate design if necessary according to available IP coresupdate design if necessary according to available IP coresupdate design if necessary according to available IP cores10.10.10.10. define interdefine interdefine interdefine inter----process communicationprocess communicationprocess communicationprocess communication11.11.11.11. define the interconnections between your unitsdefine the interconnections between your unitsdefine the interconnections between your unitsdefine the interconnections between your units
In the classical HW/SW coIn the classical HW/SW coIn the classical HW/SW coIn the classical HW/SW co----design approach, the design approach, the design approach, the design approach, the design process is continued as long as possible design process is continued as long as possible design process is continued as long as possible design process is continued as long as possible independent of its implementation. HW/SW design independent of its implementation. HW/SW design independent of its implementation. HW/SW design independent of its implementation. HW/SW design units are identified at the very end of the design units are identified at the very end of the design units are identified at the very end of the design units are identified at the very end of the design steps. In smaller designs, as it is in our case, the steps. In smaller designs, as it is in our case, the steps. In smaller designs, as it is in our case, the steps. In smaller designs, as it is in our case, the HW/SW coHW/SW coHW/SW coHW/SW co----design step is done in an early phase.design step is done in an early phase.design step is done in an early phase.design step is done in an early phase.
Step 1: identify your chip in the overall systemStep 1: identify your chip in the overall systemStep 1: identify your chip in the overall systemStep 1: identify your chip in the overall system
Step 2: define the chip IO and group them to Step 2: define the chip IO and group them to Step 2: define the chip IO and group them to Step 2: define the chip IO and group them to blocks blocks blocks blocks Step 3: identify functional units of your chipStep 3: identify functional units of your chipStep 3: identify functional units of your chipStep 3: identify functional units of your chipStep 4: find the interconnections between your Step 4: find the interconnections between your Step 4: find the interconnections between your Step 4: find the interconnections between your unitsunitsunitsunits
Step 5: identify Step 5: identify Step 5: identify Step 5: identify speedspeedspeedspeed and and and and controlcontrolcontrolcontrol sensitive taskssensitive taskssensitive taskssensitive tasksStep 6: define the “intelligence” of each Step 6: define the “intelligence” of each Step 6: define the “intelligence” of each Step 6: define the “intelligence” of each functional unitfunctional unitfunctional unitfunctional unit
Step 7: identify IP coresStep 7: identify IP coresStep 7: identify IP coresStep 7: identify IP coresStep 8: organize as much as possible IP cores Step 8: organize as much as possible IP cores Step 8: organize as much as possible IP cores Step 8: organize as much as possible IP cores (tools, core generator, old designs, internet)(tools, core generator, old designs, internet)(tools, core generator, old designs, internet)(tools, core generator, old designs, internet)
Step 9: update design if necessary according to Step 9: update design if necessary according to Step 9: update design if necessary according to Step 9: update design if necessary according to available IP coresavailable IP coresavailable IP coresavailable IP coresStep 10: define interStep 10: define interStep 10: define interStep 10: define inter----process communicationprocess communicationprocess communicationprocess communicationStep 11: define the interconnection between unitsStep 11: define the interconnection between unitsStep 11: define the interconnection between unitsStep 11: define the interconnection between units
I.I.I.I. imagine your chip working in the target system, identify imagine your chip working in the target system, identify imagine your chip working in the target system, identify imagine your chip working in the target system, identify and describe its basic functional units in a dataand describe its basic functional units in a dataand describe its basic functional units in a dataand describe its basic functional units in a data----flow viewflow viewflow viewflow view
II.II.II.II. find the RTL structure of each of the above datafind the RTL structure of each of the above datafind the RTL structure of each of the above datafind the RTL structure of each of the above data----flow flow flow flow functions and update your block diagram by allocating your functions and update your block diagram by allocating your functions and update your block diagram by allocating your functions and update your block diagram by allocating your RTL structure to one or more functional unitsRTL structure to one or more functional unitsRTL structure to one or more functional unitsRTL structure to one or more functional units
III.III.III.III. fix in detail the operation of your functional units (local fix in detail the operation of your functional units (local fix in detail the operation of your functional units (local fix in detail the operation of your functional units (local intelligence or dataintelligence or dataintelligence or dataintelligence or data----path only) and add path only) and add path only) and add path only) and add FSMs FSMs FSMs FSMs if required, if required, if required, if required, fix the detailed interconnections between your unitsfix the detailed interconnections between your unitsfix the detailed interconnections between your unitsfix the detailed interconnections between your units
IV.IV.IV.IV. design all design all design all design all FSMsFSMsFSMsFSMs, define clock strategy, use colored data, define clock strategy, use colored data, define clock strategy, use colored data, define clock strategy, use colored data----flow, be careful with the interflow, be careful with the interflow, be careful with the interflow, be careful with the inter----process communicationsprocess communicationsprocess communicationsprocess communications
V.V.V.V. VHDL coding of your RTL designVHDL coding of your RTL designVHDL coding of your RTL designVHDL coding of your RTL designVI.VI.VI.VI. test bench designtest bench designtest bench designtest bench designVII.VII.VII.VII. simulate your VHDL design with test benchsimulate your VHDL design with test benchsimulate your VHDL design with test benchsimulate your VHDL design with test bench
FSMD
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Software design project steps:Software design project steps:Software design project steps:Software design project steps:I.I.I.I. design the software structure as learned in SW design the software structure as learned in SW design the software structure as learned in SW design the software structure as learned in SW
engineering coursesengineering coursesengineering coursesengineering coursesII.II.II.II. define the data structuredefine the data structuredefine the data structuredefine the data structureIII.III.III.III. define the HW/SW communicationdefine the HW/SW communicationdefine the HW/SW communicationdefine the HW/SW communication
IV.IV.IV.IV. develop the C codedevelop the C codedevelop the C codedevelop the C codeV.V.V.V. compile & verify your C codecompile & verify your C codecompile & verify your C codecompile & verify your C code
struc
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MicroLab, VLSI-13 (10/24)
JMM v1.4
Project MP3 Player: step IProject MP3 Player: step IProject MP3 Player: step IProject MP3 Player: step I(Hardware design project steps)(Hardware design project steps)(Hardware design project steps)(Hardware design project steps)Step I: imagine your chip working in the target Step I: imagine your chip working in the target Step I: imagine your chip working in the target Step I: imagine your chip working in the target system, identify and describe its basic functional system, identify and describe its basic functional system, identify and describe its basic functional system, identify and describe its basic functional units in a dataunits in a dataunits in a dataunits in a data----flow viewflow viewflow viewflow view
download MP3 song from host to flash download MP3 song from host to flash download MP3 song from host to flash download MP3 song from host to flash memory (flow 1):memory (flow 1):memory (flow 1):memory (flow 1):
generate flash command, generate flash addressgenerate flash command, generate flash addressgenerate flash command, generate flash addressgenerate flash command, generate flash addressload byte from USB into registerload byte from USB into registerload byte from USB into registerload byte from USB into registeruse byte to execute ECC (Hamming code)use byte to execute ECC (Hamming code)use byte to execute ECC (Hamming code)use byte to execute ECC (Hamming code)update flash addressupdate flash addressupdate flash addressupdate flash addressstore byte into flashstore byte into flashstore byte into flashstore byte into flashwrite ECC code after 512 byteswrite ECC code after 512 byteswrite ECC code after 512 byteswrite ECC code after 512 bytesgenerate writegenerate writegenerate writegenerate write----totototo----flash after 512 bytesflash after 512 bytesflash after 512 bytesflash after 512 bytesuse pipeline structure to speed up data transferuse pipeline structure to speed up data transferuse pipeline structure to speed up data transferuse pipeline structure to speed up data transfer
Project MP3 Player: step IIProject MP3 Player: step IIProject MP3 Player: step IIProject MP3 Player: step II(hardware design project steps) (hardware design project steps) (hardware design project steps) (hardware design project steps) Step II: find the RTL structure of each of the Step II: find the RTL structure of each of the Step II: find the RTL structure of each of the Step II: find the RTL structure of each of the previous dataprevious dataprevious dataprevious data----flow functions and update your flow functions and update your flow functions and update your flow functions and update your block diagram by allocating your RTL block diagram by allocating your RTL block diagram by allocating your RTL block diagram by allocating your RTL structure to one or more functional unitsstructure to one or more functional unitsstructure to one or more functional unitsstructure to one or more functional units
download MP3 song from host to flash download MP3 song from host to flash download MP3 song from host to flash download MP3 song from host to flash memory (flow 1):memory (flow 1):memory (flow 1):memory (flow 1):
clkclkclkclk
enableenableenableenable
in outin outin outin out
clkclkclkclk
enableenableenableenable
in outin outin outin outECC ECC ECC ECC generatorgeneratorgeneratorgenerator
Step III: fix in detail the function of your Step III: fix in detail the function of your Step III: fix in detail the function of your Step III: fix in detail the function of your functional units (local intelligence or datafunctional units (local intelligence or datafunctional units (local intelligence or datafunctional units (local intelligence or data----path path path path only) and add only) and add only) and add only) and add FSMsFSMsFSMsFSMs if required, fix the detailed if required, fix the detailed if required, fix the detailed if required, fix the detailed interconnections between your unitsinterconnections between your unitsinterconnections between your unitsinterconnections between your units
Step Step Step Step IVaIVaIVaIVa: design all : design all : design all : design all FSMsFSMsFSMsFSMs, define clock strategy, use , define clock strategy, use , define clock strategy, use , define clock strategy, use colored datacolored datacolored datacolored data----flow, be careful with the interflow, be careful with the interflow, be careful with the interflow, be careful with the inter----process process process process communications communications communications communications
Clock strategy:Clock strategy:Clock strategy:Clock strategy: Rising edge for dataRising edge for dataRising edge for dataRising edge for data----paths, falling edge for IP paths, falling edge for IP paths, falling edge for IP paths, falling edge for IP cores and cores and cores and cores and FSMsFSMsFSMsFSMs. All handshake signals between . All handshake signals between . All handshake signals between . All handshake signals between FSMDs FSMDs FSMDs FSMDs and IP and IP and IP and IP cores on falling edge.cores on falling edge.cores on falling edge.cores on falling edge.ColorsColorsColorsColors: make a lot of copies of your RTL data path: make a lot of copies of your RTL data path: make a lot of copies of your RTL data path: make a lot of copies of your RTL data pathColorsColorsColorsColors: for each data: for each data: for each data: for each data----flow step, color the old active data paths flow step, color the old active data paths flow step, color the old active data paths flow step, color the old active data paths leaving a register blue, the new active dataleaving a register blue, the new active dataleaving a register blue, the new active dataleaving a register blue, the new active data----paths leaving a paths leaving a paths leaving a paths leaving a register green, and dataregister green, and dataregister green, and dataregister green, and data----paths treated with a combinatorial paths treated with a combinatorial paths treated with a combinatorial paths treated with a combinatorial function in the corresponding dark color. Active control signalsfunction in the corresponding dark color. Active control signalsfunction in the corresponding dark color. Active control signalsfunction in the corresponding dark color. Active control signalsand its blocks are orange. All other dataand its blocks are orange. All other dataand its blocks are orange. All other dataand its blocks are orange. All other data----signals are red. Red signals are red. Red signals are red. Red signals are red. Red signals are dominant. Be sure that no red signals enter a FSM, signals are dominant. Be sure that no red signals enter a FSM, signals are dominant. Be sure that no red signals enter a FSM, signals are dominant. Be sure that no red signals enter a FSM, and no and no and no and no darkenddarkenddarkenddarkend or red signals attack asynchronous set/reset of or red signals attack asynchronous set/reset of or red signals attack asynchronous set/reset of or red signals attack asynchronous set/reset of FFsFFsFFsFFs....
clkclkclkclk
enableenableenableenable
in outin outin outin out
clkclkclkclk
enableenableenableenable
in outin outin outin outECC ECC ECC ECC generatorgeneratorgeneratorgenerator
Step Step Step Step IVbIVbIVbIVb: design all : design all : design all : design all FSMsFSMsFSMsFSMs, define clock strategy, use , define clock strategy, use , define clock strategy, use , define clock strategy, use colored datacolored datacolored datacolored data----flow, be careful with the interflow, be careful with the interflow, be careful with the interflow, be careful with the inter----process process process process communications communications communications communications
we decide to use 3 different we decide to use 3 different we decide to use 3 different we decide to use 3 different FSMs FSMs FSMs FSMs in addition to the ones in addition to the ones in addition to the ones in addition to the ones present in IP corespresent in IP corespresent in IP corespresent in IP coresthethethethe PIC processorPIC processorPIC processorPIC processor core is the main unit, which core is the main unit, which core is the main unit, which core is the main unit, which communicates with all other FSMD or core units, thus use communicates with all other FSMD or core units, thus use communicates with all other FSMD or core units, thus use communicates with all other FSMD or core units, thus use interinterinterinter----process communication. There is no communication process communication. There is no communication process communication. There is no communication process communication. There is no communication inininin----between the other units. between the other units. between the other units. between the other units.
Step V: VHDL coding of your RTL designStep V: VHDL coding of your RTL designStep V: VHDL coding of your RTL designStep V: VHDL coding of your RTL designuse a processes for datause a processes for datause a processes for datause a processes for data----path manipulation and its path manipulation and its path manipulation and its path manipulation and its succeeding registersucceeding registersucceeding registersucceeding registeruse 2 processes for a FSM:use 2 processes for a FSM:use 2 processes for a FSM:use 2 processes for a FSM:
one process for transition table (VHDL case)one process for transition table (VHDL case)one process for transition table (VHDL case)one process for transition table (VHDL case)one process for next state (state register)one process for next state (state register)one process for next state (state register)one process for next state (state register)continuous assignment for output functioncontinuous assignment for output functioncontinuous assignment for output functioncontinuous assignment for output function
clkclkclkclk
enableenableenableenable
in outin outin outin out
clkclkclkclk
enableenableenableenable
in outin outin outin outECC ECC ECC ECC generatorgeneratorgeneratorgenerator
Step VI: test bench designStep VI: test bench designStep VI: test bench designStep VI: test bench designthe design of a test bench is one of the most time the design of a test bench is one of the most time the design of a test bench is one of the most time the design of a test bench is one of the most time consuming and important tasks. A test bench will be consuming and important tasks. A test bench will be consuming and important tasks. A test bench will be consuming and important tasks. A test bench will be rererere----used several times during the different design used several times during the different design used several times during the different design used several times during the different design steps as well as for chip test (have a look at vlsi21)steps as well as for chip test (have a look at vlsi21)steps as well as for chip test (have a look at vlsi21)steps as well as for chip test (have a look at vlsi21)
responsegeneration
andverification
controland
stimulusgeneration
Test Bench
device under test (DUT)
MicroLab, VLSI-13 (17/24)
JMM v1.4
Final System Design StepsFinal System Design StepsFinal System Design StepsFinal System Design StepsHardware design project steps:Hardware design project steps:Hardware design project steps:Hardware design project steps:
12.12.12.12. system test bench designsystem test bench designsystem test bench designsystem test bench design13.13.13.13. hardware/software system simulation with test benchhardware/software system simulation with test benchhardware/software system simulation with test benchhardware/software system simulation with test bench
14.14.14.14. synthesis of logic level designsynthesis of logic level designsynthesis of logic level designsynthesis of logic level design15.15.15.15. simulation of logic level with test benchsimulation of logic level with test benchsimulation of logic level with test benchsimulation of logic level with test bench16.16.16.16. place & route your design for target technologyplace & route your design for target technologyplace & route your design for target technologyplace & route your design for target technology
17.17.17.17. back annotation and simulation with test benchback annotation and simulation with test benchback annotation and simulation with test benchback annotation and simulation with test bench18.18.18.18. (formal design verification)(formal design verification)(formal design verification)(formal design verification)
20.20.20.20. chip test with test benchchip test with test benchchip test with test benchchip test with test bench21.21.21.21. in system testin system testin system testin system test
synt
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and r
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verif
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test
testtest
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syste
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MicroLab, VLSI-13 (18/24)
JMM v1.4
Block Block Block Block diagadiagadiagadiagammmmm of a general Systemm of a general Systemm of a general Systemm of a general System
A general system is composed of three elements:A general system is composed of three elements:A general system is composed of three elements:A general system is composed of three elements:useruseruseruseralgorithmalgorithmalgorithmalgorithmplantplantplantplant
all three items interact with each other resulting in all three items interact with each other resulting in all three items interact with each other resulting in all three items interact with each other resulting in 2 closed loops2 closed loops2 closed loops2 closed loopsThe closed loops may have realThe closed loops may have realThe closed loops may have realThe closed loops may have real----time constraintstime constraintstime constraintstime constraints
All three design entry elements will be converted All three design entry elements will be converted All three design entry elements will be converted All three design entry elements will be converted to VHDL and thus can be implemented into a to VHDL and thus can be implemented into a to VHDL and thus can be implemented into a to VHDL and thus can be implemented into a SoCSoCSoCSoC
The specifyThe specifyThe specifyThe specify----exploreexploreexploreexplore----refine design flow is extended refine design flow is extended refine design flow is extended refine design flow is extended to a specifyto a specifyto a specifyto a specify----exploreexploreexploreexplore----refinerefinerefinerefine----prototypeprototypeprototypeprototype----analyseanalyseanalyseanalysedesign flow for design flow for design flow for design flow for SoCSoCSoCSoC designs with realdesigns with realdesigns with realdesigns with real----time time time time constraintsconstraintsconstraintsconstraints
MicroLab, VLSI-13 (21/24)
JMM v1.4
SoCSoCSoCSoC with GECKO Environmentwith GECKO Environmentwith GECKO Environmentwith GECKO Environment
An An An An SoCSoCSoCSoC design using the GECKO system supports design using the GECKO system supports design using the GECKO system supports design using the GECKO system supports the two chip approachthe two chip approachthe two chip approachthe two chip approach
GECKO main board for digital partGECKO main board for digital partGECKO main board for digital partGECKO main board for digital partapplication specific GECKO expansion board for analog, application specific GECKO expansion board for analog, application specific GECKO expansion board for analog, application specific GECKO expansion board for analog, power, HF partpower, HF partpower, HF partpower, HF part
Gecko main board
Software
MicroprocessorIP Core
Real TimeSignal ProcessingHardware
HardwareIP blocks
Analogblocks
Powerblocks
Sensor
SoC
MicroLab, VLSI-13 (22/24)
JMM v1.4
The The The The GECKO systemGECKO systemGECKO systemGECKO system
GECKO GECKO GECKO GECKO main boardmain boardmain boardmain board
GECKO GECKO GECKO GECKO main boardmain boardmain boardmain board n n n n top if top if top if top if an an an an application specificapplication specificapplication specificapplication specificGECKO GECKO GECKO GECKO expansion boardexpansion boardexpansion boardexpansion board(RFID (RFID (RFID (RFID reader applicationreader applicationreader applicationreader application, 2 W, 2 W, 2 W, 2 W13.56MHz RF power)13.56MHz RF power)13.56MHz RF power)13.56MHz RF power)
to iteratively improve a design fast prototyping and to iteratively improve a design fast prototyping and to iteratively improve a design fast prototyping and to iteratively improve a design fast prototyping and data analysis steps are necessarydata analysis steps are necessarydata analysis steps are necessarydata analysis steps are necessarydifficult to model plants are preferably not be difficult to model plants are preferably not be difficult to model plants are preferably not be difficult to model plants are preferably not be modeled and directly included in the simulation modeled and directly included in the simulation modeled and directly included in the simulation modeled and directly included in the simulation looplooplooploopvariable cut between simulation and hardwarevariable cut between simulation and hardwarevariable cut between simulation and hardwarevariable cut between simulation and hardwarerespect realrespect realrespect realrespect real----time constraintstime constraintstime constraintstime constraints
define your own projectdefine your own projectdefine your own projectdefine your own projectplan the development and use the presented design plan the development and use the presented design plan the development and use the presented design plan the development and use the presented design methodologymethodologymethodologymethodologyprepare the presentation of your project, be sure prepare the presentation of your project, be sure prepare the presentation of your project, be sure prepare the presentation of your project, be sure you do have all the necessary documentation for the you do have all the necessary documentation for the you do have all the necessary documentation for the you do have all the necessary documentation for the discussed design stepsdiscussed design stepsdiscussed design stepsdiscussed design steps
MyProjectMyProjectMyProjectMyProject 2002200220022002: speed controlled dc motor: speed controlled dc motor: speed controlled dc motor: speed controlled dc motorMatlabMatlabMatlabMatlab////SimulinkSimulinkSimulinkSimulink with speed controllerwith speed controllerwith speed controllerwith speed controllerGECKO main board with dcGECKO main board with dcGECKO main board with dcGECKO main board with dc----motor electronicsmotor electronicsmotor electronicsmotor electronicsuse hardwareuse hardwareuse hardwareuse hardware----inininin----thethethethe----simulationsimulationsimulationsimulation----looplooplooploop
Implementation constraints:Implementation constraints:Implementation constraints:Implementation constraints:microprocessor with C code for „administrative“ tasksmicroprocessor with C code for „administrative“ tasksmicroprocessor with C code for „administrative“ tasksmicroprocessor with C code for „administrative“ taskspulse wide modulation for driving dc motor (hardware)pulse wide modulation for driving dc motor (hardware)pulse wide modulation for driving dc motor (hardware)pulse wide modulation for driving dc motor (hardware)A/B signal encoder for speed sensing (hardware)A/B signal encoder for speed sensing (hardware)A/B signal encoder for speed sensing (hardware)A/B signal encoder for speed sensing (hardware)driving circuitry (expansion board) as simple as possibledriving circuitry (expansion board) as simple as possibledriving circuitry (expansion board) as simple as possibledriving circuitry (expansion board) as simple as possible
Technical data:Technical data:Technical data:Technical data:dc motor has 6000 turns/minute at 5Vdc motor has 6000 turns/minute at 5Vdc motor has 6000 turns/minute at 5Vdc motor has 6000 turns/minute at 5Vspeed sensor has 12 pulses per turnspeed sensor has 12 pulses per turnspeed sensor has 12 pulses per turnspeed sensor has 12 pulses per turn
Goal: Goal: Goal: Goal: You know the basics of integrated circuit You know the basics of integrated circuit You know the basics of integrated circuit You know the basics of integrated circuit processing steps and you are familiar with the processing steps and you are familiar with the processing steps and you are familiar with the processing steps and you are familiar with the processing sequence of a sample CMOS technology.processing sequence of a sample CMOS technology.processing sequence of a sample CMOS technology.processing sequence of a sample CMOS technology.
MicroLab, VLSI-14 (2/32)
JMM v1.4
IntroductionIntroductionIntroductionIntroductionComplementary MOS (CMOS) technology is Complementary MOS (CMOS) technology is Complementary MOS (CMOS) technology is Complementary MOS (CMOS) technology is becoming the dominant candidate for VLSI becoming the dominant candidate for VLSI becoming the dominant candidate for VLSI becoming the dominant candidate for VLSI applicationsapplicationsapplicationsapplicationsCMOS provides both nCMOS provides both nCMOS provides both nCMOS provides both n----channel and pchannel and pchannel and pchannel and p----channel MOS channel MOS channel MOS channel MOS transistors on one chiptransistors on one chiptransistors on one chiptransistors on one chipon extremely expensive on extremely expensive on extremely expensive on extremely expensive fabsfabsfabsfabs cheap chips are cheap chips are cheap chips are cheap chips are producedproducedproducedproducedeach chip passes hundreds of different processing each chip passes hundreds of different processing each chip passes hundreds of different processing each chip passes hundreds of different processing stepsstepsstepsstepsrandom process disturbances cause electrical random process disturbances cause electrical random process disturbances cause electrical random process disturbances cause electrical parameter variations of the chipsparameter variations of the chipsparameter variations of the chipsparameter variations of the chipselements are never identicalelements are never identicalelements are never identicalelements are never identical
Process technology pictures and text are copied from:Process technology pictures and text are copied from:Process technology pictures and text are copied from:Process technology pictures and text are copied from:Atlas of IC Technologies, W. Atlas of IC Technologies, W. Atlas of IC Technologies, W. Atlas of IC Technologies, W. MalyMalyMalyMaly, The Benjamin Cummings , The Benjamin Cummings , The Benjamin Cummings , The Benjamin Cummings Publishing Company, ISBN 0Publishing Company, ISBN 0Publishing Company, ISBN 0Publishing Company, ISBN 0----8053805380538053----6850685068506850----7777
MicroLab, VLSI-14 (3/32)
JMM v1.4
VLSI Circuit FabricationVLSI Circuit FabricationVLSI Circuit FabricationVLSI Circuit Fabricationdepositdepositdepositdeposit thin layers of material thin layers of material thin layers of material thin layers of material and and and and etchetchetchetch into desired patterninto desired patterninto desired patterninto desired pattern
n+n+n+n+ n+n+n+n+
pppp
oxidizeoxidizeoxidizeoxidize silicon to formsilicon to formsilicon to formsilicon to formthin and thick layers ofthin and thick layers ofthin and thick layers ofthin and thick layers ofSiOSiOSiOSiO2222 to serve asto serve asto serve asto serve asinsulators.insulators.insulators.insulators.
diffusediffusediffusediffuse dopants intodopants intodopants intodopants intosubstrate to createsubstrate to createsubstrate to createsubstrate to createP/N junctionsP/N junctionsP/N junctionsP/N junctions
implantimplantimplantimplant ions to setions to setions to setions to setthresholds and achievethresholds and achievethresholds and achievethresholds and achieveprecise dopant profilesprecise dopant profilesprecise dopant profilesprecise dopant profiles
Most fabrication steps require first creating a Most fabrication steps require first creating a Most fabrication steps require first creating a Most fabrication steps require first creating a maskmaskmaskmask that determines that determines that determines that determines where the operation will occur. Masks can either be existing lawhere the operation will occur. Masks can either be existing lawhere the operation will occur. Masks can either be existing lawhere the operation will occur. Masks can either be existing layers on yers on yers on yers on the IC (these masks are “selfthe IC (these masks are “selfthe IC (these masks are “selfthe IC (these masks are “self----aligned”) or created using a lithographic aligned”) or created using a lithographic aligned”) or created using a lithographic aligned”) or created using a lithographic process and process and process and process and photoresistphotoresistphotoresistphotoresist....
Design rulesDesign rulesDesign rulesDesign rules ensure that design is still functional in the face of ensure that design is still functional in the face of ensure that design is still functional in the face of ensure that design is still functional in the face of misalignments and various sidemisalignments and various sidemisalignments and various sidemisalignments and various side----effects of the fabrication process.effects of the fabrication process.effects of the fabrication process.effects of the fabrication process.
MicroLab, VLSI-14 (4/32)
JMM v1.4
OverviewOverviewOverviewOverview
Overview of Processing StepsOverview of Processing StepsOverview of Processing StepsOverview of Processing Stepsmaking the wafersmaking the wafersmaking the wafersmaking the wafersphotolithographyphotolithographyphotolithographyphotolithographyoxidationoxidationoxidationoxidationlayer depositionlayer depositionlayer depositionlayer depositionetchingetchingetchingetchingdiffusiondiffusiondiffusiondiffusionimplantationimplantationimplantationimplantation
nnnn----wellwellwellwell
activeactiveactiveactive
polypolypolypoly
nnnn----diffusiondiffusiondiffusiondiffusion
pppp----diffusiondiffusiondiffusiondiffusion
contactscontactscontactscontacts
metal1metal1metal1metal1
via1via1via1via1
metal2metal2metal2metal2
passivationpassivationpassivationpassivation
Overview of Overview of Overview of Overview of Processing Processing Processing Processing Step SequenceStep SequenceStep SequenceStep Sequence
MicroLab, VLSI-14 (5/32)
JMM v1.4
Processing Steps:Processing Steps:Processing Steps:Processing Steps:Making the wafersMaking the wafersMaking the wafersMaking the wafers
the basic raw material used is a wafer or disk of the basic raw material used is a wafer or disk of the basic raw material used is a wafer or disk of the basic raw material used is a wafer or disk of silicon which varies from 3” to 12” in diametersilicon which varies from 3” to 12” in diametersilicon which varies from 3” to 12” in diametersilicon which varies from 3” to 12” in diameterwafers are cut in thin slices (less than 1mm) of wafers are cut in thin slices (less than 1mm) of wafers are cut in thin slices (less than 1mm) of wafers are cut in thin slices (less than 1mm) of semiconductor cylindrical ingotssemiconductor cylindrical ingotssemiconductor cylindrical ingotssemiconductor cylindrical ingotsfirst step in IC processing is the production of a first step in IC processing is the production of a first step in IC processing is the production of a first step in IC processing is the production of a singlesinglesinglesingle----crystal ingot starting from a silicon melt crystal ingot starting from a silicon melt crystal ingot starting from a silicon melt crystal ingot starting from a silicon melt with a controlled amount of impuritieswith a controlled amount of impuritieswith a controlled amount of impuritieswith a controlled amount of impurities
Complementary Photolithography is a technique Complementary Photolithography is a technique Complementary Photolithography is a technique Complementary Photolithography is a technique used in IC fabrication to transfer a desired pattern used in IC fabrication to transfer a desired pattern used in IC fabrication to transfer a desired pattern used in IC fabrication to transfer a desired pattern onto the surface of a silicon wafer. As such the onto the surface of a silicon wafer. As such the onto the surface of a silicon wafer. As such the onto the surface of a silicon wafer. As such the photolithography is a key step in the entire circuit photolithography is a key step in the entire circuit photolithography is a key step in the entire circuit photolithography is a key step in the entire circuit integration process.integration process.integration process.integration process.
alternative method for lower quantities: direct write alternative method for lower quantities: direct write alternative method for lower quantities: direct write alternative method for lower quantities: direct write procedure (Eprocedure (Eprocedure (Eprocedure (E----beam)beam)beam)beam)
Thermal oxidation is a process in which silicon (Thermal oxidation is a process in which silicon (Thermal oxidation is a process in which silicon (Thermal oxidation is a process in which silicon (SiSiSiSi) ) ) ) reacts with oxygen to form a continuous layer of reacts with oxygen to form a continuous layer of reacts with oxygen to form a continuous layer of reacts with oxygen to form a continuous layer of highhighhighhigh----quality silicon dioxide (SiOquality silicon dioxide (SiOquality silicon dioxide (SiOquality silicon dioxide (SiO2222))))oxidation of the silicon surfaceoxidation of the silicon surfaceoxidation of the silicon surfaceoxidation of the silicon surfaceoxidation through a window in the oxideoxidation through a window in the oxideoxidation through a window in the oxideoxidation through a window in the oxideselective oxide growthselective oxide growthselective oxide growthselective oxide growth
oxidation of the silicon surfaceoxidation of the silicon surfaceoxidation of the silicon surfaceoxidation of the silicon surface
Thin layers of both conduction substances and Thin layers of both conduction substances and Thin layers of both conduction substances and Thin layers of both conduction substances and insulation materials constitute an important part of insulation materials constitute an important part of insulation materials constitute an important part of insulation materials constitute an important part of any semiconductor device.any semiconductor device.any semiconductor device.any semiconductor device.epitaxyepitaxyepitaxyepitaxy (single crystal deposition)(single crystal deposition)(single crystal deposition)(single crystal deposition)PVD and CVD process (polycrystalline deposition)PVD and CVD process (polycrystalline deposition)PVD and CVD process (polycrystalline deposition)PVD and CVD process (polycrystalline deposition)
The process that immediately follows the The process that immediately follows the The process that immediately follows the The process that immediately follows the photolithography step is the removal of material photolithography step is the removal of material photolithography step is the removal of material photolithography step is the removal of material from areas of the wafer unprotected by from areas of the wafer unprotected by from areas of the wafer unprotected by from areas of the wafer unprotected by photoresistphotoresistphotoresistphotoresist. . . . Characterization by selectivity and anisotropy.Characterization by selectivity and anisotropy.Characterization by selectivity and anisotropy.Characterization by selectivity and anisotropy.
Solid state diffusion is a process which allows Solid state diffusion is a process which allows Solid state diffusion is a process which allows Solid state diffusion is a process which allows atoms to move within a solid at elevated atoms to move within a solid at elevated atoms to move within a solid at elevated atoms to move within a solid at elevated temperatures.temperatures.temperatures.temperatures.
The alternative to the diffusion technique of dopant The alternative to the diffusion technique of dopant The alternative to the diffusion technique of dopant The alternative to the diffusion technique of dopant introduction used in IC manufacturing is ion introduction used in IC manufacturing is ion introduction used in IC manufacturing is ion introduction used in IC manufacturing is ion implantation.implantation.implantation.implantation.
In p substrate only nIn p substrate only nIn p substrate only nIn p substrate only n----channelchannelchannelchannel fetsfetsfetsfets can be processed. can be processed. can be processed. can be processed. Therefore an nTherefore an nTherefore an nTherefore an n----well has to be implanted in order to hold well has to be implanted in order to hold well has to be implanted in order to hold well has to be implanted in order to hold the pthe pthe pthe p----channelchannelchannelchannel fetsfetsfetsfets. . . .
Window in the mask and cross section illustrated.Window in the mask and cross section illustrated.Window in the mask and cross section illustrated.Window in the mask and cross section illustrated.
A “thick” (0.4um) layer of silicon dioxide, called A “thick” (0.4um) layer of silicon dioxide, called A “thick” (0.4um) layer of silicon dioxide, called A “thick” (0.4um) layer of silicon dioxide, called field field field field oxideoxideoxideoxide, is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we want to makewant to makewant to makewant to make fetsfetsfetsfets....
MicroLab, VLSI-14 (17/32)
JMM v1.4
Grow Field OxideGrow Field OxideGrow Field OxideGrow Field Oxide
Formation of active regions for nFormation of active regions for nFormation of active regions for nFormation of active regions for n----channel and pchannel and pchannel and pchannel and p----channelchannelchannelchannelfetsfetsfetsfets of the CMOS process. The obtained bird’s beak of the CMOS process. The obtained bird’s beak of the CMOS process. The obtained bird’s beak of the CMOS process. The obtained bird’s beak causes the active area of the device to be significantly causes the active area of the device to be significantly causes the active area of the device to be significantly causes the active area of the device to be significantly smaller.smaller.smaller.smaller.
Now grow a “thin” (0.01um = 100 Angstroms) layer of Now grow a “thin” (0.01um = 100 Angstroms) layer of Now grow a “thin” (0.01um = 100 Angstroms) layer of Now grow a “thin” (0.01um = 100 Angstroms) layer of silicon dioxide, called gate oxide, on the surface by silicon dioxide, called gate oxide, on the surface by silicon dioxide, called gate oxide, on the surface by silicon dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen. exposing the wafer to dry oxygen. exposing the wafer to dry oxygen. exposing the wafer to dry oxygen.
The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the more oomph the more oomph the more oomph the more oomph the fetfetfetfet will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the harder it is to make it defect free. harder it is to make it defect free. harder it is to make it defect free. harder it is to make it defect free.
On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polycrystalline silicon, called polycrystalline silicon, called polycrystalline silicon, called polysilicon polysilicon polysilicon polysilicon or or or or polypolypolypoly for for for for short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and drain junctions will be formed:drain junctions will be formed:drain junctions will be formed:drain junctions will be formed:
The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron implantation, with phosphorus (an electron implantation, with phosphorus (an electron implantation, with phosphorus (an electron donordonordonordonor) which ) which ) which ) which creates two ncreates two ncreates two ncreates two n----type regions in the substrate and an type regions in the substrate and an type regions in the substrate and an type regions in the substrate and an ohmicohmicohmicohmiccontact in the ncontact in the ncontact in the ncontact in the n----well. The phosphorus also penetrates the well. The phosphorus also penetrates the well. The phosphorus also penetrates the well. The phosphorus also penetrates the poly reducing its resistance and affecting the poly reducing its resistance and affecting the poly reducing its resistance and affecting the poly reducing its resistance and affecting the nfet’snfet’snfet’snfet’sthreshold.threshold.threshold.threshold.
Once again the entire surface is doped, either by diffusion Once again the entire surface is doped, either by diffusion Once again the entire surface is doped, either by diffusion Once again the entire surface is doped, either by diffusion or ion implantation, with boron (an electron or ion implantation, with boron (an electron or ion implantation, with boron (an electron or ion implantation, with boron (an electron acceptoracceptoracceptoracceptor) ) ) ) which creates two pwhich creates two pwhich creates two pwhich creates two p----type regions in the ntype regions in the ntype regions in the ntype regions in the n----well and an well and an well and an well and an ohmicohmicohmicohmic contact in the substrate.contact in the substrate.contact in the substrate.contact in the substrate.
Finally an intermediate oxide layer is grown for isolation and Finally an intermediate oxide layer is grown for isolation and Finally an intermediate oxide layer is grown for isolation and Finally an intermediate oxide layer is grown for isolation and then then then then reflowedreflowedreflowedreflowed to to to to flattenflattenflattenflatten its surface. its surface. its surface. its surface.
Holes are etched in the oxide where contacts to poly/diff Holes are etched in the oxide where contacts to poly/diff Holes are etched in the oxide where contacts to poly/diff Holes are etched in the oxide where contacts to poly/diff are wanted.are wanted.are wanted.are wanted.
For interconnections aluminium is deposited, patterned and For interconnections aluminium is deposited, patterned and For interconnections aluminium is deposited, patterned and For interconnections aluminium is deposited, patterned and etched.etched.etched.etched.
MicroLab, VLSI-14 (27/32)
JMM v1.4
Voila: a CMOS Inverter!Voila: a CMOS Inverter!Voila: a CMOS Inverter!Voila: a CMOS Inverter!
Finally a Finally a Finally a Finally a passivationpassivationpassivationpassivation layer protects the wafer surface from layer protects the wafer surface from layer protects the wafer surface from layer protects the wafer surface from contamination and scratches. Pads are opened for bonding.contamination and scratches. Pads are opened for bonding.contamination and scratches. Pads are opened for bonding.contamination and scratches. Pads are opened for bonding.
NNNN----well, Doublewell, Doublewell, Doublewell, Double----level Metal CMOS level Metal CMOS level Metal CMOS level Metal CMOS Process StepsProcess StepsProcess StepsProcess Steps
1. Grow barrier oxide1. Grow barrier oxide1. Grow barrier oxide1. Grow barrier oxide2. 2. 2. 2. MaskMaskMaskMask/Etch n/Etch n/Etch n/Etch n----well windowwell windowwell windowwell window3. 3. 3. 3. PPPP nnnn----well implantwell implantwell implantwell implant4. Thermal drive4. Thermal drive4. Thermal drive4. Thermal drive----in to deepen nin to deepen nin to deepen nin to deepen n----wellwellwellwell5. Remove barrier oxide5. Remove barrier oxide5. Remove barrier oxide5. Remove barrier oxide6. Grow “pad” oxide6. Grow “pad” oxide6. Grow “pad” oxide6. Grow “pad” oxide7. Deposit Si7. Deposit Si7. Deposit Si7. Deposit Si3333NNNN44448. 8. 8. 8. MaskMaskMaskMask/Etch leaving active region/Etch leaving active region/Etch leaving active region/Etch leaving active region9. 9. 9. 9. BBBB channelchannelchannelchannel----stop implantstop implantstop implantstop implant10. Grow field oxide (more drive10. Grow field oxide (more drive10. Grow field oxide (more drive10. Grow field oxide (more drive----in!)in!)in!)in!)11. Remove Si11. Remove Si11. Remove Si11. Remove Si3333NNNN444412. Remove pad oxide12. Remove pad oxide12. Remove pad oxide12. Remove pad oxide13. 13. 13. 13. BBBB or or or or PPPP implant to adjust Vimplant to adjust Vimplant to adjust Vimplant to adjust VTHTHTHTH14. Grow thin (gate) oxide14. Grow thin (gate) oxide14. Grow thin (gate) oxide14. Grow thin (gate) oxide15. Deposit 15. Deposit 15. Deposit 15. Deposit PPPP----doped polysilicondoped polysilicondoped polysilicondoped polysilicon16. 16. 16. 16. MaskMaskMaskMask/Etch leaving poly wires/Etch leaving poly wires/Etch leaving poly wires/Etch leaving poly wires17. Etch exposed thin oxide17. Etch exposed thin oxide17. Etch exposed thin oxide17. Etch exposed thin oxide18. 18. 18. 18. Mask Mask Mask Mask off poff poff poff p----diffusion regionsdiffusion regionsdiffusion regionsdiffusion regions19. 19. 19. 19. SbSbSbSb or or or or AsAsAsAs nfetnfetnfetnfet source/drainsource/drainsource/drainsource/drain
implant, nimplant, nimplant, nimplant, n----well contact toowell contact toowell contact toowell contact too20. Mask all but p20. Mask all but p20. Mask all but p20. Mask all but p----diffusion regionsdiffusion regionsdiffusion regionsdiffusion regions21. 21. 21. 21. BBBB pfetpfetpfetpfet source/drain implantsource/drain implantsource/drain implantsource/drain implant22. Thermal source/drain annealing22. Thermal source/drain annealing22. Thermal source/drain annealing22. Thermal source/drain annealing
through through through through SiOSiOSiOSiO222225. Deposit first 25. Deposit first 25. Deposit first 25. Deposit first AlAlAlAl using PVDusing PVDusing PVDusing PVD26. 26. 26. 26. MaskMaskMaskMask/Etch leaving metal1 /Etch leaving metal1 /Etch leaving metal1 /Etch leaving metal1
wireswireswireswires27. Grow thick layer of 27. Grow thick layer of 27. Grow thick layer of 27. Grow thick layer of SiOSiOSiOSiO222228. Spin on thick, flat layer of28. Spin on thick, flat layer of28. Spin on thick, flat layer of28. Spin on thick, flat layer of
photoresistphotoresistphotoresistphotoresist29. Etch 29. Etch 29. Etch 29. Etch SiOSiOSiOSiO2222 and and and and photoresist photoresist photoresist photoresist
at same rate until only flatat same rate until only flatat same rate until only flatat same rate until only flatSiOSiOSiOSiO2222 remainsremainsremainsremains
30. 30. 30. 30. MaskMaskMaskMask/Etch /Etch /Etch /Etch viasviasviasvias through through through through SiOSiOSiOSiO222231. Deposit second using PVD31. Deposit second using PVD31. Deposit second using PVD31. Deposit second using PVD32. 32. 32. 32. MaskMaskMaskMask/Etch leaving metal2 /Etch leaving metal2 /Etch leaving metal2 /Etch leaving metal2
passivatepassivatepassivatepassivate circuitcircuitcircuitcircuit34. 34. 34. 34. MaskMaskMaskMask/Etch pad windows/Etch pad windows/Etch pad windows/Etch pad windows
Study CBT course on the web or on I3SStudy CBT course on the web or on I3SStudy CBT course on the web or on I3SStudy CBT course on the web or on I3S----CD:CD:CD:CD:How a silicon integrated circuit is made (How a silicon integrated circuit is made (How a silicon integrated circuit is made (How a silicon integrated circuit is made (UniUniUniUniManchester)Manchester)Manchester)Manchester)
WesteWesteWesteWeste pp168: 3.8 ex 5 (difficulty: easy):pp168: 3.8 ex 5 (difficulty: easy):pp168: 3.8 ex 5 (difficulty: easy):pp168: 3.8 ex 5 (difficulty: easy): Explain Explain Explain Explain why substrate and well contacts are important in why substrate and well contacts are important in why substrate and well contacts are important in why substrate and well contacts are important in CMOS.CMOS.CMOS.CMOS.
OverviewOverviewOverviewOverviewCMOS Layout and Design RulesCMOS Layout and Design RulesCMOS Layout and Design RulesCMOS Layout and Design RulesAnalog Layout Design ConsiderationsAnalog Layout Design ConsiderationsAnalog Layout Design ConsiderationsAnalog Layout Design Considerations
Goal: Goal: Goal: Goal: You are familiar with the basic layout design You are familiar with the basic layout design You are familiar with the basic layout design You are familiar with the basic layout design rules of therules of therules of therules of the AlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm CMOS process. You m CMOS process. You m CMOS process. You m CMOS process. You know how to layout integrated transistors, know how to layout integrated transistors, know how to layout integrated transistors, know how to layout integrated transistors, capacitors and resistors, and what has to be capacitors and resistors, and what has to be capacitors and resistors, and what has to be capacitors and resistors, and what has to be considered in order to realize quality analog considered in order to realize quality analog considered in order to realize quality analog considered in order to realize quality analog circuits, like matching and shielding.circuits, like matching and shielding.circuits, like matching and shielding.circuits, like matching and shielding.
MicroLab, VLSI-15 (2/36)
JMM v1.4
Sources of ErrorSources of ErrorSources of ErrorSources of ErrorLine registration errorsLine registration errorsLine registration errorsLine registration errorsresist exposure and developmentresist exposure and developmentresist exposure and developmentresist exposure and developmentover/under etching, lateral diffusionover/under etching, lateral diffusionover/under etching, lateral diffusionover/under etching, lateral diffusionuneven topographyuneven topographyuneven topographyuneven topography
OtherOtherOtherOther fabfabfabfab difficultiesdifficultiesdifficultiesdifficultiescontacts andcontacts andcontacts andcontacts and viasviasviasvias only on “flat” surfacesonly on “flat” surfacesonly on “flat” surfacesonly on “flat” surfacesno devices near boundaries of well no devices near boundaries of well no devices near boundaries of well no devices near boundaries of well no poly contacts over diffusionno poly contacts over diffusionno poly contacts over diffusionno poly contacts over diffusion“gate” metal must connect to diffusion“gate” metal must connect to diffusion“gate” metal must connect to diffusion“gate” metal must connect to diffusionminimum metal coverage requirements minimum metal coverage requirements minimum metal coverage requirements minimum metal coverage requirements
Electrical propertiesElectrical propertiesElectrical propertiesElectrical propertiescurrent density limitationscurrent density limitationscurrent density limitationscurrent density limitationslatchlatchlatchlatch----up prevention up prevention up prevention up prevention
We can specify the design rules using some convenient We can specify the design rules using some convenient We can specify the design rules using some convenient We can specify the design rules using some convenient units, e.g., microns but what happens if we want to units, e.g., microns but what happens if we want to units, e.g., microns but what happens if we want to units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers?manufacture the chip using different manufacturers?manufacture the chip using different manufacturers?manufacture the chip using different manufacturers?One suggestion: use an abstract unit, the One suggestion: use an abstract unit, the One suggestion: use an abstract unit, the One suggestion: use an abstract unit, the lambda, lambda, lambda, lambda, and scale and scale and scale and scale the design to the appropriate actual dimensions when the the design to the appropriate actual dimensions when the the design to the appropriate actual dimensions when the the design to the appropriate actual dimensions when the chip is to be manufactured. chip is to be manufactured. chip is to be manufactured. chip is to be manufactured. Usually all edges must be “on grid”, e.g., in the MOSIS Usually all edges must be “on grid”, e.g., in the MOSIS Usually all edges must be “on grid”, e.g., in the MOSIS Usually all edges must be “on grid”, e.g., in the MOSIS scalable rules, all edges must be on a half lambda grid, on scalable rules, all edges must be on a half lambda grid, on scalable rules, all edges must be on a half lambda grid, on scalable rules, all edges must be on a half lambda grid, on the 0.5the 0.5the 0.5the 0.5µµµµmmmm AlcatelAlcatelAlcatelAlcatel all edges must be on 0.05all edges must be on 0.05all edges must be on 0.05all edges must be on 0.05µµµµm grid.m grid.m grid.m grid.
One lambda (One lambda (One lambda (One lambda (λλλλ)= one half of the “minimum” mask )= one half of the “minimum” mask )= one half of the “minimum” mask )= one half of the “minimum” mask dimension, typically the length of a transistor channel.dimension, typically the length of a transistor channel.dimension, typically the length of a transistor channel.dimension, typically the length of a transistor channel.Under the assumption that the worst case alignment is Under the assumption that the worst case alignment is Under the assumption that the worst case alignment is Under the assumption that the worst case alignment is better than 0.75better than 0.75better than 0.75better than 0.75λλλλ, the maximum relative misalignment , the maximum relative misalignment , the maximum relative misalignment , the maximum relative misalignment between any two masks is better than 1.5between any two masks is better than 1.5between any two masks is better than 1.5between any two masks is better than 1.5λλλλ. This can be . This can be . This can be . This can be used to derive design rules and to estimate minimum used to derive design rules and to estimate minimum used to derive design rules and to estimate minimum used to derive design rules and to estimate minimum dimensions of a junction area and perimeter before a dimensions of a junction area and perimeter before a dimensions of a junction area and perimeter before a dimensions of a junction area and perimeter before a transistor has to be laid out.transistor has to be laid out.transistor has to be laid out.transistor has to be laid out.
MicroLab, VLSI-15 (9/36)
JMM v1.4
Lambda vs. Micron RulesLambda vs. Micron RulesLambda vs. Micron RulesLambda vs. Micron RulesLambdaLambdaLambdaLambda----based design rules are based on the assumption based design rules are based on the assumption based design rules are based on the assumption based design rules are based on the assumption that one can scale a design to the appropriate size before that one can scale a design to the appropriate size before that one can scale a design to the appropriate size before that one can scale a design to the appropriate size before manufacture. The assumption is thatmanufacture. The assumption is thatmanufacture. The assumption is thatmanufacture. The assumption is that all manufacturing all manufacturing all manufacturing all manufacturing dimensions scale equallydimensions scale equallydimensions scale equallydimensions scale equally, an assumption that “works” only , an assumption that “works” only , an assumption that “works” only , an assumption that “works” only over some modest span of time. For example: if a design over some modest span of time. For example: if a design over some modest span of time. For example: if a design over some modest span of time. For example: if a design is completed with a poly width of 2is completed with a poly width of 2is completed with a poly width of 2is completed with a poly width of 2λ λ λ λ and a metal width of and a metal width of and a metal width of and a metal width of 3333λ λ λ λ then minimum width metal wires will always be 50% then minimum width metal wires will always be 50% then minimum width metal wires will always be 50% then minimum width metal wires will always be 50% wider than minimum width of poly wires.wider than minimum width of poly wires.wider than minimum width of poly wires.wider than minimum width of poly wires.
Consider the following data fromConsider the following data fromConsider the following data fromConsider the following data from AlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm process m process m process m process (compare with(compare with(compare with(compare with WesteWesteWesteWeste, Table 3.2 pp145):, Table 3.2 pp145):, Table 3.2 pp145):, Table 3.2 pp145):
Scaled design is legalScaled design is legalScaled design is legalScaled design is legalbut much larger thanbut much larger thanbut much larger thanbut much larger thanit needs to be!it needs to be!it needs to be!it needs to be!
So, should one use lambda rules, or not?So, should one use lambda rules, or not?So, should one use lambda rules, or not?So, should one use lambda rules, or not?probably okay for retargeting between “similar” probably okay for retargeting between “similar” probably okay for retargeting between “similar” probably okay for retargeting between “similar” processes, e.g., when later process is a simple processes, e.g., when later process is a simple processes, e.g., when later process is a simple processes, e.g., when later process is a simple “shrink” of the earlier process. This often happens “shrink” of the earlier process. This often happens “shrink” of the earlier process. This often happens “shrink” of the earlier process. This often happens between generations as a midbetween generations as a midbetween generations as a midbetween generations as a mid----life kicker for a life kicker for a life kicker for a life kicker for a process. Some 0.35process. Some 0.35process. Some 0.35process. Some 0.35µµµµm processes are shrinks of m processes are shrinks of m processes are shrinks of m processes are shrinks of an earlier 0.5an earlier 0.5an earlier 0.5an earlier 0.5µµµµm process. Can be useful for m process. Can be useful for m process. Can be useful for m process. Can be useful for ““““fablessfablessfablessfabless” semiconductor companies.” semiconductor companies.” semiconductor companies.” semiconductor companies.most industrial designs use micron rules to get the most industrial designs use micron rules to get the most industrial designs use micron rules to get the most industrial designs use micron rules to get the extra space efficiency. Cost of retargeting by hand extra space efficiency. Cost of retargeting by hand extra space efficiency. Cost of retargeting by hand extra space efficiency. Cost of retargeting by hand is acceptable for a successful product, but usually is acceptable for a successful product, but usually is acceptable for a successful product, but usually is acceptable for a successful product, but usually it’s time for a redesign anyway.it’s time for a redesign anyway.it’s time for a redesign anyway.it’s time for a redesign anyway.invent some way of entering a design symbolically invent some way of entering a design symbolically invent some way of entering a design symbolically invent some way of entering a design symbolically but use a more sophisticated technique for but use a more sophisticated technique for but use a more sophisticated technique for but use a more sophisticated technique for producing the masks for a particular process. producing the masks for a particular process. producing the masks for a particular process. producing the masks for a particular process. Insight: Insight: Insight: Insight: relative sizes may change but topological relative sizes may change but topological relative sizes may change but topological relative sizes may change but topological relationship between components does notrelationship between components does notrelationship between components does notrelationship between components does not. So, . So, . So, . So, instead of shrinking a design, instead of shrinking a design, instead of shrinking a design, instead of shrinking a design, compactcompactcompactcompact it! it! it! it!
MicroLab, VLSI-15 (11/36)
JMM v1.4
0.50.50.50.5µµµµm CMOSm CMOSm CMOSm CMOS Alcatel MietecAlcatel MietecAlcatel MietecAlcatel Mietec ProcessProcessProcessProcessLayers and mask definition: C05MLayers and mask definition: C05MLayers and mask definition: C05MLayers and mask definition: C05M----DDDDlayer namelayer namelayer namelayer name drawndrawndrawndrawn mask namemask namemask namemask nameactiveactiveactiveactive yesyesyesyes activeactiveactiveactivenwellnwellnwellnwell yesyesyesyes nnnn----wellwellwellwellpwellpwellpwellpwell nononono (p(p(p(p----well)well)well)well)polypolypolypoly yesyesyesyes polypolypolypolynplusnplusnplusnplus nononono (n(n(n(n++++ implant)implant)implant)implant)ppluspplusppluspplus yesyesyesyes pppp++++ implantimplantimplantimplantcontactcontactcontactcontact yesyesyesyes contactcontactcontactcontactmetal_1metal_1metal_1metal_1 yesyesyesyes metal 1metal 1metal 1metal 1via_1via_1via_1via_1 yesyesyesyes via 1via 1via 1via 1metal_2metal_2metal_2metal_2 yesyesyesyes metal 2metal 2metal 2metal 2via_2via_2via_2via_2 yesyesyesyes via 2via 2via 2via 2metal_3metal_3metal_3metal_3 yesyesyesyes metal 3metal 3metal 3metal 3nitridenitridenitridenitride yesyesyesyes nitridenitridenitridenitridedractextdractextdractextdractext yesyesyesyes ----nlddnlddnlddnldd no no no no (no low doped drain,(no low doped drain,(no low doped drain,(no low doped drain, ZenerZenerZenerZener))))nlddprotnlddprotnlddprotnlddprot yesyesyesyes ----nplusprotnplusprotnplusprotnplusprot yesyesyesyes ----
MicroLab, VLSI-15 (12/36)
JMM v1.4
nwellnwellnwellnwell
C05MC05MC05MC05M----D: some logical descriptionsD: some logical descriptionsD: some logical descriptionsD: some logical descriptionslogical namelogical namelogical namelogical name used masksused masksused masksused masksnwellnwellnwellnwell ==== nwellnwellnwellnwellpwellpwellpwellpwell ==== nwellnwellnwellnwellnnnn++++diffusiondiffusiondiffusiondiffusion ==== active and active and active and active and ppluspplusppluspplus and polyand polyand polyand polypppp++++diffusiondiffusiondiffusiondiffusion ==== active and active and active and active and ppluspplusppluspplus and polyand polyand polyand polynnnn++++source/drainsource/drainsource/drainsource/drain ==== active and active and active and active and ppluspplusppluspplus and poly and and poly and and poly and and poly and nwellnwellnwellnwellpppp++++source/drainsource/drainsource/drainsource/drain ==== active and active and active and active and ppluspplusppluspplus and poly and and poly and and poly and and poly and nwellnwellnwellnwellgategategategate ==== active and polyactive and polyactive and polyactive and poly
via1 need to bevia1 need to bevia1 need to bevia1 need to becovered by metal2covered by metal2covered by metal2covered by metal2
contacts need to becontacts need to becontacts need to becontacts need to becovered by metal1covered by metal1covered by metal1covered by metal1
contactcontactcontactcontact
via1via1via1via1
via2via2via2via2
contactcontactcontactcontact
via1via1via1via1
via2via2via2via2
0.60.60.60.6µµµµmmmm
0.80.80.80.8µµµµmmmm
MicroLab, VLSI-15 (17/36)
JMM v1.4
Sticks and CompactionSticks and CompactionSticks and CompactionSticks and Compaction
Stick diagramStick diagramStick diagramStick diagram Horizontal constraintsHorizontal constraintsHorizontal constraintsHorizontal constraintsfor compaction in Xfor compaction in Xfor compaction in Xfor compaction in X
Compact X then YCompact X then YCompact X then YCompact X then Y Compact Y then XCompact Y then XCompact Y then XCompact Y then X
Compact X with jogCompact X with jogCompact X with jogCompact X with joginsertion, then Yinsertion, then Yinsertion, then Yinsertion, then Y
MicroLab, VLSI-15 (18/36)
JMM v1.4
Digital Layout: Choosing a “style”Digital Layout: Choosing a “style”Digital Layout: Choosing a “style”Digital Layout: Choosing a “style”
Vertical GatesVertical GatesVertical GatesVertical GatesGood for circuits whereGood for circuits whereGood for circuits whereGood for circuits where fetsfetsfetsfets sizes are sizes are sizes are sizes are similar and each gate has limitedsimilar and each gate has limitedsimilar and each gate has limitedsimilar and each gate has limitedfanoutfanoutfanoutfanout. Best choice for multiple . Best choice for multiple . Best choice for multiple . Best choice for multiple input static gates and forinput static gates and forinput static gates and forinput static gates and for datapathsdatapathsdatapathsdatapaths....
Horizontal GatesHorizontal GatesHorizontal GatesHorizontal GatesGood for circuits where long and Good for circuits where long and Good for circuits where long and Good for circuits where long and shortshortshortshort fetsfetsfetsfets are needed or where nodes are needed or where nodes are needed or where nodes are needed or where nodes must control manymust control manymust control manymust control many fetsfetsfetsfets. Often used . Often used . Often used . Often used in multiplein multiplein multiplein multiple----output complex gates output complex gates output complex gates output complex gates (e.g, sum/carry circuits).(e.g, sum/carry circuits).(e.g, sum/carry circuits).(e.g, sum/carry circuits).
What about routing signals between gates? Note that both layoutWhat about routing signals between gates? Note that both layoutWhat about routing signals between gates? Note that both layoutWhat about routing signals between gates? Note that both layouts block s block s block s block metal/poly routing inside the cell. Choices: metal2 routing ovemetal/poly routing inside the cell. Choices: metal2 routing ovemetal/poly routing inside the cell. Choices: metal2 routing ovemetal/poly routing inside the cell. Choices: metal2 routing over the cell or r the cell or r the cell or r the cell or routing above/below the cell.routing above/below the cell.routing above/below the cell.routing above/below the cell.
avoid long (> 50 squares) poly runsavoid long (> 50 squares) poly runsavoid long (> 50 squares) poly runsavoid long (> 50 squares) poly runsdon’t “capture” white space in a celldon’t “capture” white space in a celldon’t “capture” white space in a celldon’t “capture” white space in a celldon’t obsess over the layout, instead make adon’t obsess over the layout, instead make adon’t obsess over the layout, instead make adon’t obsess over the layout, instead make asecond pass, second pass, second pass, second pass, optimizingoptimizingoptimizingoptimizing where it countswhere it countswhere it countswhere it counts
MicroLab, VLSI-15 (19/36)
JMM v1.4
Digital Layout:Digital Layout:Digital Layout:Digital Layout:OptimisingOptimisingOptimisingOptimising ConnectionsConnectionsConnectionsConnections
Which is the better gate layout?Which is the better gate layout?Which is the better gate layout?Which is the better gate layout?
area = 133area = 133area = 133area = 133µµµµmmmm2222
area = 94area = 94area = 94area = 94µµµµmmmm2222 area = 73area = 73area = 73area = 73µµµµmmmm2222
can’t make gates toocan’t make gates toocan’t make gates toocan’t make gates toolong because of polylong because of polylong because of polylong because of polyresistance! Eventuallyresistance! Eventuallyresistance! Eventuallyresistance! Eventuallyreally large transistorsreally large transistorsreally large transistorsreally large transistorshave to broken into have to broken into have to broken into have to broken into smaller transistors insmaller transistors insmaller transistors insmaller transistors inwired in parallel.wired in parallel.wired in parallel.wired in parallel.
Analog Layout: Large TransistorsAnalog Layout: Large TransistorsAnalog Layout: Large TransistorsAnalog Layout: Large Transistors
W/L can be very large in analog circuitsW/L can be very large in analog circuitsW/L can be very large in analog circuitsW/L can be very large in analog circuitsdue to asymmetric layout, node1 has a smaller due to asymmetric layout, node1 has a smaller due to asymmetric layout, node1 has a smaller due to asymmetric layout, node1 has a smaller capacitor which should be used for the most critical capacitor which should be used for the most critical capacitor which should be used for the most critical capacitor which should be used for the most critical node (high impedance)node (high impedance)node (high impedance)node (high impedance)
Analog Layout: MatchingAnalog Layout: MatchingAnalog Layout: MatchingAnalog Layout: Matching
Using lithography techniques a variety of twoUsing lithography techniques a variety of twoUsing lithography techniques a variety of twoUsing lithography techniques a variety of two----dimensional effects can cause effective sizes of dimensional effects can cause effective sizes of dimensional effects can cause effective sizes of dimensional effects can cause effective sizes of components to differ from the sizes of the glass components to differ from the sizes of the glass components to differ from the sizes of the glass components to differ from the sizes of the glass layout masks.layout masks.layout masks.layout masks.
Goal:Goal:Goal:Goal: Matching secondMatching secondMatching secondMatching second----order size error effects is done order size error effects is done order size error effects is done order size error effects is done mainly by making larger objects out of several unitmainly by making larger objects out of several unitmainly by making larger objects out of several unitmainly by making larger objects out of several unit----sized components connected together. For best sized components connected together. For best sized components connected together. For best sized components connected together. For best accuracy, the bounding conditions around all objects accuracy, the bounding conditions around all objects accuracy, the bounding conditions around all objects accuracy, the bounding conditions around all objects should be matched, even when this means adding should be matched, even when this means adding should be matched, even when this means adding should be matched, even when this means adding extra unused components.extra unused components.extra unused components.extra unused components.
useuseuseuse interdigitatedinterdigitatedinterdigitatedinterdigitatedfinger structures finger structures finger structures finger structures for keeping the for keeping the for keeping the for keeping the effect of temp effect of temp effect of temp effect of temp and oxide and oxide and oxide and oxide thickness thickness thickness thickness gradients lowgradients lowgradients lowgradients lowuse one outside use one outside use one outside use one outside finger for M1, one finger for M1, one finger for M1, one finger for M1, one for M2for M2for M2for M2symmetry in x & ysymmetry in x & ysymmetry in x & ysymmetry in x & yfetsfetsfetsfets in analog in analog in analog in analog circuitry are circuitry are circuitry are circuitry are typically much typically much typically much typically much wider than in wider than in wider than in wider than in digital circuitsdigital circuitsdigital circuitsdigital circuits
materialmaterialmaterialmaterialpreferable poly1 preferable poly1 preferable poly1 preferable poly1 ---- poly2 structures (only C05Mpoly2 structures (only C05Mpoly2 structures (only C05Mpoly2 structures (only C05M----A)A)A)A)if not available: poly1 if not available: poly1 if not available: poly1 if not available: poly1 ---- diffusion (C05Mdiffusion (C05Mdiffusion (C05Mdiffusion (C05M----D), but D), but D), but D), but nonlinear due to voltage dependencynonlinear due to voltage dependencynonlinear due to voltage dependencynonlinear due to voltage dependencysandwich structures with poly sandwich structures with poly sandwich structures with poly sandwich structures with poly ---- metal1metal1metal1metal1
in analog design very often precise ratios of in analog design very often precise ratios of in analog design very often precise ratios of in analog design very often precise ratios of capacitors are usedcapacitors are usedcapacitors are usedcapacitors are usedmajor sources of errors in realized capacitors are major sources of errors in realized capacitors are major sources of errors in realized capacitors are major sources of errors in realized capacitors are due todue todue todue to overetchingoveretchingoveretchingoveretching and something less relevant is and something less relevant is and something less relevant is and something less relevant is an oxide thickness gradient across the surface.an oxide thickness gradient across the surface.an oxide thickness gradient across the surface.an oxide thickness gradient across the surface.
Goal:Goal:Goal:Goal: Larger capacitors are realized by a parallel Larger capacitors are realized by a parallel Larger capacitors are realized by a parallel Larger capacitors are realized by a parallel combination of smaller unitcombination of smaller unitcombination of smaller unitcombination of smaller unit----sized capacitors sized capacitors sized capacitors sized capacitors ((((overetchingoveretchingoveretchingoveretching). If unit). If unit). If unit). If unit----size capacitors are not size capacitors are not size capacitors are not size capacitors are not realizable,realizable,realizable,realizable, overetchingoveretchingoveretchingoveretching can still be minimized by can still be minimized by can still be minimized by can still be minimized by realizing arealizing arealizing arealizing a nonunitnonunitnonunitnonunit----sized capacitor with a specific sized capacitor with a specific sized capacitor with a specific sized capacitor with a specific perimeterperimeterperimeterperimeter----to area ratio. For very accurate ratios to area ratio. For very accurate ratios to area ratio. For very accurate ratios to area ratio. For very accurate ratios additionally commonadditionally commonadditionally commonadditionally common----centroidcentroidcentroidcentroid layout is used (oxide layout is used (oxide layout is used (oxide layout is used (oxide thickness gradient). thickness gradient). thickness gradient). thickness gradient).
unit sized capacitors Cunit sized capacitors Cunit sized capacitors Cunit sized capacitors C1111 are squaredare squaredare squaredare squarednonunitnonunitnonunitnonunit----sized capacitors Csized capacitors Csized capacitors Csized capacitors C2222 are rectangular and are rectangular and are rectangular and are rectangular and usually between 1 and 2 times unitusually between 1 and 2 times unitusually between 1 and 2 times unitusually between 1 and 2 times unit----sized capacitors sized capacitors sized capacitors sized capacitors (K>1)(K>1)(K>1)(K>1)
perimeterperimeterperimeterperimeter----totototo----area ratio should be kept identicalarea ratio should be kept identicalarea ratio should be kept identicalarea ratio should be kept identical
material: many different materials can be used. material: many different materials can be used. material: many different materials can be used. material: many different materials can be used. They have different nonThey have different nonThey have different nonThey have different non----ideal effects. Absolute ideal effects. Absolute ideal effects. Absolute ideal effects. Absolute accuracy is low (+accuracy is low (+accuracy is low (+accuracy is low (+----20% or less), matching can be 20% or less), matching can be 20% or less), matching can be 20% or less), matching can be made to be in the order of 1% at most.made to be in the order of 1% at most.made to be in the order of 1% at most.made to be in the order of 1% at most.
polysilicon (polysilicon (polysilicon (polysilicon (salicidedsalicidedsalicidedsalicided and nonand nonand nonand non salicidedsalicidedsalicidedsalicided in C05Min C05Min C05Min C05M----A and A and A and A and C05MC05MC05MC05M----D process)D process)D process)D process)diffusions or iondiffusions or iondiffusions or iondiffusions or ion----implanted regions (n/pimplanted regions (n/pimplanted regions (n/pimplanted regions (n/p----diff, ndiff, ndiff, ndiff, n----well)well)well)well)
sqRWLR =
tRsq
ρ=
materialmaterialmaterialmaterial typ Rsqtyp Rsqtyp Rsqtyp Rsq temptemptemptemp coeffcoeffcoeffcoeff nonidealitynonidealitynonidealitynonidealitymetal1metal1metal1metal1 72m72m72m72mΩΩΩΩ 0000 not usednot usednot usednot usedmetal2metal2metal2metal2 55m55m55m55mΩΩΩΩ 0000 not usednot usednot usednot usedmetal3metal3metal3metal3 34m34m34m34mΩΩΩΩ 0000 not usednot usednot usednot usedsalicidsalicidsalicidsalicid polypolypolypoly 2.32.32.32.3ΩΩΩΩ 4300ppm/C4300ppm/C4300ppm/C4300ppm/C parasitic capparasitic capparasitic capparasitic capnnnn++++ diffdiffdiffdiff salsalsalsal 2.32.32.32.3ΩΩΩΩ 4300ppm/C4300ppm/C4300ppm/C4300ppm/C vvvv depdepdepdep, non, non, non, non linlinlinlinpppp++++ diffdiffdiffdiff salsalsalsal 2.12.12.12.1ΩΩΩΩ 4300ppm/C4300ppm/C4300ppm/C4300ppm/C vvvv depdepdepdep,,,, nonlinnonlinnonlinnonlinunsalunsalunsalunsal nnnn++++polypolypolypoly 325325325325ΩΩΩΩ −−−−2000200020002000ppm/Cppm/Cppm/Cppm/C parasitic capparasitic capparasitic capparasitic capnnnn++++ diffdiffdiffdiff unsalunsalunsalunsal 50505050ΩΩΩΩ 1600ppm/C1600ppm/C1600ppm/C1600ppm/C vvvv depdepdepdep, non, non, non, non linlinlinlinpppp++++ diffdiffdiffdiff unsalunsalunsalunsal 70707070ΩΩΩΩ 1600ppm/C1600ppm/C1600ppm/C1600ppm/C vvvv depdepdepdep,,,, nonlinnonlinnonlinnonlinnnnn----wellwellwellwell 1.3k1.3k1.3k1.3kΩΩΩΩ 4300ppm/C4300ppm/C4300ppm/C4300ppm/C v dependentv dependentv dependentv dependent
Analog Layout: Analog Layout: Analog Layout: Analog Layout: Noise Considerations #1Noise Considerations #1Noise Considerations #1Noise Considerations #1
Where does noise coupling occurWhere does noise coupling occurWhere does noise coupling occurWhere does noise coupling occurevery time a digital gate changes its state a glitch every time a digital gate changes its state a glitch every time a digital gate changes its state a glitch every time a digital gate changes its state a glitch is injected on the digital power supply and in the is injected on the digital power supply and in the is injected on the digital power supply and in the is injected on the digital power supply and in the surrounding substratesurrounding substratesurrounding substratesurrounding substratedirectdirectdirectdirect ohmicohmicohmicohmic connections (power supply line)connections (power supply line)connections (power supply line)connections (power supply line)via electromagnetic fields (e.g. capacitive coupling via electromagnetic fields (e.g. capacitive coupling via electromagnetic fields (e.g. capacitive coupling via electromagnetic fields (e.g. capacitive coupling in and from substrate)in and from substrate)in and from substrate)in and from substrate)
How can noise be reducedHow can noise be reducedHow can noise be reducedHow can noise be reduceduse of different power supply linesuse of different power supply linesuse of different power supply linesuse of different power supply lineslayout analog and digital circuitry in different layout analog and digital circuitry in different layout analog and digital circuitry in different layout analog and digital circuitry in different sections of the chipsections of the chipsections of the chipsections of the chipprotect analog layout by guard ringsprotect analog layout by guard ringsprotect analog layout by guard ringsprotect analog layout by guard ringsuse shields connected to power and grounduse shields connected to power and grounduse shields connected to power and grounduse shields connected to power and ground
analog partanalog partanalog partanalog part digital partdigital partdigital partdigital part
padpadpadpad
pinpinpinpin
power supplypower supplypower supplypower supply
analog partanalog partanalog partanalog part digital partdigital partdigital partdigital part
padpadpadpad
pinpinpinpin
power supplypower supplypower supplypower supply
analog partanalog partanalog partanalog part digital partdigital partdigital partdigital part
power supplypower supplypower supplypower supply
padpadpadpadpadpadpadpad
pinpinpinpin
padpadpadpad
pinpinpinpin
MicroLab, VLSI-15 (31/36)
JMM v1.4
Analog Layout: Analog Layout: Analog Layout: Analog Layout: Noise Considerations #2Noise Considerations #2Noise Considerations #2Noise Considerations #2
Use of shieldsUse of shieldsUse of shieldsUse of shields
analog interconnectanalog interconnectanalog interconnectanalog interconnect digital interconnectdigital interconnectdigital interconnectdigital interconnect
Separate analog and digital parts with guard ringsSeparate analog and digital parts with guard ringsSeparate analog and digital parts with guard ringsSeparate analog and digital parts with guard rings
Summary of Analog Layout RulesSummary of Analog Layout RulesSummary of Analog Layout RulesSummary of Analog Layout Rules
When drawing layout for analog circuits, one has to When drawing layout for analog circuits, one has to When drawing layout for analog circuits, one has to When drawing layout for analog circuits, one has to consider many detailsconsider many detailsconsider many detailsconsider many detailslayout design rules, in order to get correct circuits layout design rules, in order to get correct circuits layout design rules, in order to get correct circuits layout design rules, in order to get correct circuits without shortcuts between layers, or open circuits without shortcuts between layers, or open circuits without shortcuts between layers, or open circuits without shortcuts between layers, or open circuits due to misaligned layersdue to misaligned layersdue to misaligned layersdue to misaligned layersavoid parasitic componentsavoid parasitic componentsavoid parasitic componentsavoid parasitic components
resistors: take care of length of interconnect wires and resistors: take care of length of interconnect wires and resistors: take care of length of interconnect wires and resistors: take care of length of interconnect wires and material used for interconnects Add enough contacts.material used for interconnects Add enough contacts.material used for interconnects Add enough contacts.material used for interconnects Add enough contacts.Capacitors: There is a parasitic capacitor between any Capacitors: There is a parasitic capacitor between any Capacitors: There is a parasitic capacitor between any Capacitors: There is a parasitic capacitor between any two isolation layers. Minimize size of all areas that do two isolation layers. Minimize size of all areas that do two isolation layers. Minimize size of all areas that do two isolation layers. Minimize size of all areas that do not need to have a specific size for their functionality.not need to have a specific size for their functionality.not need to have a specific size for their functionality.not need to have a specific size for their functionality.
Increase matching accuracy byIncrease matching accuracy byIncrease matching accuracy byIncrease matching accuracy byusing commonusing commonusing commonusing common centroidcentroidcentroidcentroid layoutlayoutlayoutlayoutusing non minimum sized componentsusing non minimum sized componentsusing non minimum sized componentsusing non minimum sized componentsusing capacitors with constant area to perimeter ratiousing capacitors with constant area to perimeter ratiousing capacitors with constant area to perimeter ratiousing capacitors with constant area to perimeter ratio
reduce noise coupling byreduce noise coupling byreduce noise coupling byreduce noise coupling byseparating analog and digital partsseparating analog and digital partsseparating analog and digital partsseparating analog and digital partsusing separate power suppliesusing separate power suppliesusing separate power suppliesusing separate power suppliesusing shielding techniquesusing shielding techniquesusing shielding techniquesusing shielding techniques
MicroLab, VLSI-15 (33/36)
JMM v1.4
Checking LayoutsChecking LayoutsChecking LayoutsChecking LayoutsDesign Rule CheckerDesign Rule CheckerDesign Rule CheckerDesign Rule Checker (DRC). This is a program that checks each (DRC). This is a program that checks each (DRC). This is a program that checks each (DRC). This is a program that checks each
piece of the layout against the process design rules. This is apiece of the layout against the process design rules. This is apiece of the layout against the process design rules. This is apiece of the layout against the process design rules. This is aslow process:slow process:slow process:slow process:
canonicalizecanonicalizecanonicalizecanonicalize layout into a set of leading andlayout into a set of leading andlayout into a set of leading andlayout into a set of leading andtrailing nontrailing nontrailing nontrailing non----overlapping mask edges. Some Boolean mask overlapping mask edges. Some Boolean mask overlapping mask edges. Some Boolean mask overlapping mask edges. Some Boolean mask operations may be needed. determine electrical connectivity operations may be needed. determine electrical connectivity operations may be needed. determine electrical connectivity operations may be needed. determine electrical connectivity and label each edge with the node it belongs to.and label each edge with the node it belongs to.and label each edge with the node it belongs to.and label each edge with the node it belongs to.test each edge end point against neighboringtest each edge end point against neighboringtest each edge end point against neighboringtest each edge end point against neighboringedges to check for spacing (leading edges) and width edges to check for spacing (leading edges) and width edges to check for spacing (leading edges) and width edges to check for spacing (leading edges) and width (trailing edges) violations.(trailing edges) violations.(trailing edges) violations.(trailing edges) violations.
Layout vs. SchematicLayout vs. SchematicLayout vs. SchematicLayout vs. Schematic (LVS). First a netlist is (LVS). First a netlist is (LVS). First a netlist is (LVS). First a netlist is extracted extracted extracted extracted from the from the from the from the layout. Use the electrical info generated by the DRC and then layout. Use the electrical info generated by the DRC and then layout. Use the electrical info generated by the DRC and then layout. Use the electrical info generated by the DRC and then recognize transistors are juxtapositions of channel with recognize transistors are juxtapositions of channel with recognize transistors are juxtapositions of channel with recognize transistors are juxtapositions of channel with diffusion. Then see if extracted netlist is diffusion. Then see if extracted netlist is diffusion. Then see if extracted netlist is diffusion. Then see if extracted netlist is isomorphicisomorphicisomorphicisomorphic to the to the to the to the schematic netlist. This is done by a coloring algorithm:schematic netlist. This is done by a coloring algorithm:schematic netlist. This is done by a coloring algorithm:schematic netlist. This is done by a coloring algorithm:
initialize all nodes to the same colorinitialize all nodes to the same colorinitialize all nodes to the same colorinitialize all nodes to the same colorcompute a new color for each node as some hashing compute a new color for each node as some hashing compute a new color for each node as some hashing compute a new color for each node as some hashing function involving the colors of connected (function involving the colors of connected (function involving the colors of connected (function involving the colors of connected (ieieieie, thru a, thru a, thru a, thru a fetfetfetfet) ) ) ) nodes.nodes.nodes.nodes.nodes that have a unique color are isomorphic to similarly nodes that have a unique color are isomorphic to similarly nodes that have a unique color are isomorphic to similarly nodes that have a unique color are isomorphic to similarly colored node in other networkcolored node in other networkcolored node in other networkcolored node in other networkworry about parallelworry about parallelworry about parallelworry about parallel fetsfetsfetsfets, ambiguous nodes, ambiguous nodes, ambiguous nodes, ambiguous nodes
MicroLab, VLSI-15 (34/36)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic:Next topic:Next topic:Next topic:Small signalSmall signalSmall signalSmall signal fetfetfetfet modelmodelmodelmodel
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WesteWesteWesteWeste: : : :
3.4 through 3.4.73.4 through 3.4.73.4 through 3.4.73.4 through 3.4.7
OptionalOptionalOptionalOptionalhave a look athave a look athave a look athave a look at AlcatelAlcatelAlcatelAlcatel CMOS C05MCMOS C05MCMOS C05MCMOS C05M----D design rules D design rules D design rules D design rules manualmanualmanualmanual
Ex vlsi15.1 (difficulty: easy):Ex vlsi15.1 (difficulty: easy):Ex vlsi15.1 (difficulty: easy):Ex vlsi15.1 (difficulty: easy): Assume the 0.5Assume the 0.5Assume the 0.5Assume the 0.5µµµµmmmmAlcatel MietecAlcatel MietecAlcatel MietecAlcatel Mietec process. Use the process. Use the process. Use the process. Use the λ rules to rules to rules to rules to calculate the minimal area and perimeter of the calculate the minimal area and perimeter of the calculate the minimal area and perimeter of the calculate the minimal area and perimeter of the following layout structure. following layout structure. following layout structure. following layout structure.
Result: a) AResult: a) AResult: a) AResult: a) AJ1J1J1J1=4.5=4.5=4.5=4.5µµµµmmmm2222, A, A, A, AJ2J2J2J2=3.188=3.188=3.188=3.188µµµµmmmm2222, , , , AAAAJ3J3J3J3=2.25=2.25=2.25=2.25µµµµmmmm2222, P, P, P, PJ1J1J1J1=6=6=6=6µµµµm, Pm, Pm, Pm, PJ2J2J2J2=6=6=6=6µµµµm, m, m, m, PPPPJ3J3J3J3=1.5=1.5=1.5=1.5µµµµm (see Johns&Martin pp99)m (see Johns&Martin pp99)m (see Johns&Martin pp99)m (see Johns&Martin pp99)
John&Martin pp110: 2.3 (difficulty: easy):John&Martin pp110: 2.3 (difficulty: easy):John&Martin pp110: 2.3 (difficulty: easy):John&Martin pp110: 2.3 (difficulty: easy): Show a Show a Show a Show a layout that might be used to match two capacitors layout that might be used to match two capacitors layout that might be used to match two capacitors layout that might be used to match two capacitors of size 4 and 2.314 units, where a unitof size 4 and 2.314 units, where a unitof size 4 and 2.314 units, where a unitof size 4 and 2.314 units, where a unit----sized sized sized sized capacitor is 10capacitor is 10capacitor is 10capacitor is 10µµµµm x 10m x 10m x 10m x 10µµµµm. m. m. m.
Today’s handouts:(1) Lecture Slides(2) Problem Set #5(3) Inverter Layout Tutorial
Measure twice, fab once
MicroLab, VLSI-16 (2/16)
JMM/ESA v1.0
Design for Re-use
w what’s the schematic for this cell?
w what are the “fat” fets?
w Cell was designed for placement “under” ametal2/metal3 routing grid. How was thelayout affected by this design requirement?
MicroLab, VLSI-16 (3/16)
JMM/ESA v1.0
Replicating Cells
What does this cell do?
What if we want to replicate this cell vertically, i.e., make a stack ofthe cells, to process many bits in parallel?
w what nodes are shared among the cells?w what nodes aren’t shared?w how should we arrange the cells vertically?
MicroLab, VLSI-16 (4/16)
JMM/ESA v1.0
Vertical Replication
Reflect cell about X axisso that Pfets are nextto each other: this avoidslarge ndiff/pdiff spacing.
Place shared geometrysymmetrically aboutshared boundary.
Place items that aren’tto be shared 1/2 minspacing rule from sharedboundary.
Run shared controlsignals vertically -- they’llwire themselves upautomatically?
MicroLab, VLSI-16 (5/16)
JMM/ESA v1.0
Vertical Intercell Routing
S’pose we have a signalthat will run vertically fromone cell to the next, e.g., thecarry-out from one cell becomesthe carry-in for the cell above.
Looks okay until we reflect thecell when we do the verticalreplication!
carry-in fromcell below
carry-out tocell above
Solution: we have to do therouting for vertical intercellsignals for a pair of cells,then replicate the pair(complete with routing)vertically.
MicroLab, VLSI-16 (6/16)
JMM/ESA v1.0
Building a DatapathIt’s often the case that we want to operate on many bits in parallel. A sensible way to arrange the layout of this sort of logic is as a datapathwhere data signals run horizontally between functional units andcontrol signals run vertically to all the bits of a particular functional unit:
bit #0
bit #1
bit #2
bit #3
data
control
Logic that generates the control signals can be placed at the bottom ofthe datapath. If control logic is complicated or irregular, it might be placed in a separate standard cell block and only the control signal buffers placed placed just below the datapath. Although it’s temptingto run control signals in poly (so they can control fets) this is unwise for tall datapaths because of poly resistance (e.g., 32 bits x 20u/bit= 640u = ~1000 squares = ~20k ohms!)
MicroLab, VLSI-16 (7/16)
JMM/ESA v1.0
Datapath Bit PitchHow tall should we make each bit of the datapath?That depends onw the width of the nfets and pfetsw how much in-cell routing there isw how much over-the-cell global routing there is
Global routes can be determined from datapath schematic:
SHIF
TER
BOOL
E
MULT
ADDE
R
OP EN OP EN EN ENCIN
OP1OP2
RESULT
Three global routingtracks required
Internal routing maytake additional tracks
vdd (m2)
gnd (m2)
global route (m2)
in-cell route (m2) control (m1)
Cell routing plan:
MicroLab, VLSI-16 (8/16)
JMM/ESA v1.0
Adder Datapath
tristate output enable control logic
32-bit register w/ tristate driver
32-bit carry-lookahead adder
power strapping (M1=GND, M3-VDD)
MicroLab, VLSI-16 (9/16)
JMM/ESA v1.0
Shifter Datapath
<<16 <<1 <<8 <<2 <<4shift right
>>4 >>2 >>8
MicroLab, VLSI-16 (10/16)
JMM/ESA v1.0
Design for Re-use
w what’s this cell do?
w what are the “fat” fets?
w Cell was designed for placement “under” ametal2/metal3 routing grid. How was thelayout affected by this design requirement?
MicroLab, VLSI-16 (11/16)
JMM/ESA v1.0
Breaking the Rules
BIT BIT
word line
w How are neighboring cells placed?w Isn’t the word line a long poly wire?w Where’s the p-substrate contact?
MicroLab, VLSI-16 (12/16)
JMM/ESA v1.0
Coming Up...
Next time:Scaling effects, fundamental limits. Submicron design issues. Power dissipation and packaging.
Readings for next time…Weste: 6.3.7 through 6.3.9
MicroLab, VLSI-17 (1/20)
JMM/ESA v1.0
Intro to VLSI SystemsPredicting the Future
Today’s handouts:(1) Lecture Slides(2) Mead and Conway, Chapter 9
(1981)
…I see… I see… a supercomputerthe size of a sugar cube...!
Neat. Where do I invest?
MicroLab, VLSI-17 (2/20)
JMM/ESA v1.0
Scaling
Over time, process improvements will allow MOSFETs to scale down by some factor α
What happens?
“Scaling Theory” is a model which provides first order predictions.
l/α
w/α
t/α
xj/α
tox/α
α NA
MicroLab, VLSI-17 (3/20)
JMM/ESA v1.0
Often, different dimensions will scale at different rates. But for an overall picture of what the future portends, there are two major scaling models:
1. Constant Voltage ScalingAll spatial dimensions scale equally:
W W/α
L L/α
tox tox/α
and some other dimensions do as well:d d/α depletion thickness
NA α NA doping
2. Constant Field - scale VDD too:V V/α
so that electric fields remain the same
MicroLab, VLSI-17 (4/20)
JMM/ESA v1.0
First, let’s consider constant field scaling, and use basic MOSFET models to predict the effect of scaling by α
Parameters EffectW/LCg = Cox W LId Cox (W/L) (Vgs-Vt) 2
device power = V IArea = W L device power / AreaRdiff
Rmetal
Rpoly
MicroLab, VLSI-17 (5/20)
JMM/ESA v1.0
Speedup!
Transit time τ scales as ___________
Can also compute as time to discharge gate capacitance:
Gate discharge time scales as _________
e-τ = L/(µE)
delay=Cg V/I
L
MicroLab, VLSI-17 (6/20)
JMM/ESA v1.0
Interconnect
Local (metal) Interconnect Delay = RC
R = ___________Scaled R = R ________C = ____________Scaled C = C ________
Scaled Delay = delay ___________
This turns out to be an overoptimistic prediction -more later...
L
I
Wt
d
MicroLab, VLSI-17 (7/20)
JMM/ESA v1.0
Scaling Table
First Order Scaling (Weste Table 4.12)
Parameter Scaling Model Constant Field Consant Voltage Lateral
Dynamic Power Dissipation 1/a^2 a aPower-delay product 1/a^3 1/a 1/a
Gate Area 1/a^2 1/a^2 1/aPower-density (VI/A) 1 a^3 a^2
Current Density a a^3 a^2
In lateral scaling, we onlychange the channel length L
Devices get faster, lower power,though current density goes up.
Devices get even faster,though overall power andpower density rise
MicroLab, VLSI-17 (8/20)
JMM/ESA v1.0
Die SizeWith basic scaling of the same system, we’d just end
up with smaller and smaller chips.
However, from year to year, the overall die size stays about the same or grows as we add features to the chip.
Fab improvements (mostly, bigger wafers) are what allow for bigger die.
Because the die doesn’t shrink, global interconnect, particularly clocks and on-chip buses, don’t shrink either.
MicroLab, VLSI-17 (9/20)
JMM/ESA v1.0
Global Interconnect Scaling
Interconnect scaling for global signals:
scaled R = R * α 2
scaled C = Cscaled delay = delay * α 2
Even worse: wire starts looking like lossy distributed rc wire - O(L2) delay!
In the submicron domain, this increased significance of wire has led to major CAD industry turmoil.
W/α t/α
L
d
MicroLab, VLSI-17 (10/20)
JMM/ESA v1.0
Power Scaling
Power per chip increases with constant voltage scaling and when die size grows. How does this affect us?
Junction temperature is a function of power and thermal resistance θja to environment.
Example: a 30W chip at 27 C ambient.Junction temp. = 27C + 30W*θja
Heat through pinsto PC board
chip
heat sink
θja=0.1 C/W
θja=2 C/W
Junction temp = ___________
Junction temp = _______
MicroLab, VLSI-17 (11/20)
JMM/ESA v1.0
In the submicron domain, it’s difficult to scale VDD, so power faces the “constant voltage” scaling of α2
This adds impetus to the already-important goal of reducing power of VLSI systems. Some of the main ways of doing this:
1. Reduce unnecessary on-chip transitions by careful logic design, or by disabling the clock to idle systems.
2. Reduce voltage, use more parallelism.
3. Adiabatic logic.
MicroLab, VLSI-17 (12/20)
JMM/ESA v1.0
Problems with scaling theory
Can one scale indefnitely? No.
What are the limits?
Are they fundamental limits?
Are they technical limitations?
Is the current technology close to those limits?
Is there any difference?
MicroLab, VLSI-17 (13/20)
JMM/ESA v1.0
Some limits
Current Density J increases with αL
I
Wt
Metal migration imposes a limit on current density.==> Thicker wires and more metal
layers needed.==> Increased fringing capacitance with
thicker wires.
J=I/(Wt)scaled I = I /αscaled J = J α
Punchthrough: source/drain depletion regions touch
L
Xd
VPT=(L2 q NA)/(2ε)
MicroLab, VLSI-17 (14/20)
JMM/ESA v1.0
Subthreshold leakage
Subthreshold conductance is proportional to
exp(- )
We can scale Vt by α via ion implantation.
kT/q = 0.025V does not scale.
Vt falls =====> Subthreshold current ______________ exponentially.
Example: Vt = 0.5V means that leakage current time constant is 10 7 τ
Vt = 0.1V means that leakage current time constant is 10 1 τ
Vgs-Vt
kT/q
MicroLab, VLSI-17 (15/20)
JMM/ESA v1.0
Threshold Variations
Threshold varies from transistor to transistor.
VDD
If pullup has “big” threshold,pulldown has “small” threshold,
and sum of variances > VDDthen inverter will not invert
(Vout = 0V always.)
Vout
How likely is this?
MicroLab, VLSI-17 (16/20)
JMM/ESA v1.0
Threshold Variations, cont.
Analyze using Gaussian distribution.
P(given inverter fails) = exp(-4 VDD / ∆Vth)
For given inverter...
∆Vth = 0.08V, (Mead & Conway, p. 343)VDD = 5V ===> P = 10-110
VDD = 0.5V ===> P = 10-11
But with 10,000,000 transistors on the chip, a broken chip is very likely.
Question: Should threshold varianceincrease or decrease with scaling?
MicroLab, VLSI-17 (17/20)
JMM/ESA v1.0
Lithographic Scaling Limits
Ultraviolet = λ = 0.3 µX-Ray Lithography, λ = __________Synchrotron lithography?Wavelength of an electron?Cost of FABs.Optical tricks.
Insert p. 1110 of Halliday and Resnick Here
MicroLab, VLSI-17 (18/20)
JMM/ESA v1.0
Fundamental Physical Limits
ThermodynamicHow much entropy change to set a bit?Reversability
Quantum LimitsTunnelling For Eb of 1eV, the gate oxides and depletion layers must be thicker than 1 nm. In the IBM 0.4um process, the gate thickness is 7 nm.
Thermal Limits
MicroLab, VLSI-17 (19/20)
JMM/ESA v1.0
Is this the beginning of the end?
Not really.
VLSI is not yet really up against any fundamental physical constraint.
The constraints that we’re facing are technological hurdles.
With sufficient economic incentive, technological hurdles are cleared.
Wires are a lot more important than in the past.
MicroLab, VLSI-17 (20/20)
JMM/ESA v1.0
Coming Up...
Next topic…MOS memories. Static and dynamic RAM cells. Single and double-ended bit line sensing. Multiport register files.
Readings for next time…Weste: 4.13
MicroLab, VLSI-18 (1/21)
JMM/ESA v1.0
Intro to VLSI SystemsCMOS Memories
Today’s handouts:(1) Lecture Slides
I wonder which partdoes the remembering?
MicroLab, VLSI-18 (2/21)
JMM/ESA v1.0
Semiconductor Memories
Read-only memories: ROM (non-volatile!)Mask programmedProgrammable ROM (PROM)Erasable PROM (EPROM)Electrically Erasable PROM (EEPROM)
Read/Write or Random Access memories: RAMStatic RAM (SRAM)
Dynamic RAM (DRAM)Serial-access video memories (VRAM)Synchronous DRAM (SDRAM)RAMBUS...
Usually the majority of transistors found in a modern system are devotedto data storage in the form of random-access memories. The need for increased densities and lower prices has driven the development ofimproved VLSI technology.
Uses:“main” memory ⇒ high capacity, low costcache memories, TLB’s ⇒ fast accessprogramming info (eg, FPGA) ⇒ non-volatile
MicroLab, VLSI-18 (3/21)
JMM/ESA v1.0
Design Tradeoffs
density: bits/unit area. Usually higher densityalso means lower cost per bit. Improvements dueto finer lithography, better capacitor structures,new materials with higher dielectric constants.
Speed: access time (latency) and bandwidth. Improvements due tobetter sensing (smaller voltage swing), increased parallelism(overlapped accesses), faster I/O.
Power consumption: want power todepend on access pattern notquantity of bits stored.Improvements due to lower supply voltage.
Improvements in one dimension comeat an increased cost in the other
dimensions.
MicroLab, VLSI-18 (4/21)
JMM/ESA v1.0
Memory Architecture
Row
Addr
ess D
ecod
erCol.
1Col.2
Col.3
Col.2M
Row 1
Row 2
Row 2N
Column DecoderM
N
N+M
bit lines word lines
memorycell
(one bit)
D
DATA
w Most memory layouts are “folded”, i.e., D < M. Why?w What are there practical upper bounds on M and N?w What if you want even more memory?w Why only one bit per cell? (Not a silly question!)w Why are “page-mode” accesses a good idea?
MicroLab, VLSI-18 (5/21)
JMM/ESA v1.0
ROM Circuits
R1
R2
R3
R4
C1 C2 C3 C4
NOR-basedROM array
R11000
R20100
R30010
R40001
C10010
C21001
C30101
C41110
sharedground
sharedbit linecontact
MicroLab, VLSI-18 (6/21)
JMM/ESA v1.0
ROM Layout
GND
VDD
ground andword linerefresh
pulldown
nopulldown
w Which are the word lines? the bit lines?w Why are the word lines “strapped” with M2?w What layers change when programming changes?w How often should signals be refreshed?
sharedground
sharedcontact
MicroLab, VLSI-18 (7/21)
JMM/ESA v1.0
ROM PerformancetACCESS = tROW DECODE + tCOLUMN + tCOL DECODE
tROW DECODE:If ROM is large, row decode logic is just a small percentage of total area. So we can make the driver for the word line large and thus fast. Note that we need to strap the poly word line toeliminate slow down due to poly resistance.
tCOL DECODE:As with the row decode logic, we can increase speed by increasing size of transistors in this section.
t COLUMN:We want small program transistors to keep the total area of ROM as small as possible. Also increasing size of pulldowns increases load on both word and bit lines. This means we’re limited in the speed we can achieve in pulling down the column.If CPD,DRAIN = 10fF and we have 128 rows:
Sense AmplifiersLet’s speed things up by sensing small changes in the bit line voltage using a sense amplifier:
R1
R2
C1
C1
C0
C0
column(tree)decoder
SENSE AMPtenths of a voltamplified to fullrail-to-rail swing
MicroLab, VLSI-18 (9/21)
JMM/ESA v1.0
Single-ended Sense Amp
series fets incolumn decoder
memory cell pulldowns(connected to bit line)
bit line(pullup built into
sense amp)
word line -- enables pulldownwhen row is selected
voltagereference(fets sizedto produceVREF = 3V)
M1
M2
M3
M4
MC
MD
1
2
Choose fet sizes so thatM2, MD >> MC >> M1
M3 >> M4
When bit line is not pulled down, V1 = VDD and V2 = VREF - Vth = 2V, so M3is off and M4 is on and the output is pulled low.
When a bit line pulldown is turned on, V2 starts to drop andM2 conducts well enough so that V1 drops to V2 since MC >> M1. When V1and V2 drop 0.5V to 1.5V, M3 is strongly conducting and M4 is weakly conducting, so output goes high. So small ∆V on bit line produces large output swing.
MicroLab, VLSI-18 (10/21)
JMM/ESA v1.0
SRAM Circuitsprecharge or VDD
6-T SRAM Cell
word line
Differential Sense Amp
write
wdata
bit bit
access fet
staticbistablestorageelement
long-channelfet used ascurrent source
prechargeor VDD
clk
clockedcross-coupled
sense amp
rdata
tie bulk tosource ifpossible
Use CLK ifpossible toreduce powerand improvespeed
MicroLab, VLSI-18 (11/21)
JMM/ESA v1.0
6-T SRAM Cell Layout
inverterpullup
inverterpulldown
access fetstrappedword line
VDD
GND
bit line bit line
Pulldowns do the work when access fet is turnedon, pullups can be small to save space and makethe cell easy to write.
MicroLab, VLSI-18 (12/21)
JMM/ESA v1.0
SRAM Read CycleVDD
6-T SRAM Cell
bit bit
word
word
bitVDD
data1
wordbit
bit
1
volts
time
Choose WPU, WACCESS, WINV so that:fast bit line recovery when WORD goes lowdon’t want to “flip” selected cell on read (V1 < VTH,INV)large ∆V on BIT lines to speed up sensingminimize cell size
make this big
keep away from inverter threshold
Cell pullup hasno real effect
MicroLab, VLSI-18 (13/21)
JMM/ESA v1.0
Differential Sense Amp
bit bit
long-channelfet used ascurrent “source”
VDD
rdata
4.8/0.6 4.8/0.6
4.8/0.64.8/0.6
0.9/7.2
V2 V1
VCS
12
3
MicroLab, VLSI-18 (14/21)
JMM/ESA v1.0
Fast Address Decoding
Logically, row/column decoders can be built from wide fan-in AND gates. But these are slow, place heavy loading on address wires and may be hard to fit into the pitch of the memory cell.
A2 A1 A0
A2 A1 A0
One can use predecodelogic to decode blocks ofaddresses which are thenfurther decoded usingsmaller AND gates. Theaddress lines going to thepredecode gates are lessloaded and all gates havesmaller fanin ⇒ decodehappens faster. Layoutworks better too!
MicroLab, VLSI-18 (15/21)
JMM/ESA v1.0
Multiport SRAM (Reg File)
write
wd wd
read0read1
rd0 rd1
One can increase the number of SRAM ports byadding access transistors. Writes are usuallydouble-ended; single-ended reads can be usedto save space.
An alternative design that can be easily expandedwithout worrying about unintentionally flipping thecell on reads is shown below.
writeread0read1
PU = 2/1PD = 4/1
PU = 2/2PD = 2/3
4/1
5/1
2/1
2/1
wd rd1rd0
MicroLab, VLSI-18 (16/21)
JMM/ESA v1.0
Content-addressable RAM By adding two transistors to the 6-T SRAM cell one can form an XOR gate to compare the cell contents to data on the bit lines.The output of this logic can drive a pulldown in a distributed NORgate to form a word “match” signal for a content-addressable memory (CAM).
word
match
xor gate
This node goes highif data on bit linesdoesn’t match datain the cell.
This node will bepulled down if any bitof the word doesn’tmatch
Read and Write cycles: like before…Match cycle: place data on bit lines but don’t
assert word line.
MicroLab, VLSI-18 (17/21)
JMM/ESA v1.0
CAM Architecture
weste, figure 8.76(b)
The word match lines from the CAM array can beused as WORD lines in a companion RAM to readout other data associated with the tag stored inthe CAM. Uses: fully-associative caches,translation lookaside buffers (TLBs), ...
MicroLab, VLSI-18 (18/21)
JMM/ESA v1.0
3-T Dynamic RAM
rdata
write
read
wdata
3-T DRAM Cell
precharge
CW CRCC Data is stored onCC. It’s not destroyedon read, but will leakaway through writetransistor. CW >> CC
Precharge happensbefore each r/w cycle.READ/WRITE andPRECHARGE dont’overlap.
READ:After precharge, CR is charged high.When READ is asserted CR is pulled low if there’s a stored “1” or remains unchanged if there’s a stored “0”. Asense ampis usually used to speed upthe availability of read data.
WRITE:After precharge, CW is charged high.When WRITE is asserted CW shares chargewith CC and dominates sinceCW >> CC. If WDATA isasserted, both CW and CRwill be discharged, writing a“0” into the cell; otherwisea “1” will be written.
Pros: little or no static power, smaller than SRAMCons: needs refresh, need time to precharge
Goal: Goal: Goal: Goal: You know the difference between design and You know the difference between design and You know the difference between design and You know the difference between design and fabrication defects. You know sources of defects fabrication defects. You know sources of defects fabrication defects. You know sources of defects fabrication defects. You know sources of defects and you can estimate yield. You can handle fault and you can estimate yield. You can handle fault and you can estimate yield. You can handle fault and you can estimate yield. You can handle fault models at different abstraction levels. models at different abstraction levels. models at different abstraction levels. models at different abstraction levels.
it helps to have a specification to compare against!it helps to have a specification to compare against!it helps to have a specification to compare against!it helps to have a specification to compare against!
if specification is written in a if specification is written in a if specification is written in a if specification is written in a hardware descriptionhardware descriptionhardware descriptionhardware descriptionlanguagelanguagelanguagelanguage from which the design is from which the design is from which the design is from which the design is synthesizedsynthesizedsynthesizedsynthesized thenthenthenthenthe design should be defectthe design should be defectthe design should be defectthe design should be defect----free (modulo bugs infree (modulo bugs infree (modulo bugs infree (modulo bugs inthe synthesis software!) Of course the specificationthe synthesis software!) Of course the specificationthe synthesis software!) Of course the specificationthe synthesis software!) Of course the specificationmay be buggy...may be buggy...may be buggy...may be buggy...
everyone feels better if the design/specification areeveryone feels better if the design/specification areeveryone feels better if the design/specification areeveryone feels better if the design/specification are“run” in the environment in which they will be used.“run” in the environment in which they will be used.“run” in the environment in which they will be used.“run” in the environment in which they will be used.For example, in testing a processor chip, one mightFor example, in testing a processor chip, one mightFor example, in testing a processor chip, one mightFor example, in testing a processor chip, one mightboot the operating system and run some keyboot the operating system and run some keyboot the operating system and run some keyboot the operating system and run some keyprograms, all under simulation. This leads to theprograms, all under simulation. This leads to theprograms, all under simulation. This leads to theprograms, all under simulation. This leads to theneed for lots of simulation cycles, e.g., as providedneed for lots of simulation cycles, e.g., as providedneed for lots of simulation cycles, e.g., as providedneed for lots of simulation cycles, e.g., as providedby a by a by a by a hardware emulation systemhardware emulation systemhardware emulation systemhardware emulation system. Now. Now. Now. Now----aaaa----days thesedays thesedays thesedays theseare built using a small army ofare built using a small army ofare built using a small army ofare built using a small army of FPGA’sFPGA’sFPGA’sFPGA’s. Other. Other. Other. Otherchoices: inchoices: inchoices: inchoices: in----circuit emulation, cyclecircuit emulation, cyclecircuit emulation, cyclecircuit emulation, cycle----based simulators.based simulators.based simulators.based simulators.
MicroLab, VLSI-19 (3/32)
JMM v1.4
Manufacturing DefectsManufacturing DefectsManufacturing DefectsManufacturing DefectsGoal: verify every gate is operating as expectedGoal: verify every gate is operating as expectedGoal: verify every gate is operating as expectedGoal: verify every gate is operating as expected
Defects from misalignment, dust and other particles, “stacking” Defects from misalignment, dust and other particles, “stacking” Defects from misalignment, dust and other particles, “stacking” Defects from misalignment, dust and other particles, “stacking” faults, pinholes in dielectrics, mask scratches & dirt, thicknesfaults, pinholes in dielectrics, mask scratches & dirt, thicknesfaults, pinholes in dielectrics, mask scratches & dirt, thicknesfaults, pinholes in dielectrics, mask scratches & dirt, thickness s s s variations variations variations variations ⇒ layerlayerlayerlayer----totototo----layer shorts, discontinuous wires (“opens”), layer shorts, discontinuous wires (“opens”), layer shorts, discontinuous wires (“opens”), layer shorts, discontinuous wires (“opens”), circuit sensitivities (Vcircuit sensitivities (Vcircuit sensitivities (Vcircuit sensitivities (VTHTHTHTH, L, L, L, LCHANNELCHANNELCHANNELCHANNEL).).).).Find during wafer probe.Find during wafer probe.Find during wafer probe.Find during wafer probe.
Defects from scratching in handling, damageDefects from scratching in handling, damageDefects from scratching in handling, damageDefects from scratching in handling, damageduring bonding to lead frame, manufacturing defectsduring bonding to lead frame, manufacturing defectsduring bonding to lead frame, manufacturing defectsduring bonding to lead frame, manufacturing defectsundetected during wafer probe (particularlyundetected during wafer probe (particularlyundetected during wafer probe (particularlyundetected during wafer probe (particularlyspeedspeedspeedspeed----related problems).related problems).related problems).related problems).Find during testing of packaged parts.Find during testing of packaged parts.Find during testing of packaged parts.Find during testing of packaged parts.
Defects from damage during board insertion (thermal, ESD), Defects from damage during board insertion (thermal, ESD), Defects from damage during board insertion (thermal, ESD), Defects from damage during board insertion (thermal, ESD), infant mortality (manufacturing defects that show up after a fewinfant mortality (manufacturing defects that show up after a fewinfant mortality (manufacturing defects that show up after a fewinfant mortality (manufacturing defects that show up after a fewhours of use). Also noise problems, susceptibility to latchhours of use). Also noise problems, susceptibility to latchhours of use). Also noise problems, susceptibility to latchhours of use). Also noise problems, susceptibility to latch----up...up...up...up...Find during testing/burnFind during testing/burnFind during testing/burnFind during testing/burn----in of boards.in of boards.in of boards.in of boards.
Defects that only appear after months or years of use (metal Defects that only appear after months or years of use (metal Defects that only appear after months or years of use (metal Defects that only appear after months or years of use (metal migration, oxide damage during manufacture, impurities).migration, oxide damage during manufacture, impurities).migration, oxide damage during manufacture, impurities).migration, oxide damage during manufacture, impurities).Found by customer (oops!).Found by customer (oops!).Found by customer (oops!).Found by customer (oops!).
Cost of replacing defective component increasesCost of replacing defective component increasesCost of replacing defective component increasesCost of replacing defective component increasesby an order of magnitude with each stage ofby an order of magnitude with each stage ofby an order of magnitude with each stage ofby an order of magnitude with each stage ofmanufacture.manufacture.manufacture.manufacture.
MicroLab, VLSI-19 (4/32)
JMM v1.4
Production defects in CMOS circuitsProduction defects in CMOS circuitsProduction defects in CMOS circuitsProduction defects in CMOS circuits
a lot of complex processing steps are used to a lot of complex processing steps are used to a lot of complex processing steps are used to a lot of complex processing steps are used to manufacture a chip manufacture a chip manufacture a chip manufacture a chip ----> defects> defects> defects> defectsdefects and their effect depend on circuit topology defects and their effect depend on circuit topology defects and their effect depend on circuit topology defects and their effect depend on circuit topology and processand processand processand processknowledge of chemical and physical mechanisms knowledge of chemical and physical mechanisms knowledge of chemical and physical mechanisms knowledge of chemical and physical mechanisms who lead to defects are essentialwho lead to defects are essentialwho lead to defects are essentialwho lead to defects are essentialcircuit complexity and surface determine testability circuit complexity and surface determine testability circuit complexity and surface determine testability circuit complexity and surface determine testability and yieldand yieldand yieldand yieldtestability and yield are key factors for future VLSI testability and yield are key factors for future VLSI testability and yield are key factors for future VLSI testability and yield are key factors for future VLSI technologiestechnologiestechnologiestechnologies
MicroLab, VLSI-19 (5/32)
JMM v1.4
VLSI fabrication processVLSI fabrication processVLSI fabrication processVLSI fabrication process
fabrication process consists of a sequence of well fabrication process consists of a sequence of well fabrication process consists of a sequence of well fabrication process consists of a sequence of well defined process stepsdefined process stepsdefined process stepsdefined process steps50 wafers form a batch50 wafers form a batch50 wafers form a batch50 wafers form a batcheach wafer contains 100's or 1000's of chipseach wafer contains 100's or 1000's of chipseach wafer contains 100's or 1000's of chipseach wafer contains 100's or 1000's of chipsspecific test chips are distributed on the wafersspecific test chips are distributed on the wafersspecific test chips are distributed on the wafersspecific test chips are distributed on the waferstest chips allow to monitor process parameterstest chips allow to monitor process parameterstest chips allow to monitor process parameterstest chips allow to monitor process parametersbetween a set of process steps the test structures between a set of process steps the test structures between a set of process steps the test structures between a set of process steps the test structures are measuredare measuredare measuredare measured
processsteps
monitorsteps
processcontrol
parameters
controlling
geometricalchip's
structurs
layout
measureconditionstolerances
tolerances
disturbances
environmentchanging
waferfor futherprocessing
wafernot futherprocessed
MicroLab, VLSI-19 (6/32)
JMM v1.4
VLSI fabrication process (con‘t) VLSI fabrication process (con‘t) VLSI fabrication process (con‘t) VLSI fabrication process (con‘t)
chip test on waferchip test on waferchip test on waferchip test on waferpackaged chip testpackaged chip testpackaged chip testpackaged chip test
waferfabrication
bondingpackaging
parameterand functiontest of chips
on wafer
measuringof process
parameters
parameter andfunction testof packaged
chips
parametermeasuring
of test-chipscont
rolli
ngla
yout
dist
urba
nces
MicroLab, VLSI-19 (7/32)
JMM v1.4
VLSI fabrication process (con‘t)VLSI fabrication process (con‘t)VLSI fabrication process (con‘t)VLSI fabrication process (con‘t)
parameter testparameter testparameter testparameter testtest of electrical parameters: current consumption, test of electrical parameters: current consumption, test of electrical parameters: current consumption, test of electrical parameters: current consumption, quiescent currents, voltage levels, delay times, etc.quiescent currents, voltage levels, delay times, etc.quiescent currents, voltage levels, delay times, etc.quiescent currents, voltage levels, delay times, etc.
function testfunction testfunction testfunction testtest for logical faults: binary test sequences are applied test for logical faults: binary test sequences are applied test for logical faults: binary test sequences are applied test for logical faults: binary test sequences are applied to the device under test (DUT)to the device under test (DUT)to the device under test (DUT)to the device under test (DUT)
defects occur at different fabrication steps:defects occur at different fabrication steps:defects occur at different fabrication steps:defects occur at different fabrication steps:defects at wafer fabricationdefects at wafer fabricationdefects at wafer fabricationdefects at wafer fabricationdefects at chip packagingdefects at chip packagingdefects at chip packagingdefects at chip packagingdefects during chip lifetimedefects during chip lifetimedefects during chip lifetimedefects during chip lifetime
MicroLab, VLSI-19 (9/32)
JMM v1.4
Defects at wafer fabricationDefects at wafer fabricationDefects at wafer fabricationDefects at wafer fabrication50% of all defects50% of all defects50% of all defects50% of all defects
reason:reason:reason:reason:changes in fabrication environmentchanges in fabrication environmentchanges in fabrication environmentchanges in fabrication environmentsubstrate substrate substrate substrate inhomogenitiesinhomogenitiesinhomogenitiesinhomogenities, mask misalignment, mask misalignment, mask misalignment, mask misalignmentdust particles, photolithography defectsdust particles, photolithography defectsdust particles, photolithography defectsdust particles, photolithography defects
local or global effectslocal or global effectslocal or global effectslocal or global effectselectrical effects depend on layout topologyelectrical effects depend on layout topologyelectrical effects depend on layout topologyelectrical effects depend on layout topology
changes in delay, current consumptionchanges in delay, current consumptionchanges in delay, current consumptionchanges in delay, current consumptionshorts, opensshorts, opensshorts, opensshorts, opens
MicroLab, VLSI-19 (10/32)
JMM v1.4
Defect at chip packagingDefect at chip packagingDefect at chip packagingDefect at chip packaging
effect:effect:effect:effect:normally occur at primary inputs or outputsnormally occur at primary inputs or outputsnormally occur at primary inputs or outputsnormally occur at primary inputs or outputs
easy to detecteasy to detecteasy to detecteasy to detect
MicroLab, VLSI-19 (11/32)
JMM v1.4
Defects during lifetimeDefects during lifetimeDefects during lifetimeDefects during lifetime
time
defect rate
early defects
middle life phase wear defects
time dependant mechanisms lead to defectstime dependant mechanisms lead to defectstime dependant mechanisms lead to defectstime dependant mechanisms lead to defectsearly defects: high defect rate (burnearly defects: high defect rate (burnearly defects: high defect rate (burnearly defects: high defect rate (burn----in)in)in)in)middle life phase: low defect ratemiddle life phase: low defect ratemiddle life phase: low defect ratemiddle life phase: low defect ratewear defects: defect rate climbs with timewear defects: defect rate climbs with timewear defects: defect rate climbs with timewear defects: defect rate climbs with time
defects can produce faultsdefects can produce faultsdefects can produce faultsdefects can produce faultsyield is percentage of fault free chipsyield is percentage of fault free chipsyield is percentage of fault free chipsyield is percentage of fault free chipsyield influences chip costyield influences chip costyield influences chip costyield influences chip costyield models are necessary to predict chip costyield models are necessary to predict chip costyield models are necessary to predict chip costyield models are necessary to predict chip costlocal defects produce most faultslocal defects produce most faultslocal defects produce most faultslocal defects produce most faults
assumption: local defects are statistically assumption: local defects are statistically assumption: local defects are statistically assumption: local defects are statistically independent and occur with probability independent and occur with probability independent and occur with probability independent and occur with probability ppppbinominal distributionbinominal distributionbinominal distributionbinominal distributionPrPrPrPrKKKK====kkkk = Pr = Pr = Pr = Prkkkk from from from from nnnn areas are faultyareas are faultyareas are faultyareas are faultydue to Bernoullidue to Bernoullidue to Bernoullidue to Bernoulli
with with with with nnnn to infinity and to infinity and to infinity and to infinity and pppp to zero we find to zero we find to zero we find to zero we find
expectation value expectation value expectation value expectation value
probability that a chip is fault free probability that a chip is fault free probability that a chip is fault free probability that a chip is fault free
Murphy normalized density function f(D)Murphy normalized density function f(D)Murphy normalized density function f(D)Murphy normalized density function f(D)
calculation of yield with Murphy's density function f(D)calculation of yield with Murphy's density function f(D)calculation of yield with Murphy's density function f(D)calculation of yield with Murphy's density function f(D)YYYY1111, , , , YYYY2222, , , , YYYY3333 ????(for high yield)(for high yield)(for high yield)(for high yield)
Seed's yield modelSeed's yield modelSeed's yield modelSeed's yield model
the bigger the circuit the higher the probability for the bigger the circuit the higher the probability for the bigger the circuit the higher the probability for the bigger the circuit the higher the probability for a faulty chipa faulty chipa faulty chipa faulty chipexample: 2 wafers with the same 17 defectsexample: 2 wafers with the same 17 defectsexample: 2 wafers with the same 17 defectsexample: 2 wafers with the same 17 defects
wafer with total 44 chipswafer with total 44 chipswafer with total 44 chipswafer with total 44 chipsyield 61%yield 61%yield 61%yield 61%wafer with total 316 chipswafer with total 316 chipswafer with total 316 chipswafer with total 316 chipsyield 95% yield 95% yield 95% yield 95%
defects occur during wafer fabrication, chip defects occur during wafer fabrication, chip defects occur during wafer fabrication, chip defects occur during wafer fabrication, chip packaging and during chip lifetimepackaging and during chip lifetimepackaging and during chip lifetimepackaging and during chip lifetimelocal and global defectslocal and global defectslocal and global defectslocal and global defectslocal defects dominate at mature process local defects dominate at mature process local defects dominate at mature process local defects dominate at mature process local defects are hard to find and costlylocal defects are hard to find and costlylocal defects are hard to find and costlylocal defects are hard to find and costly
MicroLab, VLSI-19 (16/32)
JMM v1.4
Fault models for integrated circuitsFault models for integrated circuitsFault models for integrated circuitsFault models for integrated circuits
complex circuits need more test timecomplex circuits need more test timecomplex circuits need more test timecomplex circuits need more test timetest time with expensive equipment leads to high test time with expensive equipment leads to high test time with expensive equipment leads to high test time with expensive equipment leads to high test cost per chiptest cost per chiptest cost per chiptest cost per chipto reduce test time fault models for structured test to reduce test time fault models for structured test to reduce test time fault models for structured test to reduce test time fault models for structured test approaches are requiredapproaches are requiredapproaches are requiredapproaches are required
if a system behaves not as expected, faults are if a system behaves not as expected, faults are if a system behaves not as expected, faults are if a system behaves not as expected, faults are presentpresentpresentpresentfaults can be modeled at different electrical levelsfaults can be modeled at different electrical levelsfaults can be modeled at different electrical levelsfaults can be modeled at different electrical levelsfaults can be caused by defectsfaults can be caused by defectsfaults can be caused by defectsfaults can be caused by defects
they occur during fabrication or life timethey occur during fabrication or life timethey occur during fabrication or life timethey occur during fabrication or life time
design errors produce designdesign errors produce designdesign errors produce designdesign errors produce design----faultsfaultsfaultsfaultsfor example faulty logic implementation of functionsfor example faulty logic implementation of functionsfor example faulty logic implementation of functionsfor example faulty logic implementation of functionsdesign validation is necessarydesign validation is necessarydesign validation is necessarydesign validation is necessary
MicroLab, VLSI-19 (17/32)
JMM v1.4
Fault models: Testing approachesFault models: Testing approachesFault models: Testing approachesFault models: Testing approachesPlan: supply a set of Plan: supply a set of Plan: supply a set of Plan: supply a set of test vectorstest vectorstest vectorstest vectors that specify an input or output that specify an input or output that specify an input or output that specify an input or output value for every pin on every cycle. Tester will load the progravalue for every pin on every cycle. Tester will load the progravalue for every pin on every cycle. Tester will load the progravalue for every pin on every cycle. Tester will load the program m m m into the pin cards, run it and report any discrepancies between into the pin cards, run it and report any discrepancies between into the pin cards, run it and report any discrepancies between into the pin cards, run it and report any discrepancies between an an an an observed output value and the expected value.observed output value and the expected value.observed output value and the expected value.observed output value and the expected value.
cycle #cycle #cycle #cycle # program for 11 pinsprogram for 11 pinsprogram for 11 pinsprogram for 11 pins
input to chip = 0, 1input to chip = 0, 1input to chip = 0, 1input to chip = 0, 1output from chip = L, Houtput from chip = L, Houtput from chip = L, Houtput from chip = L, Htritritritri----state/no compare = X state/no compare = X state/no compare = X state/no compare = X
How many vectors do we need?How many vectors do we need?How many vectors do we need?How many vectors do we need?
Exhaustive testing is not only impractical, it’sExhaustive testing is not only impractical, it’sExhaustive testing is not only impractical, it’sExhaustive testing is not only impractical, it’snot necessary! Instead we only need to verify thatnot necessary! Instead we only need to verify thatnot necessary! Instead we only need to verify thatnot necessary! Instead we only need to verify thatno no no no faultsfaultsfaultsfaults are present which may take many fewerare present which may take many fewerare present which may take many fewerare present which may take many fewervectors.vectors.vectors.vectors.
2222nnnn inputs required toinputs required toinputs required toinputs required toexhaustively test circuitexhaustively test circuitexhaustively test circuitexhaustively test circuit
2222n+mn+mn+mn+m inputs required toinputs required toinputs required toinputs required toexhaustively test circuitexhaustively test circuitexhaustively test circuitexhaustively test circuit
If n=50, m=25, 1ns/testIf n=50, m=25, 1ns/testIf n=50, m=25, 1ns/testIf n=50, m=25, 1ns/testthen test time > 10then test time > 10then test time > 10then test time > 106666 yearsyearsyearsyears
circuits are treated at different abstraction levelscircuits are treated at different abstraction levelscircuits are treated at different abstraction levelscircuits are treated at different abstraction levelsanalog or memory circuits are treated at transistor levelanalog or memory circuits are treated at transistor levelanalog or memory circuits are treated at transistor levelanalog or memory circuits are treated at transistor levelmedium size digital circuits are treated at logic levelmedium size digital circuits are treated at logic levelmedium size digital circuits are treated at logic levelmedium size digital circuits are treated at logic levelcomplex digital circuits or microprocessors are normally complex digital circuits or microprocessors are normally complex digital circuits or microprocessors are normally complex digital circuits or microprocessors are normally treated at functional leveltreated at functional leveltreated at functional leveltreated at functional level
example of fault manifestation: missing example of fault manifestation: missing example of fault manifestation: missing example of fault manifestation: missing polysiliconpolysiliconpolysiliconpolysiliconmaterialmaterialmaterialmaterial
fault dependenciesfault dependenciesfault dependenciesfault dependenciesfaults are layout dependentfaults are layout dependentfaults are layout dependentfaults are layout dependentfault are technology dependentfault are technology dependentfault are technology dependentfault are technology dependent
goals of fault modelsgoals of fault modelsgoals of fault modelsgoals of fault modelsfault models should be realistic and thus depend on fault models should be realistic and thus depend on fault models should be realistic and thus depend on fault models should be realistic and thus depend on physical defect mechanismsphysical defect mechanismsphysical defect mechanismsphysical defect mechanismsfault models should be simple and treatablefault models should be simple and treatablefault models should be simple and treatablefault models should be simple and treatable
MicroLab, VLSI-19 (20/32)
JMM v1.4
Hard to detect faultsHard to detect faultsHard to detect faultsHard to detect faults
transient (intermittent) faultstransient (intermittent) faultstransient (intermittent) faultstransient (intermittent) faultsoccur only from time to timeoccur only from time to timeoccur only from time to timeoccur only from time to timedue to environment changingdue to environment changingdue to environment changingdue to environment changingno satisfactory strategy to search themno satisfactory strategy to search themno satisfactory strategy to search themno satisfactory strategy to search them
repeating searchrepeating searchrepeating searchrepeating searchbuiltbuiltbuiltbuilt----in test: selfin test: selfin test: selfin test: self----checking circuits, errorchecking circuits, errorchecking circuits, errorchecking circuits, error----correctingcorrectingcorrectingcorrecting----circuitscircuitscircuitscircuitsredundant use of several identical circuitredundant use of several identical circuitredundant use of several identical circuitredundant use of several identical circuit----blocksblocksblocksblocks
benefits of redundant circuitsbenefits of redundant circuitsbenefits of redundant circuitsbenefits of redundant circuitsredundancy for higher functionality securityredundancy for higher functionality securityredundancy for higher functionality securityredundancy for higher functionality securityredundancy to eliminate hazardsredundancy to eliminate hazardsredundancy to eliminate hazardsredundancy to eliminate hazards
disadvantages of redundant circuitsdisadvantages of redundant circuitsdisadvantages of redundant circuitsdisadvantages of redundant circuitsfaults not detectable (masking effect)faults not detectable (masking effect)faults not detectable (masking effect)faults not detectable (masking effect)
historical perspectivehistorical perspectivehistorical perspectivehistorical perspectiveEldred proposed 1959 methods how to test Eldred proposed 1959 methods how to test Eldred proposed 1959 methods how to test Eldred proposed 1959 methods how to test computers with relays, diodes, tubes, which computers with relays, diodes, tubes, which computers with relays, diodes, tubes, which computers with relays, diodes, tubes, which behaved like switchesbehaved like switchesbehaved like switchesbehaved like switchesstimulation of development of fault models on logic stimulation of development of fault models on logic stimulation of development of fault models on logic stimulation of development of fault models on logic levellevellevellevel
stuckstuckstuckstuck----at fault modelat fault modelat fault modelat fault modelsignal can be stuck at "0" or "1"signal can be stuck at "0" or "1"signal can be stuck at "0" or "1"signal can be stuck at "0" or "1"independent of process technologyindependent of process technologyindependent of process technologyindependent of process technologydoes not model technology dependant does not model technology dependant does not model technology dependant does not model technology dependant characteristicscharacteristicscharacteristicscharacteristicsmathematical calculus existsmathematical calculus existsmathematical calculus existsmathematical calculus existsvery useful for TTL technology (or other old very useful for TTL technology (or other old very useful for TTL technology (or other old very useful for TTL technology (or other old "current" technologies, but not for "charge" "current" technologies, but not for "charge" "current" technologies, but not for "charge" "current" technologies, but not for "charge" technologies like CMOS)technologies like CMOS)technologies like CMOS)technologies like CMOS)
Traditional model, first developed for boardTraditional model, first developed for boardTraditional model, first developed for boardTraditional model, first developed for board----level level level level tests, assumes that a node gets “stuck” at a “0” or tests, assumes that a node gets “stuck” at a “0” or tests, assumes that a node gets “stuck” at a “0” or tests, assumes that a node gets “stuck” at a “0” or “1”, presumably by shorting to GND or V“1”, presumably by shorting to GND or V“1”, presumably by shorting to GND or V“1”, presumably by shorting to GND or VDDDDDDDD.
example of TTL NAND gate with many defects example of TTL NAND gate with many defects example of TTL NAND gate with many defects example of TTL NAND gate with many defects describable with stuckdescribable with stuckdescribable with stuckdescribable with stuck----at fault modelat fault modelat fault modelat fault model
R1 R2 R4
R3
T1T2
T3
T4I1
I2O
stuck at “0” = Sstuck at “0” = Sstuck at “0” = Sstuck at “0” = S----AAAA----0 = node@00 = node@00 = node@00 = node@0stuck at “1” = Sstuck at “1” = Sstuck at “1” = Sstuck at “1” = S----AAAA----1 = node@11 = node@11 = node@11 = node@1
fault detectionfault detectionfault detectionfault detectionfault free function: fault free function: fault free function: fault free function: ffff((((x))))with fault with fault with fault with fault αααα: : : : ffffαααα((((x))))
test vectors test vectors test vectors test vectors x detect fault, if condition is fulfilled:detect fault, if condition is fulfilled:detect fault, if condition is fulfilled:detect fault, if condition is fulfilled:
fault dominancefault dominancefault dominancefault dominanceTTTTαααα represents test vector set to detect fault represents test vector set to detect fault represents test vector set to detect fault represents test vector set to detect fault ααααfault fault fault fault α α α α dominates fault dominates fault dominates fault dominates fault γ γ γ γ under conditionunder conditionunder conditionunder condition
for test generation only tests for fault for test generation only tests for fault for test generation only tests for fault for test generation only tests for fault αααα are are are are necessarynecessarynecessarynecessarymultiple faults: fault masking problemsmultiple faults: fault masking problemsmultiple faults: fault masking problemsmultiple faults: fault masking problems
introduced due to imperfection of logic level fault introduced due to imperfection of logic level fault introduced due to imperfection of logic level fault introduced due to imperfection of logic level fault models, especially for CMOSmodels, especially for CMOSmodels, especially for CMOSmodels, especially for CMOStechnology dependant and thus more realistictechnology dependant and thus more realistictechnology dependant and thus more realistictechnology dependant and thus more realisticmore complex to handle and thus not useful for more complex to handle and thus not useful for more complex to handle and thus not useful for more complex to handle and thus not useful for large circuitslarge circuitslarge circuitslarge circuitstransistor level fault models:transistor level fault models:transistor level fault models:transistor level fault models:
Wadsack'sWadsack'sWadsack'sWadsack's modelmodelmodelmodelHayes' switch level modelHayes' switch level modelHayes' switch level modelHayes' switch level modelReddy's restrictions due to static dischargeReddy's restrictions due to static dischargeReddy's restrictions due to static dischargeReddy's restrictions due to static dischargerobust test setsrobust test setsrobust test setsrobust test sets
Wadsack'sWadsack'sWadsack'sWadsack's fault models for CMOS:fault models for CMOS:fault models for CMOS:fault models for CMOS:defects can lead to memory effectsdefects can lead to memory effectsdefects can lead to memory effectsdefects can lead to memory effectsfaulty combinational logic may behave like faulty combinational logic may behave like faulty combinational logic may behave like faulty combinational logic may behave like sequential logicsequential logicsequential logicsequential logicthis effect was modeled by introducing flipthis effect was modeled by introducing flipthis effect was modeled by introducing flipthis effect was modeled by introducing flip----flop's flop's flop's flop's in order to use stuckin order to use stuckin order to use stuckin order to use stuck----at modelsat modelsat modelsat modelsstuckstuckstuckstuck----at syndrome !at syndrome !at syndrome !at syndrome !
A B Y A B Y A B Y A B Y αααα/0 /0 /0 /0 ββββ/0 /0 /0 /0 γγγγ/0 a b/0 a b/0 a b/0 a b vddvddvddvdd0 0 10 0 10 0 10 0 10 1 00 1 00 1 00 1 01 0 01 0 01 0 01 0 01 1 01 1 01 1 01 1 0
VLSI circuits need simple fault modelsVLSI circuits need simple fault modelsVLSI circuits need simple fault modelsVLSI circuits need simple fault modelsgoal of test: it is sometimes sufficient to know if a goal of test: it is sometimes sufficient to know if a goal of test: it is sometimes sufficient to know if a goal of test: it is sometimes sufficient to know if a subsubsubsub----function works correctlyfunction works correctlyfunction works correctlyfunction works correctlymodel of functional faults of submodel of functional faults of submodel of functional faults of submodel of functional faults of sub----circuitcircuitcircuitcircuiteach subeach subeach subeach sub----function has its own process dependent function has its own process dependent function has its own process dependent function has its own process dependent faultsfaultsfaultsfaultsadvantage:advantage:advantage:advantage:
fast simulationfast simulationfast simulationfast simulationshort test timeshort test timeshort test timeshort test timeprocess dependentprocess dependentprocess dependentprocess dependentgood knowledge on important subgood knowledge on important subgood knowledge on important subgood knowledge on important sub----functions (ex. RAM's)functions (ex. RAM's)functions (ex. RAM's)functions (ex. RAM's)
disadvantagedisadvantagedisadvantagedisadvantageless accurateless accurateless accurateless accuratenot useful for all subnot useful for all subnot useful for all subnot useful for all sub----functionsfunctionsfunctionsfunctions
example of CMOS example of CMOS example of CMOS example of CMOS multiplexermultiplexermultiplexermultiplexer with with with with nnnn inputs: inputs: inputs: inputs: behavior under faults:behavior under faults:behavior under faults:behavior under faults:
an other input is selectedan other input is selectedan other input is selectedan other input is selectedone of the one of the one of the one of the nnnn inputs has a stuckinputs has a stuckinputs has a stuckinputs has a stuck----at faultat faultat faultat faulttwo inputs are selected (AND or OR result at output)two inputs are selected (AND or OR result at output)two inputs are selected (AND or OR result at output)two inputs are selected (AND or OR result at output)if the complementary value arrives at a selected input, if the complementary value arrives at a selected input, if the complementary value arrives at a selected input, if the complementary value arrives at a selected input, an error occurs at the outputan error occurs at the outputan error occurs at the outputan error occurs at the outputif the complementary value of the selected input arrives if the complementary value of the selected input arrives if the complementary value of the selected input arrives if the complementary value of the selected input arrives at a neighbor of the selected input, an error occurs at at a neighbor of the selected input, an error occurs at at a neighbor of the selected input, an error occurs at at a neighbor of the selected input, an error occurs at the outputthe outputthe outputthe output
8 to 1 MUX8 to 1 MUX8 to 1 MUX8 to 1 MUX8 to 1 MUX8 to 1 MUX8 to 1 MUX8 to 1 MUX
fault models are used to model the effects of fault models are used to model the effects of fault models are used to model the effects of fault models are used to model the effects of fabrication defects on abstract levelsfabrication defects on abstract levelsfabrication defects on abstract levelsfabrication defects on abstract levelsfault models allow to search directly for circuit fault models allow to search directly for circuit fault models allow to search directly for circuit fault models allow to search directly for circuit defectsdefectsdefectsdefectsfault models need to be simple and precisefault models need to be simple and precisefault models need to be simple and precisefault models need to be simple and preciseCMOS defects are bad modeled with stuckCMOS defects are bad modeled with stuckCMOS defects are bad modeled with stuckCMOS defects are bad modeled with stuck----at fault at fault at fault at fault model model model model
MicroLab, VLSI-19 (30/32)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Test pattern generation and fault simulationTest pattern generation and fault simulationTest pattern generation and fault simulationTest pattern generation and fault simulation
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WesteWesteWesteWeste::::
reading 7 through 7.2.1 reading 7 through 7.2.1 reading 7 through 7.2.1 reading 7 through 7.2.1
Ex vlsi19.1 (difficulty: easy):Ex vlsi19.1 (difficulty: easy):Ex vlsi19.1 (difficulty: easy):Ex vlsi19.1 (difficulty: easy): Calculate the yield of a Calculate the yield of a Calculate the yield of a Calculate the yield of a circuit of area 5 mmcircuit of area 5 mmcircuit of area 5 mmcircuit of area 5 mm2222 and 1 cmand 1 cmand 1 cmand 1 cm2222 if the defect rate D if the defect rate D if the defect rate D if the defect rate D is 2 defects per cmis 2 defects per cmis 2 defects per cmis 2 defects per cm2222....Result: YResult: YResult: YResult: Y5mm25mm25mm25mm2=0.91 (high yield), Y=0.91 (high yield), Y=0.91 (high yield), Y=0.91 (high yield), Y1cm21cm21cm21cm2=0.24 (low =0.24 (low =0.24 (low =0.24 (low yield equation), seeyield equation), seeyield equation), seeyield equation), see vlsivlsivlsivlsi----19/1319/1319/1319/13
Ex vlsi19.2 (difficulty: easy): Ex vlsi19.2 (difficulty: easy): Ex vlsi19.2 (difficulty: easy): Ex vlsi19.2 (difficulty: easy): Discuss the circuits Discuss the circuits Discuss the circuits Discuss the circuits function with the introduction of the stuckfunction with the introduction of the stuckfunction with the introduction of the stuckfunction with the introduction of the stuck----open open open open faultfaultfaultfault FFFFxxxx=open=open=open=open. Can this fault be modeled by a stuck. Can this fault be modeled by a stuck. Can this fault be modeled by a stuck. Can this fault be modeled by a stuck----at at at at fault?fault?fault?fault?
AAAA
BBBB
BBBBAAAA
DDDDCCCC
DDDD
CCCCXXXX
F = (A+C)(B+D)F = (A+C)(B+D)F = (A+C)(B+D)F = (A+C)(B+D)
Ex vlsi19.4 (difficulty: easy): Ex vlsi19.4 (difficulty: easy): Ex vlsi19.4 (difficulty: easy): Ex vlsi19.4 (difficulty: easy): Discuss faults due to Discuss faults due to Discuss faults due to Discuss faults due to defects at the TTLdefects at the TTLdefects at the TTLdefects at the TTL nandnandnandnand gate on transparency 22. gate on transparency 22. gate on transparency 22. gate on transparency 22. What kind of stuckWhat kind of stuckWhat kind of stuckWhat kind of stuck----at fault do you have if a) Rat fault do you have if a) Rat fault do you have if a) Rat fault do you have if a) R1111 is an is an is an is an open circuit, b)open at Iopen circuit, b)open at Iopen circuit, b)open at Iopen circuit, b)open at I1111, c) open in R, c) open in R, c) open in R, c) open in R2222
Result: a) O sResult: a) O sResult: a) O sResult: a) O s----aaaa----1, b) I1, b) I1, b) I1, b) I1111 ssss----aaaa----1, c) O s1, c) O s1, c) O s1, c) O s----aaaa----1111
MicroLab, VLSI-20 (1/26)
JMM v1.4
VLSI Design IVLSI Design IVLSI Design IVLSI Design ITest Pattern Generation and Fault SimulationTest Pattern Generation and Fault SimulationTest Pattern Generation and Fault SimulationTest Pattern Generation and Fault Simulation
Let‘s test a chip?Let‘s test a chip?Let‘s test a chip?Let‘s test a chip?
Goal: Goal: Goal: Goal: Design for testability terms like Design for testability terms like Design for testability terms like Design for testability terms like controllability and controllability and controllability and controllability and observability observability observability observability are known. You are are known. You are are known. You are are known. You are familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as with testability measure metrics.with testability measure metrics.with testability measure metrics.with testability measure metrics.
MicroLab, VLSI-20 (2/26)
JMM v1.4
TestersTestersTestersTestersThe device under testThe device under testThe device under testThe device under test(DUT) can be a site on(DUT) can be a site on(DUT) can be a site on(DUT) can be a site ona wafer or a packageda wafer or a packageda wafer or a packageda wafer or a packagedpart.part.part.part.
Each pin on the chip isEach pin on the chip isEach pin on the chip isEach pin on the chip isdriven/observed by adriven/observed by adriven/observed by adriven/observed by aseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to one data value ne data value ne data value ne data value per cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particular point ular point ular point ular point in a clock cycle. Timing of input transitions and sampling of oin a clock cycle. Timing of input transitions and sampling of oin a clock cycle. Timing of input transitions and sampling of oin a clock cycle. Timing of input transitions and sampling of outputs is utputs is utputs is utputs is controlled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of high----resolution timing generators. To increase the numberresolution timing generators. To increase the numberresolution timing generators. To increase the numberresolution timing generators. To increase the numberof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provided:d:d:d:
MicroLab, VLSI-20 (3/26)
JMM v1.4
Test pattern generationTest pattern generationTest pattern generationTest pattern generation
test generation is a time consuming tasktest generation is a time consuming tasktest generation is a time consuming tasktest generation is a time consuming taskcomputercomputercomputercomputer----aided test programs (CAT) help designer aided test programs (CAT) help designer aided test programs (CAT) help designer aided test programs (CAT) help designer but do not solve test problemsbut do not solve test problemsbut do not solve test problemsbut do not solve test problemsapproaches to manage test problem with increasing approaches to manage test problem with increasing approaches to manage test problem with increasing approaches to manage test problem with increasing circuit complexity (research fields)circuit complexity (research fields)circuit complexity (research fields)circuit complexity (research fields)
design for testabilitydesign for testabilitydesign for testabilitydesign for testabilityalgorithms to generate good test vectorsalgorithms to generate good test vectorsalgorithms to generate good test vectorsalgorithms to generate good test vectors
design for testability: controllability, design for testability: controllability, design for testability: controllability, design for testability: controllability, observabilityobservabilityobservabilityobservabilitysystem designer needs DFT knowledgesystem designer needs DFT knowledgesystem designer needs DFT knowledgesystem designer needs DFT knowledge
adadadad----hoc approaches to augment controllability: hoc approaches to augment controllability: hoc approaches to augment controllability: hoc approaches to augment controllability: partitioning, more testpartitioning, more testpartitioning, more testpartitioning, more test----padspadspadspadsstructured methods, structured methods, structured methods, structured methods, multiplexermultiplexermultiplexermultiplexer approach, scanapproach, scanapproach, scanapproach, scan----path, path, path, path, builtbuiltbuiltbuilt----in logic block observation (BILBO), boundaryin logic block observation (BILBO), boundaryin logic block observation (BILBO), boundaryin logic block observation (BILBO), boundary----scan, scan, scan, scan, signature analysis, etc...signature analysis, etc...signature analysis, etc...signature analysis, etc...
MicroLab, VLSI-20 (4/26)
JMM v1.4
Algorithms for test pattern Algorithms for test pattern Algorithms for test pattern Algorithms for test pattern generationgenerationgenerationgeneration
basic concepts for test generation for stuckbasic concepts for test generation for stuckbasic concepts for test generation for stuckbasic concepts for test generation for stuck----at fault at fault at fault at fault models in combinational circuitsmodels in combinational circuitsmodels in combinational circuitsmodels in combinational circuitsalgebraic test generation: algebraic test generation: algebraic test generation: algebraic test generation: booleanbooleanbooleanboolean differencedifferencedifferencedifferenceDDDD----algorithmalgorithmalgorithmalgorithmPodemPodemPodemPodem and FAN algorithmsand FAN algorithmsand FAN algorithmsand FAN algorithmscontrollability and controllability and controllability and controllability and observabilityobservabilityobservabilityobservability measuringmeasuringmeasuringmeasuring
algebraic method: algebraic method: algebraic method: algebraic method: booleanbooleanbooleanboolean differencedifferencedifferencedifferencecircuits function with input vector circuits function with input vector circuits function with input vector circuits function with input vector x
for for for for iiiithththth component of vector component of vector component of vector component of vector x with fix value we definewith fix value we definewith fix value we definewith fix value we define
definition of definition of definition of definition of booleanbooleanbooleanboolean differencedifferencedifferencedifference
circuit with fault circuit with fault circuit with fault circuit with fault α:α:α:α: stuckstuckstuckstuck----atatatat----1 at input 1 at input 1 at input 1 at input xxxxiiii
to detect sto detect sto detect sto detect s----aaaa----1 faults the two functions 1 faults the two functions 1 faults the two functions 1 faults the two functions ffff((((x) and ) and ) and ) and ffffαααα(1) (1) (1) (1) must produce different results, so the test vector set is must produce different results, so the test vector set is must produce different results, so the test vector set is must produce different results, so the test vector set is defined by defined by defined by defined by TTTT=1=1=1=1
(((( ))))xg independent of independent of independent of independent of xxxxiiii
MicroLab, VLSI-20 (7/26)
JMM v1.4
Boolean difference: exampleBoolean difference: exampleBoolean difference: exampleBoolean difference: example
Example Ex 20.1 (medium): Example Ex 20.1 (medium): Example Ex 20.1 (medium): Example Ex 20.1 (medium): circuit with stuckcircuit with stuckcircuit with stuckcircuit with stuck----atatatat----1 1 1 1 fault at fault at fault at fault at xxxx3333. Find all test patterns which detect the . Find all test patterns which detect the . Find all test patterns which detect the . Find all test patterns which detect the the fault with means of the the fault with means of the the fault with means of the the fault with means of the booleanbooleanbooleanboolean difference.difference.difference.difference.
≥ 1
G1
≥ 1
G5
G3
&
G4
&
x1
x2
x3
x4
y
s1
s2
s3
G2
MicroLab, VLSI-20 (8/26)
JMM v1.4
Test generation: DTest generation: DTest generation: DTest generation: D----algorithmalgorithmalgorithmalgorithm
Basics:Basics:Basics:Basics:fault fault fault fault sensitisationsensitisationsensitisationsensitisation (provoke error)(provoke error)(provoke error)(provoke error)fault propagationfault propagationfault propagationfault propagationline justification line justification line justification line justification
DDDD----notationnotationnotationnotationa signal with value D is fault free if D = 1a signal with value D is fault free if D = 1a signal with value D is fault free if D = 1a signal with value D is fault free if D = 1a signal with value D is faulty if D=0a signal with value D is faulty if D=0a signal with value D is faulty if D=0a signal with value D is faulty if D=0a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0a signal with value D is faulty if D=1a signal with value D is faulty if D=1a signal with value D is faulty if D=1a signal with value D is faulty if D=1
if test vector exists it will be foundif test vector exists it will be foundif test vector exists it will be foundif test vector exists it will be foundprogrammable for computersprogrammable for computersprogrammable for computersprogrammable for computers
disadvantage:disadvantage:disadvantage:disadvantage:conflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculationsnot usable for large circuitsnot usable for large circuitsnot usable for large circuitsnot usable for large circuits
MicroLab, VLSI-20 (9/26)
JMM v1.4
≥ 1
G1
≥ 1
G5
G3
&
G4
&
x1
x2
x3
x4
y
s1
s2
s3
G2
Test generation: Path Test generation: Path Test generation: Path Test generation: Path sensitisationsensitisationsensitisationsensitisation
Example Ex20.2 (easy):Example Ex20.2 (easy):Example Ex20.2 (easy):Example Ex20.2 (easy): circuit with stuckcircuit with stuckcircuit with stuckcircuit with stuck----atatatat----1 fault 1 fault 1 fault 1 fault at at at at xxxx3333. Find test vectors with means of D. Find test vectors with means of D. Find test vectors with means of D. Find test vectors with means of D----algorithmalgorithmalgorithmalgorithm
Step 1: Step 1: Step 1: Step 1: Sensitize circuitSensitize circuitSensitize circuitSensitize circuit. Find input values that . Find input values that . Find input values that . Find input values that produce a value on the faulty node that’s different produce a value on the faulty node that’s different produce a value on the faulty node that’s different produce a value on the faulty node that’s different from the value forced by the fault. For our Sfrom the value forced by the fault. For our Sfrom the value forced by the fault. For our Sfrom the value forced by the fault. For our S----AAAA----1 1 1 1 fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.
Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such input values exist?input values exist?input values exist?input values exist?Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not, which should one choose?which should one choose?which should one choose?which should one choose?What’s left to do?What’s left to do?What’s left to do?What’s left to do?
Step 2: Step 2: Step 2: Step 2: Fault propagationFault propagationFault propagationFault propagation. Select a path that . Select a path that . Select a path that . Select a path that propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y in our example).in our example).in our example).in our example).
SSSS----AAAA----1111
XXXX
MicroLab, VLSI-20 (11/26)
JMM v1.4
≥ 1
G1
≥ 1
G5
G3
&
G4
&
x1
x2
x3
x4
y
s1
s2
s3
G2
Test generation: Line justificationTest generation: Line justificationTest generation: Line justificationTest generation: Line justification
Step 3: Step 3: Step 3: Step 3: Line justificationLine justificationLine justificationLine justification. Find a set of input . Find a set of input . Find a set of input . Find a set of input values that enables the selected path values that enables the selected path values that enables the selected path values that enables the selected path (backtracking).(backtracking).(backtracking).(backtracking).
Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such input values exist?input values exist?input values exist?input values exist?Is the set of enabling input values unique? Is the set of enabling input values unique? Is the set of enabling input values unique? Is the set of enabling input values unique? If not, which should one choose?If not, which should one choose?If not, which should one choose?If not, which should one choose?
SSSS----AAAA----1111
XXXX
MicroLab, VLSI-20 (12/26)
JMM v1.4
Test generation: PODEM, FANTest generation: PODEM, FANTest generation: PODEM, FANTest generation: PODEM, FAN
more recent algorithms like more recent algorithms like more recent algorithms like more recent algorithms like PodemPodemPodemPodem, FAN or others , FAN or others , FAN or others , FAN or others basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to detect them as early as possibledetect them as early as possibledetect them as early as possibledetect them as early as possibleconcept: concept: concept: concept:
take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with higher probabilityhigher probabilityhigher probabilityhigher probability
controllability and controllability and controllability and controllability and observabilityobservabilityobservabilityobservability measuring measuring measuring measuring necessarynecessarynecessarynecessary
MicroLab, VLSI-20 (13/26)
JMM v1.4
PODEMPODEMPODEMPODEM
PodemPodemPodemPodem algorithm is simpler to understand than Dalgorithm is simpler to understand than Dalgorithm is simpler to understand than Dalgorithm is simpler to understand than D----algorithmalgorithmalgorithmalgorithmbacktrack (branchbacktrack (branchbacktrack (branchbacktrack (branch----andandandand----bound) algorithm is usedbound) algorithm is usedbound) algorithm is usedbound) algorithm is used
small steps to reach objectivesmall steps to reach objectivesmall steps to reach objectivesmall steps to reach objectiveif objective leads to deadif objective leads to deadif objective leads to deadif objective leads to dead----end, go backend, go backend, go backend, go back
backtrack (branchbacktrack (branchbacktrack (branchbacktrack (branch----andandandand----bound) in bound) in bound) in bound) in PodemPodemPodemPodem::::all signals are initialised to "X"all signals are initialised to "X"all signals are initialised to "X"all signals are initialised to "X"fault sensitisation fault sensitisation fault sensitisation fault sensitisation during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only one step to primary outputs (branch)one step to primary outputs (branch)one step to primary outputs (branch)one step to primary outputs (branch)immediate line justification of selected signal to primary immediate line justification of selected signal to primary immediate line justification of selected signal to primary immediate line justification of selected signal to primary inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of decision tree)decision tree)decision tree)decision tree)succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict situations (bound)situations (bound)situations (bound)situations (bound)new branchnew branchnew branchnew branch
MicroLab, VLSI-20 (14/26)
JMM v1.4
PODEM: ExamplePODEM: ExamplePODEM: ExamplePODEM: Example
Heuristics in FAN algorithmHeuristics in FAN algorithmHeuristics in FAN algorithmHeuristics in FAN algorithmfault propagationfault propagationfault propagationfault propagation
propagate to PO on path which is best observablepropagate to PO on path which is best observablepropagate to PO on path which is best observablepropagate to PO on path which is best observable
line justificationline justificationline justificationline justificationstart with the most difficult path to controlstart with the most difficult path to controlstart with the most difficult path to controlstart with the most difficult path to control
heuristics help to find test vectors fasterheuristics help to find test vectors fasterheuristics help to find test vectors fasterheuristics help to find test vectors faster
MicroLab, VLSI-20 (16/26)
JMM v1.4
Controllability and Controllability and Controllability and Controllability and observabilityobservabilityobservabilityobservabilitymeasuremeasuremeasuremeasure
often used to solve often used to solve often used to solve often used to solve npnpnpnp----complete problemscomplete problemscomplete problemscomplete problemsheuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a given timegiven timegiven timegiven timetestability measure methods:testability measure methods:testability measure methods:testability measure methods:
sandiasandiasandiasandia controllability/controllability/controllability/controllability/observabilityobservabilityobservabilityobservability analysis analysis analysis analysis program (program (program (program (scoapscoapscoapscoap))))each node in a circuit gets values for its each node in a circuit gets values for its each node in a circuit gets values for its each node in a circuit gets values for its controllability, controllability, controllability, controllability, observabilityobservabilityobservabilityobservability and testabilityand testabilityand testabilityand testabilityhigh values indicate nodes which are hard to control high values indicate nodes which are hard to control high values indicate nodes which are hard to control high values indicate nodes which are hard to control or to observeor to observeor to observeor to observedistinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllabilitydistinguish between combinational and sequential distinguish between combinational and sequential distinguish between combinational and sequential distinguish between combinational and sequential valuesvaluesvaluesvalues
MicroLab, VLSI-20 (17/26)
JMM v1.4
ObservabilityObservabilityObservabilityObservability & Controllability& Controllability& Controllability& ControllabilityWhen propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often faced faced faced faced with several choices for which should be the next gate in our pawith several choices for which should be the next gate in our pawith several choices for which should be the next gate in our pawith several choices for which should be the next gate in our path.th.th.th.
XXXX????
????
We’d like to have a way to measure the We’d like to have a way to measure the We’d like to have a way to measure the We’d like to have a way to measure the observabilityobservabilityobservabilityobservability of a node, i.e., of a node, i.e., of a node, i.e., of a node, i.e., some indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outputs of puts of puts of puts of the chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whose se se se output was easiest to observe.output was easiest to observe.output was easiest to observe.output was easiest to observe.
Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between alternative ways of forcing a particular value:alternative ways of forcing a particular value:alternative ways of forcing a particular value:alternative ways of forcing a particular value:
want 0 herewant 0 herewant 0 herewant 0 herewhich input shouldwhich input shouldwhich input shouldwhich input shouldwe try to set to 0?we try to set to 0?we try to set to 0?we try to set to 0?
In this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure thecontrollabilitycontrollabilitycontrollabilitycontrollability of a node, i.e., some indication of howof a node, i.e., some indication of howof a node, i.e., some indication of howof a node, i.e., some indication of howeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringbacktracking we could choose the input that wasbacktracking we could choose the input that wasbacktracking we could choose the input that wasbacktracking we could choose the input that waseasiest to control.easiest to control.easiest to control.easiest to control.
combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate output output output output yyyy dependent on inputs dependent on inputs dependent on inputs dependent on inputs xxxx1111........xxxx3333
OR gate:OR gate:OR gate:OR gate:
AND gate:AND gate:AND gate:AND gate:
combinational "1" and "0" combinational "1" and "0" combinational "1" and "0" combinational "1" and "0" observabilityobservabilityobservabilityobservability of a logic gate of a logic gate of a logic gate of a logic gate dependent on output dependent on output dependent on output dependent on output yyyy and inputs and inputs and inputs and inputs xxxx2,2,2,2,xxxx3333
OR gate:OR gate:OR gate:OR gate:
AND gate:AND gate:AND gate:AND gate:
initialization (initialization (initialization (initialization (NNNN are internal nodes, are internal nodes, are internal nodes, are internal nodes, X,YX,YX,YX,Y are PI, PO's)are PI, PO's)are PI, PO's)are PI, PO's)
hmmm. I guesshmmm. I guesshmmm. I guesshmmm. I guesssmaller numberssmaller numberssmaller numberssmaller numbersare better...are better...are better...are better...
“testability” measure assumes that the further a node“testability” measure assumes that the further a node“testability” measure assumes that the further a node“testability” measure assumes that the further a nodeis from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe
if more than one, choose minif more than one, choose minif more than one, choose minif more than one, choose min
goals of fault simulation:goals of fault simulation:goals of fault simulation:goals of fault simulation:analyze circuit under faults conditionanalyze circuit under faults conditionanalyze circuit under faults conditionanalyze circuit under faults conditionqualify test sequence, fault coveragequalify test sequence, fault coveragequalify test sequence, fault coveragequalify test sequence, fault coveragereduce fault set during test generationreduce fault set during test generationreduce fault set during test generationreduce fault set during test generationgood quality fault models necessarygood quality fault models necessarygood quality fault models necessarygood quality fault models necessary
alternative to fault simulation in test generation alternative to fault simulation in test generation alternative to fault simulation in test generation alternative to fault simulation in test generation procedures:procedures:procedures:procedures:
parallel fault simulationparallel fault simulationparallel fault simulationparallel fault simulationprinciple: computing with 1principle: computing with 1principle: computing with 1principle: computing with 1----bit or bit or bit or bit or nnnn----bit wide bit wide bit wide bit wide variables need similar computing timevariables need similar computing timevariables need similar computing timevariables need similar computing timetest of ntest of ntest of ntest of n----1 faults at the same time1 faults at the same time1 faults at the same time1 faults at the same time
C'=[01110]MA
A'=[01000]A=[00000]
C=[01100]
MB
B'=[00100]B=[00000]MC≥ 1
bitposition fault1 fault free2 A s-a-13 B s-a-14 C s-a-15 C s-a-0
Fault GradingFault GradingFault GradingFault GradingSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsusing the techniques described here. Willusing the techniques described here. Willusing the techniques described here. Willusing the techniques described here. Willthey detect all the faulty parts?they detect all the faulty parts?they detect all the faulty parts?they detect all the faulty parts?
You could see how many different faultsYou could see how many different faultsYou could see how many different faultsYou could see how many different faultsyour vectors detect by inserting eachyour vectors detect by inserting eachyour vectors detect by inserting eachyour vectors detect by inserting eachpossible fault one at a time, running thepossible fault one at a time, running thepossible fault one at a time, running thepossible fault one at a time, running thevectors, then check to see if some outputvectors, then check to see if some outputvectors, then check to see if some outputvectors, then check to see if some outputwas different from the “good” machine onwas different from the “good” machine onwas different from the “good” machine onwas different from the “good” machine onsome cycle. Need some cycle. Need some cycle. Need some cycle. Need *lots**lots**lots**lots* of simulation…of simulation…of simulation…of simulation…probably impractical for large circuits evenprobably impractical for large circuits evenprobably impractical for large circuits evenprobably impractical for large circuits evenwith hardwarewith hardwarewith hardwarewith hardware----accelerated simulator.accelerated simulator.accelerated simulator.accelerated simulator.
You can use the same sorts of statisticalYou can use the same sorts of statisticalYou can use the same sorts of statisticalYou can use the same sorts of statisticalsampling techniques that other QAsampling techniques that other QAsampling techniques that other QAsampling techniques that other QAprograms employ: programs employ: programs employ: programs employ: randomlyrandomlyrandomlyrandomly select a setselect a setselect a setselect a setof faults, fault grade your vectors onof faults, fault grade your vectors onof faults, fault grade your vectors onof faults, fault grade your vectors onthose faults and use standard statisticalthose faults and use standard statisticalthose faults and use standard statisticalthose faults and use standard statisticaltechniques to see if fault coverage exceedstechniques to see if fault coverage exceedstechniques to see if fault coverage exceedstechniques to see if fault coverage exceedsa desired level. The level of confidence maya desired level. The level of confidence maya desired level. The level of confidence maya desired level. The level of confidence maybe increased by increasing the number ofbe increased by increasing the number ofbe increased by increasing the number ofbe increased by increasing the number ofsamples.samples.samples.samples.
MicroLab, VLSI-20 (23/26)
JMM v1.4
ConclusionConclusionConclusionConclusion
defects during chip fabrication are inevitabledefects during chip fabrication are inevitabledefects during chip fabrication are inevitabledefects during chip fabrication are inevitablefaults model defects on higher abstraction levelsfaults model defects on higher abstraction levelsfaults model defects on higher abstraction levelsfaults model defects on higher abstraction levelshigher chip complexity, more gates and less pads higher chip complexity, more gates and less pads higher chip complexity, more gates and less pads higher chip complexity, more gates and less pads reduce controllability, reduce controllability, reduce controllability, reduce controllability, observabilityobservabilityobservabilityobservability and thus and thus and thus and thus testabilitytestabilitytestabilitytestabilitytest pattern generation is going to be time test pattern generation is going to be time test pattern generation is going to be time test pattern generation is going to be time consuming and thus costlyconsuming and thus costlyconsuming and thus costlyconsuming and thus costlystructured design for test during chip development structured design for test during chip development structured design for test during chip development structured design for test during chip development is requiredis requiredis requiredis required
MicroLab, VLSI-20 (24/26)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Design for TestabilityDesign for TestabilityDesign for TestabilityDesign for Testability
Readings for next time…Readings for next time…Readings for next time…Readings for next time…WWWWesteesteesteeste: : : :
Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium): The digital circuit The digital circuit The digital circuit The digital circuit suffers from error suffers from error suffers from error suffers from error αααα ssss----aaaa----0. Try to find test patterns 0. Try to find test patterns 0. Try to find test patterns 0. Try to find test patterns by means of Dby means of Dby means of Dby means of D----algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use the the the the booleanbooleanbooleanboolean difference to calculate the test patterns.difference to calculate the test patterns.difference to calculate the test patterns.difference to calculate the test patterns.Result: T=xResult: T=xResult: T=xResult: T=x1111 xxxx2222 xxxx3333 xxxx4444 found by found by found by found by booleanbooleanbooleanboolean differencedifferencedifferencedifference
Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy): Calculate the Calculate the Calculate the Calculate the ScoapScoapScoapScoapcombinational controllability and combinational controllability and combinational controllability and combinational controllability and observabilityobservabilityobservabilityobservability values values values values for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO)Result: xResult: xResult: xResult: x1111 (1,1,7), x(1,1,7), x(1,1,7), x(1,1,7), x2222 (1,1,7), x(1,1,7), x(1,1,7), x(1,1,7), x3333 (1,1,5), x(1,1,5), x(1,1,5), x(1,1,5), x4 4 4 4 (1,1,5), (1,1,5), (1,1,5), (1,1,5), ssss1111 (3,2,5), s(3,2,5), s(3,2,5), s(3,2,5), s2222 (2,4,3), s(2,4,3), s(2,4,3), s(2,4,3), s3333 (2,3,3), y (4,5,0)(2,3,3), y (4,5,0)(2,3,3), y (4,5,0)(2,3,3), y (4,5,0)
Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy): a) circuit with stucka) circuit with stucka) circuit with stucka) circuit with stuck----atatatat----0 fault at 0 fault at 0 fault at 0 fault at ssss1111. b) circuit with stuck. b) circuit with stuck. b) circuit with stuck. b) circuit with stuck----atatatat----0 fault at 0 fault at 0 fault at 0 fault at xxxx1111. Find all test patterns which detect the the fault . Find all test patterns which detect the the fault . Find all test patterns which detect the the fault . Find all test patterns which detect the the fault with means of the with means of the with means of the with means of the booleanbooleanbooleanboolean difference.difference.difference.difference.Result equations a) x=(xResult equations a) x=(xResult equations a) x=(xResult equations a) x=(x1111+x+x+x+x2222)x)x)x)x3333, b) x=x, b) x=x, b) x=x, b) x=x1111xxxx2222xxxx3333
MicroLab, VLSI-21 (1/94)
JMM v1.4
VLSI Systems DesignTop-down Design and HDLs
Overview?Top down design-flow, VHDL hardware description language, test-bench methodology
Goal: You are able to design circuits with the VHDL language with behavioral, dataflow and structural modeling. You are familiar with the top down design flow and the test-bench methodology.
It seems I have tohurry up!
MicroLab, VLSI-21 (2/94)
JMM v1.4
The Need for HDLsA specification is an engineering contract that lists all the goals for a project:
?goals include area, power, throughput, latency, functionality, test coverage, costs (NREs and piece costs). Helps you figure out when you’re done and how to make engineering tradeoffs. Later on goals help remind everyone (especially management) what was agreed to!
?partition the project into modules with well-defined interfaces so that each module can be worked on by a separate team. Gives the SW types a head start too! (Hardware/software codesign)
?A behavioral model serves as an executable specification that documents the exact behavior of all the individual modules and their interfaces. Since one can run tests, this model can be refined and finally verified through simulation.
We need a way to talk about what hardware should do without actually designing the hardware itself, i.e., need to separate functionality from implementation. We need a
Hardware Description Language
chapter 1
MicroLab, VLSI-21 (3/94)
JMM v1.4
The Need for HDLs cont.
?easier to explore ideas in HDLs than in logic gates?stepwise refinement: HDLs allow to describe
designs at various levels of abstraction?HDLs sustain description-synthesis method?pitfalls: abstract models are not precise
?first HDLs were introduced in late 70s?difficulties to develop general purpose HDL for
signal-processing and real-time applications and ...?portability needs lead to standardizations (Institute
of electrical and electronics engineering, IEEE)
MicroLab, VLSI-21 (4/94)
JMM v1.4
Hardware Description Languages
?textual HDLsVHDL, Verilog-HDL, HardwareC, etc.
?graphic HDLsSpecdChart, etc. (control & dataflow graphs)
?tabular HDLsBIF, etc. (FSMD models in tabular forms)
VHSIC HDL, Very High Speed Integrated Circuits. ADA-like verbose syntax, lots of redundancy
C-like concise syntax
Extensible types andsimulation engine. Logicrepresentations are notbuilt in and have evolvedwith time (IEEE-1164).
Built-in types and logicrepresentations. Oddly,this has led to slightlyincompatible simulatorsfrom different vendors.
Design is composed ofentities each of which can have multiple architectures. A configuration chooses what architecture is used for a given instance of an entity.
Design is composed ofmodules.
Behavioral, structural,logic-level modeling
Behavioral, structural,logic-level modeling
Synthesizable subset... Synthesizable subset...
Harder to learn and use,not technology-specific,DoD mandate.
Easy to learn and use,fast simulation, good forlogic. Gateway Design Automation
MicroLab, VLSI-21 (6/94)
JMM v1.4
Introduction to VHDL & Verilog
?rich & powerful language?data type driven
language?goal: documentation of
large complex systems
language structures?entity (hierarchy
interface)?architecture (behavior
of system)?configuration (binding
of entity and architecture)?package (library of
global types or blocks)
?simple & efficient language?hardware driven
language?goal: automatic
synthesis
language structures?module (blocks or sub-
blocks)?#include (file
structuring)
VHDL Verilog-HDL
MicroLab, VLSI-21 (7/94)
JMM v1.4
Introduction to VHDL & Verilog cont.
language features?signal data types (in, out, bidir, signal-strength ...)?hardware structures (memory, register-files, ...)?logic operators (shift, rotation, masking, ...)?asynchronous structures (set, reset of memories)?parallel or synchronous structures?constraints (pin, technology, area, delays, ...)?inter-process communications (shared medium,
message passing, ...)
VHDL
MicroLab, VLSI-21 (8/94)
JMM v1.4
Signals, Delays, Events, Concurrency
?digital systems in contrast to software systems are fundamentally about signals?signals in contrast to variables do have delays which
leads to signal waveforms?digital systems are comprised of components?digital systems do have concurrency of operation?events on signals lead to computations that may
generate events on other signals
a
b
sum
carry
5 10 15 20 25 30 35 40
time (ns)
event
chapter 2
MicroLab, VLSI-21 (9/94)
JMM v1.4
Signal Values
?signal values are physically associated to wires?VHDL language supports signal type: ?type: bit, values: ‘0’, ‘1’?type: bit_vector, values: “0001”, etc
?VHDL package IEEE 1164 supports signal type:?type: std_ulogic and vector std_ulogic_vector?std_ulogic is a 9 value logic
value interpretation
U un-initializedX forcing unknown0 forcing 01 forcing 1Z high impedanceW weak unknownL weak 0H weak 1- don’t care
MicroLab, VLSI-21 (10/94)
JMM v1.4
Resolved Signals
?it is common for components in a digital system to have multiple sources for the value of an input signal?many designs use buses: a group of signals that can
be shared among multiple sources?the values on shared signals will be determined
upon the type of interconnection, like wired logic?the signal values depend on its implementation? the VHDL simulator has to resolve the signals value? The IEEE 1164 package offers std_logic and
std_logic_vector signal types for resolved version of the signal std_ulogic and std_ulogic_vector
resolved signal necessary
unresolved signal
wired-or logic
MicroLab, VLSI-21 (11/94)
JMM v1.4
Entity
?the design entity is a primary programming abstraction in VHDL?entity defines the interface of a component, without
giving any information about the component behavior
+
entity HalfAdder isport (a,b : in bit;
sum,carry : out bit);end HalfAdder;
a
b
sum
carry
library IEEE;use IEEE.std_logic_1164.allentity HalfAdder is
port (a,b : in std_ulogic; sum,carry : out std_ulogic);
end HalfAdder;
chapter 3
MicroLab, VLSI-21 (12/94)
JMM v1.4
Exercises Ex401: Entity
?Ex401 (difficulty: easy): Define the entities of the following digital components. Use the unresolved 9 value logic of the IEEE 1164 package. Each component has to be edited in a separate file with the components name plus extension “.vhd” . The files have to be analyzed by the Synopsys command: gvan
Mux4to1i0
i1
sel
zi2i3
D_ffd
rNot
q
clk
sNot
qNot
a
bc
op
n z
8 bit data
32 bit data6 bit op-code
Alu32
use first letter ofcomponent name in capital,and first letter of signalname in small cap
MicroLab, VLSI-21 (13/94)
JMM v1.4
Architecture
?the design architecture is a primary programming abstraction in VHDL?architecture describes the internal behavior of a
component, without giving any information about the component IO’s?The behavioral description can take many forms.
These forms differ in the levels of abstraction and detail.
architecture behavior of HalfAdder is-- comment: declaration of variablesbegin...
end behavior;
functional descriptionof the system
MicroLab, VLSI-21 (14/94)
JMM v1.4
Entity-Architecture: Hierarchy(VHDL vs. Verilog)
library IEEE;use IEEE.std_logic_1164.all;entity FullAdder is
port (a,b,ci: in std_logic; co,s:out std_logic);end FullAdder;
architecture behavior of FullAdder is-- comment: declaration of variables...
L1: s1 <= (a xor b) after gate_delay;L2: s2 <= (cIn and s1) after gate_delay;L3: s3 <= (a and b) after gate_delay;L4: sum <= (s1 xor cIn) after gate_delay;L5: cOut <= (s2 or s3) after gate_delay;
end dataflow;
architecturedeclarativesegment
architecturebody
+
s1
s2
s3
L1L4
L3L2
L5
MicroLab, VLSI-21 (18/94)
JMM v1.4
Signal Assignments #1
?simple signal assignments
sum<=(a xor b) after 5 ns, (a or b) after 10 ns, (not a) after 15 ns;
sig <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;
clock <= ‘0’, not(clock) after 5 ns;
5 10 15 20 25 30 35 40
time (ns)
5 10 15 20 25 30 35 40
time (ns)
a <= “00000000_00000000”, to_stdlogicvector(x”abcd”) after 5 ns;
Type conversion from hexadecimalto std_logic_vector is defined in package std_logic_1164
MicroLab, VLSI-21 (19/94)
JMM v1.4
Conditional Signal Assignment #2
?The right hand value is computed immediately and assigned at some point in the future using the afterclause
library IEEE;use IEEE.std_logic_1164.all;
entity Mux4to1 isport (i0,i1,i2,i3: in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);z : out std_logic_vector(7 downto 0));
end Mux4to1;
architecture dataflow of Mux4to1 isbegin
z <= i0 after 5 ns when sel=“00” elsei1 after 5 ns when sel=“01” elsei2 after 5 ns when sel=“10” elsei3 after 5 ns when sel=“11” else“00000000” after 5 ns;
end dataflow;
one singlesignalassignment
MicroLab, VLSI-21 (20/94)
JMM v1.4
Exercises Ex402: Conditional Signal Assignment
?Ex402 (difficulty: easy): Define the VHDL code of a 1bit ALU with the operations: AND, OR, FullAdder. Use the resolved 9 value logic of the IEEE 1164 package. The Simple1bitALU.vhd file has to be analyzed and simulated by the Synopsyscommands: gvan and vhdldbx
a
bresult
opcode
carry
Alu32carryIn
MicroLab, VLSI-21 (21/94)
JMM v1.4
Delays: Delta Delay Model?The VHDL language distinguished between tree
delay models:?Delta delay model?Inertial delay model (default)?Transport delay model
? Delta delay model?If no delay is specified, a delta delay is assumed. A delta
delay is as small as zero delay. It is used by the simulator which sums delta delays to zero.
in1in2zs1s2s3s4
0 10 20 30 40 50 60 70
10 ? 2? 3?
in2s2s3z
architecture delta_delay of Comb issignal s1,s2,s3,s4: std_logic:=0;begin
s1 <=not(in1);s2 <=not(in2);s3 <=not(s1 and in2);s4 <=not(s2 and in1);z <=not(s3 and s4);
end delta_delay;
MicroLab, VLSI-21 (22/94)
JMM v1.4
Delays: Inertial Delay Model
?Digital circuits have a certain amount of inertia. For example it takes a finite amount of time and a certain amount of energy for the output of a gate to respond to a change on the input? Inertial delay model (default)?a pulse shorter than the propagation delay will not
propagate to the output
input
out1
out2
5 10 15 20 25 30 35 40
time (ns)
2 ns
8 nsoutput for delay: 8 ns
output for delay: 2 ns
inputout
out1 <= (a xor b) after 8 ns;out2 <= (a xor b) after 2 ns;
VHDL’93!sum <=reject 2 ns inertial (a xor b) after 5 ns;
MicroLab, VLSI-21 (23/94)
JMM v1.4
Delays: Transport Delay Model
?Unlike switching devices, wires have a comparatively less inertia, As a result, wires will propagate signals with very small pulse width.?In modern technologies with increasingly small
feature sizes the wire delays dominate.? Transport delay model (default)?any pulse will propagate to the output, independent of
the delay
input
out1
5 10 15 20 25 30 35 40
time (ns)
8 ns output for delay: 8 ns
inputout
out1 <= transport (a xor b) after 8 ns;
MicroLab, VLSI-21 (24/94)
JMM v1.4
Delay Model in Practice?Accurate delay
modeling of wire delays is possible, although in practice it is difficult to obtain accurate estimates of the wire delay without proceeding through physical design and layout of the circuit.
library IEEE;use IEEE.std_logic_1164.all;
entity HalfAdder isport (a,b: in std_logic;
carry,sum:out std_logic);end HalfAdder;
architecture transport_delay of HalfAdder issignal s1,s2: std_logic:=‘0’;begin
s1 <= (a xor b) after 2 ns;s2 <= (a and b) after 2 ns;sum <= transport s1 after 4 ns;carry <= transport s2 after 4 ns;
end transport_delay;
s1
s2
ab
sum
carry
absumcarrys1s2
0 2 4 6 8 10 12 14
time (ns)
inertial
transport
MicroLab, VLSI-21 (25/94)
JMM v1.4
Exercises vlsi21: Conditional Assignments
?Ex403 (difficulty: easy): Write and simulate a VHDL model of a 2-bit comparator (compare on equality, filename: Comp2.vhd).
?Ex405 (difficulty: easy): Construct and test a VHDL module for generating the following waveforms.
?Ex vlsi21 (difficulty: easy): Have a look at the exercises at the end of chapter 3 of “VHDL: Starter’s Guide”
Comp2a
bc
abc
0 10 20 30 40 50 60
time (ns)
MicroLab, VLSI-21 (26/94)
JMM v1.4
The Process Construct #1
?The continuous assignment model is used when components correspond to gates.?The process construct enables the use of
conventional programming language constructs.?In contrast to concurrent signal assignment
statements a process is a sequentially executed block of code.?Control flow within a process is strictly sequential.?With respect to simulation time a process executes
entity Memory isport (addr,wrData: in std_logic_vector(31 downto 0);
wr,rd: in std_logic;rdData :out std_logic_vector(31 downto 0));
end Memory;
architecture behavioral of Memory istype memArray is array(0 to 1024) of std_logic_vector(31 downto 0);beginMemProcess: process(addr,wr)variable mem: memArray :=(
?The execution of a process is initiated whenever an event occurs on any signal in the sensitivity list?Once started the process executes to completion in
zero (simulation) time.?Processes execute concurrently with other
processes and concurrent signal assignments.?Concurrent signal assignments are in fact only
special cases of processes.
architecture behavior of MyBlock2 isbeginprocess(a,b)begin
c <= a and b after 5 ns;end process;
end behavior;
architecture behavior of MyBlock1 isbegin
c <= a and b after 5 ns;end behavior;
identical behavior
concurrent signal assignment
process
MicroLab, VLSI-21 (29/94)
JMM v1.4
VHDL vs. Verilog: Events
?process sensitivity listbegin statements; end process;?wait on/until/for
aReg:=a;bReg:=(x“00000000“) & b;for index in 1 to 32 loopif bReg(0)= ‘ 1‘ thenbReg(63 downto 32):=bReg(63 downto 32)+aReg(31 downto 0);
end if;bReg(63 downto 0):= ‘ 0‘ & bReg(63 downto 1);
end loop;m<=bReg after modulDelay;
end process;end behavioral;
Multiplier(32 bit)
a
b m
MicroLab, VLSI-21 (35/94)
JMM v1.4
Exercises vlsi21: Loops
?Ex405 (difficulty: easy): Write a VHDL code for a combinational shift logic block with 8 bit data buses with zero fill. Use the 2 bit signal shiftNumto indicate the number of bits to be shifted. If a std_logic_vector has to be converted to an integertype, the conv_integer() function from the std_logic_unsigned package can be used.
ShiftdataIn
shiftLeft shiftRight
shiftNum
dataOut
MicroLab, VLSI-21 (36/94)
JMM v1.4
More on Processes
?Never assign a value to a signal in different processes (multiple drives).
?Upon initialization all processes are executed at once.?Thereafter processes are executed in a data-driven
manner: ?activated by events on signal list of the process or?by waiting on occurrences of specific events using wait
statements
process Ay<=‘0‘;
process By<=‘1‘;
conflict- two drivers!- not synthesisable!
MicroLab, VLSI-21 (37/94)
JMM v1.4
The Wait Statement
?A more general way to specify when a process executes is the wait statement.?Wait statements explicitly specify the conditions
under which a process may resume execution after being suspended. ?With wait statements a process can be suspended at
multiple points.
wait for time expression;example: wait for 20 ns;
wait on signal;example: wait on clk,reset,status;
wait until condition;example: wait until (a = ‘1‘);
wait until inputData‘event;transmitData<=inputData;request<=‘1‘;
wait until acknowledge=‘1‘;request<=‘0‘;
wait until acknowledge=‘0‘; end process;
end behavioral;
consumer: processvariable receiveData:
std_logic_vector(31 downto 0);begin
wait until request=‘1‘;receiveData:=transmitData;acknowledge<=‘1‘;
wait until request=‘0‘;acknowledge<=‘0‘;
end process;
MicroLab, VLSI-21 (42/94)
JMM v1.4
Exercises vlsi21: Handshake
?Ex vlsi21.8a (difficulty: easy): Write a VHDL model for communication between an input processand an output process using handshaking protocol. The input process can only read a single word (32 bit) at a time. The output device requires a reversing byte order, which is performed by the input process. Assign a delay of 1 ns to each handshake signal.
?Ex vlsi21.8b (difficulty: medium, optional):Rewrite the above handshake model by using a clk1, clk2 signal for the two synchronous processes as well as a rst for initialization, and a start signal to initiate one data transfer. Do not use any wait constructions within the processes.
output processinput process
AsyncComm
inputData outputData
MicroLab, VLSI-21 (43/94)
JMM v1.4
Attributesattribute functionsignal’event function returning a Boolean value
signifying a change in value on this signalsignal’active function returning a Boolean value
signifying an assignment made to this signal (may not be a new value)
signal’last_event function returning the time since thelast event
signal’last_active function returning the time since the signal was last active
signal’last_value function returning the previous value of this signal
signal’left returns the leftmost value of signal in its defined range
signal’right returns the rightmost value of signal in its defined range
signal’hight returns the highest value of signal in its defined range
signal’low returns the lowest value of signal in its defined range
signal’ascending returns true if signal has an ascending range of values
signal’length returns the number of elements in the array signal
entity Periodic isport(Z: out std_logic);end Periodic;
architecture behavioral of Periodic isbeginprocessbegin
Z<=‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;wait for 50 ns;
end process;end behavioral;
Z
0 10 20 30 40 50
time (ns)
library IEEE;use IEEE.std_logic_1164.all;
entity TwoPhase isport(phi1,phi2,reset: out std_logic);end twoPhase;
architecture behavioral of TwoPhase isbeginreset_process: reset<=‘1’, ‘0’ after 10 ns;clock_process: processbegin
phi1<=‘1’, ‘0’ after 10 ns;phi2<=‘0’, ‘1’ after 12 ns, ‘0’ after 18 ns;wait for 20 ns;
end process;end behavioral;
resetphi1phi2
0 10 20 30 40 50time (ns)
60
MicroLab, VLSI-21 (45/94)
JMM v1.4
Modeling Finite State Machines
enable
clk
outputprocess
reset
stateregister
inputDataoutputData
outSig0outSig1outSig2
statetransitionprocess
architecture behavioral of MooreFSM istype StateType is (MyState,YourState,InitState);signal state : StateType;signal outputData: std_logic_vector(5 downto 0);begin
?Ex409 (difficulty: easy): Write a VHDL model for a traffic light controller. Use a Moore type FSM. The signal carPresent indicates cars running on the main street which always have priority. If no cars are present on the main street, the secondary street gets green lights.
0 0 11 0 0
red orang
egre
en
GreenState
OrangeState
RedState1
RedState2
carPresent
carPresent
carPresent
carPresent
mainsecond
1 0 00 1 0
red orang
egre
en
mainsecond
1 0 00 0 1
red orang
egre
en
mainsecond
0 1 01 0 0
red orang
egre
en
mainsecond
reset
MicroLab, VLSI-21 (47/94)
JMM v1.4
Modeling Structure
?a structural model of a system is described in terms of interconnection of its components? a structural model consists of 3 features:?component declaration?signal declaration?component interconnection
ab
sumcarry
HalfAdder3
ab
sumcarry
HalfAdder3ab
sumcarry
HalfAdder3in1in2
cIn
sum
cOut
s1
s2
s3
za
b
OR2
ports
componentdeclaration
componentinterconnectionH1 H2
O3
component label
za
b
OR2
chapter 5
MicroLab, VLSI-21 (48/94)
JMM v1.4
Example: Structural Model
library IEEE;use IEEE.std_logic_1164.all;
entity FullAdder3 isport (in1,in2,cIn: in std_logic;
sum,cOut: out std_logic);end FullAdder3;
architecture structural of FullAdder3 iscomponent HalfAdder3port(a,b: in std_logic;
sum,carry: out std_logic);end component;
component OR2port(a,b: in std_logic;
z: out std_logic);end component;
signal s1,s2,s3: std_logic;
beginH1: HalfAdder3 port map(a=>in1,b=>in2,
sum=>s1,carry=>s3);H2: HalfAdder3 port map(a=>s1,b=>cIn,
sum=>sum,carry=>s2);O3: OR2 port map(a=>s2,b=>s3,
z=>cOut);end structural;
component declaration
signal declaration
componentinterconnection(netlist)
component behaviordescribed elsewhere
MicroLab, VLSI-21 (49/94)
JMM v1.4
Exercises vlsi21: Structural Model
? Ex410 (difficulty: medium): Write a VHDL code for the structural model of the FullAdder3 described in the previous transparency. Assume a delay of 1 ns for all logic gates
a) Write the structural VHDL code for a HalfAdder.b) Write the VHDL codes for the necessary logic
gates like OR2 and others in one file (logicgates.vhd)
b) Write the VHDL code for FullAdder3 c) Analyze and simulate the whole circuit. Be aware
of the correct sequence of analyzing.
MicroLab, VLSI-21 (50/94)
JMM v1.4
VHDL vs. Verilog: StructuralDescription
library IEEE;use IEEE.std_logic_1164.all;entity FullAdder4 is
port (a,b,cIn:in std_logic; cOut,sum:out std_logic);
end FullAdder4;
architecture flatStructure of FullAdder4 iscomponent XOR
port(a,b: in std_logic; z:out std_logic);end component;component AND2
port(a,b: in std_logic; z:out std_logic);end component;component OR3
port(a,b,c: in std_logic; z:out std_logic);end component;signal net1,net2,net3,net4:std_logic;
beginu1: XOR port map (a,b,net1);u2: XOR port map (cIn,net1,sum);u3: AND2 port map (cIn,a,net2);u4: AND2 port map (cIn,b,net3);u5: AND2 port map (a,b,net4);u6: OR3 port map (net2,net3,net4,cOut);
architecture dataFlow of FullAdder5 issignal tmp: std_logic_vector(1 downto 0);begin
tmp <= ‘0‘ & a + b + cIn;cOut <= tmp(1);sum <= tmp(0);
end behavior; module FullAdder5 (a,b,cIn,sum,cOut);input a,b,cIn;output cOut,sum;
assign cOut,sum = a + b + cIn;endmodule
VHDL
Verilog-HDL
MicroLab, VLSI-21 (52/94)
JMM v1.4
Hierarchy, Abstraction, and Accuracy
?Structural models simply describe interconnections?Structural models do not describe any form of
behavior?Hierarchy expresses different levels of detail?Structural models are a way to manage large,
complex designs?Modern designs have several 10 millions of gates?Simulation time: the more detailed a design is
described, the more events are generated and thus the larger the simulation time will be needed.
FullAdder3
OR2 HalfAdder3
AND2 XOR2
top level
bottom level
MicroLab, VLSI-21 (53/94)
JMM v1.4
Generics?The VHDL language provides the ability to construct
parameterized models using the concept of generics
library IEEE;use IEEE.std_logic_1164.all;
entity HalfAdder4 isgeneric(adderDelay: Time:=3 ns);port(a,b : in std_logic;
sum,carry: out std_logic;end HalfAdder4;
architecture genericDelay of HalfAdder4 iscomponent AND2 isgeneric(andDelay: Time);port(a,b : in std_logic; z: out std_logic;end component;
component XOR2 isgeneric(xorDelay: Time);port(a,b : in std_logic; z: out std_logic;end component;
beginC1: XOR2 generic map(12 ns) port map(a,b,sum);C2: AND2 generic map(adderDelay) port map(a,b,carry);end genericDelay;
entity AND2 isgeneric(andDelay: Time);port(a,b : in std_logic; z: out std_logic;end AND2;
architecture genericDelay of AND2 isbegin
z<=a and b after andDelay;end genericDelay;
values to genericscan be assigned atdifferent locations
no semi columnneeded
MicroLab, VLSI-21 (54/94)
JMM v1.4
More on Generics?Within a structural model there are two ways in
which the values of generic constants of lower level components can be specified:?in the component declaration?in the component instantiation
?If both are specified, then the value provided by the generic map() takes precedence.?If neither is specified, then the default value
defined in the model is used.library IEEE;use IEEE.std_logic_1164.all;entity GenericOR isgeneric(n: positive:=2);port(in1: in std_logic_vector((n-1) downto 0); z: out std_logic);end GenericOR;
architecture behavioral of GenericOR isbeginprocess(in1)variable sum: std_logic:=‘0‘;
beginsum:=‘0‘;for i in 0 to (n-1) loopsum:=sum or in1(i);
end loop;z<=sum;
end process;end behavioral;
MicroLab, VLSI-21 (55/94)
JMM v1.4
Exercises vlsi21: Hierarchy, Generic
? Ex411 (difficulty: medium): Write a VHDL code of an 8 bit ALU based on the definitions made in Ex402 with the Simple1BitALU.
a) Write a behavioral VHDL code for ALU8b.vhd b) Write the structural VHDL code for ALU8 in one
file ALU8s.vhd. Assume a delay of 1 ns for all logic gates. What is the worst case delay of the ALU8.
? Ex412 (difficulty: easy): Write a VHDL code of an n bit register with reset and enable inputs (NbitRegister.vhd).
MicroLab, VLSI-21 (56/94)
JMM v1.4
Configuration
?Structural models may employ different levels of abstraction?Each component in a structural model may be
described as a behavioral or a structural model?Configuration allows stepwise refinement in a
Configuration associates an architecturedescription to each component:
- behavioral or - structural for
FullAdder3
MicroLab, VLSI-21 (57/94)
JMM v1.4
Configuration: Component Binding
q
clk
reset
d
Comb(combinational
logic) carry
ab
sum
architecture gataLevel of Comb is- - -
architecture lowPower of Comb is- - -
architecture highSpeed of Comb is- - -
architecture behavioral of Comb is- - -
?Example of binding architectures: A bit-serial adder?one of the different architectures must be
bound to the component C1 for simulation?entity is not bound as interfaces do not change
C1
C2Dff
rst clock
carryIn
MicroLab, VLSI-21 (58/94)
JMM v1.4
Configuration: Default Binding Rules
?To analyze different implementations, we simply change the configuration, compile and simulate.?When newer component models become available we
bind the new architecture to the component
Default binding rules:?if the entity name is the same as the component
name, then this entity is bound to the component?if there are different architectures in the working
directory, the last compiled architecture is bound to the entity
MicroLab, VLSI-21 (59/94)
JMM v1.4
Example: Configuration
configuration CFG_HighSpeed of SerialAdder is
for structuralfor C1: Comb use entity WORK.Comb(highSpeed);end for;
for C2: Dff use entity MyLibrary.MyDff(behavioral)generic map(gateDelay=>5 ns)port map(my_clk=>clk, my_d=>d,
my_q=>q, my_rst=>rst);end for;
end for;
end CFG_HighSpeed;
library nameentity namearchitecture name
entity nameconfiguration name(used for simulation)
if different component than described in entity is used, thenI/O mapping must be declared.
q
clk
reset
d
Comb(combinational
logic)carry
in1in2
C1
C2 MyDff
rst clock
carryIn
highSpeed
behavioral
sum
MicroLab, VLSI-21 (60/94)
JMM v1.4
Exercises vlsi21: Configuration
? Ex 413 (difficulty: easy): Write a VHDL code of the bit-serial adder shown in the previous transparency SerialAdder.vhd
a) Construct a model for the two components Comb and MyDff and place them both in your WORK library (don‘t use the library MyLibrary yet).
b) Adapt the configuration, compile and simulate it.
? Ex414 (difficulty: medium): Consider the circuit shown below (ConfigExample). Construct a structural model comprised of three components. However in the configuration use only two components by using a n-input AND gate.
&
&
1?
i1i2i3
o1
MicroLab, VLSI-21 (61/94)
JMM v1.4
Subprograms, Packages and Libraries
?VHDL provides mechanisms for structuring programs, reusing software modules, and otherwise managing design complexity.
?Packages contain definitions of procedures and functions that can be shared across different VHDL models.?Packages may contain user defined data types and
constants and can be placed in libraries.
?Summary: procedures, functions, packages and libraries provide facilities for creating and maintaining modular and reusable VHDL programs.
chapter 6
MicroLab, VLSI-21 (62/94)
JMM v1.4
Functions
?Functions are used to compute a value based on the values of the input parameters. Functions are placed in declarative parts. Example of function definition:
?Functions cannot modify parameter values (procedures can). Example of function call:
?Functions execute in zero simulation time, thus wait statements cannot exist in functions. Parameters are restricted to be of mode in.
function rising_edge (signal clock: in std_logic) return boolean;
rising_edge(clk)
function rising_edge (signal clock: std_logic) return boolean isvariable edge: boolean:=false;begin
edge:=(clock= ‘ 1‘ and clock‘event);return(edge);
end rising_edge;
mode not necessary
MicroLab, VLSI-21 (63/94)
JMM v1.4
Example: Type Conversion Function with Functions
?As VHDL is a type sensitive language, type conversions are quite often necessary.
?Many conversion procedures as well as resolution functions can be found in std_logic_1164 or std_logic_arith libraries and others. Have a look at $SYNOPSYS/packages/IEEE/src/
function to_bitvector(svalue: std_logic_vector) return bit_vector isvariable outvalue: bit_vector(svalue‘length-1 downto 0);beginfor i in svalue‘range loopcase svalue i iswhen ‘0‘ => outvalue i:=‘0‘;when ‘1‘ => outvalue i:=‘1‘;when others => outvalue i:=‘0‘;end case;
end loop;end to_bitvector;
note: size is not declared
MicroLab, VLSI-21 (64/94)
JMM v1.4
Procedures?Procedures are subprograms that can modify one or
more of the input parameters. Example of procedure declaration reading from a file f:
?if the class of the procedure parameters is not explicitly declared, then the following rules apply:?parameters of mode in are assumed to be of class constant?parameters of mode out or inout are assumed to be of class
variable
?Variables declared within a procedure are initialized on each call to the procedure and their values do not persists across invocations of the procedure.?Signals cannot be declared within procedures?Poor programming: Procedures declared within
process can make assignments to signals corresponding to the ports of the encompassing entity.?Procedure call:
procedure read_v1d (variable f: in text; v: out std_logic_vector);
Example: Procedurelibrary IEEE;use IEEE.std_logic_1164.all;entity CPU isport(di: out std_logic_vector(31 downto );
addr: out std_logic_vector(2 downto 0);r,w: out std_logic;do: in std_logic_vector(31 downto 0);s: in std_logic);
end CPU;
architecture behavioral of CPU isprocedure Mread(address: in std_logic_vector(2 downto 0);
signal r: out std_logic;signal s: in std_logic;signal addr: out std_logic_vector(2 downto 0);signal data: out std_logic_vector(31 downto 0)) is
beginaddr<=address;r<=‘1‘;wait until s=‘1‘;data <= do;r<=‘0‘;
end Mread;
begin-- CPU behavioral-- descriptionend behavioral;
procedure Mwrite(address: in std_logic_vector(2 downto 0);signal data: in std_logic_vector(31 downto 0);signal addr: out std_logic_vector(2 downto 0);signal w: out std_logic;signal di: out std_logic_vector(31 downto 0)) is
beginaddr<=address;w<=‘1‘;wait until s=‘1‘;di <= data;w<=‘0‘;
end Mwrite;
MicroLab, VLSI-21 (66/94)
JMM v1.4
Overloading
?A very useful feature of the VHDL language is the ability to overload a subprogram or an operator.?Imagine writing different Flip-Flop models with no
and with asynchronous inputs and with different argument types. With the overloading feature only one single Flip-Flop name can be used.?Example for Dff calls:
?From the type and number of arguments we can tell which procedure we meant to use.?Note that in std_logic_1164.vhd the boolean
functions and, or, etc have been defined for std_logic types, the functions +,*, etc have been defined for certain predefined types of the language such as integer. See also std_logic_arith package.
Dff(clk,d,q,qbar);
Dff(clk,d,q,qbar,reset,clear);
function “*“(arg1,ar2: std_logic_vector) return std_logic_vector;
function “+“(arg1,ar2: singed) return signed;
MicroLab, VLSI-21 (67/94)
JMM v1.4
Packages
?Locally related functions and procedures can be grouped into packages, and thus easily be shared among designs and people.
package MyLibraryPackage is---- type declarations-- function declarations-- procedure declarations--end MyLibraryPackage;
package body MyLibraryPackage is---- functions-- procedures--end MyLibraryPackage;
package declaration
package body
similar to VHDL entitydefines interfaces
similar to VHDL architecturedefines behavior
?package declaration needs to be analyzed first, and then package body can be analyzed.?Packages are used as libraries and referenced within
VHDL design units via the use clause.
MicroLab, VLSI-21 (68/94)
JMM v1.4
Example: Package Declaration
package std_logic_1164 is
type std_ulogic is (‘U‘, -- uninitialized‘X‘, -- forcing unknown‘0‘, -- forcing 0‘1‘, -- forcing 1‘Z‘, -- high impedance‘W‘, -- weak unknown‘L‘, -- weak 0‘H‘, -- weak 1‘-‘ -- don‘t care);
type std_ulogic_vector is array (natural range <>) of std_ulogic;subtype std_logic is resolved std_ulogic;
type std_logic_vector is array (natural range <>) of std_logic;
?Each design unit - entity, architecture, package - is analyzed (compiled) and placed in a design library.?Libraries are generally implemented as directories
and are referenced by a logical name.?In VHDL the libraries STD and WORK are
implicitly declared.?WORK is the working design library normally
placed in a local directory.?Once a library has been declared, all of the
functions, procedures and type declarations of a package can be accessed.
visibility must be establishedfor each design unit – entity-separately
all functions, procedures, typed are visible
only the „xnor“ function is visible
library IEEE;use IEEE.std_logic_1164.all;
library IEEE;use IEEE.std_logic_1164.xnor;
MicroLab, VLSI-21 (70/94)
JMM v1.4
Example: Libraries and Packages
package MyPackage is--end MyPackage;
package body MyPackage is--end MyPackage;
MyPackage.vhd
DEFAULT: ./WORK
MyLibrary : ./libuse = . ./srctimebase = ns
.synopsys_vss.setup
/home/MyHome/- VHDLdesign/
- WORK/- lib/- src/
design environment .synopsys_vss.setup
source file: MyPackage.vhd
cd /home/MyHome/VHDLdesigngvan –w MyLibrary src/MyPackage.vhd
gvan MyVHDLdesign.vhd
in a unix shell:analyze the package MyPackageanalyze the design MyVHDLdesign
library MyLibrary;use MyLibrary.MyPackage.all;-- use MyLibrary.all;
entity MyVHDLdesign is...
MyVHDLdesign.vhd
Synopsys tools on unix workstations
componentscan also beplaced intolibraries
libraryWORK
libraryMyLibrary
MicroLab, VLSI-21 (71/94)
JMM v1.4
Exercises vlsi21: Libraries & Packages? Ex415 (difficulty: medium): The small circuit
ConfigExample from exercise Ex414 shall be rewritten by using the components OR2 and ANDnfrom the library MyLibrary.
a) Write the VHDL file MyComponents.vhd holding the two components OR2 and ANDn and compile it into the library MyLibrary.
b) Rewrite the ConfigExample circuit using only library elements and call it LibraryExample.vhd, compile and simulate it.
? Ex416 (difficulty: medium): Write the VHDL package MyPackage with the functions OneCounter (counting ‚1‘) and ParityGenerator should accept std_logic_vectors or bit_vectors of any size), and analyze it into the library MyLibrary. Use the defined functions in your design PackageExample to show its functionality.
&
&
1?
i1i2i3
o1
OR2
ANDn
ANDn
MicroLab, VLSI-21 (72/94)
JMM v1.4
Exercises vlsi21: Packages? Ex417 (difficulty: medium): The bit-serial adder of
exercise Ex413 shall we rewritten using a procedure call for the Dff instead of a component (SerialAdder2.vhd). Place the procedure into a package MyPackage and analyze it into the library MyLibrary. Verify the functionality.
q
clk
reset
d
Comb(combinational
logic)carry
in1in2
C1
Dff
rst clock
carryIn
highSpeed
behavioral
sum
libraryMyLibrary
MicroLab, VLSI-21 (73/94)
JMM v1.4
VHDL vs. Verilog: Data Types
?type driven language?predefined data types
in packages: character, integer, real, bit, std_logic, textio, ...
?enumerate types?arrays?records?pointers
?arrays?run-time constants:
parameter?continuous driven
nets: wire, tri, ...?triggered assignments:
reg, integer, real, ...
VHDL Verilog-HDL
MicroLab, VLSI-21 (74/94)
JMM v1.4
VHDL vs. Verilog: Operators
Operator type function VHDL Verilog arithmetic a + b + + a - b - - a * b * * a / b / / a-b*n a div b mod % a-(a/b)*b rem logical a and b and & a or b or ¦ not(a and b) nand ~& a exor b xor ^ shift logic srl,sll >> shift arith. sra,sla rotate ror, rol reduction, concatenation
beginz(3) <= not(a and b and enable);z(0) <= not(abar and bbar and enable);abar <= not a;z(2) <= not(a and bbar and enable);abar <= not a;z(1) <= not(abar and b and enable);
end dataflow;
All the signal assignment statements (“<=“) happenconcurrently after some specified delay which defaultsto 1 “delta”, an infinitesimally small delay. Note thatconcurrent statements are always “running” so wheneverA, B or ENABLE change then ABAR, BBAR, and Z(0 to 3)will also change after some delay.
The delay in assigning a signal its new value means thatthe following statement is meaningful (it generates aperiodic waveform):
entity Demux2x4 is port(a,b,enable: in std_logic;z: out std_logic_vector(0 to 3););
end Demux2x4;
architecture behavioral of Demux2x4 isbegin
process(a,b,enable)variable abar,bbar: std_logic;
beginabar := not a;bbar := not b;if (enable = ‘1’) then
z(3) <= not(a and b);z(2) <= not(a and bbar);z(1) <= not(abar and b);z(0) <= not(abar and bbar);
elsez <= “1111”;
end if;end process;
end behavioral;
Statements within a process are executed sequentially,like a program. The process is scheduled for executionafter any events are processed for variables on itssensitivity list. Values of local variables are maintainedbetween executions.
local variables (separatecopies for each instanceof Demux2x4)
Process statementscan be compiled sobehavioral simulationscan be quite fast.
vector constant
MicroLab, VLSI-21 (81/94)
JMM v1.4
Synthesis
Idea: once an behavioral model has been finished why not use it to automatically synthesize a logic implementation in much the same was as a compiler generates executable code from a source program?
Synthesis programs process the HDL then
?infer logic and state elements
?perform technology-independent optimizations(e.g., logic simplification, state assignment)
Synopsys, Inc. is the current leader inproviding synthesis tools and synthesizableHDL modules.
a.k.a. “silicon compilers”
MicroLab, VLSI-21 (82/94)
JMM v1.4
Logic SynthesisZ <= (A and B) or C; if (SEL = ‘1’) then Z <= B;
else Z <= A;end if;
process(word)variable result: std_logic;
beginresult := ‘0’;for j in 0 to 3 loopresult := result xor word(j);
end loop;parity <= result;
end process;
signal x,y,sum: std_logic_vector(3 downto 0);sum <= unsigned(x) + unsigned(y);
ABC
ABC
Z
Z
10A
B
SEL
Z
A
BSEL Z
fulladder
Y(0)X(0)
SUM(0)
0full
adder
Y(1)X(1)
fulladder
Y(2)X(2)
fulladder
Y(3)X(3)
SUM(1) SUM(2) SUM(3)
NC
WORD(1) WORD(0)
WORD(2)
WORD(3) PARITY
MicroLab, VLSI-21 (83/94)
JMM v1.4
FSM Examplearchitecture behavioral of Moore is
type StateType is (S0,S1,S2,S3);signal current,next: StateType;
begin
process(current) -- state transitionbegin
case current iswhen S0 =>
if (a=‘1’) then next<=S2; end if;when S1 =>
if (a=‘1’) then next<=S0; else next<=S2; end if;when S2 =>
if (x=‘1’) then next<=S3; end if;when S3 =>
if (x=‘1’) then next<=S1; end if;end case;
end process;
process(current) -- output logicbegin
case current iswhen S0 => z <= ‘0’;when S1 => z <= ‘0’;when S2 => z <= ‘1’;when S3 => z <= ‘1’;
end case;end process;
process(clk,reset) -- state registerbegin
if (reset=‘0’) then current<=S0;elsif (clk’event and clk=‘1’) then
current <= next;end if;
end process;end behavioral;
S0
S2
S3
S1
a
a
aa
a
aa
a
z=0
z=0 z=1
z=1
MicroLab, VLSI-21 (84/94)
JMM v1.4
Further Reading
ISBN 0-13-181447-8 ISBN 0-7923-9472-0
Also:
?D. Perry, VHDL, Second Edition, McGraw Hill, 1993
? see VHDL tutorials at I3S-CD or on the web http://www.microlab.ch/academics/courses/vlsi/g.html
? don‘t forget to study the CBT tutorial on VHDL
MicroLab, VLSI-21 (85/94)
JMM v1.4
Test Bench /1
?avoid interactive simulation, because it can never be used again?test benches reduce total simulation development
time?test benches are used to verify designs during
stepwise refinement?test bench methodology bridges simulation with
automatic test equipment (ATE)
I can relaxmy test bench does everything automatically
MicroLab, VLSI-21 (86/94)
JMM v1.4
Test Bench /2
?compare a test bench with MicroLab-I3S:?there are chips and PCBs needed to be tested?there is a nice measurement equipment?there are skilled and hard working people?there are no signals coming or going to the outside of the
lab
responsegeneration
andverification
controland
stimulusgeneration
Test Bench
device under test (DUT)
why do we need MicroLabif my test bench does thejob as well
MicroLab, VLSI-21 (87/94)
JMM v1.4
Test Bench in Design Flowdesign ofVHDL model
test bench
inp out
test bench
inp out
simulation ofVHDL model
synthesis oflogic model
simulation oflogic model
place & routephysical design
simulation ofextracted model
ASIC fabrication
prototype test(ASIC)
FPGA synthesisplace & route
FPGA test(debugger)
test bench
inp outVHDLmodel
test benchtest machine
inp outFPGAchip
test benchtest machine
inp outASICchip
MicroLab, VLSI-21 (88/94)
JMM v1.4
VHDL Test Benchuse IEEE.std_logic_1164.allentity TestBench isend TestBench;architecture sample of TestBench is
signal clk, a: bit;signal b: bit;component MyCircuit
port(clk,a:in bit; b: out bit);end component;
beginDUT: MyCircuit port map (clk,a,b);processbeginclk <= ‘0’, ‘1‘ after 20 ns, ‘0‘ after 70 ns; wait for 100 ns;
end process;TestPatternGenerator: blockbegin
processbegina <= ‘0’; -- test cycle 1wait for 100 ns;a <= ‘1’; -- test cycle 2wait for 100 ns;...
end process;end block;
end sample;
test bench hasno inputs, no outputs
call of device under test(DUT)
clk generation
test pattern generationon a cycle by cycle basis
response patternverification notyet implemented!
MicroLab, VLSI-21 (89/94)
JMM v1.4
Test Bench - Test Cycle
?design strictly synchronous circuits?cycle based test benches
clock
apply input patterns capture output response
test cycle
input
output
valid
stable stable stable
MicroLab, VLSI-21 (90/94)
JMM v1.4
ProTest Test Machine
?test bench controls CAD simulator and test machine?low cost rapid prototyping and test system
MicroLab, VLSI-21 (91/94)
JMM v1.4
Conclusions
?HDLs are very useful for behavioral hardware system descriptions?abstract models do not precisely reflect the reality?restriction to synthesizable coding is necessary?technology independency opens the possibility to
fast FPGA prototyping?test benches increase chip quality and highly
decrease simulation time
MicroLab, VLSI-21 (92/94)
JMM v1.4
Exercises: VLSI-21: Test-Bench
?CAD Ex418: Test-Bench (difficulty: easy) Instead of interactive simulation or writing macros for interactive simulation, it is state-of-the-art to use test-benches for simulation and chip test. Write a test bench file tb_SerialAdder2.vhd for the previous exercise Ex417. Generate the clock signal with a process and write sequential test cycles for the input signals. Be aware that the test-bench has no input and output signals, but calls the unit-under-test (UUT) and generates all stimuli.
test bench
inp outVHDLmodel
MicroLab, VLSI-21 (93/94)
JMM v1.4
Coming Up...
?Next topic…CAD exercises and mini FPGA projects PWM, blackjack
dealer, simple microprocessor, etc
?Readings for next time...VHDL tutorialsA Prototype Test System for ASICs and FPGAs with a Tight
Link to VHDL and Verilog-HDL Based CAD Simulators, DATE’99. Design Automation and Test Engineering in Europe Conference, Jacomet et. al. (see on the MicroLabweb)
On a Development Environment for Real-Time information Processing in System-on-Chip Solutions, SBCCI’01, IEEE 14th Symposium on Integrated Circuit and System Design, Brazil Sept. 2001, Jacomet et. al. (see on the MicroLab web)
MicroLab, VLSI-21 (94/94)
JMM v1.4
Exercises: VLSI-21 #1
?CAD Ex45x: PWM Project (difficulty: easy; time: medium): Design of a pulse width modulator (PWM) controlling a DC-motor. The PWM shall have an microprocessor interface. The VHDL design is simulated, compiled and implemented into an FPGA and is supposed to drive small dc motor.
?CAD Ex450: (difficulty: easy): Design the VHDL code of the PWM element. The btrdy and acksignals are handshake signals for communication with the microprocessor data bus. A value 0 on the 8-bit data bus will switch off the dc motor (pOut=‘1‘), a non-zero value will generate a PWM signal with an on-time of (data/256)*100% of a period. Analyze the VHDL syntax with gvan.
PWMpOut
data
btrdyack
8
clk
rst
PWM period
(data/266) * 100%
MicroLab, VLSI-21 (95/94)
JMM v1.4
Exercises: VLSI-21 #2
?CAD Ex451: (difficulty: easy): Design a test-bench for the PWM. Simulate your VHDL code with the Synopsis VSS simulator and use your test-bench to verify its correct behavior.?Result: see exercise Ex451 on the MicroLab web
?CAD Ex452 (difficulty: easy): Synthesize the PWM VHDL code into a gate level schematic for a Xilinx FPGA target technology. Connect your VHDL signals to the correct FPGA pins. Perform the place&route of the logic elements. ?Result: see exercise Ex452 on the MicroLab web
?CAD Ex453 (difficulty: easy): Download your PWM circuit into an FPGA and and applying different PWM values to your circuit by the GECKO User Interface tool. Use an oscilloscope to verify its correct output behavior. This exercise has to be done in MicroLab, using the GECKO system.?Result: see exercise Ex453 on the MicroLab web
MicroLab, VLSI-21 (96/94)
JMM v1.4
Exercises: VLSI-21 #3
?CAD Ex400 (difficulty: easy): Design VHDL a 2:1 multiplexer. Use a dataflow model. Simulate your VHDL code with the Synopsys VSS simulator. Get familiar with interactive simulation.?Result: see exercise Ex400 on the microlab web
?CAD Ex401 (difficulty: medium): Design in VHDL a the SN74160 synchronous decimal counter. Use a behavioral model. Simulate your VHDL code with the Synopsis VSS simulator and use macros for interactive simulation.?Result: see exercise Ex401 on the microlab web
?CAD Ex402 (difficulty: easy): Schematic entry of the blackjack-dealer on block-level using SynopsysSGE tool.?Result: see exercise Ex402 on the microlab web
MicroLab, VLSI-21 (97/94)
JMM v1.4
Exercises: VLSI-21 #4
?CAD Ex403 (difficulty: easy): Skeleton VHDL code generation for blackjack-dealer from block-level schematics using Synopsys SGE tool.?Result: see exercise Ex403 on the microlab web
?CAD Ex404 (difficulty: medium): Design the VHDL code of your blackjack-dealer. Use the prepared templates as a guide.?Result: see exercise Ex404 on the microlab web
?CAD Ex405 (difficulty: medium): Write a VHDL test bench for your blackjack dealer. Generate the following sequence of card values: 3, 11, 11, 7, 2, 11, 6.?Result: see exercise Ex404 on the microlab web
(final result is: 21)
MicroLab, VLSI-21 (98/94)
JMM v1.4
Exercises: VLSI-21 #5
?CAD Ex406 (difficulty: easy): Synthesize the blackjack dealer VHDL code into a gate level schematic for a Xilinx FPGA target technology. Perform the place&route of the logic element. ?Result: see exercise Ex406 on the microlab web
?CAD Ex407 (difficulty: medium): Perform a back-annotation of your FPGA chip and simulate it again with the real timing information. Does your chip still work? Look for the errors.?Result: see exercise Ex407 on the microlab web
?CAD Ex408 (difficulty: medium): Download your blackjack dealer circuit into an FPGA and run your test bench again on the ProTest test system. This exercise has to be done in MicroLab.?Result: see exercise Ex408 on the microlab web
MicroLab, VLSI-22 (1/40)
JMM v1.4
VLSI Design IVLSI Design IVLSI Design IVLSI Design IAutomatic Synthesis of Digital CircuitsAutomatic Synthesis of Digital CircuitsAutomatic Synthesis of Digital CircuitsAutomatic Synthesis of Digital Circuits
Why should I not enjoyWhy should I not enjoyWhy should I not enjoyWhy should I not enjoylife instead of drawing life instead of drawing life instead of drawing life instead of drawing schematics if CAD tools schematics if CAD tools schematics if CAD tools schematics if CAD tools can do the job for me?can do the job for me?can do the job for me?can do the job for me?
Goal: Goal: Goal: Goal: You are familiar with the design abstraction You are familiar with the design abstraction You are familiar with the design abstraction You are familiar with the design abstraction domains, the descriptiondomains, the descriptiondomains, the descriptiondomains, the description----synthesis design method, synthesis design method, synthesis design method, synthesis design method, the design strategies as well as the three synthesis the design strategies as well as the three synthesis the design strategies as well as the three synthesis the design strategies as well as the three synthesis steps. You know the FSMD architectural model as steps. You know the FSMD architectural model as steps. You know the FSMD architectural model as steps. You know the FSMD architectural model as well as the well as the well as the well as the interprocessinterprocessinterprocessinterprocess communication models.communication models.communication models.communication models.
MicroLab, VLSI-22 (2/40)
JMM v1.4
IntroductionIntroductionIntroductionIntroduction
system complexity is increasingsystem complexity is increasingsystem complexity is increasingsystem complexity is increasingproduct lifetime is decreasingproduct lifetime is decreasingproduct lifetime is decreasingproduct lifetime is decreasingdesign efficiency is essentialdesign efficiency is essentialdesign efficiency is essentialdesign efficiency is essentialnew design methods are necessarynew design methods are necessarynew design methods are necessarynew design methods are necessaryhigher abstraction levels are introducedhigher abstraction levels are introducedhigher abstraction levels are introducedhigher abstraction levels are introducedCAD tools able to handle large amounts of data are CAD tools able to handle large amounts of data are CAD tools able to handle large amounts of data are CAD tools able to handle large amounts of data are neededneededneededneeded
lowlowlowlow----level building blocks,level building blocks,level building blocks,level building blocks,highhighhighhigh----level architecturelevel architecturelevel architecturelevel architecture
Gee, I skipped these stepsGee, I skipped these stepsGee, I skipped these stepsGee, I skipped these stepswhen doing the project!when doing the project!when doing the project!when doing the project!
bottombottombottombottom----up approachup approachup approachup approachstructure of a system is describedstructure of a system is describedstructure of a system is describedstructure of a system is describedknowledge of an experienced designer is difficult to knowledge of an experienced designer is difficult to knowledge of an experienced designer is difficult to knowledge of an experienced designer is difficult to automateautomateautomateautomate
toptoptoptop----down approachdown approachdown approachdown approachbehaviour of a system is describedbehaviour of a system is describedbehaviour of a system is describedbehaviour of a system is describedtechnology independenttechnology independenttechnology independenttechnology independentCAD algorithms can search the solution space very CAD algorithms can search the solution space very CAD algorithms can search the solution space very CAD algorithms can search the solution space very quicklyquicklyquicklyquickly
DDDD QQQQ
clkclkclkclk
&&&&if data-ready then
bus := data;else
bus := high-Z;end if;
MicroLab, VLSI-22 (6/40)
JMM v1.4
Design methods for VLSI circuits Design methods for VLSI circuits Design methods for VLSI circuits Design methods for VLSI circuits
use advantages of topuse advantages of topuse advantages of topuse advantages of top----down and bottomdown and bottomdown and bottomdown and bottom----up design up design up design up design methodsmethodsmethodsmethods
automatic optimisations are not always ideal, automatic optimisations are not always ideal, automatic optimisations are not always ideal, automatic optimisations are not always ideal, but but but but an optimisation of a 70’000 gate design on a an optimisation of a 70’000 gate design on a an optimisation of a 70’000 gate design on a an optimisation of a 70’000 gate design on a 100’000 gate gate100’000 gate gate100’000 gate gate100’000 gate gate----array makes no sensearray makes no sensearray makes no sensearray makes no sense
need of abstract design languagesneed of abstract design languagesneed of abstract design languagesneed of abstract design languagesneed to keep the design cycle shortneed to keep the design cycle shortneed to keep the design cycle shortneed to keep the design cycle short
what it is nowwhat it is nowwhat it is nowwhat it is nowtoptoptoptop----down or bottomdown or bottomdown or bottomdown or bottom----up ?up ?up ?up ?
VLSI designs can be performed in 3 abstraction VLSI designs can be performed in 3 abstraction VLSI designs can be performed in 3 abstraction VLSI designs can be performed in 3 abstraction domains:domains:domains:domains:
each domain gives different freedoms to the each domain gives different freedoms to the each domain gives different freedoms to the each domain gives different freedoms to the designer designer designer designer
parallel or serial algorithmsparallel or serial algorithmsparallel or serial algorithmsparallel or serial algorithmslogic technology and bitlogic technology and bitlogic technology and bitlogic technology and bit----sliceslicesliceslicefullfullfullfull----custom and macrocustom and macrocustom and macrocustom and macro----cells ...cells ...cells ...cells ...
description and verification of first ideasdescription and verification of first ideasdescription and verification of first ideasdescription and verification of first ideasfunction and not implementation is askedfunction and not implementation is askedfunction and not implementation is askedfunction and not implementation is askedmodelling with general purpose languagesmodelling with general purpose languagesmodelling with general purpose languagesmodelling with general purpose languages
modulamodulamodulamodula----2, 2, 2, 2, pascalpascalpascalpascal, c, c++, lisp, ..., c, c++, lisp, ..., c, c++, lisp, ..., c, c++, lisp, ...matlabmatlabmatlabmatlab, , , , mathematicamathematicamathematicamathematica, ..., ..., ..., ...vhdlvhdlvhdlvhdl, , , , verilogverilogverilogverilog----hdlhdlhdlhdl, cathedral, ..., cathedral, ..., cathedral, ..., cathedral, ...graphic languages as graphic languages as graphic languages as graphic languages as veeveeveevee, ..., ..., ..., ...
transformation to structural domain: synthesistransformation to structural domain: synthesistransformation to structural domain: synthesistransformation to structural domain: synthesis
description and verification of a solutiondescription and verification of a solutiondescription and verification of a solutiondescription and verification of a solutionimplementation decisions takenimplementation decisions takenimplementation decisions takenimplementation decisions takenrestrictions like delay, signal strength, etc.restrictions like delay, signal strength, etc.restrictions like delay, signal strength, etc.restrictions like delay, signal strength, etc.modelling stylesmodelling stylesmodelling stylesmodelling styles
transformation to physical domain: transformation to physical domain: transformation to physical domain: transformation to physical domain: logic minimization, place and route toolslogic minimization, place and route toolslogic minimization, place and route toolslogic minimization, place and route tools
description and verification of physical description and verification of physical description and verification of physical description and verification of physical implementationimplementationimplementationimplementationprocess technology specific implementationprocess technology specific implementationprocess technology specific implementationprocess technology specific implementationfloorplanfloorplanfloorplanfloorplan, mask, mask, mask, mask----layout, packaginglayout, packaginglayout, packaginglayout, packagingdescription formatsdescription formatsdescription formatsdescription formats
design domains are divided in several abstraction design domains are divided in several abstraction design domains are divided in several abstraction design domains are divided in several abstraction levels:levels:levels:levels:system levelsystem levelsystem levelsystem levelmicro architecture levelmicro architecture levelmicro architecture levelmicro architecture levellogic levellogic levellogic levellogic levelcircuit levelcircuit levelcircuit levelcircuit level
MicroLab, VLSI-22 (13/40)
JMM v1.4
Abstraction: System LevelAbstraction: System LevelAbstraction: System LevelAbstraction: System Level
highest abstraction levelhighest abstraction levelhighest abstraction levelhighest abstraction leveldescription with description with description with description with HDLsHDLsHDLsHDLs or graphical block diagramsor graphical block diagramsor graphical block diagramsor graphical block diagrams
register transfer system is a pure sequential register transfer system is a pure sequential register transfer system is a pure sequential register transfer system is a pure sequential machinemachinemachinemachineuse of memory elements and combinational logicuse of memory elements and combinational logicuse of memory elements and combinational logicuse of memory elements and combinational logicregister transfer is a complete specification on register transfer is a complete specification on register transfer is a complete specification on register transfer is a complete specification on what a chip will do on every cyclewhat a chip will do on every cyclewhat a chip will do on every cyclewhat a chip will do on every cycle
circuit description on a quite low abstraction levelcircuit description on a quite low abstraction levelcircuit description on a quite low abstraction levelcircuit description on a quite low abstraction leveltoday only used to design optimised functional today only used to design optimised functional today only used to design optimised functional today only used to design optimised functional blocksblocksblocksblocks
lowest abstraction levellowest abstraction levellowest abstraction levellowest abstraction leveltransistor schematic or masktransistor schematic or masktransistor schematic or masktransistor schematic or mask----layoutlayoutlayoutlayoutcomparable to machine code in computer sciencecomparable to machine code in computer sciencecomparable to machine code in computer sciencecomparable to machine code in computer science
the goal is a fast as possible transfer of an idea to the goal is a fast as possible transfer of an idea to the goal is a fast as possible transfer of an idea to the goal is a fast as possible transfer of an idea to a chipa chipa chipa chipdescriptions in the 3 abstraction domainsdescriptions in the 3 abstraction domainsdescriptions in the 3 abstraction domainsdescriptions in the 3 abstraction domainsstrategies used:strategies used:strategies used:strategies used:
basic idea: divide and conquerbasic idea: divide and conquerbasic idea: divide and conquerbasic idea: divide and conquerdividing in modules, subdividing in modules, subdividing in modules, subdividing in modules, sub----modules until complexity modules until complexity modules until complexity modules until complexity of subof subof subof sub----modules is comprehensiblemodules is comprehensiblemodules is comprehensiblemodules is comprehensiblecomparison to software engineering: split programs comparison to software engineering: split programs comparison to software engineering: split programs comparison to software engineering: split programs in modules, procedures, subroutines.in modules, procedures, subroutines.in modules, procedures, subroutines.in modules, procedures, subroutines.
goal is reduction of complexitygoal is reduction of complexitygoal is reduction of complexitygoal is reduction of complexityidea: divide in similar building blocksidea: divide in similar building blocksidea: divide in similar building blocksidea: divide in similar building blocksidentical blocks, subidentical blocks, subidentical blocks, subidentical blocks, sub----blocks, cells, transistor sizesblocks, cells, transistor sizesblocks, cells, transistor sizesblocks, cells, transistor sizes1111----dim. arrays: bitdim. arrays: bitdim. arrays: bitdim. arrays: bit----slice techniqueslice techniqueslice techniqueslice technique2222----dim. arrays: systolic arraysdim. arrays: systolic arraysdim. arrays: systolic arraysdim. arrays: systolic arrays
different modules should not influence each otherdifferent modules should not influence each otherdifferent modules should not influence each otherdifferent modules should not influence each othersubsubsubsub----modules with well formed interfaces:modules with well formed interfaces:modules with well formed interfaces:modules with well formed interfaces:do not use transmission gatesdo not use transmission gatesdo not use transmission gatesdo not use transmission gateswell defined signal types and strengthswell defined signal types and strengthswell defined signal types and strengthswell defined signal types and strengthswell defined interconnection widths, etc.well defined interconnection widths, etc.well defined interconnection widths, etc.well defined interconnection widths, etc.
idea: reduction of complexity due to information idea: reduction of complexity due to information idea: reduction of complexity due to information idea: reduction of complexity due to information hidinghidinghidinghidingfew global variablesfew global variablesfew global variablesfew global variables
reduction of interreduction of interreduction of interreduction of inter----module influencesmodule influencesmodule influencesmodule influencesreduction of global wiringreduction of global wiringreduction of global wiringreduction of global wiring
time locality leads to time locality leads to time locality leads to time locality leads to synchronsynchronsynchronsynchron designs (compare designs (compare designs (compare designs (compare local variables in software engineering)local variables in software engineering)local variables in software engineering)local variables in software engineering)
I can’t see anythingI can’t see anythingI can’t see anythingI can’t see anything
automatic synthesis: transformation of a design automatic synthesis: transformation of a design automatic synthesis: transformation of a design automatic synthesis: transformation of a design from behavioural to structural domainfrom behavioural to structural domainfrom behavioural to structural domainfrom behavioural to structural domainsilicon compilation: transformation from silicon compilation: transformation from silicon compilation: transformation from silicon compilation: transformation from behavioural to physical domainbehavioural to physical domainbehavioural to physical domainbehavioural to physical domain
automatic synthesis tools on high abstraction levels automatic synthesis tools on high abstraction levels automatic synthesis tools on high abstraction levels automatic synthesis tools on high abstraction levels do not exist yetdo not exist yetdo not exist yetdo not exist yetnot every description is not every description is not every description is not every description is synthesizablesynthesizablesynthesizablesynthesizablesynthesis is a design process and not a only a synthesis is a design process and not a only a synthesis is a design process and not a only a synthesis is a design process and not a only a coding as in software engineeringcoding as in software engineeringcoding as in software engineeringcoding as in software engineeringsynthesis steps:synthesis steps:synthesis steps:synthesis steps:
allocation defines the necessary resourcesallocation defines the necessary resourcesallocation defines the necessary resourcesallocation defines the necessary resourcesclocking strategy, pipelining, memory structure etc. clocking strategy, pipelining, memory structure etc. clocking strategy, pipelining, memory structure etc. clocking strategy, pipelining, memory structure etc. have to be definedhave to be definedhave to be definedhave to be definedmanual allocation reduces the search space of manual allocation reduces the search space of manual allocation reduces the search space of manual allocation reduces the search space of design solutionsdesign solutionsdesign solutionsdesign solutionstradetradetradetrade----off between chipoff between chipoff between chipoff between chip----area and performancearea and performancearea and performancearea and performance
parallel implementations of designs have high parallel implementations of designs have high parallel implementations of designs have high parallel implementations of designs have high throughput, but consume large areasthroughput, but consume large areasthroughput, but consume large areasthroughput, but consume large areas
s1
s4
s6
s8s10 s14 s18 s22
areaareaareaarea
delaydelaydelaydelay
MicroLab, VLSI-22 (25/40)
JMM v1.4
Allocation: ExampleAllocation: ExampleAllocation: ExampleAllocation: Example
RTL exampleRTL exampleRTL exampleRTL examplex = a + b;x = a + b;x = a + b;x = a + b;y = a * c;y = a * c;y = a * c;y = a * c;z = x + d;z = x + d;z = x + d;z = x + d;x = y x = y x = y x = y ---- d;d;d;d;x = x + c;x = x + c;x = x + c;x = x + c;allocation: 1 adder, 1 multiplier, 1 allocation: 1 adder, 1 multiplier, 1 allocation: 1 adder, 1 multiplier, 1 allocation: 1 adder, 1 multiplier, 1 substractorsubstractorsubstractorsubstractor
scheduling defines the operation sequencingscheduling defines the operation sequencingscheduling defines the operation sequencingscheduling defines the operation sequencingoperations are bound to clock cyclesoperations are bound to clock cyclesoperations are bound to clock cyclesoperations are bound to clock cyclesscheduling principles:scheduling principles:scheduling principles:scheduling principles:
resource limited: given a set of resources, solutions for a resource limited: given a set of resources, solutions for a resource limited: given a set of resources, solutions for a resource limited: given a set of resources, solutions for a minimal execution time has to be foundminimal execution time has to be foundminimal execution time has to be foundminimal execution time has to be foundtimetimetimetime----limited: given a total execution time, a minimal set limited: given a total execution time, a minimal set limited: given a total execution time, a minimal set limited: given a total execution time, a minimal set of resources has to be foundof resources has to be foundof resources has to be foundof resources has to be found
MicroLab, VLSI-22 (27/40)
JMM v1.4
Scheduling: ExampleScheduling: ExampleScheduling: ExampleScheduling: Example
resource limited schedulingresource limited schedulingresource limited schedulingresource limited schedulingeach operation is bound to a clock cycleeach operation is bound to a clock cycleeach operation is bound to a clock cycleeach operation is bound to a clock cyclesolutions for minimal execution timesolutions for minimal execution timesolutions for minimal execution timesolutions for minimal execution time
directed directed directed directed acyclicacyclicacyclicacyclic graphs can be usedgraphs can be usedgraphs can be usedgraphs can be used
binding phase: operations and memory accesses binding phase: operations and memory accesses binding phase: operations and memory accesses binding phase: operations and memory accesses within the clock cycles are bound to the hardware within the clock cycles are bound to the hardware within the clock cycles are bound to the hardware within the clock cycles are bound to the hardware resourcesresourcesresourcesresourcesresources can be reused in different clock cyclesresources can be reused in different clock cyclesresources can be reused in different clock cyclesresources can be reused in different clock cyclesbinding steps:binding steps:binding steps:binding steps:
variables are bound to memory elementsvariables are bound to memory elementsvariables are bound to memory elementsvariables are bound to memory elementsoperations are bound to functional blocksoperations are bound to functional blocksoperations are bound to functional blocksoperations are bound to functional blocksinterconnection elements are bound for data transfers interconnection elements are bound for data transfers interconnection elements are bound for data transfers interconnection elements are bound for data transfers (busses, (busses, (busses, (busses, multiplexersmultiplexersmultiplexersmultiplexers))))
MicroLab, VLSI-22 (29/40)
JMM v1.4
Binding: ExampleBinding: ExampleBinding: ExampleBinding: Example
variables are bound to memoriesvariables are bound to memoriesvariables are bound to memoriesvariables are bound to memoriestemporary variables xtemporary variables xtemporary variables xtemporary variables x1111 and xand xand xand x2222 are not used are not used are not used are not used simultaneouslysimultaneouslysimultaneouslysimultaneously
synthesis is based on the knowledge of a set of synthesis is based on the knowledge of a set of synthesis is based on the knowledge of a set of synthesis is based on the knowledge of a set of architecture models and design stylesarchitecture models and design stylesarchitecture models and design stylesarchitecture models and design stylesdesign styles:design styles:design styles:design styles:
parallel or serial parallel or serial parallel or serial parallel or serial datapathdatapathdatapathdatapathinterrupt or polling controlinterrupt or polling controlinterrupt or polling controlinterrupt or polling controlmemory access types (cache ...)memory access types (cache ...)memory access types (cache ...)memory access types (cache ...)
combinational logic:combinational logic:combinational logic:combinational logic:non non non non subdividablesubdividablesubdividablesubdividable unitsunitsunitsunits
Architectural Models:Architectural Models:Architectural Models:Architectural Models:FinitFinitFinitFinit State MachinesState MachinesState MachinesState Machines
finitfinitfinitfinit state machines (FSM) are classical control state machines (FSM) are classical control state machines (FSM) are classical control state machines (FSM) are classical control structuresstructuresstructuresstructuresautonomous FSMautonomous FSMautonomous FSMautonomous FSM
Architectural Models:Architectural Models:Architectural Models:Architectural Models:Control Unit / Data PathControl Unit / Data PathControl Unit / Data PathControl Unit / Data Path
FSMsFSMsFSMsFSMs are used for control unit tasksare used for control unit tasksare used for control unit tasksare used for control unit tasksdatapathsdatapathsdatapathsdatapaths are used as functional unitsare used as functional unitsare used as functional unitsare used as functional unitscontrol unit control unit control unit control unit ---- datapathdatapathdatapathdatapath model (FSMD model)model (FSMD model)model (FSMD model)model (FSMD model)
FSMD is used as process on system levelFSMD is used as process on system levelFSMD is used as process on system levelFSMD is used as process on system levelsystem consists of a set of processessystem consists of a set of processessystem consists of a set of processessystem consists of a set of processeshierarchical FSMD modelhierarchical FSMD modelhierarchical FSMD modelhierarchical FSMD modelprocess synchronization is neededprocess synchronization is neededprocess synchronization is neededprocess synchronization is needed
behavioural modelling uses abstract models, which do not behavioural modelling uses abstract models, which do not behavioural modelling uses abstract models, which do not behavioural modelling uses abstract models, which do not model the reality preciselymodel the reality preciselymodel the reality preciselymodel the reality preciselyimplementation constraints / pitfallsimplementation constraints / pitfallsimplementation constraints / pitfallsimplementation constraints / pitfalls
deactivation of set and reset of latches simultaneouslydeactivation of set and reset of latches simultaneouslydeactivation of set and reset of latches simultaneouslydeactivation of set and reset of latches simultaneouslyclock skew in shift registers lead to races of clock and data clock skew in shift registers lead to races of clock and data clock skew in shift registers lead to races of clock and data clock skew in shift registers lead to races of clock and data (two phase clocking strategy)(two phase clocking strategy)(two phase clocking strategy)(two phase clocking strategy)Moore and Mealy Moore and Mealy Moore and Mealy Moore and Mealy FSMsFSMsFSMsFSMs have hazardshave hazardshave hazardshave hazardsasynchronous inputs lead to undefined FSM statesasynchronous inputs lead to undefined FSM statesasynchronous inputs lead to undefined FSM statesasynchronous inputs lead to undefined FSM states
never use:never use:never use:never use:gated clocksgated clocksgated clocksgated clockscombinatorial outputs for asynchronous inputscombinatorial outputs for asynchronous inputscombinatorial outputs for asynchronous inputscombinatorial outputs for asynchronous inputsasynchronous inputs as FSM inputs asynchronous inputs as FSM inputs asynchronous inputs as FSM inputs asynchronous inputs as FSM inputs
MicroLab, VLSI-22 (39/40)
JMM v1.4
ConclusionsConclusionsConclusionsConclusions
descriptiondescriptiondescriptiondescription----synthesis method synthesis method synthesis method synthesis method system design with system design with system design with system design with HDLsHDLsHDLsHDLs (parallel constructions, (parallel constructions, (parallel constructions, (parallel constructions, RTL level)RTL level)RTL level)RTL level)toptoptoptop----down and bottomdown and bottomdown and bottomdown and bottom----up designup designup designup designabstract models are not preciseabstract models are not preciseabstract models are not preciseabstract models are not precise
races, hazards, delays, signal strength, ...races, hazards, delays, signal strength, ...races, hazards, delays, signal strength, ...races, hazards, delays, signal strength, ...
silicon compiler does not existsilicon compiler does not existsilicon compiler does not existsilicon compiler does not exist
MicroLab, VLSI-22 (40/40)
JMM v1.4
Coming Up...Coming Up...Coming Up...Coming Up...
Next time...Next time...Next time...Next time...Hardware description languagesHardware description languagesHardware description languagesHardware description languages
VLSI Design IVLSI Design IVLSI Design IVLSI Design IDesign for TestDesign for TestDesign for TestDesign for Test
He’s dead Jim...He’s dead Jim...He’s dead Jim...He’s dead Jim...
OverviewOverviewOverviewOverviewdesign for test architecturesdesign for test architecturesdesign for test architecturesdesign for test architecturesadadadad----hoc, scan based, builthoc, scan based, builthoc, scan based, builthoc, scan based, built----inininin
Goal: Goal: Goal: Goal: You are familiar with testability metrics and You are familiar with testability metrics and You are familiar with testability metrics and You are familiar with testability metrics and you know adyou know adyou know adyou know ad----hoc test structures as well as scanhoc test structures as well as scanhoc test structures as well as scanhoc test structures as well as scan----based test structures. Built in test structures as based test structures. Built in test structures as based test structures. Built in test structures as based test structures. Built in test structures as BILBO and boundary scan can be applied.BILBO and boundary scan can be applied.BILBO and boundary scan can be applied.BILBO and boundary scan can be applied.
MicroLab, VLSI-23 (2/24)
JMM v1.3
Design For TestDesign For TestDesign For TestDesign For TestWhat can we do to increase testability?What can we do to increase testability?What can we do to increase testability?What can we do to increase testability?
increaseincreaseincreaseincrease observabilityobservabilityobservabilityobservabilityadd more pins (?!)add more pins (?!)add more pins (?!)add more pins (?!)add small “probe” bus, selectivelyadd small “probe” bus, selectivelyadd small “probe” bus, selectivelyadd small “probe” bus, selectivelyenable different values onto busenable different values onto busenable different values onto busenable different values onto bususe a hash function to “compress” ause a hash function to “compress” ause a hash function to “compress” ause a hash function to “compress” asequence of values (e.g., the values of asequence of values (e.g., the values of asequence of values (e.g., the values of asequence of values (e.g., the values of abus over many clock cycles) into abus over many clock cycles) into abus over many clock cycles) into abus over many clock cycles) into asmall number of bits for later readsmall number of bits for later readsmall number of bits for later readsmall number of bits for later read----outoutoutoutcheap readcheap readcheap readcheap read----out of all state informationout of all state informationout of all state informationout of all state information
increase increase increase increase controllabilitycontrollabilitycontrollabilitycontrollabilityuseuseuseuse muxesmuxesmuxesmuxes to isolate subto isolate subto isolate subto isolate sub----modules andmodules andmodules andmodules andselect sources of test data as inputsselect sources of test data as inputsselect sources of test data as inputsselect sources of test data as inputsprovide easy setup of internal stateprovide easy setup of internal stateprovide easy setup of internal stateprovide easy setup of internal state
Design strategies for test (design for testability):Design strategies for test (design for testability):Design strategies for test (design for testability):Design strategies for test (design for testability):adadadad----hoc testinghoc testinghoc testinghoc testingscanscanscanscan----based approachesbased approachesbased approachesbased approachesselfselfselfself----test and builttest and builttest and builttest and built----in testingin testingin testingin testing
AdAdAdAd----hoc test techniques are a collection of ideas hoc test techniques are a collection of ideas hoc test techniques are a collection of ideas hoc test techniques are a collection of ideas aimed at reducing the test time. Common aimed at reducing the test time. Common aimed at reducing the test time. Common aimed at reducing the test time. Common techniques are:techniques are:techniques are:techniques are:
partitioning large sequential circuitspartitioning large sequential circuitspartitioning large sequential circuitspartitioning large sequential circuitsadding test pointsadding test pointsadding test pointsadding test pointsaddingaddingaddingadding multiplexersmultiplexersmultiplexersmultiplexersproviding for easy state accessproviding for easy state accessproviding for easy state accessproviding for easy state access
bus oriented test techniquebus oriented test techniquebus oriented test techniquebus oriented test technique
ModuleModuleModuleModuleAAAA
ModuleModuleModuleModuleBBBB
ModuleModuleModuleModuleAAAA
ModuleModuleModuleModuleBBBB
multiplexermultiplexermultiplexermultiplexer based testingbased testingbased testingbased testing
Module A test: test1,test2=0,1Module A test: test1,test2=0,1Module A test: test1,test2=0,1Module A test: test1,test2=0,1
Module AModule AModule AModule A Module BModule BModule BModule B
testtesttesttest1111
11110000
11110000
0 10 10 10 1 1 01 01 01 0
A outA outA outA out B outB outB outB out
A A A A inpinpinpinp B B B B inpinpinpinp
A controlA controlA controlA control
B controlB controlB controlB control
testtesttesttest2222
MicroLab, VLSI-23 (5/24)
JMM v1.3
ScanScanScanScan----based test techniques #1based test techniques #1based test techniques #1based test techniques #1IdeaIdeaIdeaIdea: have a mode in which all registers are chained: have a mode in which all registers are chained: have a mode in which all registers are chained: have a mode in which all registers are chainedinto one giant shift register which can be loaded/into one giant shift register which can be loaded/into one giant shift register which can be loaded/into one giant shift register which can be loaded/readreadreadread----out bit serially. Test remaining (combinational)out bit serially. Test remaining (combinational)out bit serially. Test remaining (combinational)out bit serially. Test remaining (combinational)logic bylogic bylogic bylogic by
(1) in “test” mode, shift in new values for all(1) in “test” mode, shift in new values for all(1) in “test” mode, shift in new values for all(1) in “test” mode, shift in new values for allregister bits thus setting up the inputs to theregister bits thus setting up the inputs to theregister bits thus setting up the inputs to theregister bits thus setting up the inputs to thecombinational logiccombinational logiccombinational logiccombinational logic
(2) clock the circuit once in “normal” mode, latching(2) clock the circuit once in “normal” mode, latching(2) clock the circuit once in “normal” mode, latching(2) clock the circuit once in “normal” mode, latchingthe outputs of the combinational logic back intothe outputs of the combinational logic back intothe outputs of the combinational logic back intothe outputs of the combinational logic back intothe registersthe registersthe registersthe registers
(3) in “test” mode, shift out the values of all(3) in “test” mode, shift out the values of all(3) in “test” mode, shift out the values of all(3) in “test” mode, shift out the values of allregister bits and compare against expectedregister bits and compare against expectedregister bits and compare against expectedregister bits and compare against expectedresults. One can shift in new test values at theresults. One can shift in new test values at theresults. One can shift in new test values at theresults. One can shift in new test values at thesame time (i.e., combine steps 1 and 3).same time (i.e., combine steps 1 and 3).same time (i.e., combine steps 1 and 3).same time (i.e., combine steps 1 and 3).
partial serial scan: sometimes it is not area and partial serial scan: sometimes it is not area and partial serial scan: sometimes it is not area and partial serial scan: sometimes it is not area and speed efficient to implement scan in every location speed efficient to implement scan in every location speed efficient to implement scan in every location speed efficient to implement scan in every location where a register is used (signal processing)where a register is used (signal processing)where a register is used (signal processing)where a register is used (signal processing)
R1R1R1R1 CLCLCLCL
R2R2R2R2 CLCLCLCL
R4R4R4R4
CLCLCLCL
R5R5R5R5R6R6R6R6
CLCLCLCL
R3R3R3R3
MicroLab, VLSI-23 (7/24)
JMM v1.3
Level sensitive scan designLevel sensitive scan designLevel sensitive scan designLevel sensitive scan designA popular approach is the level sensitive scan A popular approach is the level sensitive scan A popular approach is the level sensitive scan A popular approach is the level sensitive scan design technique from T.W. Williams (LSSD)design technique from T.W. Williams (LSSD)design technique from T.W. Williams (LSSD)design technique from T.W. Williams (LSSD)
the circuit is level sensitive (steady state response is the circuit is level sensitive (steady state response is the circuit is level sensitive (steady state response is the circuit is level sensitive (steady state response is independent of circuit and wire delays within a circuit): independent of circuit and wire delays within a circuit): independent of circuit and wire delays within a circuit): independent of circuit and wire delays within a circuit): hazard freehazard freehazard freehazard freeeach register may be converted to a serial shift registereach register may be converted to a serial shift registereach register may be converted to a serial shift registereach register may be converted to a serial shift register
CombCombCombComblogiclogiclogiclogic
DDDDCCCCIIIIAAAA
BBBB
DDDDCCCCIIIIAAAA
BBBB
DDDDCCCCIIIIAAAA
BBBB
DDDDCCCCIIIIAAAA
BBBB
DDDDCCCCIIIIAAAA
BBBB
DDDDCCCCIIIIAAAA
BBBB
seria
l data
inse
rial d
ata in
seria
l data
inse
rial d
ata in
seria
l data
out
seria
l data
out
seria
l data
out
seria
l data
out
shift
shift
shift
shift
- ---clk clkclkclk c1 c1c1c1 c2 c2c2c2
c1c1c1c1
shiftshiftshiftshift----clkclkclkclk
c2c2c2c2
normal operationnormal operationnormal operationnormal operationshift data into shift data into shift data into shift data into regregregreg AAAA shift shift shift shift regregregreg B outB outB outB out
regregregreg AAAA regregregreg BBBB
DDDDCCCCIIIIAAAA
TTTT1111DDDDBBBB
TTTT2222
LLLL1111 LLLL2222
MicroLab, VLSI-23 (8/24)
JMM v1.3
Scan ElementsScan ElementsScan ElementsScan Elements
LSSD LSSD LSSD LSSD
scan FFscan FFscan FFscan FF
DDDDCCCCIIIIAAAA
TTTT1111DDDDBBBB
TTTT2222
LLLL1111 LLLL2222
&&&&
&&&&
&&&&
&&&&&&&&
&&&&&&&& &&&&
&&&& &&&&
DDDD
CCCCIIII
AAAA
TTTT1111 DDDD
BBBB
TTTT2222
LLLL1111
LLLL2222
clkclkclkclk
DDDD QQQQDDDD
TITITITI
TETETETE
QQQQ11110000
clkaclkaclkaclka
clkaclkaclkaclka
clkaclkaclkaclka
clkaclkaclkaclka
clkbclkbclkbclkb
clkbclkbclkbclkbclkbclkbclkbclkb
clkbclkbclkbclkb
TETETETE
TETETETE
TETETETEDDDD
TITITITI
QQQQ
MicroLab, VLSI-23 (9/24)
JMM v1.3
SelfSelfSelfSelf----Test Techniques: BILBOTest Techniques: BILBOTest Techniques: BILBOTest Techniques: BILBOProblem:Problem:Problem:Problem: ScanScanScanScan----based approach is great for testing combinational logic based approach is great for testing combinational logic based approach is great for testing combinational logic based approach is great for testing combinational logic but can be impractical when trying to test memory blocks, etc. bbut can be impractical when trying to test memory blocks, etc. bbut can be impractical when trying to test memory blocks, etc. bbut can be impractical when trying to test memory blocks, etc. because ecause ecause ecause of the number of separate test values required to get adequate fof the number of separate test values required to get adequate fof the number of separate test values required to get adequate fof the number of separate test values required to get adequate fault ault ault ault coverage.coverage.coverage.coverage.
Solution:Solution:Solution:Solution: use onuse onuse onuse on----chip circuitry to generate test datachip circuitry to generate test datachip circuitry to generate test datachip circuitry to generate test dataand check the results. Can be used at every powerand check the results. Can be used at every powerand check the results. Can be used at every powerand check the results. Can be used at every power----ononononto verify correct operation!to verify correct operation!to verify correct operation!to verify correct operation!
Generate pseudoGenerate pseudoGenerate pseudoGenerate pseudo----randomrandomrandomrandomdata for most circuits bydata for most circuits bydata for most circuits bydata for most circuits byusing, e.g., a linear feedbackusing, e.g., a linear feedbackusing, e.g., a linear feedbackusing, e.g., a linear feedbackshift register (LFSR).shift register (LFSR).shift register (LFSR).shift register (LFSR).Memory tests use moreMemory tests use moreMemory tests use moreMemory tests use moresystematicsystematicsystematicsystematic FSMsFSMsFSMsFSMs to createto createto createto createADDR and DATA patterns.ADDR and DATA patterns.ADDR and DATA patterns.ADDR and DATA patterns.
For pseudoFor pseudoFor pseudoFor pseudo----random inputrandom inputrandom inputrandom inputdata simply compute somedata simply compute somedata simply compute somedata simply compute somehash of output values andhash of output values andhash of output values andhash of output values andcompare against expectedcompare against expectedcompare against expectedcompare against expectedvalue (“signature”) at end ofvalue (“signature”) at end ofvalue (“signature”) at end ofvalue (“signature”) at end oftest. Memory data can betest. Memory data can betest. Memory data can betest. Memory data can bechecked cyclechecked cyclechecked cyclechecked cycle----bybybyby----cycle.cycle.cycle.cycle.
MicroLab, VLSI-23 (10/24)
JMM v1.3
Linear Feedback Shift Register (LFSR)Linear Feedback Shift Register (LFSR)Linear Feedback Shift Register (LFSR)Linear Feedback Shift Register (LFSR)IfIfIfIf CCCCiiii’s’s’s’s are not programmable, can eliminate are not programmable, can eliminate are not programmable, can eliminate are not programmable, can eliminate AND gates and some XOR gates...AND gates and some XOR gates...AND gates and some XOR gates...AND gates and some XOR gates...
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
clkclkclkclk
DDDD QQQQ
&&&&
=1=1=1=1
cccc1111
&&&&=1=1=1=1
cccc2222&&&&
=1=1=1=1
cccc3333
&&&&
=1=1=1=1
ccccnnnn----1111
&&&&
ccccnnnn
. . . .. . . .. . . .. . . .
nn
nn xcxcxcxcxc ++++ −
−1
13
32
1 21
with a small number of XOR gates the cycle with a small number of XOR gates the cycle with a small number of XOR gates the cycle with a small number of XOR gates the cycle time is very fast. Cycle through fixed sequence time is very fast. Cycle through fixed sequence time is very fast. Cycle through fixed sequence time is very fast. Cycle through fixed sequence of states (can be as long as 2of states (can be as long as 2of states (can be as long as 2of states (can be as long as 2nnnn----1 for some1 for some1 for some1 for some n’sn’sn’sn’s). ). ). ). Handy for large moduloHandy for large moduloHandy for large moduloHandy for large modulo----n counters.n counters.n counters.n counters.different responses for different initial statesdifferent responses for different initial statesdifferent responses for different initial statesdifferent responses for different initial statesdifferent responses for differentdifferent responses for differentdifferent responses for differentdifferent responses for different cccciiii
Signature AnalysisSignature AnalysisSignature AnalysisSignature Analysissignature analysis is used to compact a data stream signature analysis is used to compact a data stream signature analysis is used to compact a data stream signature analysis is used to compact a data stream into a so called signatureinto a so called signatureinto a so called signatureinto a so called signaturedifferent responses for differentdifferent responses for differentdifferent responses for differentdifferent responses for different cccciiii, many well, many well, many well, many well----known CRC (cyclic redundancy check) polynomials known CRC (cyclic redundancy check) polynomials known CRC (cyclic redundancy check) polynomials known CRC (cyclic redundancy check) polynomials correspond to a specific choice ofcorrespond to a specific choice ofcorrespond to a specific choice ofcorrespond to a specific choice of cccciiii’s’s’s’s....
polynomials for maximal long sequences for n equal polynomials for maximal long sequences for n equal polynomials for maximal long sequences for n equal polynomials for maximal long sequences for n equal 1 up to 321 up to 321 up to 321 up to 32
n n n n f(x)f(x)f(x)f(x)1,2,3,4,6,7,15,221,2,3,4,6,7,15,221,2,3,4,6,7,15,221,2,3,4,6,7,15,22 1+x+1+x+1+x+1+x+xxxxnnnn
examples of examples of examples of examples of CRC’sCRC’sCRC’sCRC’s
MicroLab, VLSI-23 (13/24)
JMM v1.3
BILBO #1BILBO #1BILBO #1BILBO #1
Very popular builtVery popular builtVery popular builtVery popular built----in test structure is the builtin test structure is the builtin test structure is the builtin test structure is the built----in in in in logic block observation (BILBO) fromlogic block observation (BILBO) fromlogic block observation (BILBO) fromlogic block observation (BILBO) from KoenemannKoenemannKoenemannKoenemannBILBO operate in 4 different modesBILBO operate in 4 different modesBILBO operate in 4 different modesBILBO operate in 4 different modes
example of a BILBO element with polynomials 1+x+xexample of a BILBO element with polynomials 1+x+xexample of a BILBO element with polynomials 1+x+xexample of a BILBO element with polynomials 1+x+x4444
Idea:Idea:Idea:Idea: CMOS logic should draw no currentCMOS logic should draw no currentCMOS logic should draw no currentCMOS logic should draw no currentwhen it’s not switching. So after initializingwhen it’s not switching. So after initializingwhen it’s not switching. So after initializingwhen it’s not switching. So after initializingcircuit to eliminate tricircuit to eliminate tricircuit to eliminate tricircuit to eliminate tri----state fights, disablestate fights, disablestate fights, disablestate fights, disablepseudopseudopseudopseudo----NMOS gates, etc., the powerNMOS gates, etc., the powerNMOS gates, etc., the powerNMOS gates, etc., the power----supplysupplysupplysupplycurrent should be zero after all signals havecurrent should be zero after all signals havecurrent should be zero after all signals havecurrent should be zero after all signals havesettled.settled.settled.settled.
Good for detecting bridging faults (shorts).Good for detecting bridging faults (shorts).Good for detecting bridging faults (shorts).Good for detecting bridging faults (shorts).May want to try several different circuitMay want to try several different circuitMay want to try several different circuitMay want to try several different circuitstates to ensure all parts of the chipstates to ensure all parts of the chipstates to ensure all parts of the chipstates to ensure all parts of the chiphave been observed.have been observed.have been observed.have been observed.
The IEEE 1149.1 boundary scan architecture The IEEE 1149.1 boundary scan architecture The IEEE 1149.1 boundary scan architecture The IEEE 1149.1 boundary scan architecture provides a standardized serial scan path through the provides a standardized serial scan path through the provides a standardized serial scan path through the provides a standardized serial scan path through the I/O pins of a chip (also called JTAG)I/O pins of a chip (also called JTAG)I/O pins of a chip (also called JTAG)I/O pins of a chip (also called JTAG)at the board level, chips obeying the standard may at the board level, chips obeying the standard may at the board level, chips obeying the standard may at the board level, chips obeying the standard may be connected in a variety of series and parallel be connected in a variety of series and parallel be connected in a variety of series and parallel be connected in a variety of series and parallel combinations for board testing (replacing bead of combinations for board testing (replacing bead of combinations for board testing (replacing bead of combinations for board testing (replacing bead of nails)nails)nails)nails)standardized tests:standardized tests:standardized tests:standardized tests:
connectivity tests between componentsconnectivity tests between componentsconnectivity tests between componentsconnectivity tests between componentssampling and setting chip I/Ossampling and setting chip I/Ossampling and setting chip I/Ossampling and setting chip I/Osdistribution an collection of selfdistribution an collection of selfdistribution an collection of selfdistribution an collection of self----test or builttest or builttest or builttest or built----inininin----test test test test resultsresultsresultsresults
IO pad andIO pad andIO pad andIO pad andboundary cellboundary cellboundary cellboundary cell
serial data inserial data inserial data inserial data inserial data outserial data outserial data outserial data out
serial test interconnectserial test interconnectserial test interconnectserial test interconnectPCB interconnectPCB interconnectPCB interconnectPCB interconnect
MicroLab, VLSI-23 (17/24)
JMM v1.3
Boundary Scan: Test Access PortBoundary Scan: Test Access PortBoundary Scan: Test Access PortBoundary Scan: Test Access Port
The test access port (TAP) is a definition of the The test access port (TAP) is a definition of the The test access port (TAP) is a definition of the The test access port (TAP) is a definition of the interface that needs to be included in an ICinterface that needs to be included in an ICinterface that needs to be included in an ICinterface that needs to be included in an IC
TCK: test clock inputTCK: test clock inputTCK: test clock inputTCK: test clock inputTMS: test mode selectTMS: test mode selectTMS: test mode selectTMS: test mode selectTDI: test date inputTDI: test date inputTDI: test date inputTDI: test date inputTDO: test data outputTDO: test data outputTDO: test data outputTDO: test data outputTRST: optional signal for asynchronous reset the TAPTRST: optional signal for asynchronous reset the TAPTRST: optional signal for asynchronous reset the TAPTRST: optional signal for asynchronous reset the TAP
the test architecturethe test architecturethe test architecturethe test architecture
test data registerstest data registerstest data registerstest data registers
Boundary Scan: TAP controllerBoundary Scan: TAP controllerBoundary Scan: TAP controllerBoundary Scan: TAP controller
State machine for the TAP controller. TMS is the State machine for the TAP controller. TMS is the State machine for the TAP controller. TMS is the State machine for the TAP controller. TMS is the control signal.control signal.control signal.control signal.
BoundaryBoundaryBoundaryBoundary----scan: DRscan: DRscan: DRscan: DRTAP data register (DR)TAP data register (DR)TAP data register (DR)TAP data register (DR)
boundary scan register is a special case of a data boundary scan register is a special case of a data boundary scan register is a special case of a data boundary scan register is a special case of a data register. It allows circuit board interconnections to be register. It allows circuit board interconnections to be register. It allows circuit board interconnections to be register. It allows circuit board interconnections to be tested, external components tested, and the state of the tested, external components tested, and the state of the tested, external components tested, and the state of the tested, external components tested, and the state of the chip digital I/Os to be sampled. The boundary scan chip digital I/Os to be sampled. The boundary scan chip digital I/Os to be sampled. The boundary scan chip digital I/Os to be sampled. The boundary scan register is mandatory.register is mandatory.register is mandatory.register is mandatory.internal data registers are optional and add additional internal data registers are optional and add additional internal data registers are optional and add additional internal data registers are optional and add additional access to the circuit.access to the circuit.access to the circuit.access to the circuit.the bypass register is a 1 bit register used to bypass a the bypass register is a 1 bit register used to bypass a the bypass register is a 1 bit register used to bypass a the bypass register is a 1 bit register used to bypass a whole chip.whole chip.whole chip.whole chip.
Minimum 3 instructionsMinimum 3 instructionsMinimum 3 instructionsMinimum 3 instructionsBypass (all 0): it is used to bypass any serial data Bypass (all 0): it is used to bypass any serial data Bypass (all 0): it is used to bypass any serial data Bypass (all 0): it is used to bypass any serial data registers in a chip with a 1 bit register. This allows registers in a chip with a 1 bit register. This allows registers in a chip with a 1 bit register. This allows registers in a chip with a 1 bit register. This allows specific chips to be tested in a serialspecific chips to be tested in a serialspecific chips to be tested in a serialspecific chips to be tested in a serial----scan chain without scan chain without scan chain without scan chain without having to shift through the accumulated SR stages in all having to shift through the accumulated SR stages in all having to shift through the accumulated SR stages in all having to shift through the accumulated SR stages in all the chipsthe chipsthe chipsthe chipsExtestExtestExtestExtest (all 1): testing of off chip circuitry(all 1): testing of off chip circuitry(all 1): testing of off chip circuitry(all 1): testing of off chip circuitrysample/preload: places the boundary scan registers (at sample/preload: places the boundary scan registers (at sample/preload: places the boundary scan registers (at sample/preload: places the boundary scan registers (at the chips I/O pins) in the DR chain, and samples or the chips I/O pins) in the DR chain, and samples or the chips I/O pins) in the DR chain, and samples or the chips I/O pins) in the DR chain, and samples or preloads the chips I/Ospreloads the chips I/Ospreloads the chips I/Ospreloads the chips I/Os
optional recommended instructions:optional recommended instructions:optional recommended instructions:optional recommended instructions:IntestIntestIntestIntest: single: single: single: single----step testing of internal circuitry via the step testing of internal circuitry via the step testing of internal circuitry via the step testing of internal circuitry via the boundary scan registersboundary scan registersboundary scan registersboundary scan registersRunbistRunbistRunbistRunbist: run internal self: run internal self: run internal self: run internal self----testing procedures within a chiptesting procedures within a chiptesting procedures within a chiptesting procedures within a chip
MicroLab, VLSI-23 (23/24)
JMM v1.3
Coming Up...Coming Up...Coming Up...Coming Up...
Next time:Next time:Next time:Next time:Top down design. Hardware description languages,Top down design. Hardware description languages,Top down design. Hardware description languages,Top down design. Hardware description languages,logic synthesis.logic synthesis.logic synthesis.logic synthesis.
Ex vlsi22.1 (difficulty: easy): Ex vlsi22.1 (difficulty: easy): Ex vlsi22.1 (difficulty: easy): Ex vlsi22.1 (difficulty: easy): calculate the pseudocalculate the pseudocalculate the pseudocalculate the pseudo----random sequence of an LFSR with the implemented random sequence of an LFSR with the implemented random sequence of an LFSR with the implemented random sequence of an LFSR with the implemented polynomial 1+x+xpolynomial 1+x+xpolynomial 1+x+xpolynomial 1+x+x3 3 3 3 use the start value x=1 use the start value x=1 use the start value x=1 use the start value x=1 Result: 1,3,7,6,5,2,4,1,...Result: 1,3,7,6,5,2,4,1,...Result: 1,3,7,6,5,2,4,1,...Result: 1,3,7,6,5,2,4,1,...
MicroLab, VLSI-24(1/22)
JMM v1.3
VLSI Design IIVLSI Design IIVLSI Design IIVLSI Design IISmall Signal FET Model Small Signal FET Model Small Signal FET Model Small Signal FET Model
and Diode Modelsand Diode Modelsand Diode Modelsand Diode Models
OverviewOverviewOverviewOverviewsmall signal equivalent circuit for small signal equivalent circuit for small signal equivalent circuit for small signal equivalent circuit for fet fet fet fet and diodesand diodesand diodesand diodesadvanced large advanced large advanced large advanced large fet fet fet fet modeling and secondmodeling and secondmodeling and secondmodeling and second----order order order order effectseffectseffectseffects
Goal: Goal: Goal: Goal: You can use the small signal equivalent circuit You can use the small signal equivalent circuit You can use the small signal equivalent circuit You can use the small signal equivalent circuit of a diode and a MOS transistor. You are able to of a diode and a MOS transistor. You are able to of a diode and a MOS transistor. You are able to of a diode and a MOS transistor. You are able to determine the parameters of a determine the parameters of a determine the parameters of a determine the parameters of a fet fet fet fet and have the and have the and have the and have the feeling for a MOS feeling for a MOS feeling for a MOS feeling for a MOS fetfetfetfet. You are familiar with . You are familiar with . You are familiar with . You are familiar with advanced modeling like weak inversion, shortadvanced modeling like weak inversion, shortadvanced modeling like weak inversion, shortadvanced modeling like weak inversion, short----channel effects and leakage.channel effects and leakage.channel effects and leakage.channel effects and leakage.
MicroLab, VLSI-24(2/22)
JMM v1.3
Summary: Large Signal ModelSummary: Large Signal ModelSummary: Large Signal ModelSummary: Large Signal Model
MOS MOS MOS MOS fetsfetsfetsfets have 3 regions of operationhave 3 regions of operationhave 3 regions of operationhave 3 regions of operationcutoff region (cutoff region (cutoff region (cutoff region (subthresholdsubthresholdsubthresholdsubthreshold): V): V): V): VGSGSGSGS <= <= <= <= VVVVthththth
linear region (triode region): Vlinear region (triode region): Vlinear region (triode region): Vlinear region (triode region): VGSGSGSGS> > > > VVVVthththth ; 0< V; 0< V; 0< V; 0< VDSDSDSDS< < < < VVVVDSsatDSsatDSsatDSsat
active region (saturated region): Vactive region (saturated region): Vactive region (saturated region): Vactive region (saturated region): VGSGSGSGS> > > > VVVVthththth ; ; ; ; VVVVDSsatDSsatDSsatDSsat< V< V< V< VDSDSDSDS
active regionactive regionactive regionactive region
linear regionlinear regionlinear regionlinear region
0=DSI
A
Sirds qNk ε2=
02 Φ+−=
effDS
rds
VVLkλ
−=i
ATF n
NV lnφ
MicroLab, VLSI-24(3/22)
JMM v1.3
Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Cutoff or Cutoff or Cutoff or Cutoff or subthreshold subthreshold subthreshold subthreshold regionregionregionregion
Channel is not inverted and thereforeChannel is not inverted and thereforeChannel is not inverted and thereforeChannel is not inverted and thereforeIIIIDSDSDSDS=0=0=0=0
A more precise definition, which is better suited for A more precise definition, which is better suited for A more precise definition, which is better suited for A more precise definition, which is better suited for analog design takes into account that analog design takes into account that analog design takes into account that analog design takes into account that teh teh teh teh channel channel channel channel becomes not suddenly inverted when the gatebecomes not suddenly inverted when the gatebecomes not suddenly inverted when the gatebecomes not suddenly inverted when the gate----source source source source voltage is increased. Depending on the gatevoltage is increased. Depending on the gatevoltage is increased. Depending on the gatevoltage is increased. Depending on the gate----source source source source voltage, we define three regions of inversion:voltage, we define three regions of inversion:voltage, we define three regions of inversion:voltage, we define three regions of inversion:
Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Short Channel EffectsShort Channel EffectsShort Channel EffectsShort Channel Effects
As device dimensions are scaled down, shortAs device dimensions are scaled down, shortAs device dimensions are scaled down, shortAs device dimensions are scaled down, short----channel channel channel channel effects degrade the operation of effects degrade the operation of effects degrade the operation of effects degrade the operation of mosmosmosmos fetsfetsfetsfetsmobility degradation: short channels and large mobility degradation: short channels and large mobility degradation: short channels and large mobility degradation: short channels and large electric fields provoke more electron collisions. electric fields provoke more electron collisions. electric fields provoke more electron collisions. electric fields provoke more electron collisions. Carrier velocity saturates as it is not anymore Carrier velocity saturates as it is not anymore Carrier velocity saturates as it is not anymore Carrier velocity saturates as it is not anymore proportional to the electric filed:proportional to the electric filed:proportional to the electric filed:proportional to the electric filed:
hot carrier effects specially in hot carrier effects specially in hot carrier effects specially in hot carrier effects specially in nfets nfets nfets nfets due higher due higher due higher due higher mobility: high velocity electrons can generate mobility: high velocity electrons can generate mobility: high velocity electrons can generate mobility: high velocity electrons can generate electron hole pairs in drain to substrate:electron hole pairs in drain to substrate:electron hole pairs in drain to substrate:electron hole pairs in drain to substrate:reduced output impedancereduced output impedancereduced output impedancereduced output impedance
c
nd
EEE
+≅1
µν
( )2
12 effeff
oxnD V
LW
VCIθ
µ+
= where is the where is the where is the where is the square lawsquare lawsquare lawsquare law
cLE1=θ
coxnsx WECR
µ1≅ RRRRsxsxsxsx
IIIIdddd
UUUUGSGSGSGSU’U’U’U’GSGSGSGS
nnnn++++ nnnn++++
drain to source drain to source drain to source drain to source currentcurrentcurrentcurrent
VVVVGGGG>>>>>>>>VVVVthththth VVVVDDDD>>0>>0>>0>>0
punch punch punch punch through currentthrough currentthrough currentthrough current
MicroLab, VLSI-24(5/22)
JMM v1.3
Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Advanced Large Signal Modeling: Leakage CurrentsLeakage CurrentsLeakage CurrentsLeakage Currents
An important secondAn important secondAn important secondAn important second----order device limitation is the order device limitation is the order device limitation is the order device limitation is the leakage current of the junctions (ex sampleleakage current of the junctions (ex sampleleakage current of the junctions (ex sampleleakage current of the junctions (ex sample----and and and and hold time)hold time)hold time)hold time)the intrinsic concentration is a strong function of the intrinsic concentration is a strong function of the intrinsic concentration is a strong function of the intrinsic concentration is a strong function of temperature, the leakage current is also strongly temperature, the leakage current is also strongly temperature, the leakage current is also strongly temperature, the leakage current is also strongly dependent of temperature (approx. doubles for 11C)dependent of temperature (approx. doubles for 11C)dependent of temperature (approx. doubles for 11C)dependent of temperature (approx. doubles for 11C)leakage current of a reverseleakage current of a reverseleakage current of a reverseleakage current of a reverse----biased junction:biased junction:biased junction:biased junction:
dij
IK xnqA
I02τ
≅( )pn τττ +≅21
0
( )RA
sid V
qNx +Φ= 0
2ε
electron and hole lifetimeelectron and hole lifetimeelectron and hole lifetimeelectron and hole lifetimejunction areajunction areajunction areajunction area
MicroLab, VLSI-24(6/22)
JMM v1.3
Small Signal Equivalent CircuitsSmall Signal Equivalent CircuitsSmall Signal Equivalent CircuitsSmall Signal Equivalent CircuitsWhy do we love them?Why do we love them?Why do we love them?Why do we love them?
Find IFind IFind IFind Idddd of a transistor in active region when the gate of a transistor in active region when the gate of a transistor in active region when the gate of a transistor in active region when the gate is driven with a voltage source is driven with a voltage source is driven with a voltage source is driven with a voltage source VVVVgsgsgsgs=V=V=V=V0000sin(sin(sin(sin(ωωωωt)t)t)t)It is handy to use simple linear equations !It is handy to use simple linear equations !It is handy to use simple linear equations !It is handy to use simple linear equations !
What are small signal parameters?What are small signal parameters?What are small signal parameters?What are small signal parameters?Instead of using nonlinear transistor curves, we Instead of using nonlinear transistor curves, we Instead of using nonlinear transistor curves, we Instead of using nonlinear transistor curves, we determine the operating point and use the derivative determine the operating point and use the derivative determine the operating point and use the derivative determine the operating point and use the derivative in this pointin this pointin this pointin this point
– small signal parameters are denoted with small letterssmall signal parameters are denoted with small letterssmall signal parameters are denoted with small letterssmall signal parameters are denoted with small letters– small signal parameters are very handy for building small signal parameters are very handy for building small signal parameters are very handy for building small signal parameters are very handy for building
The most important small signal component is the The most important small signal component is the The most important small signal component is the The most important small signal component is the transconductancetransconductancetransconductancetransconductance. The behavior of a . The behavior of a . The behavior of a . The behavior of a transconductancetransconductancetransconductancetransconductance is the one of a voltage controlled is the one of a voltage controlled is the one of a voltage controlled is the one of a voltage controlled current source. It describes the change of output current source. It describes the change of output current source. It describes the change of output current source. It describes the change of output current when the input voltage is varied.current when the input voltage is varied.current when the input voltage is varied.current when the input voltage is varied.ggggmmmm main main main main transconductancetransconductancetransconductancetransconductance, describes the , describes the , describes the , describes the amplification of the drain current when a voltage is amplification of the drain current when a voltage is amplification of the drain current when a voltage is amplification of the drain current when a voltage is applied between gate and source.applied between gate and source.applied between gate and source.applied between gate and source.ggggdsdsdsds transconductancetransconductancetransconductancetransconductance, accounting for finite output , accounting for finite output , accounting for finite output , accounting for finite output impedance of transistor. Models channel length impedance of transistor. Models channel length impedance of transistor. Models channel length impedance of transistor. Models channel length modulation effect, when drain to source voltage modulation effect, when drain to source voltage modulation effect, when drain to source voltage modulation effect, when drain to source voltage varies.varies.varies.varies.ggggssss transconductancetransconductancetransconductancetransconductance, describing how the output , describing how the output , describing how the output , describing how the output current depends on the source to substrate voltage current depends on the source to substrate voltage current depends on the source to substrate voltage current depends on the source to substrate voltage (body effect).(body effect).(body effect).(body effect).
the negative sign is eliminatedthe negative sign is eliminatedthe negative sign is eliminatedthe negative sign is eliminatedby changing the current direction by changing the current direction by changing the current direction by changing the current direction in the equivalent circuitin the equivalent circuitin the equivalent circuitin the equivalent circuit
MicroLab, VLSI-24(9/22)
JMM v1.3
SmallSmallSmallSmall----Signal Modeling in the Active Signal Modeling in the Active Signal Modeling in the Active Signal Modeling in the Active Region (Low Frequency)Region (Low Frequency)Region (Low Frequency)Region (Low Frequency)
the alternate lowthe alternate lowthe alternate lowthe alternate low----frequency T modelfrequency T modelfrequency T modelfrequency T model
the lowthe lowthe lowthe low----frequency modelfrequency modelfrequency modelfrequency model
Depending on the terminal voltages, and the relative size of Depending on the terminal voltages, and the relative size of Depending on the terminal voltages, and the relative size of Depending on the terminal voltages, and the relative size of the parameters, some of the components may be ignored. the parameters, some of the components may be ignored. the parameters, some of the components may be ignored. the parameters, some of the components may be ignored. This helps to reduce the complexity of hand calculations.This helps to reduce the complexity of hand calculations.This helps to reduce the complexity of hand calculations.This helps to reduce the complexity of hand calculations.
MicroLab, VLSI-24(10/22)
JMM v1.3
MOSFET Capacitance Estimation MOSFET Capacitance Estimation MOSFET Capacitance Estimation MOSFET Capacitance Estimation in Active Regionin Active Regionin Active Regionin Active Region
The dynamic response of MOS systems strongly depends on The dynamic response of MOS systems strongly depends on The dynamic response of MOS systems strongly depends on The dynamic response of MOS systems strongly depends on the parasitic capacitance associated with the MOS transistor.the parasitic capacitance associated with the MOS transistor.the parasitic capacitance associated with the MOS transistor.the parasitic capacitance associated with the MOS transistor.
SmallSmallSmallSmall----Signal Modeling Signal Modeling Signal Modeling Signal Modeling in the Active Regionin the Active Regionin the Active Regionin the Active Region
the small signal modelthe small signal modelthe small signal modelthe small signal model
Gate capacitance Gate capacitance Gate capacitance Gate capacitance CCCCgsgsgsgs is normally the largest parasitic is normally the largest parasitic is normally the largest parasitic is normally the largest parasitic cap of cap of cap of cap of fetfetfetfet. . . . The gateThe gateThe gateThe gate----drain overlap capacitance drain overlap capacitance drain overlap capacitance drain overlap capacitance CCCCgdgdgdgd is normally is normally is normally is normally small, can however play a role when the voltage gain is small, can however play a role when the voltage gain is small, can however play a role when the voltage gain is small, can however play a role when the voltage gain is large (Miller effect).large (Miller effect).large (Miller effect).large (Miller effect).Source capacitance Source capacitance Source capacitance Source capacitance CCCCsbsbsbsb is normally second largest is normally second largest is normally second largest is normally second largest capacitance, since it includes channel bulk capacitance.capacitance, since it includes channel bulk capacitance.capacitance, since it includes channel bulk capacitance.capacitance, since it includes channel bulk capacitance.Drain capacitance Drain capacitance Drain capacitance Drain capacitance CCCCdbdbdbdb normally smallest capacitance.normally smallest capacitance.normally smallest capacitance.normally smallest capacitance.
MicroLab, VLSI-24(12/22)
JMM v1.3
SmallSmallSmallSmall----Signal Modeling Signal Modeling Signal Modeling Signal Modeling in the Triode regionin the Triode regionin the Triode regionin the Triode region
a simplified triodea simplified triodea simplified triodea simplified triode----region model for small Vregion model for small Vregion model for small Vregion model for small VDSDSDSDS
vvvvssss
rrrrdsdsdsdsCCCCgsgsgsgs
CCCCsbsbsbsb
CCCCgdgdgdgd
CCCCdbdbdbdb
vvvvdddd
vvvvgggg
xswjxjxchxxb CPCAAC ,21
−+
+=
021
21
GXoxoxovoxchgdgs WCWLCCWLCACC +=+==
In the triode region a resistor modeling the conductanceIn the triode region a resistor modeling the conductanceIn the triode region a resistor modeling the conductanceIn the triode region a resistor modeling the conductanceof the channel is normally sufficient.of the channel is normally sufficient.of the channel is normally sufficient.of the channel is normally sufficient.
( )
−−= 2
21
DSDSthGSoxDS VVVVLWCI µ
effoxdsds
VLWCg
rµ≅=1
The accurate modeling of The accurate modeling of The accurate modeling of The accurate modeling of high frequency operation high frequency operation high frequency operation high frequency operation of a of a of a of a fet fet fet fet in triode region in triode region in triode region in triode region is nontrivial. We use a is nontrivial. We use a is nontrivial. We use a is nontrivial. We use a simplified model.simplified model.simplified model.simplified model.
MicroLab, VLSI-24(13/22)
JMM v1.3
SmallSmallSmallSmall----Signal Modeling Signal Modeling Signal Modeling Signal Modeling in cutin cutin cutin cut----off regionoff regionoff regionoff region
a simplified cuta simplified cuta simplified cuta simplified cut----off region modeloff region modeloff region modeloff region model
xswjxjxXxb CPCAC ,−+=
0GXoxovgdgs WCCWLCC ===
As the channel has disappeared we have:As the channel has disappeared we have:As the channel has disappeared we have:As the channel has disappeared we have:
vvvvssssCCCCgsgsgsgs
CCCCsbsbsbsb
CCCCgdgdgdgd
CCCCdbdbdbdb
vvvvdddd
vvvvgggg
CCCCgbgbgbgb
but we also have a new capacitor:but we also have a new capacitor:but we also have a new capacitor:but we also have a new capacitor:
oxchgb CAC =
The capacitors The capacitors The capacitors The capacitors CCCCsbsbsbsb and and and and CCCCdbdbdbdb are smaller as the channel is are smaller as the channel is are smaller as the channel is are smaller as the channel is not present :not present :not present :not present :
Note that the metal Note that the metal Note that the metal Note that the metal contacts to the contacts to the contacts to the contacts to the diode are connected diode are connected diode are connected diode are connected to heavily doped to heavily doped to heavily doped to heavily doped regionregionregionregion
SchottkySchottkySchottkySchottky diodediodediodediodemetal contacts to metal contacts to metal contacts to metal contacts to lightly doped lightly doped lightly doped lightly doped semiconductor semiconductor semiconductor semiconductor forms a forms a forms a forms a SchottkySchottkySchottkySchottkydiodediodediodediode
If a diode is reverseIf a diode is reverseIf a diode is reverseIf a diode is reverse----biased, current flow is biased, current flow is biased, current flow is biased, current flow is extremely small and primarily due to thermal or extremely small and primarily due to thermal or extremely small and primarily due to thermal or extremely small and primarily due to thermal or optically generated carriers.optically generated carriers.optically generated carriers.optically generated carriers.
LargeLargeLargeLarge----signal model for forward biased junctionsignal model for forward biased junctionsignal model for forward biased junctionsignal model for forward biased junction
TDV
V
SD eII =
+∝
DADS NNAI 11
jdT ACCC +=
T
DTd VIC τ=
jMR
jj
V
CC
Φ+
=
0
0
1
SmallSmallSmallSmall----signal model for a forwardsignal model for a forwardsignal model for a forwardsignal model for a forward----biased diodebiased diodebiased diodebiased diode
T
D
D
D
d VI
dVdI
r==1
rrrrdddd CCCCjjjj CCCCdddd
pppp++++ nnnn
electric fieldelectric fieldelectric fieldelectric field
depletion regiondepletion regiondepletion regiondepletion region
dominant for dominant for dominant for dominant for large currentslarge currentslarge currentslarge currents
((((CCCCdddd=0 for forward biased =0 for forward biased =0 for forward biased =0 for forward biased Schottky Schottky Schottky Schottky diodes)diodes)diodes)diodes)
( )DA
ADsij NN
NNqC
+Φ=
00 2
ε
MicroLab, VLSI-24(16/22)
JMM v1.3
Coming Up...Coming Up...Coming Up...Coming Up...
Next time:Next time:Next time:Next time:Basic current mirrors and single stage amplifiers.Basic current mirrors and single stage amplifiers.Basic current mirrors and single stage amplifiers.Basic current mirrors and single stage amplifiers.
Readings for next time…Readings for next time…Readings for next time…Readings for next time…Johns&MartinJohns&MartinJohns&MartinJohns&Martin: : : :
1 through 1.1 (1 through 1.1 (1 through 1.1 (1 through 1.1 (pnpnpnpn junctions)junctions)junctions)junctions)1.2 (1.2 (1.2 (1.2 (mosmosmosmos transistor)transistor)transistor)transistor)1.2 (advanced 1.2 (advanced 1.2 (advanced 1.2 (advanced mosmosmosmos modeling)modeling)modeling)modeling)
CAD Exercises for next time…CAD Exercises for next time…CAD Exercises for next time…CAD Exercises for next time…Ex600: simulation of static behavior of Ex600: simulation of static behavior of Ex600: simulation of static behavior of Ex600: simulation of static behavior of nfetnfetnfetnfetEx600a: output resistance and channel length Ex600a: output resistance and channel length Ex600a: output resistance and channel length Ex600a: output resistance and channel length modulationmodulationmodulationmodulationEx600b: weak Ex600b: weak Ex600b: weak Ex600b: weak vsvsvsvs strong inversionstrong inversionstrong inversionstrong inversion
Johns&Martin 1.1 pp7: Ex1.4 (difficulty: easy): Johns&Martin 1.1 pp7: Ex1.4 (difficulty: easy): Johns&Martin 1.1 pp7: Ex1.4 (difficulty: easy): Johns&Martin 1.1 pp7: Ex1.4 (difficulty: easy): Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. a) Calculate the total D. a) Calculate the total D. a) Calculate the total D. a) Calculate the total zerozerozerozero----bias depletion capacitance Cbias depletion capacitance Cbias depletion capacitance Cbias depletion capacitance CTTTT----j0j0j0j0 of a pof a pof a pof a p++++nwellnwellnwellnwelldiode with an area of 5diode with an area of 5diode with an area of 5diode with an area of 5µµµµm times 5m times 5m times 5m times 5µµµµm. Do not use m. Do not use m. Do not use m. Do not use the Spice parameter CJ. b) At 3V reversethe Spice parameter CJ. b) At 3V reversethe Spice parameter CJ. b) At 3V reversethe Spice parameter CJ. b) At 3V reverse----bias the bias the bias the bias the capacitance capacitance capacitance capacitance CCCCjjjj has to be calculated again.has to be calculated again.has to be calculated again.has to be calculated again.
ResultResultResultResult: a) C: a) C: a) C: a) CTTTT----j0j0j0j0=16.3fF, b) C=16.3fF, b) C=16.3fF, b) C=16.3fF, b) CTTTT----jjjj=8.98fF=8.98fF=8.98fF=8.98fFJohns&Martin 1.1 pp10: Ex1.6 (difficulty: medium): Johns&Martin 1.1 pp10: Ex1.6 (difficulty: medium): Johns&Martin 1.1 pp10: Ex1.6 (difficulty: medium): Johns&Martin 1.1 pp10: Ex1.6 (difficulty: medium):
Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D and D and D and D and MMMMjjjj=0.5 (use Spice =0.5 (use Spice =0.5 (use Spice =0.5 (use Spice parameter CJ). A reversed biased pparameter CJ). A reversed biased pparameter CJ). A reversed biased pparameter CJ). A reversed biased p++++nwellnwellnwellnwell diode is diode is diode is diode is charged from 0V to 3.3V through a 10kcharged from 0V to 3.3V through a 10kcharged from 0V to 3.3V through a 10kcharged from 0V to 3.3V through a 10kΩΩΩΩ resistor. resistor. resistor. resistor. Calculate the time to charge the diode to 2Calculate the time to charge the diode to 2Calculate the time to charge the diode to 2Calculate the time to charge the diode to 2/3 of /3 of /3 of /3 of its its its its end end end end valuevaluevaluevalue....
Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. a) Derive the lowD. a) Derive the lowD. a) Derive the lowD. a) Derive the low----frequency parameters for an frequency parameters for an frequency parameters for an frequency parameters for an nfet nfet nfet nfet with W=10with W=10with W=10with W=10µµµµm and m and m and m and L=0.5L=0.5L=0.5L=0.5µµµµm at m at m at m at VVVVgsgsgsgs=1.1V, =1.1V, =1.1V, =1.1V, VVVVdsdsdsds= = = = VVVVeffeffeffeff , , , , VVVVsbsbsbsb= 0.5= 0.5= 0.5= 0.55555V. V. V. V. b) What is the new value of b) What is the new value of b) What is the new value of b) What is the new value of rrrrdsdsdsds if the drainif the drainif the drainif the drain----source source source source voltage is increased by 0.5voltage is increased by 0.5voltage is increased by 0.5voltage is increased by 0.55555V.V.V.V.
ResultResultResultResult: a) : a) : a) : a) ggggmmmm=0.98mA/V, =0.98mA/V, =0.98mA/V, =0.98mA/V, ggggssss=0.143mA/V, =0.143mA/V, =0.143mA/V, =0.143mA/V, rrrrdsdsdsds=208k=208k=208k=208kΩΩΩΩ, b) , b) , b) , b) rrrrdsdsdsds=12.8k=12.8k=12.8k=12.8kΩ ????Ω ????Ω ????Ω ????
Johns&Martin 1.2 pp33: 1.10 (difficulty: easy): Johns&Martin 1.2 pp33: 1.10 (difficulty: easy): Johns&Martin 1.2 pp33: 1.10 (difficulty: easy): Johns&Martin 1.2 pp33: 1.10 (difficulty: easy): Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. Find the TD. Find the TD. Find the TD. Find the T----model model model model parameter parameter parameter parameter rrrrssss for the for the for the for the nfet nfet nfet nfet for example 1.9a.for example 1.9a.for example 1.9a.for example 1.9a.
Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. Find the gD. Find the gD. Find the gD. Find the gdsdsdsds for the for the for the for the nfetnfetnfetnfet for example 1.9 working in triode region with for example 1.9 working in triode region with for example 1.9 working in triode region with for example 1.9 working in triode region with VVVVdsdsdsds near zero.near zero.near zero.near zero.
Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. a) Find ID. a) Find ID. a) Find ID. a) Find IDDDD for an for an for an for an nfetnfetnfetnfetwith W=10with W=10with W=10with W=10µµµµm, L=0.5m, L=0.5m, L=0.5m, L=0.5µµµµm and Vm and Vm and Vm and VGSGSGSGS=1.1V, V=1.1V, V=1.1V, V=1.1V, VDSDSDSDS= = = = VVVVeffeffeffeff . b) Assuming . b) Assuming . b) Assuming . b) Assuming λλλλ remains constant, estimate remains constant, estimate remains constant, estimate remains constant, estimate the new value of Ithe new value of Ithe new value of Ithe new value of IDDDD if Vif Vif Vif VDSDSDSDS is increased by 0.3V. is increased by 0.3V. is increased by 0.3V. is increased by 0.3V.
ResultResultResultResult: a) I: a) I: a) I: a) IDDDD=487=487=487=487µµµµA, b) IA, b) IA, b) IA, b) IDDDD= 513= 513= 513= 513µµµµAAAA
Ex600a: Johns&Martin 1.9 pp79: 1.8 (difficulty: Ex600a: Johns&Martin 1.9 pp79: 1.8 (difficulty: Ex600a: Johns&Martin 1.9 pp79: 1.8 (difficulty: Ex600a: Johns&Martin 1.9 pp79: 1.8 (difficulty: easy): easy): easy): easy): Assuming process C05MAssuming process C05MAssuming process C05MAssuming process C05M----D. Simulate a D. Simulate a D. Simulate a D. Simulate a fetfetfetfetW=10W=10W=10W=10µµµµm, L=2m, L=2m, L=2m, L=2µµµµm in its active region m in its active region m in its active region m in its active region (V(V(V(VGSGSGSGS=2V) and measure the drain current at =2V) and measure the drain current at =2V) and measure the drain current at =2V) and measure the drain current at VVVVDS1DS1DS1DS1=2V and at V=2V and at V=2V and at V=2V and at VDS2DS2DS2DS2=3V. Estimate the output =3V. Estimate the output =3V. Estimate the output =3V. Estimate the output impedance impedance impedance impedance rrrrdsdsdsds and the channel length modulation and the channel length modulation and the channel length modulation and the channel length modulation factor factor factor factor λλλλ....
Ex vlsi24.1 (difficulty: easy):Ex vlsi24.1 (difficulty: easy):Ex vlsi24.1 (difficulty: easy):Ex vlsi24.1 (difficulty: easy): Assuming process Assuming process Assuming process Assuming process C05MC05MC05MC05M----D. Find the capacitances of an D. Find the capacitances of an D. Find the capacitances of an D. Find the capacitances of an nfetnfetnfetnfet as shown as shown as shown as shown below in its active region for below in its active region for below in its active region for below in its active region for VVVVsbsbsbsb=1V, =1V, =1V, =1V, VVVVdbdbdbdb=2V. =2V. =2V. =2V.
Ex vlsi24.2 (difficulty: easy):Ex vlsi24.2 (difficulty: easy):Ex vlsi24.2 (difficulty: easy):Ex vlsi24.2 (difficulty: easy): Assume the transistors Assume the transistors Assume the transistors Assume the transistors are designed with minimal dimensions using the are designed with minimal dimensions using the are designed with minimal dimensions using the are designed with minimal dimensions using the 0.50.50.50.5µµµµm m m m Alcatel MietecAlcatel MietecAlcatel MietecAlcatel Mietec process. Use the process. Use the process. Use the process. Use the λ rules to rules to rules to rules to calculate the calculate the calculate the calculate the CCCCgsgsgsgs, , , , CCCCsbsbsbsb and and and and CCCCdbdbdbdb capacitances for its capacitances for its capacitances for its capacitances for its active region. Compare the values with a single active region. Compare the values with a single active region. Compare the values with a single active region. Compare the values with a single device device device device fetfetfetfet. . . .
ResultResultResultResult: a) : a) : a) : a) CCCCdbdbdbdb=26.6fF, =26.6fF, =26.6fF, =26.6fF, CCCCsbsbsbsb=49.1fF, =49.1fF, =49.1fF, =49.1fF, CCCCgsgsgsgs=34.8fF, =34.8fF, =34.8fF, =34.8fF, ((((seeseeseesee Johns&Martin pp103ff)Johns&Martin pp103ff)Johns&Martin pp103ff)Johns&Martin pp103ff)
Ex600b: (difficulty: easy, medium time):Ex600b: (difficulty: easy, medium time):Ex600b: (difficulty: easy, medium time):Ex600b: (difficulty: easy, medium time): Assume the Assume the Assume the Assume the transistors are designed with W=10transistors are designed with W=10transistors are designed with W=10transistors are designed with W=10µµµµm and m and m and m and L=2L=2L=2L=2µµµµm using the 0.5m using the 0.5m using the 0.5m using the 0.5µµµµm m m m Alcatel MietecAlcatel MietecAlcatel MietecAlcatel Mietec process. process. process. process. Simulate the Simulate the Simulate the Simulate the fetfetfetfet with Spice in strong and weak with Spice in strong and weak with Spice in strong and weak with Spice in strong and weak inversion. Visualize Vinversion. Visualize Vinversion. Visualize Vinversion. Visualize VGSGSGSGS vs vs vs vs IIIIDSDSDSDS, , , , sqrt sqrt sqrt sqrt IIIIDSDSDSDS and log Iand log Iand log Iand log IDS DS DS DS and identify the different regions and find Iand identify the different regions and find Iand identify the different regions and find Iand identify the different regions and find ID0D0D0D0....
Result: compare with transparency Result: compare with transparency Result: compare with transparency Result: compare with transparency #3#3#3#3
MicroLab, vlsi-25 (1/26)
JMM v1.2
VLSI Design IIVLSI Design IIVLSI Design IIVLSI Design IIBasic Current Mirrors and Basic Current Mirrors and Basic Current Mirrors and Basic Current Mirrors and Single Stage AmplifiersSingle Stage AmplifiersSingle Stage AmplifiersSingle Stage Amplifiers He !He !He !He !
That‘s me !That‘s me !That‘s me !That‘s me !
Goal: Goal: Goal: Goal: You know the properties of the different You know the properties of the different You know the properties of the different You know the properties of the different amplifier stages and are able to choose the one amplifier stages and are able to choose the one amplifier stages and are able to choose the one amplifier stages and are able to choose the one which is best suited for your application. You can which is best suited for your application. You can which is best suited for your application. You can which is best suited for your application. You can determine the determine the determine the determine the fet fet fet fet dimensions from a given circuit dimensions from a given circuit dimensions from a given circuit dimensions from a given circuit specification. You are familiar with current mirrors. specification. You are familiar with current mirrors. specification. You are familiar with current mirrors. specification. You are familiar with current mirrors. You can apply two possible techniques for You can apply two possible techniques for You can apply two possible techniques for You can apply two possible techniques for improving the output impedance. You know the improving the output impedance. You know the improving the output impedance. You know the improving the output impedance. You know the resulting limitations on the output voltage swing.resulting limitations on the output voltage swing.resulting limitations on the output voltage swing.resulting limitations on the output voltage swing.
MicroLab, vlsi-25 (2/26)
JMM v1.2
OutlineOutlineOutlineOutline
Current mirrorsCurrent mirrorsCurrent mirrorsCurrent mirrors Single stage amplifiers with active loadsSingle stage amplifiers with active loadsSingle stage amplifiers with active loadsSingle stage amplifiers with active loads
Johns&MartinJohns&MartinJohns&MartinJohns&Martin nodal analysis methodnodal analysis methodnodal analysis methodnodal analysis method simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1) commoncommoncommoncommon----source amplifier (chap 3.2)source amplifier (chap 3.2)source amplifier (chap 3.2)source amplifier (chap 3.2) sourcesourcesourcesource----follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3) common gate amplifier (chap 3.4)common gate amplifier (chap 3.4)common gate amplifier (chap 3.4)common gate amplifier (chap 3.4) source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5) highhighhighhigh----outputoutputoutputoutput----impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6) cascodecascodecascodecascode gain stage (chap 3.7)gain stage (chap 3.7)gain stage (chap 3.7)gain stage (chap 3.7)
Simple CMOS Current MirrorSimple CMOS Current MirrorSimple CMOS Current MirrorSimple CMOS Current Mirror Used as bias current sourceUsed as bias current sourceUsed as bias current sourceUsed as bias current source Used to multiply currentsUsed to multiply currentsUsed to multiply currentsUsed to multiply currents Used as high output impedanceUsed as high output impedanceUsed as high output impedanceUsed as high output impedance
QQQQ1111 and Qand Qand Qand Q2222 have the same sizehave the same sizehave the same sizehave the same size both transistors are in active regionboth transistors are in active regionboth transistors are in active regionboth transistors are in active region
small signal model of small signal model of small signal model of small signal model of diode connected transistordiode connected transistordiode connected transistordiode connected transistor
MicroLab, vlsi-25 (5/26)
JMM v1.2
Simple CMOS Current Mirror Simple CMOS Current Mirror Simple CMOS Current Mirror Simple CMOS Current Mirror (small signal analysis)(small signal analysis)(small signal analysis)(small signal analysis)
Small signal model of overall CMOS current mirrorSmall signal model of overall CMOS current mirrorSmall signal model of overall CMOS current mirrorSmall signal model of overall CMOS current mirror
as there is no current through gas there is no current through gas there is no current through gas there is no current through gm1m1m1m1 ----> v> v> v> vgs2gs2gs2gs2=0 =0 =0 =0
rrrrds2ds2ds2ds2 ~~~~++++
----vvvvxxxx
iiiixxxx
rrrroutoutoutout of CMOS current mirror is:of CMOS current mirror is:of CMOS current mirror is:of CMOS current mirror is:
2dsout rr =
MicroLab, vlsi-25 (6/26)
JMM v1.2
Common Source AmplifierCommon Source AmplifierCommon Source AmplifierCommon Source Amplifier
the common source topology is the most popular the common source topology is the most popular the common source topology is the most popular the common source topology is the most popular gain stage, especially when highgain stage, especially when highgain stage, especially when highgain stage, especially when high----input impedance is input impedance is input impedance is input impedance is requiredrequiredrequiredrequired
a common use of simple current mirrors in a singlea common use of simple current mirrors in a singlea common use of simple current mirrors in a singlea common use of simple current mirrors in a single----stage amplifier with an active loadstage amplifier with an active loadstage amplifier with an active loadstage amplifier with an active load
active loads represent highactive loads represent highactive loads represent highactive loads represent high----impedance output loads impedance output loads impedance output loads impedance output loads without using high impedance resistors or large without using high impedance resistors or large without using high impedance resistors or large without using high impedance resistors or large power supply voltages.power supply voltages.power supply voltages.power supply voltages.
for a given supply voltage a larger gain can be for a given supply voltage a larger gain can be for a given supply voltage a larger gain can be for a given supply voltage a larger gain can be achieved using active loads.achieved using active loads.achieved using active loads.achieved using active loads.
for example, if a 1Mfor example, if a 1Mfor example, if a 1Mfor example, if a 1MΩΩΩΩ load were required with a load were required with a load were required with a load were required with a 100100100100µµµµA bias current, a 100A bias current, a 100A bias current, a 100A bias current, a 100µµµµA x 1MA x 1MA x 1MA x 1MΩΩΩΩ=100V =100V =100V =100V power supply would be necessarypower supply would be necessarypower supply would be necessarypower supply would be necessary
IIIIbiasbiasbiasbias QQQQ1111
QQQQ2222
rrrroutoutoutout
QQQQ3333
VVVVinininin
VVVVoutoutoutout
active loadactive loadactive loadactive load
common sourcecommon sourcecommon sourcecommon sourceamplifier stageamplifier stageamplifier stageamplifier stage
MicroLab, vlsi-25 (7/26)
JMM v1.2
Common Source AmplifierCommon Source AmplifierCommon Source AmplifierCommon Source Amplifier(small signal analysis)(small signal analysis)(small signal analysis)(small signal analysis)
it is assumed, that the bias current is such that it is assumed, that the bias current is such that it is assumed, that the bias current is such that it is assumed, that the bias current is such that both transistors Qboth transistors Qboth transistors Qboth transistors Q2222 and Qand Qand Qand Q3333 are in active region.are in active region.are in active region.are in active region.
commoncommoncommoncommon----drain amplifier is commonly used as drain amplifier is commonly used as drain amplifier is commonly used as drain amplifier is commonly used as voltage buffers and thus is called sourcevoltage buffers and thus is called sourcevoltage buffers and thus is called sourcevoltage buffers and thus is called source----follower follower follower follower
ideally the small signal voltage gain is close to ideally the small signal voltage gain is close to ideally the small signal voltage gain is close to ideally the small signal voltage gain is close to unityunityunityunity
as the circuit has no voltage gain it does have a as the circuit has no voltage gain it does have a as the circuit has no voltage gain it does have a as the circuit has no voltage gain it does have a current gaincurrent gaincurrent gaincurrent gain
dc level of the output voltage is not the same as dc level of the output voltage is not the same as dc level of the output voltage is not the same as dc level of the output voltage is not the same as the dc level of the input voltagethe dc level of the input voltagethe dc level of the input voltagethe dc level of the input voltage
note that the body effect is the major limitation on note that the body effect is the major limitation on note that the body effect is the major limitation on note that the body effect is the major limitation on the smallthe smallthe smallthe small----signal gainsignal gainsignal gainsignal gain
SourceSourceSourceSource----FollowerFollowerFollowerFollower(small signal analysis)(small signal analysis)(small signal analysis)(small signal analysis)
Note that the voltage controlled current source that Note that the voltage controlled current source that Note that the voltage controlled current source that Note that the voltage controlled current source that models the body effect of the models the body effect of the models the body effect of the models the body effect of the nfetnfetnfetnfet has been has been has been has been includedincludedincludedincluded
In order to minimize circuit equation errors, a In order to minimize circuit equation errors, a In order to minimize circuit equation errors, a In order to minimize circuit equation errors, a consistent methodology should be maintained when consistent methodology should be maintained when consistent methodology should be maintained when consistent methodology should be maintained when writing nodal equations:writing nodal equations:writing nodal equations:writing nodal equations: the first term is always the node at which the currents the first term is always the node at which the currents the first term is always the node at which the currents the first term is always the node at which the currents
are being summedare being summedare being summedare being summed
this node voltage is multiplied by the sum of all this node voltage is multiplied by the sum of all this node voltage is multiplied by the sum of all this node voltage is multiplied by the sum of all admittances connected to the nodeadmittances connected to the nodeadmittances connected to the nodeadmittances connected to the node
the next negative terms are the adjacent node voltages, the next negative terms are the adjacent node voltages, the next negative terms are the adjacent node voltages, the next negative terms are the adjacent node voltages, and each is and each is and each is and each is mutipliedmutipliedmutipliedmutiplied by all connecting admittancesby all connecting admittancesby all connecting admittancesby all connecting admittances
the last terms are any current sources with a multiplying the last terms are any current sources with a multiplying the last terms are any current sources with a multiplying the last terms are any current sources with a multiplying negative sign used if the current is shown to flow into negative sign used if the current is shown to flow into negative sign used if the current is shown to flow into negative sign used if the current is shown to flow into the nodethe nodethe nodethe node
SourceSourceSourceSource----FollowerFollowerFollowerFollower(small signal analysis, con‘t)(small signal analysis, con‘t)(small signal analysis, con‘t)(small signal analysis, con‘t)
ggggs1s1s1s1 is 5 to 10% of the value of gis 5 to 10% of the value of gis 5 to 10% of the value of gis 5 to 10% of the value of gm1m1m1m1, g, g, g, gds1ds1ds1ds1 and gand gand gand gds2 ds2 ds2 ds2 are are are are in the order of 1/10 of gin the order of 1/10 of gin the order of 1/10 of gin the order of 1/10 of gs1 s1 s1 s1
the body effect parameter gthe body effect parameter gthe body effect parameter gthe body effect parameter gs1s1s1s1 is the major source of is the major source of is the major source of is the major source of the error causing the gain less than unitythe error causing the gain less than unitythe error causing the gain less than unitythe error causing the gain less than unity
CommonCommonCommonCommon----gate stage with active load is used when gate stage with active load is used when gate stage with active load is used when gate stage with active load is used when relatively small input impedance is desiredrelatively small input impedance is desiredrelatively small input impedance is desiredrelatively small input impedance is desired
Application examples: input impedance of 50Application examples: input impedance of 50Application examples: input impedance of 50Application examples: input impedance of 50ΩΩΩΩ to to to to terminate a transmission line, or first stage of terminate a transmission line, or first stage of terminate a transmission line, or first stage of terminate a transmission line, or first stage of amplifier to amplify current instead of voltageamplifier to amplify current instead of voltageamplifier to amplify current instead of voltageamplifier to amplify current instead of voltage
CommonCommonCommonCommon----Gate AmplifierGate AmplifierGate AmplifierGate Amplifier(small signal analysis)(small signal analysis)(small signal analysis)(small signal analysis)
11 gss vv −= thusthusthusthus
active loadactive loadactive loadactive loadrrrrinininin
only active only active only active only active charge presentcharge presentcharge presentcharge present
MicroLab, vlsi-25 (14/26)
JMM v1.2
Summary: Gain StagesSummary: Gain StagesSummary: Gain StagesSummary: Gain Stages
common source amplifier:common source amplifier:common source amplifier:common source amplifier: gain stage with high gain stage with high gain stage with high gain stage with high input impedance.input impedance.input impedance.input impedance.
common drain amplifiercommon drain amplifiercommon drain amplifiercommon drain amplifier (source follower): used as (source follower): used as (source follower): used as (source follower): used as voltage buffers with small signal voltage gain close voltage buffers with small signal voltage gain close voltage buffers with small signal voltage gain close voltage buffers with small signal voltage gain close to 1, but can produce current gain.to 1, but can produce current gain.to 1, but can produce current gain.to 1, but can produce current gain.
common gate amplifier:common gate amplifier:common gate amplifier:common gate amplifier: used as gain stage when a used as gain stage when a used as gain stage when a used as gain stage when a small input impedance is desired and can be used as small input impedance is desired and can be used as small input impedance is desired and can be used as small input impedance is desired and can be used as first stage of an amplifier designed to amplify first stage of an amplifier designed to amplify first stage of an amplifier designed to amplify first stage of an amplifier designed to amplify current rather than voltage.current rather than voltage.current rather than voltage.current rather than voltage.
( )211 dsdsmin
outv rrg
vvA −==
2111
1
dsdssm
m
in
outv gggg
gvvA
+++==
1
111
1
111
/1dsL
dssm
Lds
dssms
s
in
outv gG
ggg
GggggG
GvvA
+++
++++
==
MicroLab, vlsi-25 (15/26)
JMM v1.2
SourceSourceSourceSource----Degenerated Current MirrorDegenerated Current MirrorDegenerated Current MirrorDegenerated Current Mirror General consequence of General consequence of General consequence of General consequence of finit finit finit finit output resistance:output resistance:output resistance:output resistance:
deviation in large signal behaviordeviation in large signal behaviordeviation in large signal behaviordeviation in large signal behavior difficulties as active loaddifficulties as active loaddifficulties as active loaddifficulties as active load
the output impedance of the basic 2 transistor current the output impedance of the basic 2 transistor current the output impedance of the basic 2 transistor current the output impedance of the basic 2 transistor current mirror can be increased by mirror can be increased by mirror can be increased by mirror can be increased by degeneration resistors degeneration resistors degeneration resistors degeneration resistors RRRRssss IIIIinininin
HighHighHighHigh----Output Impedance Current MirrorsOutput Impedance Current MirrorsOutput Impedance Current MirrorsOutput Impedance Current MirrorsCascodeCascodeCascodeCascode Current MirrorCurrent MirrorCurrent MirrorCurrent Mirror
the output impedance of a the output impedance of a the output impedance of a the output impedance of a cascodecascodecascodecascode current mirror is current mirror is current mirror is current mirror is increased by a factor 10 to 100 compared to a basic increased by a factor 10 to 100 compared to a basic increased by a factor 10 to 100 compared to a basic increased by a factor 10 to 100 compared to a basic current mirrorcurrent mirrorcurrent mirrorcurrent mirror
a disadvantage is the reduced output voltage swing a disadvantage is the reduced output voltage swing a disadvantage is the reduced output voltage swing a disadvantage is the reduced output voltage swing because transistors may enter triode regionbecause transistors may enter triode regionbecause transistors may enter triode regionbecause transistors may enter triode region
CascodeCascodeCascodeCascode Current MirrorCurrent MirrorCurrent MirrorCurrent Mirror
reduced output voltage swingreduced output voltage swingreduced output voltage swingreduced output voltage swing
IIIIinininin
QQQQ3333 QQQQ4444
rrrroutoutoutout
IIIIoutoutoutout
QQQQ1111 QQQQ2222
VVVVoutoutoutout
transistor in active regiontransistor in active regiontransistor in active regiontransistor in active regionVVVVdsdsdsds > > > > VVVVeffeffeffeff = = = = VVVVgsgsgsgs ---- VVVVtntntntn
all transistor have the same size and current Iall transistor have the same size and current Iall transistor have the same size and current Iall transistor have the same size and current Idddd::::VVVVgsgsgsgs = = = = VVVVeffeffeffeff + + + + VVVVtntntntn
MicroLab, vlsi-25 (18/26)
JMM v1.2
CascodeCascodeCascodeCascode Current Mirror (con‘t)Current Mirror (con‘t)Current Mirror (con‘t)Current Mirror (con‘t)
very high output impedancevery high output impedancevery high output impedancevery high output impedance IIIIinininin
HighHighHighHigh----OutputOutputOutputOutput----Impedance Current MirrorsImpedance Current MirrorsImpedance Current MirrorsImpedance Current MirrorsWilson Current MirrorWilson Current MirrorWilson Current MirrorWilson Current Mirror
very similar performance than very similar performance than very similar performance than very similar performance than cascodecascodecascodecascode current current current current mirror but 1/2 of its output impedancemirror but 1/2 of its output impedancemirror but 1/2 of its output impedancemirror but 1/2 of its output impedance
shuntshuntshuntshunt----series feedback to increase output impedanceseries feedback to increase output impedanceseries feedback to increase output impedanceseries feedback to increase output impedance
IIIIinininin
QQQQ3333 QQQQ4444
rrrroutoutoutout
IIIIoutoutoutout
QQQQ1111 QQQQ2222
rrrrinininin
QQQQ2222 senses output current and mirrors it to Isenses output current and mirrors it to Isenses output current and mirrors it to Isenses output current and mirrors it to Id1 d1 d1 d1 to. to. to. to. IIIIinininin and Iand Iand Iand Id1 d1 d1 d1 must precisely match otherwise Vmust precisely match otherwise Vmust precisely match otherwise Vmust precisely match otherwise Vg3g3g3g3 increases/decreases.increases/decreases.increases/decreases.increases/decreases.
MicroLab, vlsi-25 (20/26)
JMM v1.2
CascodeCascodeCascodeCascode Gain StageGain StageGain StageGain Stage cascodecascodecascodecascode configuration for single stage amplifiers is configuration for single stage amplifiers is configuration for single stage amplifiers is configuration for single stage amplifiers is
commonly used in modern IC designcommonly used in modern IC designcommonly used in modern IC designcommonly used in modern IC design quite large gain for single stage due to large impedance quite large gain for single stage due to large impedance quite large gain for single stage due to large impedance quite large gain for single stage due to large impedance
at the output at the output at the output at the output to enable the large gain, high quality to enable the large gain, high quality to enable the large gain, high quality to enable the large gain, high quality cascodecascodecascodecascode current current current current mirrors at the output are necessarymirrors at the output are necessarymirrors at the output are necessarymirrors at the output are necessary
large gain normally without any speed degradationlarge gain normally without any speed degradationlarge gain normally without any speed degradationlarge gain normally without any speed degradation voltage across input drive voltage across input drive voltage across input drive voltage across input drive fetfetfetfet is limited is limited is limited is limited
minimizing short channel effects in modern technologiesminimizing short channel effects in modern technologiesminimizing short channel effects in modern technologiesminimizing short channel effects in modern technologies configuration: commonconfiguration: commonconfiguration: commonconfiguration: common----sourcesourcesourcesource----connected transistor connected transistor connected transistor connected transistor
feeding into a commonfeeding into a commonfeeding into a commonfeeding into a common----gategategategate----connected transistorconnected transistorconnected transistorconnected transistor
source degenerated current mirror:source degenerated current mirror:source degenerated current mirror:source degenerated current mirror: by by by by addding addding addding addding a a a a resistor RS at the source node of a current mirror resistor RS at the source node of a current mirror resistor RS at the source node of a current mirror resistor RS at the source node of a current mirror fetfetfetfet, the output impedance can be increased:, the output impedance can be increased:, the output impedance can be increased:, the output impedance can be increased:
cascodecascodecascodecascode current mirror:current mirror:current mirror:current mirror: the output impedance of a the output impedance of a the output impedance of a the output impedance of a current mirror can further be increased by using current mirror can further be increased by using current mirror can further be increased by using current mirror can further be increased by using cascode fetscascode fetscascode fetscascode fets::::
cascodecascodecascodecascode gain stage:gain stage:gain stage:gain stage: due to the large impedance at due to the large impedance at due to the large impedance at due to the large impedance at the output, high gain can be realized with the output, high gain can be realized with the output, high gain can be realized with the output, high gain can be realized with cascodecascodecascodecascodegain stages:gain stages:gain stages:gain stages:
2
21
−≅=ds
m
in
outv g
gvvA
442 mdsdsout
outout grr
ivr ≅=
tneffout VVV +≥ 2
( )[ ]222 1 smsdsout
outout ggRr
ivr ++==
MicroLab, vlsi-25 (23/26)
JMM v1.2
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic…Frequency response of single stage amplifiersFrequency response of single stage amplifiersFrequency response of single stage amplifiersFrequency response of single stage amplifiers
Readings for next time…Readings for next time…Readings for next time…Readings for next time…Johns&MartinJohns&MartinJohns&MartinJohns&Martin: : : : nodal analysis methodnodal analysis methodnodal analysis methodnodal analysis method simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1)simple CMOS current mirror (chap 3.1) commoncommoncommoncommon----source amplifier (chap 3.2)source amplifier (chap 3.2)source amplifier (chap 3.2)source amplifier (chap 3.2) sourcesourcesourcesource----follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3)follower or common drain amplifier (chap 3.3) common gate amplifier (chap 3.4)common gate amplifier (chap 3.4)common gate amplifier (chap 3.4)common gate amplifier (chap 3.4) source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5)source degenerated current mirror (chap 3.5) highhighhighhigh----outputoutputoutputoutput----impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6)impedance current mirrors (chap 3.6) cascodecascodecascodecascode gain stage (chap 3.7)gain stage (chap 3.7)gain stage (chap 3.7)gain stage (chap 3.7)
Exercises: Exercises: Exercises: Exercises: Have a look at the exercises in Have a look at the exercises in Have a look at the exercises in Have a look at the exercises in Johns&MartinJohns&MartinJohns&MartinJohns&Martin.... CAD exercise Ex601CAD exercise Ex601CAD exercise Ex601CAD exercise Ex601
Johns&Martin chap 3.1 pp127: 3.1 (difficulty: easy):Johns&Martin chap 3.1 pp127: 3.1 (difficulty: easy):Johns&Martin chap 3.1 pp127: 3.1 (difficulty: easy):Johns&Martin chap 3.1 pp127: 3.1 (difficulty: easy):Consider the current mirror shown on transparency Consider the current mirror shown on transparency Consider the current mirror shown on transparency Consider the current mirror shown on transparency vlsi25/3 where vlsi25/3 where vlsi25/3 where vlsi25/3 where IIIIinininin=100=100=100=100µµµµA and each transistor has A and each transistor has A and each transistor has A and each transistor has W=10W=10W=10W=10µµµµm and L=2m and L=2m and L=2m and L=2µµµµm. Given m. Given m. Given m. Given rrrrdsdsdsds=88000 [L =88000 [L =88000 [L =88000 [L ((((µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)], find r)], find r)], find r)], find routoutoutout for the current mirror for the current mirror for the current mirror for the current mirror and the value of gand the value of gand the value of gand the value of gm1m1m1m1. Also estimate the change in . Also estimate the change in . Also estimate the change in . Also estimate the change in IIIIoutoutoutoutfor a 0.5V change in the output voltage. for a 0.5V change in the output voltage. for a 0.5V change in the output voltage. for a 0.5V change in the output voltage.
Result: rResult: rResult: rResult: rout out out out =1.76M=1.76M=1.76M=1.76MΩΩΩΩ, g, g, g, gm1m1m1m1=0.45mA/V, =0.45mA/V, =0.45mA/V, =0.45mA/V, dIdIdIdIoutoutoutout=0.28=0.28=0.28=0.28µΑµΑµΑµΑ
Johns&Martin chap 3.2 pp129: 3.2 (difficulty: easy):Johns&Martin chap 3.2 pp129: 3.2 (difficulty: easy):Johns&Martin chap 3.2 pp129: 3.2 (difficulty: easy):Johns&Martin chap 3.2 pp129: 3.2 (difficulty: easy):Consider the common source stage shown on Consider the common source stage shown on Consider the common source stage shown on Consider the common source stage shown on transparency vlsi25/7 where transparency vlsi25/7 where transparency vlsi25/7 where transparency vlsi25/7 where IIIIinininin=100=100=100=100µµµµA and all A and all A and all A and all transistor have W=10transistor have W=10transistor have W=10transistor have W=10µµµµm and L=2m and L=2m and L=2m and L=2µµµµm. Given m. Given m. Given m. Given rrrrdsndsndsndsn=88000 [L (=88000 [L (=88000 [L (=88000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)], )], )], )], rrrrdspdspdspdsp=50000 =50000 =50000 =50000 [L ([L ([L ([L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. What is the gain of the )]. What is the gain of the )]. What is the gain of the )]. What is the gain of the stage. stage. stage. stage.
Result: AResult: AResult: AResult: Av v v v ====----287287287287
Johns&Martin chap 3.3 pp131: 3.3 (difficulty: easy):Johns&Martin chap 3.3 pp131: 3.3 (difficulty: easy):Johns&Martin chap 3.3 pp131: 3.3 (difficulty: easy):Johns&Martin chap 3.3 pp131: 3.3 (difficulty: easy):Consider the source follower shown on transparency Consider the source follower shown on transparency Consider the source follower shown on transparency Consider the source follower shown on transparency vlsi25/8 where vlsi25/8 where vlsi25/8 where vlsi25/8 where IIIIbiasbiasbiasbias=100=100=100=100µµµµA and all transistors A and all transistors A and all transistors A and all transistors designed with designed with designed with designed with AlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm process have m process have m process have m process have W=10W=10W=10W=10µµµµm and L=2m and L=2m and L=2m and L=2µµµµm. Given m. Given m. Given m. Given γγγγnnnn=0.45V=0.45V=0.45V=0.45V1/21/21/21/2, , , , VVVVsbsbsbsb=2V, and =2V, and =2V, and =2V, and rrrrdsdsdsds----nnnn=88000 [L (=88000 [L (=88000 [L (=88000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. )]. )]. )]. What is the gain of the stage. What is the gain of the stage. What is the gain of the stage. What is the gain of the stage.
Result: AResult: AResult: AResult: Av v v v =0.88=0.88=0.88=0.88
Johns&Martin chap 3.5 pp136: 3.4 (difficulty: easy):Johns&Martin chap 3.5 pp136: 3.4 (difficulty: easy):Johns&Martin chap 3.5 pp136: 3.4 (difficulty: easy):Johns&Martin chap 3.5 pp136: 3.4 (difficulty: easy):Consider the source degenerated current mirror Consider the source degenerated current mirror Consider the source degenerated current mirror Consider the source degenerated current mirror shown on transparency vlsi25/15 where shown on transparency vlsi25/15 where shown on transparency vlsi25/15 where shown on transparency vlsi25/15 where IIIIbiasbiasbiasbias=100=100=100=100µµµµA and all transistors designed withA and all transistors designed withA and all transistors designed withA and all transistors designed withAlcatelAlcatelAlcatelAlcatel 0.50.50.50.5µµµµm process have W=100m process have W=100m process have W=100m process have W=100µµµµm and m and m and m and L=2L=2L=2L=2µµµµm. Given m. Given m. Given m. Given γγγγnnnn=0.45V=0.45V=0.45V=0.45V1/21/21/21/2,,,, VVVVsbsbsbsb=2V, =2V, =2V, =2V, RRRRssss=5k=5k=5k=5kΩΩΩΩ, , , , and and and and rrrrdsdsdsds----nnnn=88000 [L (=88000 [L (=88000 [L (=88000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. What is )]. What is )]. What is )]. What is the increase in output resistance compared to simple the increase in output resistance compared to simple the increase in output resistance compared to simple the increase in output resistance compared to simple current mirror. current mirror. current mirror. current mirror.
Result: increase=9.1, rResult: increase=9.1, rResult: increase=9.1, rResult: increase=9.1, rout out out out =16M=16M=16M=16MΩΩΩΩ
Johns&Martin chap 3.6 pp138: 3.5 (difficulty: easy):Johns&Martin chap 3.6 pp138: 3.5 (difficulty: easy):Johns&Martin chap 3.6 pp138: 3.5 (difficulty: easy):Johns&Martin chap 3.6 pp138: 3.5 (difficulty: easy):Consider the Consider the Consider the Consider the cascodecascodecascodecascode current mirror shown on current mirror shown on current mirror shown on current mirror shown on transparency vlsi25/15 where transparency vlsi25/15 where transparency vlsi25/15 where transparency vlsi25/15 where IIIIinininin=100=100=100=100µµµµA and all A and all A and all A and all transistors have W=10transistors have W=10transistors have W=10transistors have W=10µµµµm and L=2m and L=2m and L=2m and L=2µµµµm. Given m. Given m. Given m. Given VVVVSB4SB4SB4SB4=1V and =1V and =1V and =1V and rrrrdsdsdsds----nnnn=50000 [L (=50000 [L (=50000 [L (=50000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. )]. )]. )]. What is the output impedance and the minimal What is the output impedance and the minimal What is the output impedance and the minimal What is the output impedance and the minimal output voltage. output voltage. output voltage. output voltage.
Result: rResult: rResult: rResult: rout out out out =527k=527k=527k=527kΩΩΩΩ, , , , VVVVoutoutoutout(min)=1.5V(min)=1.5V(min)=1.5V(min)=1.5V
Johns&Martin chap 3.7 pp142: 3.6 (difficulty: easy):Johns&Martin chap 3.7 pp142: 3.6 (difficulty: easy):Johns&Martin chap 3.7 pp142: 3.6 (difficulty: easy):Johns&Martin chap 3.7 pp142: 3.6 (difficulty: easy):Consider the telescopic Consider the telescopic Consider the telescopic Consider the telescopic cascodecascodecascodecascode gain stage shown on gain stage shown on gain stage shown on gain stage shown on transparency vlsi25/20 assuming gtransparency vlsi25/20 assuming gtransparency vlsi25/20 assuming gtransparency vlsi25/20 assuming gmmmm=0.5mA/V =0.5mA/V =0.5mA/V =0.5mA/V and and and and rrrrdsdsdsds=100k=100k=100k=100kΩΩΩΩ. What is the output impedance and . What is the output impedance and . What is the output impedance and . What is the output impedance and gain. gain. gain. gain.
Result: rResult: rResult: rResult: rout out out out =2.5M=2.5M=2.5M=2.5MΩΩΩΩ, A, A, A, Avvvv====----1250125012501250
Circuit AnalysisCircuit AnalysisCircuit AnalysisCircuit Analysis the precise way:the precise way:the precise way:the precise way: solving complex equationssolving complex equationssolving complex equationssolving complex equations the approximate way:the approximate way:the approximate way:the approximate way: find the dominant polefind the dominant polefind the dominant polefind the dominant pole the handy way:the handy way:the handy way:the handy way: let Spice do it preciselylet Spice do it preciselylet Spice do it preciselylet Spice do it precisely
Goal: Goal: Goal: Goal: You are able to identify the dominant pole in a You are able to identify the dominant pole in a You are able to identify the dominant pole in a You are able to identify the dominant pole in a transistor circuit. You can approximately determine transistor circuit. You can approximately determine transistor circuit. You can approximately determine transistor circuit. You can approximately determine the contribution of each node in a circuit to the the contribution of each node in a circuit to the the contribution of each node in a circuit to the the contribution of each node in a circuit to the total frequency response.total frequency response.total frequency response.total frequency response.
MicroLab, vlsi26 (2/29)
JMM v1.2
OutlineOutlineOutlineOutline
Frequency responseFrequency responseFrequency responseFrequency response commoncommoncommoncommon----source amplifiersource amplifiersource amplifiersource amplifier sourcesourcesourcesource----follower amplifierfollower amplifierfollower amplifierfollower amplifier sourcesourcesourcesource----follower amplifier with compensation techniquefollower amplifier with compensation techniquefollower amplifier with compensation techniquefollower amplifier with compensation technique cascode gain stagecascode gain stagecascode gain stagecascode gain stage
Gray&MeyerGray&MeyerGray&MeyerGray&Meyer estimation of dominant polesestimation of dominant polesestimation of dominant polesestimation of dominant poles zerozerozerozero----Value Time Constant Analysis (pp500 Value Time Constant Analysis (pp500 Value Time Constant Analysis (pp500 Value Time Constant Analysis (pp500 ffffffff)))) (Analysis and Design of Analog Integrated Circuits, 3rd (Analysis and Design of Analog Integrated Circuits, 3rd (Analysis and Design of Analog Integrated Circuits, 3rd (Analysis and Design of Analog Integrated Circuits, 3rd
edition, Wiley and Sons, ISBNedition, Wiley and Sons, ISBNedition, Wiley and Sons, ISBNedition, Wiley and Sons, ISBN----0471047104710471----59984599845998459984----0)0)0)0)
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseDominant Pole ApproximationDominant Pole ApproximationDominant Pole ApproximationDominant Pole Approximation
precise calculation of frequency response is a precise calculation of frequency response is a precise calculation of frequency response is a precise calculation of frequency response is a complex task and thus different approximation complex task and thus different approximation complex task and thus different approximation complex task and thus different approximation methods existmethods existmethods existmethods exist
one method is the zeroone method is the zeroone method is the zeroone method is the zero----value time constant analysisvalue time constant analysisvalue time constant analysisvalue time constant analysis first some ideas about dominantfirst some ideas about dominantfirst some ideas about dominantfirst some ideas about dominant----pole approximation pole approximation pole approximation pole approximation
are developedare developedare developedare developed
transfer function by smalltransfer function by smalltransfer function by smalltransfer function by small----signal analysissignal analysissignal analysissignal analysis
very often the zeros are unimportant, thusvery often the zeros are unimportant, thusvery often the zeros are unimportant, thusvery often the zeros are unimportant, thus
(((( ))))
−−−−
−−−−
−−−−====
nnnn22221111 ppppssss1111
ppppssss1111
ppppssss1111
KKKKssssAAAA
Where K is a constant and pWhere K is a constant and pWhere K is a constant and pWhere K is a constant and p1111,p,p,p,p2222 ... are poles of the transfer function,... are poles of the transfer function,... are poles of the transfer function,... are poles of the transfer function,
thusthusthusthus ∑∑∑∑====
−−−−====nnnn
1111iiii iiii1111 pppp
1111bbbb
MicroLab, vlsi26 (4/29)
JMM v1.2
Dominant Pole Approximation Dominant Pole Approximation Dominant Pole Approximation Dominant Pole Approximation ((((con’tcon’tcon’tcon’t 2)2)2)2)
an important practical case occurs when one pole is dominantan important practical case occurs when one pole is dominantan important practical case occurs when one pole is dominantan important practical case occurs when one pole is dominant
the gain the gain the gain the gain magnitutemagnitutemagnitutemagnitute in the frequency domain isin the frequency domain isin the frequency domain isin the frequency domain is
with a dominant pole we simply getwith a dominant pole we simply getwith a dominant pole we simply getwith a dominant pole we simply get
(((( ))))
ωωωω++++
≅≅≅≅ωωωω2222
1111pppp1111
KKKKjjjjAAAA
∑∑∑∑====
−−−−====nnnn
1111iiii iiii1111 pppp
1111bbbb
MicroLab, vlsi26 (5/29)
JMM v1.2
Dominant Pole Approximation Dominant Pole Approximation Dominant Pole Approximation Dominant Pole Approximation ((((con’tcon’tcon’tcon’t 3)3)3)3)
this approximation will be quite accurate as long as this approximation will be quite accurate as long as this approximation will be quite accurate as long as this approximation will be quite accurate as long as 1111pppp≅≅≅≅ωωωω
thus for a dominant pole situation the thus for a dominant pole situation the thus for a dominant pole situation the thus for a dominant pole situation the ----3dB frequency is 3dB frequency is 3dB frequency is 3dB frequency is
1111dBdBdBdB3333 pppp≅≅≅≅ωωωω−−−−1111
dBdBdBdB3333 bbbb1111≅≅≅≅ωωωω−−−−
s planes planes planes planeωωωωjjjj
σσσσpppp1111pppp2222pppp3333
pole plot for a circuit with a dominant polepole plot for a circuit with a dominant polepole plot for a circuit with a dominant polepole plot for a circuit with a dominant pole
MicroLab, vlsi26 (6/29)
JMM v1.2
ZeroZeroZeroZero----Value Time ConstantValue Time ConstantValue Time ConstantValue Time Constant
Method for finding the time constant associated Method for finding the time constant associated Method for finding the time constant associated Method for finding the time constant associated with a capacitor in the small signal equivalent with a capacitor in the small signal equivalent with a capacitor in the small signal equivalent with a capacitor in the small signal equivalent circuitcircuitcircuitcircuit
replace the capacitor replace the capacitor replace the capacitor replace the capacitor CCCCxxxx by a voltage source by a voltage source by a voltage source by a voltage source VVVVxxxx
set all independent sources to groundset all independent sources to groundset all independent sources to groundset all independent sources to ground set all other network capacitors to zeroset all other network capacitors to zeroset all other network capacitors to zeroset all other network capacitors to zero find admittance find admittance find admittance find admittance YYYYxxxx (=1/R(=1/R(=1/R(=1/Rxxxx) which is driven by a ) which is driven by a ) which is driven by a ) which is driven by a
voltage source voltage source voltage source voltage source VVVVxxxx
the time constant the time constant the time constant the time constant ττττxxxx is given by:is given by:is given by:is given by:
xxx CR=τ
MicroLab, vlsi26 (7/29)
JMM v1.2
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseZeroZeroZeroZero----Value Time ConstantValue Time ConstantValue Time ConstantValue Time Constant
We can show that with this choice We can show that with this choice We can show that with this choice We can show that with this choice od od od od variables the circuit equations are of the form:variables the circuit equations are of the form:variables the circuit equations are of the form:variables the circuit equations are of the form:
MicroLab, vlsi26 (8/29)
JMM v1.2
ZeroZeroZeroZero----Value Time ConstantValue Time ConstantValue Time ConstantValue Time Constant((((con’t con’t con’t con’t 1)1)1)1)
The poles of the transfer function are the zeros of the determinThe poles of the transfer function are the zeros of the determinThe poles of the transfer function are the zeros of the determinThe poles of the transfer function are the zeros of the determinant ant ant ant ∆∆∆∆ of theof theof theof thecircuit equations, which can be written in the form:circuit equations, which can be written in the form:circuit equations, which can be written in the form:circuit equations, which can be written in the form:
Consider now the term KConsider now the term KConsider now the term KConsider now the term K1111s, this is the sum of the terms involving s that are s, this is the sum of the terms involving s that are s, this is the sum of the terms involving s that are s, this is the sum of the terms involving s that are obtained when the system determinant is evaluated. However it isobtained when the system determinant is evaluated. However it isobtained when the system determinant is evaluated. However it isobtained when the system determinant is evaluated. However it is apparent,apparent,apparent,apparent,that s only occurs when associated with a capacitance:that s only occurs when associated with a capacitance:that s only occurs when associated with a capacitance:that s only occurs when associated with a capacitance:
The terms are constants. hThe terms are constants. hThe terms are constants. hThe terms are constants. h1111 can be evaluated by expanding the determinantcan be evaluated by expanding the determinantcan be evaluated by expanding the determinantcan be evaluated by expanding the determinantabout the first row:about the first row:about the first row:about the first row:
With cofactors With cofactors With cofactors With cofactors ∆∆∆∆xxxxxxxx of the determinant. The term of the determinant. The term of the determinant. The term of the determinant. The term sCsCsCsCππππ is found by evaluatingis found by evaluatingis found by evaluatingis found by evaluating∆∆∆∆11111111 with Cwith Cwith Cwith Cµµµµ and and and and CCCCxxxx equal zeroequal zeroequal zeroequal zero
0000CCCCCCCC111111111111 xxxxhhhh ========µµµµ
∆∆∆∆====
MicroLab, vlsi26 (9/29)
JMM v1.2
ZeroZeroZeroZero----Value Time ConstantValue Time ConstantValue Time ConstantValue Time Constant((((con’t con’t con’t con’t 2)2)2)2)
Now consider expansion of the determinant about the second row.Now consider expansion of the determinant about the second row.Now consider expansion of the determinant about the second row.Now consider expansion of the determinant about the second row.
With cofactors With cofactors With cofactors With cofactors ∆∆∆∆xxxxxxxx of the determinant. The term of the determinant. The term of the determinant. The term of the determinant. The term sCsCsCsCµµµµ is found by evaluatingis found by evaluatingis found by evaluatingis found by evaluating∆∆∆∆22222222 with with with with CCCCππππ and and and and CCCCxxxx equal zeroequal zeroequal zeroequal zero
ZeroZeroZeroZero----Value Time ConstantValue Time ConstantValue Time ConstantValue Time Constant((((con’t con’t con’t con’t 3)3)3)3)
(((( ))))ssssiiiivvvv 11111111
1111
1111
∆∆∆∆∆∆∆∆====
Now consider putting iNow consider putting iNow consider putting iNow consider putting i2222=i=i=i=i3333=0 and solving for v=0 and solving for v=0 and solving for v=0 and solving for v1111
The drivingThe drivingThe drivingThe driving----point resistance at the point resistance at the point resistance at the point resistance at the CCCCππππ node pair with all capacitors node pair with all capacitors node pair with all capacitors node pair with all capacitors equal to zero:equal to zero:equal to zero:equal to zero:
0000CCCCCCCCCCCC11111111
0000
0000CCCCCCCC11111111
xxxx
xxxx
====================
ππππµµµµ
µµµµ
∆∆∆∆∆∆∆∆====
∆∆∆∆
∆∆∆∆
We now defineWe now defineWe now defineWe now define
0000CCCCCCCC0000
111111110000 xxxx
RRRR ========ππππ µµµµ∆∆∆∆∆∆∆∆====
We can write now:We can write now:We can write now:We can write now:
Thus the sum of the zeroThus the sum of the zeroThus the sum of the zeroThus the sum of the zero----value time constants leads to the value time constants leads to the value time constants leads to the value time constants leads to the ----3dB frequency3dB frequency3dB frequency3dB frequency∑∑∑∑
≅≅≅≅ωωωω−−−−0000
dBdBdBdB3333 TTTT1111
MicroLab, vlsi26 (11/29)
JMM v1.2
Summary: Frequency Analysis MethodsSummary: Frequency Analysis MethodsSummary: Frequency Analysis MethodsSummary: Frequency Analysis MethodsThe precise way:The precise way:The precise way:The precise way: Add the parasitic capacitors to the equivalent circuit. Use Add the parasitic capacitors to the equivalent circuit. Use Add the parasitic capacitors to the equivalent circuit. Use Add the parasitic capacitors to the equivalent circuit. Use
nodal analysis for evaluating the transfer function.nodal analysis for evaluating the transfer function.nodal analysis for evaluating the transfer function.nodal analysis for evaluating the transfer function.The approximate way:The approximate way:The approximate way:The approximate way: if there exists a pole pif there exists a pole pif there exists a pole pif there exists a pole p1111 <<p<<p<<p<<p2222, p, p, p, p3333 ,..., and the transfer ,..., and the transfer ,..., and the transfer ,..., and the transfer
function is already given be the transfer function function is already given be the transfer function function is already given be the transfer function function is already given be the transfer function A(s)=N(s)/D(s) A(s)=N(s)/D(s) A(s)=N(s)/D(s) A(s)=N(s)/D(s) with with with with the pole pthe pole pthe pole pthe pole p1111 is given by:is given by:is given by:is given by:
the dominant pole may be found directly in the circuit the dominant pole may be found directly in the circuit the dominant pole may be found directly in the circuit the dominant pole may be found directly in the circuit diagram by looking for the node with the largest diagram by looking for the node with the largest diagram by looking for the node with the largest diagram by looking for the node with the largest impedance. Take care of the Miller Effect.impedance. Take care of the Miller Effect.impedance. Take care of the Miller Effect.impedance. Take care of the Miller Effect.
The time constant (and its influence on the frequency The time constant (and its influence on the frequency The time constant (and its influence on the frequency The time constant (and its influence on the frequency response) associated with a single parasitic capacitor can response) associated with a single parasitic capacitor can response) associated with a single parasitic capacitor can response) associated with a single parasitic capacitor can be estimated with the zero value time constant method:be estimated with the zero value time constant method:be estimated with the zero value time constant method:be estimated with the zero value time constant method: set all independent sources to zeroset all independent sources to zeroset all independent sources to zeroset all independent sources to zero replace the interesting capacitor replace the interesting capacitor replace the interesting capacitor replace the interesting capacitor CCCCxxxx by a voltage source by a voltage source by a voltage source by a voltage source VVVVxxxx
set all other capacitors to zeroset all other capacitors to zeroset all other capacitors to zeroset all other capacitors to zero evaluate the impedance Revaluate the impedance Revaluate the impedance Revaluate the impedance Rxxxx seen by the voltage source seen by the voltage source seen by the voltage source seen by the voltage source VVVVxxxx
the time constant is equal to the time constant is equal to the time constant is equal to the time constant is equal to CCCCxxxxRRRRxxxx
The handy way:The handy way:The handy way:The handy way: AC analysis with SpiceAC analysis with SpiceAC analysis with SpiceAC analysis with Spice
nnsbsbsbsD ++++= l
2211)(
11 /1 bp =
MicroLab, vlsi26 (12/29)
JMM v1.2
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseCommonCommonCommonCommon----Source AmplifierSource AmplifierSource AmplifierSource Amplifier
precise calculation of frequency response is most precise calculation of frequency response is most precise calculation of frequency response is most precise calculation of frequency response is most often left to computer simulationsoften left to computer simulationsoften left to computer simulationsoften left to computer simulations
much insight can be obtained by finding the much insight can be obtained by finding the much insight can be obtained by finding the much insight can be obtained by finding the dominant frequency effects (dominant poles, zeros)dominant frequency effects (dominant poles, zeros)dominant frequency effects (dominant poles, zeros)dominant frequency effects (dominant poles, zeros)
vvvvgs1gs1gs1gs1
ggggm1m1m1m1vvvvgs1gs1gs1gs1
RRRRinininin
~~~~++++
----vvvvinininin
vvvvoutoutoutout
CCCC2222RRRR2222CCCCgs1gs1gs1gs1
CCCCgd1gd1gd1gd1
CCCCdbdbdbdb of Qof Qof Qof Q1111 and Qand Qand Qand Q2222and load Cand load Cand load Cand load CLLLL
rrrrdsdsdsds of Qof Qof Qof Q1111 and Qand Qand Qand Q2222
Frequency Analysis (Frequency Analysis (Frequency Analysis (Frequency Analysis (con’tcon’tcon’tcon’t))))
bbbbsssssasasasa1111ggggCCCC
ssss1111RRRRgggg
vvvvvvvv
22221111mmmm
1111gdgdgdgd22221111mmmm
inininin
outoutoutout
++++++++
−−−−−−−−====
at frequencies at frequencies at frequencies at frequencies where gain has justwhere gain has justwhere gain has justwhere gain has juststarted to decreasestarted to decreasestarted to decreasestarted to decrease
for for for for RRRRinininin >> R>> R>> R>> R2222Miller capacitanceMiller capacitanceMiller capacitanceMiller capacitance
analysis for high frequencies for widely separated polesanalysis for high frequencies for widely separated polesanalysis for high frequencies for widely separated polesanalysis for high frequencies for widely separated poles
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseSourceSourceSourceSource----Follower AmplifierFollower AmplifierFollower AmplifierFollower Amplifier
source followers can have complex poles and thus source followers can have complex poles and thus source followers can have complex poles and thus source followers can have complex poles and thus exhibit overshootexhibit overshootexhibit overshootexhibit overshoot
a compensation technique resulting in only real axis a compensation technique resulting in only real axis a compensation technique resulting in only real axis a compensation technique resulting in only real axis poles is shown, resulting in no overshootingpoles is shown, resulting in no overshootingpoles is shown, resulting in no overshootingpoles is shown, resulting in no overshooting
1. gain from v1. gain from v1. gain from v1. gain from vg1g1g1g1 to to to to vvvvoutoutoutout is foundis foundis foundis found2. admittance 2. admittance 2. admittance 2. admittance YYYYgggg looking into gate of Qlooking into gate of Qlooking into gate of Qlooking into gate of Q1111 without considering Cwithout considering Cwithout considering Cwithout considering Cgd1gd1gd1gd1 is foundis foundis foundis found3. Gain from 3. Gain from 3. Gain from 3. Gain from iiiiinininin to vto vto vto vg1g1g1g1 is foundis foundis foundis found4. overall gain from v4. overall gain from v4. overall gain from v4. overall gain from vinininin to to to to vvvvoutoutoutout is found and results interpretedis found and results interpretedis found and results interpretedis found and results interpreted
1. gain from v1. gain from v1. gain from v1. gain from vg1g1g1g1 to to to to vvvvoutoutoutout is foundis foundis foundis found2. admittance 2. admittance 2. admittance 2. admittance YYYYgggg looking into gate of Qlooking into gate of Qlooking into gate of Qlooking into gate of Q1111 without considering Cwithout considering Cwithout considering Cwithout considering Cgd1gd1gd1gd1 is foundis foundis foundis found3. Gain from 3. Gain from 3. Gain from 3. Gain from iiiiinininin to vto vto vto vg1g1g1g1 is foundis foundis foundis found4. overall gain from v4. overall gain from v4. overall gain from v4. overall gain from vinininin to to to to vvvvoutoutoutout is found and results interpretedis found and results interpretedis found and results interpretedis found and results interpreted
2. admittance2. admittance2. admittance2. admittance YYYYgggg looking into gate of Qlooking into gate of Qlooking into gate of Qlooking into gate of Q1111 without considering Cwithout considering Cwithout considering Cwithout considering Cgd1gd1gd1gd1 is foundis foundis foundis found
3. Gain from3. Gain from3. Gain from3. Gain from iiiiinininin to vto vto vto vg1g1g1g1 is foundis foundis foundis found
(((( ))))ccccsssssbsbsbsbaaaa
GGGGggggCCCCCCCCssss
iiii
vvvv2222
1111ssss1111mmmmssss1111gsgsgsgs
inininin
1111gggg
++++++++++++++++++++
====
4. overall gain from v4. overall gain from v4. overall gain from v4. overall gain from vinininin totototo vvvvoutoutoutout is found and results interpretedis found and results interpretedis found and results interpretedis found and results interpreted
ωωωω0000 is the pole frequencyis the pole frequencyis the pole frequencyis the pole frequencyQ is the Q factorQ is the Q factorQ is the Q factorQ is the Q factor (((( )))) (((( )))) (((( ))))
22220000
2222
0000
ssssQQQQ
ssss1111
ssssNNNN0000AAAAssssAAAA
ωωωω++++
ωωωω++++
====
There is no peaking and the transfer functions maximum is at dc There is no peaking and the transfer functions maximum is at dc There is no peaking and the transfer functions maximum is at dc There is no peaking and the transfer functions maximum is at dc if:if:if:if:
707707707707....00002222////1111QQQQ ≅≅≅≅<<<<2222////1111QQQQ ====ωωωω0000 is the is the is the is the ----3dB frequency if:3dB frequency if:3dB frequency if:3dB frequency if:
eeee100100100100overshootovershootovershootovershoot %%%% −−−−ππππ−−−−====For the source follower:For the source follower:For the source follower:For the source follower: (((( ))))
Source follower circuits can exhibit large amounts of overshoot Source follower circuits can exhibit large amounts of overshoot Source follower circuits can exhibit large amounts of overshoot Source follower circuits can exhibit large amounts of overshoot under certainunder certainunder certainunder certainconditions. In practical conditions. In practical conditions. In practical conditions. In practical uE uE uE uE circuits the parasitic circuits the parasitic circuits the parasitic circuits the parasitic capacitances capacitances capacitances capacitances and the outputand the outputand the outputand the outputcapacitance results in only moderate overshoot for worstcapacitance results in only moderate overshoot for worstcapacitance results in only moderate overshoot for worstcapacitance results in only moderate overshoot for worst----case conditions.case conditions.case conditions.case conditions.
source followers can have complex poles and thus source followers can have complex poles and thus source followers can have complex poles and thus source followers can have complex poles and thus exhibit overshootexhibit overshootexhibit overshootexhibit overshoot
overshooting may be reduced by:overshooting may be reduced by:overshooting may be reduced by:overshooting may be reduced by: increasing increasing increasing increasing CCCCinininin or or or or CCCCssss or bothor bothor bothor both adding a adding a adding a adding a compensation networkcompensation networkcompensation networkcompensation network
(see Johns/Martin pp160(see Johns/Martin pp160(see Johns/Martin pp160(see Johns/Martin pp160----162)162)162)162)
MicroLab, vlsi26 (19/29)
JMM v1.2
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseCommonCommonCommonCommon----Gate AmplifierGate AmplifierGate AmplifierGate Amplifier
(see Johns/Martin pp160(see Johns/Martin pp160(see Johns/Martin pp160(see Johns/Martin pp160----162)162)162)162)
The frequency response of the commonThe frequency response of the commonThe frequency response of the commonThe frequency response of the common----gate stage gate stage gate stage gate stage is usually superior to that of the commonis usually superior to that of the commonis usually superior to that of the commonis usually superior to that of the common----source source source source stage due to the low impedance, stage due to the low impedance, stage due to the low impedance, stage due to the low impedance, rrrrinininin, at the source , at the source , at the source , at the source node, assuming Gnode, assuming Gnode, assuming Gnode, assuming GLLLL=(=(=(=(sCsCsCsCLLLL+g+g+g+gds2ds2ds2ds2)is not considerably )is not considerably )is not considerably )is not considerably smaller than gsmaller than gsmaller than gsmaller than gds1ds1ds1ds1....
(see Johns/Martin pp163)(see Johns/Martin pp163)(see Johns/Martin pp163)(see Johns/Martin pp163)
Both the Wilson and the cascode current mirrors Both the Wilson and the cascode current mirrors Both the Wilson and the cascode current mirrors Both the Wilson and the cascode current mirrors introduce highintroduce highintroduce highintroduce high----frequency poles into the signal frequency poles into the signal frequency poles into the signal frequency poles into the signal transfer function.transfer function.transfer function.transfer function.
The approximate time constant of these poles is The approximate time constant of these poles is The approximate time constant of these poles is The approximate time constant of these poles is CCCCgsgsgsgs/g/g/g/gmmmm, the roof of this statement can be found by , the roof of this statement can be found by , the roof of this statement can be found by , the roof of this statement can be found by doing highdoing highdoing highdoing high----frequency, smallfrequency, smallfrequency, smallfrequency, small----signal analysis.signal analysis.signal analysis.signal analysis.
IIIIinininin
QQQQ3333 QQQQ4444
rrrroutoutoutout
IIIIoutoutoutout
QQQQ1111 QQQQ2222
VVVVoutoutoutout IIIIinininin
QQQQ3333 QQQQ4444
rrrroutoutoutout
IIIIoutoutoutout
QQQQ1111 QQQQ2222
rrrrinininin
MicroLab, vlsi26 (21/29)
JMM v1.2
Frequency ResponseFrequency ResponseFrequency ResponseFrequency ResponseCascode Gain StageCascode Gain StageCascode Gain StageCascode Gain Stage
The exact highThe exact highThe exact highThe exact high----frequency analysis of a cascode gain frequency analysis of a cascode gain frequency analysis of a cascode gain frequency analysis of a cascode gain stage is usually left to simulation on a computer.stage is usually left to simulation on a computer.stage is usually left to simulation on a computer.stage is usually left to simulation on a computer.
at highat highat highat high----frequencies, the time constant due to the frequencies, the time constant due to the frequencies, the time constant due to the frequencies, the time constant due to the output node almost always dominates since the output node almost always dominates since the output node almost always dominates since the output node almost always dominates since the impedance is so large at that node:impedance is so large at that node:impedance is so large at that node:impedance is so large at that node: CCCCoutoutoutout=(C=(C=(C=(Cgd2gd2gd2gd2+C+C+C+Cdb2db2db2db2)+C)+C)+C)+CLLLL++++CCCCbiasbiasbiasbias
CCCCLLLL is normally the major contributoris normally the major contributoris normally the major contributoris normally the major contributor
IIIIbiasbiasbiasbias
QQQQ1111
QQQQ2222
VVVVoutoutoutoutVVVVbiasbiasbiasbias
VVVVinininin
CCCCLLLL
LLLLmmmm
2222
LLLLoutoutoutoutdBdBdBdB3333 CCCCgggg
gggg2222
CCCCRRRR1111 dsdsdsds≅≅≅≅≅≅≅≅ωωωω−−−−
MicroLab, vlsi26 (22/29)
JMM v1.2
Cascode Gain StageCascode Gain StageCascode Gain StageCascode Gain Stage((((con’t con’t con’t con’t 1)1)1)1)
ZeroZeroZeroZero----value time constant analysis method usedvalue time constant analysis method usedvalue time constant analysis method usedvalue time constant analysis method used
All independent sources have to be set to zero All independent sources have to be set to zero All independent sources have to be set to zero All independent sources have to be set to zero (v(v(v(vinininin=0)=0)=0)=0)
MicroLab, vlsi26 (23/29)
JMM v1.2
Cascode Gain StageCascode Gain StageCascode Gain StageCascode Gain Stage((((con’t con’t con’t con’t 2)2)2)2)
nodes vnodes vnodes vnodes vg1g1g1g1,v,v,v,vs2s2s2s2 the capacitor Cthe capacitor Cthe capacitor Cthe capacitor Cgd1gd1gd1gd1 is replaced by a voltage source is replaced by a voltage source is replaced by a voltage source is replaced by a voltage source vvvvxxxx in order in order in order in order to calculate the input resistance seen from that node.to calculate the input resistance seen from that node.to calculate the input resistance seen from that node.to calculate the input resistance seen from that node.
admittance looking into the sourceadmittance looking into the sourceadmittance looking into the sourceadmittance looking into the sourceof a cascode transistor is Yof a cascode transistor is Yof a cascode transistor is Yof a cascode transistor is Ys2s2s2s2
MicroLab, vlsi26 (24/29)
JMM v1.2
Cascode Gain StageCascode Gain StageCascode Gain StageCascode Gain Stage((((con’t con’t con’t con’t 3)3)3)3)
2222ssss1111dsdsdsds1111dddd YYYYggggGGGG ++++====admittance looking into the sourceadmittance looking into the sourceadmittance looking into the sourceadmittance looking into the sourceof a cascode transistor is Yof a cascode transistor is Yof a cascode transistor is Yof a cascode transistor is Ys2s2s2s2 vvvvoutoutoutoutggggm2m2m2m2vvvvs2s2s2s2
(see cascode current mirror (see cascode current mirror (see cascode current mirror (see cascode current mirror impedance, pp137, impedance, pp137, impedance, pp137, impedance, pp137, vlsivlsivlsivlsi----25/17)25/17)25/17)25/17)
(((( ))))ininininmmmmdsdsdsds
1111gdgdgdgd1111CgdCgdCgdCgd RRRRgggg11112222rrrr
CCCC ++++≅≅≅≅ττττ
2222rrrrgggg
CCCC2222dsdsdsdsmmmm
1111gdgdgdgd1111CgdCgdCgdCgd ≅≅≅≅ττττ for for for for RRRRinininin is large and equal is large and equal is large and equal is large and equal rrrrdsdsdsds
MicroLab, vlsi26 (25/29)
JMM v1.2
Cascode Gain StageCascode Gain StageCascode Gain StageCascode Gain Stage((((con’t con’t con’t con’t 4)4)4)4)
node vnode vnode vnode vs2s2s2s2 the resistance seen by the capacitor Cthe resistance seen by the capacitor Cthe resistance seen by the capacitor Cthe resistance seen by the capacitor Cs2s2s2s2 is ris ris ris rds1ds1ds1ds1 in in in in paralell paralell paralell paralell with the impedance seen looking in the source of Qwith the impedance seen looking in the source of Qwith the impedance seen looking in the source of Qwith the impedance seen looking in the source of Q2222 which which which which is approximately is approximately is approximately is approximately rrrrdsdsdsds, thus:, thus:, thus:, thus:
2222rrrr
CCCC dsdsdsds2222ssss2222CsCsCsCs ≅≅≅≅ττττ
node node node node vvvvoutoutoutout
2222
rrrrggggCCCC
2222mmmm
2222dddd2222CdCdCdCddsdsdsds≅≅≅≅ττττ
The resistance seen by CThe resistance seen by CThe resistance seen by CThe resistance seen by Cd2d2d2d2 is the output impedance of theis the output impedance of theis the output impedance of theis the output impedance of thecascode amplifier, thus:cascode amplifier, thus:cascode amplifier, thus:cascode amplifier, thus:
Cascode Gain StageCascode Gain StageCascode Gain StageCascode Gain StageCommentsCommentsCommentsComments
High frequencies considerationsHigh frequencies considerationsHigh frequencies considerationsHigh frequencies considerations
IIIIbiasbiasbiasbias
QQQQ1111
QQQQ2222
VVVVoutoutoutoutVVVVbiasbiasbiasbias
VVVVinininin
CCCCLLLL
(((( ))))dBdBdBdB3333
vvvv
////ssss1111AAAA
ssssAAAA−−−−ωωωω++++
====
(((( ))))LLLL
1111mmmm
dBdBdBdB3333
vvvv
sCsCsCsCgggg
////ssssAAAA
ssssAAAA −−−−≅≅≅≅ωωωω
≅≅≅≅−−−−
one pole dominates, thus the gain is:one pole dominates, thus the gain is:one pole dominates, thus the gain is:one pole dominates, thus the gain is:
at frequencies substantial larger than at frequencies substantial larger than at frequencies substantial larger than at frequencies substantial larger than ωωωω----3dB3dB3dB3dB::::
upper limit of the unityupper limit of the unityupper limit of the unityupper limit of the unity----gain frequency of an gain frequency of an gain frequency of an gain frequency of an amplifier that uses a cascode gain stage is limited amplifier that uses a cascode gain stage is limited amplifier that uses a cascode gain stage is limited amplifier that uses a cascode gain stage is limited by source node of Qby source node of Qby source node of Qby source node of Q2222::::
22222222
2222effeffeffeffpppp
2222ssss2222pppp LLLL2222
VVVV33331111 µµµµ>>>>
ττττ====ωωωω
MicroLab, vlsi26 (27/29)
JMM v1.2
Coming Up...Coming Up...Coming Up...Coming Up...
Next topic…Next topic…Next topic…Next topic… BasicBasicBasicBasic OpAmpOpAmpOpAmpOpAmp design and compensationdesign and compensationdesign and compensationdesign and compensation
Readings for next time…Readings for next time…Readings for next time…Readings for next time… Johns&MartinJohns&MartinJohns&MartinJohns&Martin: Sections 3.11: Sections 3.11: Sections 3.11: Sections 3.11
Exercises: Exercises: Exercises: Exercises: Have a look at the exercises in Have a look at the exercises in Have a look at the exercises in Have a look at the exercises in Johns&MartinJohns&MartinJohns&MartinJohns&Martin....
Johns&Martin chap 3.11 pp156: 3.8 (difficulty: easy):Johns&Martin chap 3.11 pp156: 3.8 (difficulty: easy):Johns&Martin chap 3.11 pp156: 3.8 (difficulty: easy):Johns&Martin chap 3.11 pp156: 3.8 (difficulty: easy):Consider the commonConsider the commonConsider the commonConsider the common----source amplifier shown on source amplifier shown on source amplifier shown on source amplifier shown on transparency transparency transparency transparency vlsivlsivlsivlsi----26/6 where26/6 where26/6 where26/6 where IIIIinininin=100=100=100=100µµµµA and all A and all A and all A and all transistors have W=100transistors have W=100transistors have W=100transistors have W=100µµµµm and L=1.6m and L=1.6m and L=1.6m and L=1.6µµµµm. Givenm. Givenm. Givenm. GivenRRRRinininin=180k=180k=180k=180kΩ,Ω,Ω,Ω, CCCCLLLL=0.3pF=0.3pF=0.3pF=0.3pF,,,, CCCCgs1gs1gs1gs1=0.2pF=0.2pF=0.2pF=0.2pF,,,, CCCCgd1gd1gd1gd1=15fF=15fF=15fF=15fF,,,,CCCCdb1db1db1db1=20fF=20fF=20fF=20fF,,,, CCCCdb2db2db2db2=36fF=36fF=36fF=36fF,,,, µµµµnnnnCCCCoxoxoxox=90=90=90=90µµµµA/VA/VA/VA/V2222,,,,µµµµppppCCCCoxoxoxox=30=30=30=30µµµµA/VA/VA/VA/V2222, and, and, and, and rrrrdsdsdsds----nnnn=8000 [L (=8000 [L (=8000 [L (=8000 [L (µµµµm)]/[ID m)]/[ID m)]/[ID m)]/[ID ((((mAmAmAmA)],)],)],)], rrrrdspdspdspdsp=12000 [L (=12000 [L (=12000 [L (=12000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. )]. )]. )]. Estimate the 3db frequency response. Estimate the 3db frequency response. Estimate the 3db frequency response. Estimate the 3db frequency response.
Johns&Martin chap 3.11 pp160: 3.9 (difficulty: easy):Johns&Martin chap 3.11 pp160: 3.9 (difficulty: easy):Johns&Martin chap 3.11 pp160: 3.9 (difficulty: easy):Johns&Martin chap 3.11 pp160: 3.9 (difficulty: easy):Analyse Analyse Analyse Analyse the source follower and assume that the source follower and assume that the source follower and assume that the source follower and assume that IIIIbiasbiasbiasbias=100=100=100=100µµµµA and all transistors have W=100A and all transistors have W=100A and all transistors have W=100A and all transistors have W=100µµµµm m m m and L=1.6and L=1.6and L=1.6and L=1.6µµµµm. Givenm. Givenm. Givenm. Given RRRRinininin=180k=180k=180k=180kΩ,Ω,Ω,Ω, CCCCLLLL=10pF=10pF=10pF=10pF,,,,CCCCgs1gs1gs1gs1=0.2pF=0.2pF=0.2pF=0.2pF,,,, CCCCgd1gd1gd1gd1=15fF=15fF=15fF=15fF,,,, CCCCsb1sb1sb1sb1=40fF=40fF=40fF=40fF,,,, CCCCinininin=30fF=30fF=30fF=30fF,,,,µµµµnnnnCCCCoxoxoxox=90=90=90=90µµµµA/VA/VA/VA/V2222,,,, µµµµppppCCCCoxoxoxox=30=30=30=30µµµµA/VA/VA/VA/V2222, and, and, and, and rrrrdsdsdsds----
nnnn=8000 [L (=8000 [L (=8000 [L (=8000 [L (µµµµm)]/[ID (m)]/[ID (m)]/[ID (m)]/[ID (mAmAmAmA)]. Find )]. Find )]. Find )]. Find ωωωω0000, Q, and , Q, and , Q, and , Q, and ωωωωzzzz of the source follower. of the source follower. of the source follower. of the source follower.
Johns&Martin chap 3.11 pp166:3.11 (difficulty: easy):Johns&Martin chap 3.11 pp166:3.11 (difficulty: easy):Johns&Martin chap 3.11 pp166:3.11 (difficulty: easy):Johns&Martin chap 3.11 pp166:3.11 (difficulty: easy):Assume that for the input transistors and the Assume that for the input transistors and the Assume that for the input transistors and the Assume that for the input transistors and the cascode transistors, gcascode transistors, gcascode transistors, gcascode transistors, gmmmm=1mA/V, =1mA/V, =1mA/V, =1mA/V, rrrrdsdsdsds=100k=100k=100k=100kΩΩΩΩ, , , , RRRRinininin=180k=180k=180k=180kΩ,Ω,Ω,Ω, CCCCLLLL=5pF=5pF=5pF=5pF,,,, CCCCgsgsgsgs=0.2pF=0.2pF=0.2pF=0.2pF,,,, CCCCgdgdgdgd=15fF=15fF=15fF=15fF,,,,CCCCsbsbsbsb=40fF=40fF=40fF=40fF,,,, CCCCdbdbdbdb=20fF=20fF=20fF=20fF,,,, CCCCbiasbiasbiasbias=20fF=20fF=20fF=20fF,,,, Estimate the Estimate the Estimate the Estimate the ----dB frequency of the cascode amplifier (transparency dB frequency of the cascode amplifier (transparency dB frequency of the cascode amplifier (transparency dB frequency of the cascode amplifier (transparency 19). 19). 19). 19).
Johns&Martin chap 3.11 pp168: 3.12 (difficulty: easy):Johns&Martin chap 3.11 pp168: 3.12 (difficulty: easy):Johns&Martin chap 3.11 pp168: 3.12 (difficulty: easy):Johns&Martin chap 3.11 pp168: 3.12 (difficulty: easy):Estimate the lower bound on the frequency of the Estimate the lower bound on the frequency of the Estimate the lower bound on the frequency of the Estimate the lower bound on the frequency of the second pole of a foldedsecond pole of a foldedsecond pole of a foldedsecond pole of a folded----cascode amplifier for a cascode amplifier for a cascode amplifier for a cascode amplifier for a 0.80.80.80.8µµµµm technology, where a typical value of 0.25V m technology, where a typical value of 0.25V m technology, where a typical value of 0.25V m technology, where a typical value of 0.25V is chosen for Vis chosen for Vis chosen for Vis chosen for Veff2eff2eff2eff2. L. L. L. L2222=1.5L=1.5L=1.5L=1.5Lminminminmin, , , , µµµµpppp=0.02m=0.02m=0.02m=0.02m2222/Vs. /Vs. /Vs. /Vs.
Analog MicroelectronicsBasic OpAmp Design and Compensation
Today’s handouts:(1) Lecture Slides
MicroLab, vlsi27 (2/34)
JMM v1.0
Outline
u Johns&MartinuMOS differential pair and gain stage (chap 3.8)u two-stage CMOS OpAmp (chap 5.1)
u gainu frequency responseu systematic offset voltageu n- or p-channel input stage
u feedback and OpAmp compensation (chap 5.2)u first-order model of closed loop-amplifieru linear settling timeu OpAmp compensationu compensation of two-stage OpAmpu lead compensationu making compensation independent of process and tempu biasing OpAmp to have stable transconductance
u Exercises (5.3-5.5)u hand calculationsu spice simulations
MicroLab, vlsi27 (3/34)
JMM v1.0
MOS Differential Pair and Gain Stage
u most integrated amplifiers have differential input, realized with a differential transistor pair
Ibias
Q1 Q2
V+
ID2
V-
ID2
u a low-frequency small-signal equivalent circuit is based on the T model for the MOS transistor
rs1
v+is2
v-
id2=is2
rs2
id1=is1
is1
gate current is zero in T model
MicroLab, vlsi27 (4/34)
JMM v1.0
MOS Differential Pair (con’t 1)
to simplify analysis the output impedance of the transistor is ignored
−+ −≡ vvv in
Definition:
2m1m
in
2s1s
in1s1d g/1g/1
vrr
vii+
=+
==
since both Q1 and Q2 have the same bias currents, gm1=gm2
in1m
1d v2
gi =
rs1
v+is2
v-
id2=is2
rs2
id1=is1
is1
is1
in1m
2d v2
gi −=
2d1dout iii −≡Definition:
in1mout vgi =thus:
MicroLab, vlsi27 (5/34)
JMM v1.0
MOS Differential Pair (con’t 2)
If a differential pair has a current mirror as an active load, a completedifferential-input, single-ended-output gain stage can be realized.
Ibias
Q1 Q2vin
id4is1
Q4 routQ3
vout
is1+
-
to simplify analysis the output impedance of the transistor is ignored
1s3d4d iii −==
1s2d ii −=and
( ) inout1mout1sout4d2dout vrgri2riiv ==−−=
this result assumes that the output impedance is purely resistive, if thereis also a capacitive load CL we get:
out1mv zgA = ( )Loutout sC/1rz =where
Thus, for this differential stage, a very simple model is used. This model implicitlyassumes that the time constant at the outputnode is much larger than the time constantdue to the parasitic capacitances at Q1 and Q2
vout
vin
+
-gm1vin rout CL
zout
MicroLab, vlsi27 (6/34)
JMM v1.0
MOS Differential Pair (con’t 3)
The evaluation of the output resistance rout is determined by using thesmall-signal equivalent circuit and applying a voltage at the output node.Note that the T-model is used for Q1, Q2 and Q3, and the the hybrid-πmodel is used for Q4.
Ibias
Q1 Q2vin
id4is1
Q4 routQ3
vout
is1+
-
x
xout i
vr ≡
( )4ds2ds1mv rrgA =
4ds2dsout rrr =
rs1
is1
is1 rds1 rs2
is2
is2rds2
vx +-
is5 ix1 ix4 ix
ix3ix2
rds4rds3//rs3
gm4vava
+
-
MicroLab, vlsi27 (7/34)
JMM v1.0
MOS Differential Pair (con’t 4)
The evaluation of the large signal amplification is determined by using thelarge-signal transistor model in the active region of the fets.Note that the T-model is used for Q1, Q2 and Q3, and the the hybrid-πmodel is used for Q4.
( )2tnGS
ox0D VV
LW
2CI −
µ=
Ibias
Q1 Q2VIN
ID4IS1
Q4 IoutQ3
Vout
ID2+
-
ID1
2bias
4IN
2
bias
2IN
bias2D1DOUT I4V
IVIIII β
−β
=−=
( )2tnGSD VV
2I −
β=
-1.5
-1
-0.5
0
0.5
1
1.5
-3 -2 -1 0 1 2 3
bias
OUT
II
2
b i a sI D I/V β
4.5I/ b i a s =βtypical value for Ibias=0.1mA: mV187VIN =
MicroLab, vlsi27 (8/34)
JMM v1.0
Two-Stage CMOS OpAmp
u Basic OpAmp design are discussedu OpAmp gainu frequency responseu slew rateu systematic offset voltageu n-channel or p-channel input stage
-A2 1A1-
+
CC
Vin Vout
second gain stage
differentialinput stage
outputbuffer
singleended output e.x. common-source
gain stage withactive load
capacitor ensures stability when OpAmp
is used in feedbackCC is often calledMiller capacitanceto illustrate itseffect on input
output gain stage only present when resistive loads need to be driven
MicroLab, vlsi27 (9/34)
JMM v1.0
CMOS realization of a two-stage OpAmp
bias circuit differential inputfirst stage
common sourcesecond stage
outputbuffer
u p-channel input stageu all transistor lengths are 1.6µm (1µm process)u reasonable sizes for lengths of the transistors might be somewhere
between 1.5 and 2 times the minimum transistor length
p-well processnecessary
Q1 Q2Vin
-
Q4Q3
Vin+
Q15 Q13
Q12Q14
Q10
Q11 Q525 25
25 25
100 25
300
300 300
150 150
Rb
Q7
300 500
Q6
Q8
300
Q9
Q16CC
Vout
VDD
VSS
500
MicroLab, vlsi27 (10/34)
JMM v1.0
Two-Stage OpAmpGain
u overall gain for low frequency application is the most critical parameter of an OpAmp
( )4111 dsdsmv rrgA =
222
11
11
biasoxpDoxpm
IL
WCI
LW
Cg
=
= µµ
tiDGiDi
idsi VV
IL
r +≅ α
gain of the first stage(differential stage)
approximation to the finite outputresistance, where a is technology dependent parameter: 5e-6 V1/2/mignoring short channel effects
gain of the second stage(common-source stage)
( )7672 dsdsmv rrgA −=
989
93
dsdsmL
mv gggG
gA
+++=gain of the third stage
(common-drain stage)
9889
93
dsdssmL
mv ggggG
gA
++++=gain of the third stage
with body effect (bulknot connected to source)
FSB
ms V
gg
φγ
22 +=body effect constant γ=0.5V1/2
2φF=0.7V
MicroLab, vlsi27 (11/34)
JMM v1.0
Two-Stage OpAmpFrequency Response
u frequency response where capacitor Cc causes the magnitude of the gain to decrease, but still well below unity gain frequency (open-loop gain = 1)
ð midband frequencyu only compensation capacitor CC repsectedu assume Q16 is not present (resistor for lead
compensation, effect only at unity gain frequency)u discuss simplified circuit:
Q1 Q2vin-
Q4Q3
vin+
Q5300
300 300
150 150
Vbias
CC
-A2 A3 vout
v1 v2
i=gm1 vin
( )C
mv sC
gsA 1≅
C
mta C
g 1≅ω
midband gain
untity gain frequency
MicroLab, vlsi27 (12/34)
JMM v1.0
Two-Stage OpAmpSlew Rate
u slew rate SR is the maximum rate the output changes when input signals are large
u at slew rate limitation all current of Q5 goes either in Q1 or Q2
ð this current has to go through CC
maxdtdv
SR out≡
taeffC
D VCI
SR ω112
==
increasing Veff1 and ω ta increases SRp-channel fet inputs increases SRincreasing Veff1 reduces transconductance gm1
Q1 Q2vin-
Q4Q3
vin+
Q5300
300 300
150 150
Vbias
CC
-A2 A3 vout
v1 v2
I
MicroLab, vlsi27 (13/34)
JMM v1.0
Two-Stage OpAmpSystematic Offset Voltage Cancelation
u two-stage OpAmps may have a systematic input offset voltage if not properly designedu the differential input is zero: vin
+= vin-
u ID6 = ID7, which requires a well defined VGS7 value
( )( )
( )( )5
6
4
7 2LWLW
LWLW
//
//
=
Q1 Q2Vin
-
Q4Q3
Vin+
Q5300
300 300
150 150
Q7
300
Q6300
Vout
VDD
Vbias
MicroLab, vlsi27 (14/34)
JMM v1.0
Two-Stage OpAmpn- or p- channel input stage
u comparison between n- and p-channel input stage OpAmpsu overal dc gain is largely unaffected since both designs
have one stage with n-channel and one stage with one or more p-channel driving fets.
u for a given power dissipation, and therefore bias current, having a p-channel input-pair stage maximizes the slew rate.
u having a p-channel input first stage implies that the second stage has an n-channel input drive fet. This arrangement maximizes the transconductance of the drive fet of teh 2nd stage, which is critical when high frequency operation is important.
u output stage: n-channel source follower is preferable because this will have less of a voltage drop (if separate p-well is used). Its higher transconductance reduces the effect of the load cap on the second pole. There is also less degradation on the gain when small load resistances are being driven.
ð p-channel input fets for the first stage is almost always the best choice
MicroLab, vlsi27 (15/34)
JMM v1.0
Feedback and OpAmp Compensation
u OpAmps in closed-loop configurations are discussed and how to compensate an OpAmp to ensure that the closed-loop configuration is not only stable but has a good settling characteristic.
u Optimum compensation of OpAmps is typically considered to be one of the most difficult parts in the OpAmp design procedure.u first-order model of closed-loop amplifieru linear settling timeu OpAmp compensationu compensating the two-stage OpAmpu lead compensationumaking compensation independent of process and
temperatureu biasing an OpAmp to have stable transconductances
MicroLab, vlsi27 (16/34)
JMM v1.0
First Order Model of Closed-Loop Amplifier
u First order model of transfer function of a dominant-pole compensated OpAmp:
( ) ( )1
0
1 psA
sAω/+
= real axisdominant pole
( )1
01pta
taA
jAωω
ω/
≅≡
10 pta A ωω ≅
( )s
sA taω≅
+ A(s)
β-
Ain(s) Aout(s)
( ) ( )( )sA
sAsACL β+
=1
( ) ( )taCL s
sAβωβ /+
=1
11
gain
unity gain frequency definition
unity gain frequency of first order OpAmp model
for midband frequencies tap ωωω <<<<1
closed-loop gain
tadB βωω ≅−3
MicroLab, vlsi27 (17/34)
JMM v1.0
Linear Settling Time
u the settling time performance is an important design parameter of OpAmpsu the charge transfer in SC circuits is closely related to
OpAmps step responseu settling time is defined as the time it takes for an
OpAmp to reach a specified percentage of its final value when a step input is applied
u linear settling time portion is due to the finite unity gain frequency (independent on output step size)
u nonlinear settling time portion is due to the slew rate limit (dependent on output step size)
ð unity gain frequency estimation for linear settling time portion
( ) ( )τ/tstepout eVtv −−= 1
tadB βωωτ
11
3
==−
( )τstep
tout
Vtv
dtd
==0
-3dB frequency determines the settling-time response for s step input
step response for a closed-loop OpAmp
if slew rate is larger,no SR limit will occur
MicroLab, vlsi27 (18/34)
JMM v1.0
OpAmp Compensation(second order model)
u for compensating OpAmps the first order model is insufficient, because it ignores poles and zeros at high frequencies which may cause instabilities.
u a more accurate open-loop transfer model adds one additional pole (real axis poles and zeros):
( ) ( )( )eqp ssA
sAωω // ++
=11 1
0
first dominant pole higher frequency poles
uωeq may be approximated with a set of real-axis poles and zeros:
∑∑==
−≅n
i zi
m
i pieq 12
111ωωω
u phase margin PM is an often used measure how far an OpAmp with feedback is from becoming unstable
( )eqttjLGPM ωωω /tan)()( 190180 −−=−−∠≡ oo
( ) eqt PM ωω −= o90tan
( ) ( )eqjLG ωωω /tan 190 −−−=∠ o
independent of β
unity gain of LG
MicroLab, vlsi27 (19/34)
JMM v1.0
OpAmp Compensation(second order model con’t)
u Closed-loop gain if β is frequency independent (if ωt is far away from high frequency poles and zeros)
( ) ( )0
2
0
1
0
1111
1A
sA
sA
sAeqp
CLCL
ββωω
++
++
+=
//
ββ1
1 0
00 ≅
+=
AA
ACL
u General equation for a second order transfer function:
( )20
22
1ωωs
QsK
sH
o
++=
u comparing:( )( ) eqtaeqpA ωβωωωβω ≅+= 100 1
( )( )eq
ta
eqp
eqpAQ
ωβω
ωω
ωωβ≅
+
+=
// 11
1
1
10
14 2
100 −
−
= Q
π
overshoot %
MicroLab, vlsi27 (20/34)
JMM v1.0
OpAmp Compensation(2nd order transfer function)
u Relationship between Q factor and phase marginu transfer function: Q=sqrt(1/2):
u no peakingu widest passbandu ω0 = ω-3dB
u step response: Q<=0.5 (real poles and zeros)u no peaking
u step response: Q > 0.5u percentage of overshoot to be calculated
u Phase margin is much larger than supposed to be necessary (80 to 85)
MicroLab, vlsi27 (21/34)
JMM v1.0
Compensating the Two-Stage OpAmp
u Capacitor CC realizes dominant-pole compensation and thereby control ωp1 and ωta :
u fet Q16 is included to realize a left-half-plane zero at frequencies around or slightly above ωt (lead-compensation). Q16 has Vds=0V and thus is in triode region:
Q1 Q2Vin
-
Q4Q3
Vin+
Q5300
300 300
150 150
Q7
300
Q6300
Vout2
VDD
Vbias
Q16
Vbias CC
10 pta A ωω =
1616
161
effoxn
dsC
VL
WCrR
==µ
MicroLab, vlsi27 (22/34)
JMM v1.0
Compensating the Two-Stage OpAmpsmall-signal model
u simplified small-signal model of two-stage OpAmp for compensation analysis
gm7v1
R1C2R2
C1
CCv1
gm1vin1
RC vout2
241 dsds rrR =
762 dsds rrR =7421 gsdbdb CCCC ++=
2672 Ldbdb CCCC ++=
Cmp CRRg 2171
1≅ω
21
72 CC
gmp +
≅ω
C
mz C
g 7−=ω
( )CmCz RgC −
−=
711
/ω
analysis shown in Johns&Martin
dominant pole: nondominant pole:
for RC=0:
lead compemsation(RC not zero)
MicroLab, vlsi27 (23/34)
JMM v1.0
Compensating the Two-Stage OpAmp(discussion)
u increasing gm7 separates poles (pole-splitting)u however, right-hand plane zero introduces negative
phase shift into transfer functionu increasing CC moves ωp1 and ωz1 to low frequency
and thus does not help
RR
II
1pω2pω zω
gm7
CCCC
+
+=
21
11pp
sssD
ωω)(
Cmp CRRg 2171
1≅ω
21
72 CC
gmp +
≅ω
C
mz C
g 7−=ω
MicroLab, vlsi27 (24/34)
JMM v1.0
Compensating the Two-Stage OpAmp(lead compensation)
u with a non-zero RC, a third pole is introduced, but is at high frequency and has almost no effect
u However the zero opens a number of possibilities:
u one could eliminate the right-half plane zero:
u one could choose RC to be even larger and thus move the right-half-plane zero into the left half plane to cancel the nondominant pole ωp2:
u one could choose RC even larger to move the now left-half-plane zero to a frequency slightly greater than the unity-gain frequency that would result without the resistor - say 20% larger (recommended):
( )CmCz RgC −
−=
711
/ω
71 mC gR /=
++=
CmC C
CCg
R 21
7
11
1211
mC g
R.
≅tz ωω 21.=
MicroLab, vlsi27 (25/34)
JMM v1.0
Lead CompensationDesign Procedure
Start by choosing, somewhat arbitrarily,Using Spice, find the frequency at which a -125°
phase shift exists. Let the gain at this frequency be denoted A’ and ωt.Choose a new CC so that ωt becomes the unity-gain
frequency of the loop gain, thus resulting in a 55° phase margin. This can be achieved by taking CCaccording to the equation (iterations possible):
Choose RC according:
The resulting phase margin is approximately 85° (leaving 5° for process variations). It may be neces-sary to iterate on RC to optimize the phase marginIf after step 4 the phase margin is not adequate, then
increase CC while leaving RC constantReplace RC by a fet with the following size:
pF' 5≅CC
'' ACC CC =
CtC C
Rω211
.=
1616
161
effoxn
dsC
VL
WCrR
==µ
MicroLab, vlsi27 (26/34)
JMM v1.0
Compensation Independent of Process and Temperature
u Making lead compensation process and temperature insensitive
u the ratios of all transconductances remain relatively constant over process and temperature variations as all fets depend on the same biasing network:
u when a resistor is used to realize lead compensation, RC can also be made to track the inverse of transconductance (1/gm7), and thus the lead compensation will be mostly independent of process and temperature variantions:
( )CmCz RgC −
−=
711
/ω
21
72 CC
gmp +
≅ωC
mta C
g 1≅ω
MicroLab, vlsi27 (27/34)
JMM v1.0
Compensation Independent of Process and Temperature (con’t 2)
1616
161
effoxn
dsC
VL
WCrR
==µ
( ) 777 effoxnm VLWCg /µ=
Making RC proportional to 1/gm7
The product RC 1/gm7 needs to be constant
( )( ) 1616
777
eff
effmC VLW
VLWgR
/
/=
Therefor, all that remains is to ensure that Veff16/Veff7 is independent of process and temperature variations. The ratio can be made constant by deriving Vgs16 from the same biasing circuit used to derive Vgs7
u The following approach results in the possibility of on-chip “resistors”, realized by using triode-region fets that are accurately ratioed with respect to a single off-chip resistor -> modern µcircuit design
MicroLab, vlsi27 (28/34)
JMM v1.0
Compensation Independent of Process and Temperature (con’t 3)
if
Q7
300
Q6
Q16
Vb
CC
Q13
Q12
Q1125
25
25
Vbias
Va
713 effeff VV =
then ba VV =then (gates connected)
1216 effeff VV =
thus12
13
16
7
eff
eff
eff
eff
V
V
V
V=
to make 713 effeff VV = we need
( ) ( )13
13
7
7 22LWC
ILWC
I
oxn
D
oxn
D
// µµ=
( )( )13
7
13
7
LWLW
II
D
D
//
= however the current is set by Q6, Q11
( )( )11
6
13
7
LWLW
II
D
D
//
=
( )( )
( )( )13
11
7
6
LWLW
LWLW
//
//
=
as ID12=ID13 are equal ( )( )
( )( )13
12
16
77 LW
LWLWLW
gR mC //
//
=
condition to be satisfied
MicroLab, vlsi27 (29/34)
JMM v1.0
Biasing an OpAmp to Have Stable Transconductances
u Fet transconductances are the probably the most important parameters in OpAmps to be stabilized
u the following approach matches transconductances to conductance of a resistor
u as a result, the fet transconductances are independent of power-supply voltage as well as process and temperature variations
Q15 Q13
Q12Q14
Q10
Q1125 25
25 25
100 25
Rb
( ) ( )1110 LWLW // =assuming
( )( )
bm R
LWLW
g
−
= 15
13
13
12//
( ) ( )1315 4 LWLW // =for
bm R
g1
13 =
( )( ) 13
1313m
Dn
Diiimi g
ILWILW
g ×=//
µµ
MicroLab, vlsi27 (30/34)
JMM v1.0
Exercises VLSI-27
Ex ana3.9 (difficulty: easy): Consider a differential pair amplifier shown on transparency vlsi-27/3 where Ibias=200µA and all transistors have W=100µm and L=1.6µm. GivenµnCox=92µA/V2 and rds-n=8000 [L (µm)]/[ID (mA)]. Find the output impedance and the gain.
Result: Av =68.6V/V, rout=64kΩ (see Johns/Martin pp146)
Ex ana5.1 (difficulty: easy): Find the gain of theOpAmp shown on transparency vlsi-27/9. Assume ID5=100µA, first stage VDG=0.5V, 2nd and 3rd stage VDG=1V and bulk of Q8 connected to VSS. Given µnCox =3µpCox=96µA/V2, VDD=-VSS=2.5V, RL=10kΩ, γ=0.5V1/2, φF=0.35V, α=5e6V1/2/m, Vtn=- Vtn=0.8V.
Result: Av =-6092V/V (see Johns/Martin pp224)
MicroLab, vlsi27 (31/34)
JMM v1.0
Exercises VLSI-27 (con’t 2)
Ex ana5.2 (difficulty: easy): Find the unity gain frequency of the OpAmp shown on transparency vlsi-27/9, with CC=5pF . Assume ID5=100µA, first stage VDG=0.5V, 2nd and 3rd stage VDG=1V and bulk of Q8 connected to VSS. Given µnCox=3µpCox=96µA/V2, VDD=-VSS=2.5V, RL=10kΩ, γ=0.5V1/2, φF=0.35V, α=5e6V1/2/m, Vtn=- Vtn=0.8V.
Result: fta = 24.7MHz (see Johns/Martin pp227)
Ex ana5.3 (difficulty: easy): Find the slew rate of OpAmp on transparency vlsi-27/9, with CC=5pF . Assume ID5=100µA. What circuit chane could be done to double the slew rate but to keep ωta and bias currents unchanged?
Result: SR = 20V/µs, to double SR: CC=2.5pF and W1= W2= 75µm (see Johns/Martin pp229)
MicroLab, vlsi27 (32/34)
JMM v1.0
Exercises VLSI-27 (con’t 3)
Ex ana5.4 (difficulty: easy): Consider the OpAmpshown on transparency vlsi-27/9, where Q3 qnd Q4are each changed to widths of 120µm and we want the output stage have a bias current of 150µA. Find the new sizes of Q6 qnd Q7 such that there is no systematic offset voltage.
Ex ana5.5 (difficulty: easy): One phase of an SC circuit is shown, where the input can be modelled as a voltage step. If 0.1% accuracy is needed in the linear settling-time portion corresponding to 100ns, find the required unity-gain frequency in terms of the capacitance values, C1 and C2 and in absolute values. For C2=10C1 and for C2=0.2C1.
Result: fta = 12.1MHz, fta = 66.0MHz, (see Johns/Martin pp235)
+
-+
C1C2
voutA(s)
MicroLab, vlsi27 (33/34)
JMM v1.0
Exercises VLSI-27 (con’t 4)
Ex ana5.7 (difficulty: medium): OpAmp has an open-loop transfer function given by:
Assume that ω2=2π 50MHz and A0=104
a) Assuming ωz=inf, find ωp1 and the unity-gain frequency ωt‘ so that the OpAmp has a unity-gain phase margin of 55°
b) Assuming ωz=1.2 ωt‘ (use ωt‘ from a), what is the unity-gain frequency ωt. Also find the new phase margin.
Result: a) ωt‘=2π 35MHz, ωp1=2π 4.27kHz, b) ωt=2π 46.6MHz, PM= -85° (see Johns/Martin pp245)
( ) ( )( )( )21
0
111
ωωω
///
sssA
sAp
z
+++
=
MicroLab, vlsi27 (34/34)
JMM v1.0
Coming Up...
u Next topic… Advanced Current Mirrors and OpAmps
u Readings for next time… Johns&Martin: Sections 3.8 and 5
u Exercises: Have a look at the exercises in Johns&Martin.
MicroLab, vlsi28 (1/12)
JMM v1.0
Analog MicroelectronicsAdvanced Current Mirrors and OpAmp Design
Today’s handouts:(1) Lecture Slides
MicroLab, vlsi28 (2/12)
JMM v1.0
Outline
u Johns&Martinu advanced current mirrors (chap 6.1)
u wide-swing current mirrorsu wide-swing constant-transconductance bias circuitu enhanced output-impedance current mirrors (not yet)u wide-swing current mirror with enhanced output
impedance (not yet)
u folded-cascode OpAmp (chap 6.2)u small signal analysisu slew rate
u Exercises (6.8 & 6.10)u spice simulationsu problems
MicroLab, vlsi28 (3/12)
JMM v1.0
Advanced current mirrorswide-swing current mirrors
u The classical two-stage OpAmp was dicussed in vlsi27.
u Recently a number of alternate OpAmps designs have been gaining in popularity. They make use of more advanced current mirrors.
u Wide-swing current mirror:u as shorter channel lengths are used, it becomes more
difficult to achieve reasonable OpAmp gains due to transistor output-impedance degradation caused to short-channel effects.
u Conventional cascode current mirrors limit the signal swings available.
èwide-swing current mirror
MicroLab, vlsi28 (4/12)
JMM v1.0
Wide-swing current mirrors
( ) effout VnV 1+>
efftn nVV >for Q4:
u The basic idea is to bias the drain-source voltages of transistors Q2 and Q3 to be close to the mini-mum possible without them going to triode region.
u Choice of Ibias:u Ibias equal to maximum of Iin (all fets in saturation)u Ibias equal to nominal of Iin (for larger Iin, fets in triode, but
probably only during slew-rate)
u Design hints:u a common choice for n is unityu Q5 larger (0,1V to 0.15V) in order to offset the increased
threshold voltages for Q1 and Q4 due to their body effectsu L of Q1 , Q4 and Q5 are twice minimal channel length, L of Q2
and Q3 are just slightly larger than minimal channel length (high frequency poles)
Iin
Q4 Q1
Iout=Iin
Q3 Q2
VoutIbias
Q5
LW / LW /
2nLW /
2nLW /
( )21+nLW /
Vbias
MicroLab, vlsi28 (5/12)
JMM v1.0
Wide-swing constant-transconductance bias circuit
Q8Q7
Q11
Q9
Q6 Q10
Q14
Q18
Q15
Q16Q1
Q2
Q4
Q3
Q5
Q12
Q13
Q17
20/1 20/120/1
20/1.6 20/1.6 20/1.6
5/1.6
2/20
10/110/1
10/1
10/1
10/1.610/1.6 10/1.6
40/1 10/12.5/1.6
Vbias-n
Vbias-p
Vcasc-n
Vcasc-p small W/L
RB
bias loop cascode bias start-up circuitry
see vlsi-27slide 29
injects current as longas ID’s are zero
MicroLab, vlsi28 (6/12)
JMM v1.0
Enhanced output-impedance current mirror
u Another variation of the cascode current mirror is the enhanced output-impedance current mirror shown as simplified version
u basic idea: use of feedback amplifier to keep the drain-source voltage across Q2 stable, irrespetive of the output voltage
ð the additional amplifier increases the output impedance (see classical cascode current mirror, vlsi-25 slides 16, 17)
( )ArrgR dsdsmout +≅ 1211
Iin+
-A
Iout Rout
Q3 Q2
Q1Vbias
MicroLab, vlsi28 (7/12)
JMM v1.0
Folded-cascode OpAmp
u many modern integrated CMOS OpAmps are designed to drive only capacitive loads
u capacitive-only loads do not need voltage buffers to obtain low output impedance of the OpAmp
u thus it is possible to realize OpAmps having higher speed and larger signal swings than those who must drive resistive loads
u these improvements are obtained by having only one single high-impedance node at the OpAmp output that drives only capacitive loads
u all internal nodes have relatively low impedance (around gm) thus the speed is optimized
u the compensation is usually achieved by the load capacitance
u the most important parameter is their transconductance: operational transconductance amplifier OTA
MicroLab, vlsi28 (8/12)
JMM v1.0
Folded-cascode OpAmp con’t
Q7
Q8
Q12
Q10
Vout
Ibias1
Q11
Q9
Q3 Q4
Q1 Q2
Q5 Q6
CL
VB1
Ibias2VB2
Vin +-
current mirror
wide-swing cascode current mirror
differential-inputsingle-ended output
Q13
may be replaced by a wide-swingconstant-transconductance bias networkand thus VB1, VB2 would be Vcasc-n, Vcasc-p
Purpose of Q12, Q13- increase slew-rate performance- recovering improvement from slew-rate
compensation
folded cascode fets(see vlsi-25 slide 19)
Design hints:- Ibias1 and Ibias2 should be derived from a single bias network- any current mirrors should be designed by parallel combination of unit size fets
MicroLab, vlsi28 (9/12)
JMM v1.0
Folded-cascode OpAmpsmall-signal analysis
( )( ) ( )sZgsVsV
A Lmin
outv 1==
Assumption: gm5 and gm6 are much larger than gds3 and gds4- differential output current from drains of differential pair Q1 and Q2 is
applied to the load capacitance- the small-signal current from Q1 passes directly from source
to drain of Q6 and thus to CL (indirect for Q2 to Q5 and CL)
2
2dsm
outrg
r ≅
(for gm1 = gm2)
( )Lout
outmv Csr
rgsA
+=
11
L
mv sC
gA 1≅for mid-band and
high frequenciesthus the unity-gainfrequency is
L
mt C
g 1≅ω
(see vlsi-25 slide 20)
Design hint:- for large load capacitances a maximal transconductance of input fets
maximizes band width, use n-channel fets- input bias current 4 times larger than cascode current (maximizing dc gain)
Lead compensation (series resistance RC to CL)
( ) ( )L
LCm
LCout
mv sC
CsRg
sCRr
gsA
+≅
++
=1
111
11
/RC can be choosen to place a zero at 1.2 times unity-gain frequency
MicroLab, vlsi28 (10/12)
JMM v1.0
Folded-cascode OpAmpslew-rate
u The diode connected fets Q12 and Q13 are turned off during normal operation and have almost no effect
u slew-rate limiting behavior:u assume there is a large differential input voltage that
causes Q1 to be turned on hard and Q2 to be turned offu since Q2 is off, all of the bias current of Q4 will be
directed to through cascode fet Q5 through n-channel current mirror and out of the load capacitance
u the output voltage will decrease linearly with a slew-rate given by:
u Q1 and current source Ibias will go into triode region, moving the drain voltage of Q1 to the negative power supply
u Q12 and Q13 clamp the drain voltages so they don’t change as much during slew-rate limitation
u in addition Q12 and Q13 increase the bias currents for Q3and Q4 and thus for CL
L
d
CI
SR 4≅
MicroLab, vlsi28 (11/12)
JMM v1.0
Exercises VLSI-28
Ex ana6.2 (difficulty: medium): find reasonable fet sizes for the folded-cascode OpAmp: Assume pos/neg 2.5V power supply, power dissipation maximal 2mW, current ratio 4:1 between input and cascode fets, bias current or Q11 is 1/30 of Q3 (thus ignoring it for power dissipation), maximum fet width is 300um, L=1.6um and Veff=0.25V for all except input fets, W1=W2=300um, rounding widths to 10um, CL=10pF, unCox= 3upCox= 96uA/V2
a) find all fet sizes, unitiy gain frequency, b) slew-rate with and without clamp fetsc) reasonable lead compensation RC
Result: a) Q1 to Q4=300um, Q5, Q6=60um, Q7 to Q10=20um, Q11 to Q12=10um, ωt=2π 38MHzb) SR= 32V/us,c) RC=347Ω (see Johns/Martin pp271-273)
MicroLab, vlsi28 (12/12)
JMM v1.0
Coming Up...
u Next topic… Comparators
u Readings for next time… Johns&Martin: Sections 6.1 and 6.2
u Exercises: Have a look at the exercises in Johns&Martin.
MicroLab, VLSI-30 (1/27)
JMM v1.4
VLSI Systems DesignFSM-D Architecture Model
Goal: You are able to use logic gates and flip-flops wisely and not only in an ad-hoc manner. You master the finite state machine data path model.
data-path(RTL logic)
cotrol path(finite state machine)
FSM-D
inputs
(sensors)
outputs
(actuators)
data
control
control control
data
MicroLab, VLSI-30 (2/27)
JMM v1.4
Architecture Philosophy
?FSM-D architecture model is composed of 2 blocks:?finite state machine (FSM)?data-path (D)
?Goal of FSM-D architecture model?structured design approach?ressource optimization?readability, documentation
?compare a test bench with MicroLab-I3S:?there are chips and PCBs needed to be tested?there is a nice measurement equipment?there are skilled and hard working people?there are no signals coming or going to the outside of
the lab
responsegeneration
andverification
controland
stimulusgeneration
Test Bench
device under test (DUT)
MicroLab, VLSI-30 (24/27)
JMM v1.4
Design Step 9:Test-Bench Design – Test Cycle
?cycle based test?apply input patterns at begining of test cycle?capture response after rising or falling clock edge
clock
inputs
outputs
(sync)
stable stable
applystimuli
captureresponse
test cycle
MicroLab, VLSI-30 (25/27)
JMM v1.4
Design Step 9:Test-Bench Design – Simulation
?cycle based test?apply input patterns at begining of test cycle?observe response after rising or falling clock edge?visualize data-path registers and FSM state
MicroLab, VLSI-30 (26/27)
JMM v1.4
Errors and Pitfalls
?asynchronous external inputs to FSM provoke state hazards?imagine a 0.1 ns hazard can be captured in state register?imagine 100 states in FSM?imagine 100 MHz clock frequency?100 errors per second
? input synchronization for all „external“ (non-synchronous) FSM inputs
transitionlogic
outputlogic
stateregister
i[k]o[k]
s[k]
s[k+1]
new state alwayswith hazardsinput
synchronizationregister
non-synchronousinputs
FSM
MicroLab, VLSI-30 (27/27)
JMM v1.4
Summary and Conclusion
?FSM-D architectural model supports structured design approach?9 design step approach for FSM-D design
presented?task re-distribution between FSM and data-oath is
crucial:?Ass counting (0, 1 or 2) n Black Jack dealer. Who
should do it? FSM or data-path?
?workers/manager analogy is used to assign sub-tasks to control-path (manager) and data-path (specialized workers)
