Nagasaki Institute of Applied Science Prof. Yoshito TANAKA Relativistic Heavy Ion Collider (RIHC) at Brookhaven National Laboratory in USA. http://www.bnl.gov/rhic/ PHENIX Detector System developed by the Japan-US High Energy Collaboration Treaty. RICH FEE System 19inch rack x 8 Custom-made Source-synchronous Backplane. Data transfer speed is reached up to 640Mbyte/s. AMU MAX writing rate 12MHZ MIN writing time 40ns(12bit) Dynamic range 0.5 4.5V Droop time 100mV/s ADC ADC type Wilkinson Range 9 12 bits MAX clock 230MHz (Double edge) 9U Custom-made Module • Orbit 1.2u CMOS 3.5 x 4.5 84pin PLCC • MOSIS SCMOS • TAC 8ch • Integrator 8ch • Trigger sum 2ch PHENIX PHENIX Trajectory of particles: Detector traces ten thousands of tracks using electronics and computer system. 400 collaborators all over the world contribute the PHENIX experiment. Japanese Institutions are University of Tokyo, Tsukuba University, KEK, Riken, Hiroshima University, Waseda University, Nagasaki Institute of Applied Science. PHENIX RICH FEE Project: Size of human Front-End Electronics System for High Energy Physics Experiment developed by Nagasaki Institute of Applied Science, University of Tokyo, Waseda University and Oak Ridge National Laboratory. 5120 channels of analog signals are acquired, formatted and sent to Data Collection Module via fibers. Mixed signal Custom chips were developed using MOSIS service. A custom-made backplane was deve- loped to be possible to transfer data using source-synchronous mode. The system is dedicated to PHENIX Project of Relativistic Heavy Ion Collider (RHIC) under operating since 2000 at Brookhaven National Laboratory in USA. The system has been started developing in 1996 and has finished in 1999. Publication is found in IEEE Transaction on Nuclear Science Vol.47, pp. 1995-2002 (2000) Y. Tanaka and Student VLSI System Laboratory ~ LSI Design & System Development ~
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Nagasaki Institute of Applied Science Prof. Yoshito TANAKA
Relativistic Heavy Ion Collider (RIHC) at Brookhaven National Laboratory in USA.http://www.bnl.gov/rhic/
PHENIX Detector System developed bythe Japan-US High Energy Collaboration Treaty.
RICH FEE System（19inch rack x 8）
Custom-made Source-synchronousBackplane. Data transfer speed is reached up to 640Mbyte/s.
AMUMAX writing rate 12MHZ
MIN writing time 40ns(12bit)
Dynamic range 0.5～4.5V
Droop time 100mV/s
ADCADC type Wilkinson型
Range 9～12 bits
MAX clock 230MHz
(Double edge)
9U Custom-made Module
• Orbit 1.2u CMOS3.5ｍｍ x 4.5ｍｍ84pin PLCC
• MOSIS SCMOS
• TAC 8ch
• Integrator 8ch
• Trigger sum 2ch
PHENIXPHENIX実験用読み出し回路の開発実験用読み出し回路の開発
Trajectory of particles:Detector traces ten thousandsof tracks using electronics andcomputer system.
400 collaborators all over the world contribute the PHENIX experiment.Japanese Institutions areUniversity of Tokyo, Tsukuba University, KEK, Riken, Hiroshima University, WasedaUniversity, Nagasaki Institute of Applied Science.
PHENIX RICH FEE Project:
Size of human
Front-End Electronics System for High Energy Physics Experiment developed by Nagasaki Institute of Applied Science, University of Tokyo, Waseda University and Oak Ridge National Laboratory. 5120 channels of analog signals are acquired, formatted and sent to Data Collection Module via fibers. Mixed signal Custom chips were developed using MOSIS service. A custom-made backplane was deve-loped to be possible to transfer data using source-synchronous mode.
The system is dedicated to PHENIX Project of Relativistic Heavy Ion Collider (RHIC) under operating since 2000 at Brookhaven NationalLaboratory in USA. The system has been started developing in 1996and has finished in 1999. Publication is found in IEEE Transaction on Nuclear Science Vol.47, pp. 1995-2002 (2000)
Y. Tanaka and Student
VLSI System Laboratory ~ LSI Design & System Development ~
TEST Board
Pulse generator（HP 8161A)
Digitaloscilloscope(Tektronix TDS360)
Digitalmulti-meter（HP 34401A）
GPIB Board
OS:Windows95
Software：National Instrument LabView5.0
GPIB Board：National Instrument AT-GPIB/TNT
I/O Board：Advantech PCL-720
I/O Board
Ten thousands of analog chips have been mass-produced. 24 hours test shift wascarried out by graduate students from Nagasaki, Waseda and Tokyo. Test cost tends to be underestimated in general and was not able to be included in government funds. Of course, commercial tester is too expensive for us. Even-tually LSI test system was developed and tested chips manually for the project.
Doctor course, Master course and Bachelor course studentsdesign digital, analog and mixed-signal LSIs in the room.
PC-base testing is performed in the YTLAB usingvarious instruments. Very fast signal is treated onthe test board, basically signal is generated by particular instrument, and is acquired directly by parallel port of PC and also by particular instrument via GPIB.Publication is found in CNS University of Tokyo, CNS-REP-36, July 2001, ISSN 1343-2230
All of software was developed using LabView toolkits for digital functiontest, DC test, Timing test and etc. Some calibration circuit was implementedon the chip as a kind of simple BIST. Test items: Serial set, DC Bias, Output Signal, VGA Cal., TAC Cal.,VGA Gain, TAC, TAC RMS, TAC Ramp, Trigger Sum, TS Offset
Ten thousands chip was shipped from USA. Student met a hardtime. Just TEST! TEST! TEST!.
NA Agilent E3595A/87512A/41800ASA Agilent E9001/85024AAWG Agilent 33120A, 33250AMultimeter Agilent 34401A
Fast signals are controlled by FPGA,while slow signals are handled by PC directly. 14-bit ADCs are implementedand digital data aresent to PC in parallel.Setup data are downloaded serially.
Layout & etc. Cadence Synthesis SynopsysP/R Apollo Analog Sim. HSpiceMentor CalibreMagma ALTERA Orcad/PSpicePADSMultiSimMATLAB
Main Control Panel of the Test System:
Print Circuit Boardfor the test :
Main Instruments in YTLAB :
Design Software:
Design Room:
Block diagram of the System :
Ten thousands Chips! :
10101010553022105
# ofLic.
LSI Test System for PHENIX Project:
Telescope Array 計画
A new pipelined ADC technology and a wide spread of digital video system enable us to use a fast and wide dynamic-range ADC for all channels. The pipelined ADC is fabricated in a CMOS process, and it has superior characteristics of low power, low cost and high speed. A 12-bit, 5-Msample/sec ADC is commercially available in less than $7.While the fast ADC system could give us more information on air shower, it increases data size almost 100 times. Thus a large bandwidthis required in data acquisition system. Furthermore, to maximize themerit of the fast digitization, it is indispensable to process the data in real time to increase signal to noise ratio. This is particularly important in the fluorescence measurement since the signal waveform variesgreatly depend on the zenith angle and the impact parameter.To process the digital data in real time, a large processing power is required. Fortunately, recent progress in digital products introduces high-performance, low-cost DSPs (Digital Signal Processors). Thereare several DSPs, which performances are more than 100 MIPS and the price is less than $10. By using these DSPs we will be able to search optimal gate width for fluorescence signal in real time.To realize the new approach described above, we have developed a signal finder module which implements high-speed ADCs and DSPs.
The highest energy cosmic rays can only be observed on the earth byway of their interaction in the earth's atmosphere. Cascades of particlesare initiated by cosmic ray particles striking air molecules. The showerarrives at the earth's surface as millions of particles. On dark moon-lessnights, nitrogen fluorescence produced by air shower induced ionizationcan be detected by a sky covering array of photomultipliers. A giant array of air fluorescence detectors using 100 thousand photomultiplier tubes (PMT) will be constructed to study the highest energy cosmic rays by the Telescope Array project.
Japan Institute for Cosmic Ray Research,University of Tokyo,Nagasaki Institute of Applied Science,Kochi University,Ehime University,Hiroshima City University,Kobe University,Konan University,Kinki University,Osaka City University,Nara Women's University,Fukui University of Technology,Nagoya University,Shinshu University,Yamanashi University,Yokohama National University,KanagawaUniversity,Shibaura Institute of Technology,Saitama University,University of Tokyo,Tokyo Institute of Technology,Tokyo Metropolitan University,Science University of Tokyo,TohoUniversity,Miyagi University of Education,National Astronomical Observatory of Japan,KEK,NASDA,National Institute ofRadiological sciences,Communications Research Laboratory29 Institutes, 60 Collaborators
USAUniversity of Utah,Columbia University,Rutgers University,Montana State University,UCLA,University of New Mexico6 Institutes,29 Collaborators
Australia University of Adelaide 1 Institute, 3 Collaborators
Signal Finder Module (VME 9U ) :
Telescope Array Station :
DSP Software Development :
Trigger Module :
The telescope Array consists of 10 measurement stations installed in the West Desert of USA, near Salt Lake City, Utah. Each station is separated by 30-40 km. Each measurement station is equipped with two (upper and lower) rings of 20 imaging telescopes arranged in a circle of φ~30 m. Atotal of 40 reflecting telescopes with 3 m φmirror is installed in a station.http://www-ta.icrr.u-tokyo.ac.jp/
DSP program for the Signal Finder Module was developedhere in Nagasaki. All of the program are written in assemblylanguage to process the code as fast as possible. The SF module is controlled by a Linux-base PC viaVME bus. The code is downloadedto 16 DSPs (TI ) controlled by a Master DSP. Each DSP calculatesinput data from 16-bit ADC and find a sunken signal in background noise originated form cosmic rays. Each DSP acquires the data every 200ns and searches the signal in every overlapped 256us windows. If the signal is found in the windows, DSP transports the data to shared memory on the board. The master DSP transports the data to data acquisition system.
Trigger module reconstructs the signals from each DSP and find a 3D track of the cosmic rays. The trigger module consists of DSPs and FPGAs. Oncethe track is found, trigger signal sends to the data acquisition system. Buffered data in each SF module are selected and acquired via the computer network. Publication is found in Proc. of 26th International Cosmic Ray Conference, Salt Lake City, Utah, August 17-25, Vol.5, pp. 393-396 (1999).
Participating Institutions in TA project :
Telescope Array Project
A CMOS integrated circuit has been developed for the front-end electronics of the DSP-based pipelined data-acquisition system in the TA detector. A charge integration of the signal from the PMT is essential in a calorimetric measurement. We integrated four channels of high-precision charge integrators with a wide dynamic range into a CMOS chip. We have newly designed an offset-compensated charge integrator to reduce the offset voltage and the 1/f noise. We expect that the offset voltage and the maximum 1/f noise can be reduced to less than 1mV and 5mV/sqrt Hz, respectively with this technique. Eventually, we can achieve 18-bit dynamic range and 5MHz charge integration with this LSI. Design and testing of the chip were completed in 2001. Publication is found in IEEE transaction on Nuclear Science Vol.49, No.4, August 2002.
Charge Successive Integrator (CSI) LSI :
Main Control Window :
LSI Test System and Test Board:
Charge Successive Integrator (CSI) LSI :
The chip was designed and fabricated using the ROHM double-poly triple-metal 0.6-um CMOS process. Since the chip fabrication program of the VLSI Design and Education Center (VDEC), the University of Tokyo established in 1996, this was the first chip with the goal of mass-production. However, the chip mass-production is still stopped because the TA project will be rearranged into the new project.
A PC-based test system was developed for CSI LSI testing.The test board is controlled by NI digital I/O (PCI-DIO-96PCI) interface card. A pulse generator (LeCroy 9210) is controlled by NI GPIB card. Measurement data are also acquired by the cards. Very fast FIFO memories are implemented on the board to buffer the digital data from pipeline ADC. Now 5MHz pipeline ADC is installed, but an ability of high speed data acquisition with this system is reached to 50MHz, in 54-bit parallel. Buffer depth is limited in 16k words, through.
All of software program was developed using LabView toolkits.A variety of programs are developed to control the instruments.
Test items: DAC INL, DAC DNL, CSI Offset, CSI Linearity
LSI development and Testing for the TA project
ArtLogic Inc.
ArtLogic Inc.
Two companies, AOR LTD. and ArtLogic Inc., are collaborating with the YTLAB on site of our university campus. They have an own office in the venture business incubation center of Institute for Innovative Science and Technology (IIST), Nagasaki Instituteof Applied Science (NIAS). YTLAB is officially collaborating another one company, Com-Hearts Japan, also. Off course many companies help us to develop system LSI and circuit system including wire-bonding, print circuit board manufacturingand assembling. YTLAB is mainly collaborating with University of Tokyo, Waseda University, High Energy Accelerator Research Organization (KEK), and Heidelberg University in Germany.
A Large Ion Collider Experiment at CERN (ALICE)
Examples of AOR production
Electronics system for Transition Radiation Detector (TRD)
Long Wire Bonding by 25um diameter Al for TRD Multi-Chip Module:
The TRD provides electron identification in the central barrel of the ALICE detector. Front-end electronics is placed on the TRD detector and sandwiched between the TRD stacks. Two types of LSI are mounted on the electronics board as multi-chip modules. To obtain the best resolution, the material on the front-end electronics must be reduced.
Testing methods for LCD driver and ADC are researched with ArtLogicInc. Our goal of research is reduction in cost of the testing by new method.
Collaboration with ArtLogic Inc.
Collaboration with AOR, LTD.
Two LSIs on the MCM are bonded by very long Al wires (~50mm). This trial is done by Japanese company, Hara-Seiki Industry Co., LTD.
A system LSI for communication system is developed with0.35um CMOS process. This program is supported by TechnologyDevelopment Fund of Nagasaki Prefecture.
We are recruiting Doctor and Master Course Graduate Students !
YTLAB welcomes students from outside Japan. Already students from Indonesia and China are researching in the lab. YTLAB also welcomes Doctor course students from company. Two Doctor course students from company will start to research in the lab next year. We have scholarship ~50k JPY/month for oversea student. Our school fees are below.
Doctor course : 500kJPY/year for Japanese student260kJPY/year for oversea student 375k JPY/year for Japanese student working for company
Master course : 1,140k JPY/year for Japanese student678k JPY/year for oversea student
Contact: Prof. Dr. Yoshito Tanaka, Nagasaki Institute of Applied Science, 536 Aba-machi, Nagasaki 851-0193, Japan e-mail: [email protected] Fax: +81-95-830-1126
The ALICE Collaboration is building a dedicated heavy-ion detector to exploit the unique physics potential of nucleus-nucleus interactions at LHC energies. Its aim is to study the physics of strongly interacting matter at extreme energy densities, where the formation of a new phase of matter, the quark-gluon plasma, is expected.
Current Collaboration with Companiesand Other Universities
