VLSI Unit 1_MOS

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MOS fundamentals

Metal-oxide-semiconductor FET is the most important device in modern microelectronics.

In this chapter, we will study:– Ideal MOS structure electrostatics– MOS band diagram under applied bias– Gate voltage relationship– I-V characteristics, transfer characteristics– Enhancement and depletion MOS– Channel length modulation, body effect– Biasing of MOSFETs, capacitances in MOS .

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MOS Transistor

• An MOS structure is created by superimposing several layers of conducting, insulating, and transistor forming materials to create sandwich like structure shown in fig 1.

• A MOS transistor can be modeled as a 3-terminal device that acts like a voltage controlled resistance. As suggested by Figure 2 an input voltage applied to one terminal controls the resistance between the remaining two terminals.

• In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”).

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Fig. 1

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MOS Transistor

Figure 1 The MOS transistor as a voltage-controlledresistance.

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MOS Transistor

The basic electrical properties of the semiconductor (Si), the equilibrium concentration of mobile carriers in Si ,always obeys the

Mass Action Law given by,

Assuming that the substrate is uniformly doped with an accepter concentration NA, the Equilibrium electron and hole concentration in the P type substrate.

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Energy Band Diagram For P-Type Silicon

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Fermi Potential

For P-type Fermi Potential

For n-type Fermi Potential

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Electron affinity: It is the potential difference between conduction band level and vacuum (free space) level.It is denoted by qX.

Work Function: The energy required for an electron to move from Fermi level into free space.

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Energy Band Diagram of the components of MOS

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Energy Band Diagram of the Combined MOS System

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MOS Transistor

•Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication used to involve fewer processing steps.•There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used for the resistance-controlled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Figure 2.

Figure 2 Circuit symbol for an n-channel MOS (NMOS) transistor.

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• The terminals are called gate, source, and drain. The voltage from gate to source (Vgs) in an NMOS transistor is normally zero or positive. If Vgs = 0, then the resistance from drain to source (Rds) is very high, in the order of a megohm (106 ohms) or more. As we increase Vgs (i.e.,increase the voltage on the gate), Rds decreases to a very low value, 10 ohms or less in some devices.

• In an n-MOS transistor the majority carriers are electrons.• A positive voltage applied on the gate with respect to the

substrate enhances the number of electrons in the channel and hence increases the conductivity of the channel.

MOS Transistor

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MOS system under External Bias

Accumulation Region:

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Depletion Region:

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Energy band diagrams and charge density diagrams describing MOS capacitor in p-type Si

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The thickness xd of Depletion Region: Assume mobile hole charge in thin horizontal layer parallel to the surface is

The change in surface potential

Integrating along with vertical dimension

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Thus depth of depletion region

And the depletion region charge density,

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Inversion Region:

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The maximum depletion depth xdm

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Structure and Operation of MOSFET

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Circuit symbol of n-type MOSFET

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Circuit symbol of p-type MOSFET

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Formation of depletion region in n-type enhancement MOSFET

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Band diagram for MOS underneath gate

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Formation of inversion region in n-type enhancement MOSFET

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Threshold Voltage

Work function difference is

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Threshold Voltage

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Threshold Voltage

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MOSFET Operation

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MOSFET Operation

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MOSFET Operation

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MOSFET Current-Voltage Characteristics

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Gradual Channel Approximation

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Boundary Conditions for channel voltage Vc(y) are:

Now assume that the entire channel region between the source and The drain is inverted,

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Let QI(y) be the total mobile electron charge in the surface inversionlayer then,

Now consider the incremental resistance dR of the differential channel segment shown in fig (a) then,

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Fig (a)

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Applying Ohm’s law for this segment yields the voltage dropalong the incremental segment dy, in the y direction.

This equation can be integrated along the channel,

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Now put the value of QI(y), we get

Assume that the channel voltage Vc is the only variable, the Drain current is found as follows.

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This current equation can be rewritten as

Where the parameters k and k’ are defined as

Eq. -1

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The drain current equation-1 has been derived under following assumptions,

Which guarantee that entire channel region between source and drain is inverted. This condition is corresponds to the linearoperating region for the MOSFET.

Beyond the linear region boundary MOS transistor is assumed To be in saturation.

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Boundary for Saturation are

In Saturation region VDS = VDSAT , the saturation current can be foundby substituting in eq. -1

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MOSFET ID-VGS Transfer Characteristics

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Channel Length Modulation

Consider the inversion layer charge QI (y), that represents the total electron charge on the surface, the inversion layer charge at thesource end of the channel,

the inversion layer charge at the drain end of the channel,

Now at the edge of the saturation,

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In saturation region inversion layer charge at drain end becomesZero,

This condition is called pinched-off at the drain end at y=L.

If VDS > VDSAT , the large portion of the channel becomespinched-off .This is called channel length modulation. Under this condition length

of the channel is called effective channel length.

Where ∆L is the length of the channel segment with QI = 0shown in fig (b)

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Fig (b)

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Hence the pinch-off point moves from drain end of the channeltowards source with increase in VDS the remaining portion is in depletion mode. The channel voltage at L’<y<L ,

The drain current under this condition

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Put L’ = L - ∆L, then saturation current can be rewrite

But

To simplify the analysis even further, we will use following Empirical relation between ∆L and VDS

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Here λ is an empirical model parameter and is called channel length modulation coefficient .Assume λ. VDS << 1, the saturation current can be written

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Body Effect

The threshold voltage is not constant with respect to the VSB .This is known as substrate bias effect or body effect.

Where γ is called substrate bias or body effect coefficient.

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Terminal Voltages and Currents for N,P Channel MOSFET

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Current Voltages Equation for N- Channel MOSFET

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Current Voltages Equation for P- Channel MOSFET

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MOSFET Capacitances

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MOSFET Capacitances

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MOSFET CapacitancesOxide Related Capacitances:

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MOSFET Capacitances

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MOSFET Capacitances

Cut Off Mode: Cgs = Cgd = 0 and

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MOSFET Capacitances

Linear Mode: Cgb = 0 and

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MOSFET Capacitances

Saturation Mode: Cgd = Cgb = 0 and

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MOSFET Capacitances

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MOSFET Capacitances

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MOSFET Capacitances

Junction Capacitances (Csb and Cdb):

Fig-1

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MOSFET Capacitances

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MOSFET Capacitances

The depletion region thickness (xd):

Where φ0 is built in potential

The depletion region charge Qj

Eq. – 1Here A is the junction area.

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MOSFET CapacitancesThe junction capacitances associated with the depletion region is defined as

Differentiating eq.-1 with respect to V we get expression forJunction capacitance

In general form

Eq-2

Eq-3

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MOSFET Capacitances

The parameter m in eq-3 is called grading coefficient and Cj0 is the zero bias junction capacitance per unit area.

The equivalent large signal capacitance can be defined as

Eq-4

Bu substituting eq-3 into eq-4, we obtain

Eq-5

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MOSFET CapacitancesFor a special case of abrupt p-n junction eq-5 becomes

Eq-6

This equation can be written in a simpler form

Where Keq is the dimension less coefficient is called voltage equivalence factor (0 < Keq < 1)

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MOSFET Capacitances

Assuming that NA (sw) is the sidewall doping density, thezero bias junction capacitance per unit area Cj0 (sw).

Where φ0sw is built in potential. Since all the sidewalls have a same depth xj , the zero bias junction capacitance per unit length

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MOSFET Capacitances

The voltage equivalence factor Keq (sw)

The equivalent large signal junction capacitance Ceq (sw) for a sidewall of length ( perimeter) P can be calculated as

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MOSFET Capacitances

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MOSFET Capacitances

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MOS Transistor

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nMOS Enhancement transistor

P-Si

electrons

N-channelMOSFET(NMOS)uses p-type substrate

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MOSFET operation

ID

VD

Pinch-off

VG1

VG2

VG3

VG3 > VG2 > VG1

When a positive voltage VG is applied to the gate relative to the substrate, mobile negative charges (electrons) gets attracted to Si-oxide interface. These induced electrons form the channel.

For a given value of VG, the current ID increases with VD, and finally saturates.

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Ideal MOS capacitor

Oxide has zero charge, and no current can pass through it.No charge centers are present in the oxide or at the oxide-semiconductor interface.Semiconductor is uniformly doped

M = S

= + (EC – EF)FB

Let us consider a simple MOS capacitor and call it “ideal”

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Equilibrium energy band diagram for an ideal MOS structure

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Effect of an applied bias

Let us ground the semiconductor and start applying different voltages, VG, to the gate

VG can be positive, negative or zero with respect to the semiconductor

EF, metal – EF, semiconductor = – q VG

(Since electron energy = q V, when V < 0, electron energy increases)

Since oxide has no charge, d Eoxide / dx = / = 0; i.e. the E-field inside the oxide is constant.

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Consider p-type Si, apply VG < 0

EC

Ei

EVEFs

GqV

m' Accumulation

of holes

xqx

ioxide

oxide 1const.0 EEE

The oxide energy band has constant slope as shown. No current flows in Si EF in Si is constant.

Negative voltage attracts holes to the Si-oxide interface.This is called accumulation condition.Ei – EF shouldincreases near thesurface of Si.

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Accumulation condition, VG < 0, p-type Si

––––

+

+

Sheet of holes

smallcharge density

E

EM O p-type Si

VG < 0

Sheet ofelectrons

x

x

Accumulation of holes nearsilicon surface, and electronsnear the metal surface.

Similar to a parallel platecapacitor structure.

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Consider p-type Si, apply VG > 0 (Depletion condition)

EFM

EC

EiEFsEV

DepletionE

OM S

positive

0negative

+

+

+- - - -

- - - -

E

Finite depletion layerwidth

E

x

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Consider p-Si, apply VG >> 0 (Inversion condition)

EC

Ei

EV

EFM

+

+

+

+

- - - - - - -

- - - - - - --

-

Immobile acceptors

Mobile electrons

x

EFM

EFS

E

E

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Inversion condition

If we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, Ei can be below EF indicating large concentration of electrons in the conduction band.

We say the material near the surface is “inverted”. The “inverted” layer is not gotten by doping, but by applying E-field. Where did we get the electrons from?

When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition isstart of “inversion”, and the voltage VG applied to gate is called VT

(threshold voltage). For VG > VT, the Si surface is inverted.

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Energy band diagrams and charge density

diagrams describing MOS

capacitor in n-type Si

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Energy band diagrams and charge density diagrams describing MOS capacitor in p-type Si

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Example 1

Construct line plots that visually identify the voltage ranges corresponding to accumulation, depletion and inversion in ideal n-type Si (i.e. p-channel) and p-type Si (i.e. n-channel) MOS devices.

Answer:

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VLSI Unit 1_MOS

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