Unit-1

1. With neat sketches, explain in detail, all the steps involved in electron lithographyprocess. (16) (R07-April 2010)

2. (a) What are the steps involved in the nMOS fabrication?(b) In what way PMOS fabrication is different from nMOS fabrication.(c) Which fabrication is preferred and why? [8+4+4] (R07-April 2010)

3. With neat sketches explain BICMOS fabrication process in a P well. [16] (R07-April 2010)

4. Explain the following:(a) Thermal oxidation technique(b) Kinetics of thermal oxidation. [8+8] (R07-April 2010) (R05-Apr/May 2008)

5. Describe in detail, the diffusion process in IC fabrication. [16] (R07-April/May 2009)

6. Describe different methods for fabricating integrated resistors. [16] (R07-April/May 2009)

7. Mention different growth technologies of thin oxides and describe any one techniquein detail. [16] (R07-April/May 2009)

8. Describe probe testing in VLSI design process. [16] (R07-April/May 2009)

9. (a) Discuss the main processing steps in a CMOS N - well fabrication. (b) Explain twin tub structure, mentioning its merits and demerits. (R07-Nov/Dec 2009)

10. (a) Discuss the recent trends in IC Technology.(b) What are the advantages of ICs over discrete components?(c) List the limitations of IC’s. [8+4+4] (R07-Nov/Dec 2009)

11. With neat sketches necessary, explain the oxidation process in the IC fabricationprocess. [16] (R07-Nov/Dec 2009) (RR-Apr/May 2007)(RR-Aug/Sep 2007) (RR-APR/MAY 2006)

12. Explain the MOS Transistor operation with the help of neat sketches in the follow-ing modes(a) Enhancement mode(b) Depletion mode. [8+8] (R07-Nov/Dec 2009)

12. Describe the two commonly used methods for obtaining integrated capacitor.[16] (R05-Apr/May 2008)

13. With neat sketches, explain in detail, all the steps involved in electron lithographyprocess. [16] (R05-Apr/May 2008) (RR-APR/MAY 2006)

14. (a) What is Moore’s law? Explain its relevance with respect to evolution of ICTechnology.(b) What is the size of silicon wafer used for manufacturing state-of-the art VLSIICs?(c) What is the minimum feature size of current commercial VLSI devices?[8+4+4] (R05-Apr/May 2008)

15. (a) With neat sketches explain how resistors and capacitors are fabricated in p-well process.(b) With neat sketches explain how resistors and capacitors are fabricated in n-well process. [8+8] (RR-Apr/May 2007)

16. With neat sketches explain the ION- lithography process. [16] (RR-Apr/May 2007)

17. Explain about the following two oxidation methods.(a) High pressure oxidation.(b) Plasma oxidation. [8+8] (RR-Apr/May 2007)

18. Explain about the following packaging design considerations.(a) Electrical considerations.(b) Mechanical design consideration. [8+8] (RR-Aug/Sep 2007)

19. (a) Clearly explain the diffusion process in IC fabrication.(b) Clearly explain various diffusion effects in silicon with emphasis on VLSI ap-plication. [8+8] (RR-Aug/Sep 2007)

20. (a) Mention the properties of the twin oxide.(b) Clearly explain about ION implantation step in IC fabrication. [6+10] (RR-Aug/Sep 2007)

21. Explain about the following packaging design considerations.(a) VLSI design rules.(b) Thermal design consideration. [8+8] (RR-APR/MAY 2006)

22. With neat sketches explain Atmospheric- pressure chemical vapor deposition method. [16] (RR-APR/MAY 2006)

23. With neat sketches explain how Diodes and Resistors are fabricated in Bipolarprocess. [16] (RR-APR/MAY-2007) (RR-Apr/May 2006)

24. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] (RR-APR/MAY 2007) (RR-Aug/Sep 2007)(RR-Apr/May 2006)

25. (a) With neat sketches explain how resistors and capacitors are fabricated in p-well process.(b) With neat sketches explain how resistors and capacitors are fabricated in n-well process. [8+8] ] (RR-APR/MAY 2007)

26. (a) With neat sketches explain CMOS fabrication using n-well process.(b) Explain how capacitors are fabricated in CMOS process. [10+6] (RR-APR/MAY 2007) (RR-Apr/May 2006)

Unit 2

1. (a) Define the threshold voltage of a MOS device and explains its significance.(b) Explain the effect of threshold voltage on MOSFET current equation. [8+8](R07-April 2010) (RR-Aug/Sep 2007) (RR-Apr/May 2006)

2. (a) Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region.(b) A PMOS transistor is operated in triode region with the following parameters.VGS=- 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, μnCox =95μnA/V 2. Find itsdrain current and drain source resistance. [8+8] (R07-April 2010)

3. (a) Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10;μnCox = 92μA/V 2.(b) Define the term threshold voltage of MOSFET and explain its significance.[8+8] (R07-April 2010)

4. (a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics.(b) Explain how the BiCMOS inverter performance can be improved. [8+8] (R07-April 2010) (R05- APR/MAY-2008)

5. a) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L)=10;μnCox =92 μ A/V 2 and Vds =Veff+0.5V, the output impedance constant λ = 95.3 x 10 -

3/V -1

b) Explain figure of merit of MOS transistor. [8+8] (R05-April/May 2009)

6. a) A CMOS inverter is built in a process where k’n=100μA/V2, Vtn=+0.7V, k’n =42

μA/V2 , Vtp=-0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and (W/L)p= 14.b) Discuss the CMOS invertors transfer characteristics. [8+8] (R05-April/May 2009)

7. a) Derive the nMOS inverter transfer characteristics. b) Explain the possibility of using a CMOS inverter as an amplifier. [8+8] (R05-April/May 2009)

8. a) Derive the relationship between drain to source current Ids and drain to source voltage Vds in non saturation and saturation region b) Sketch the Ids versus Vds graph for enhancement mode device. [10+6] (R05- April/May 2009) (R05-Nov/Dec 2009)

9. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratiobetween Zpu and Zpd if nMOS inverter is to be driven from another nMOS inverter?[16] (R05-Nov/Dec 2009)

10. (a) Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region.(b) A PMOS transistor is operated in triode region with the following parameters.VGS=- 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, μnCox =95μA/V 2. Find itsdrain current and drain source resistance. [8+8] (R05-Nov/Dec 2009)

11. (a) Explain nMOS inverter and latch up in CMOS circuits?(b) Draw the nMOS transistor circuit model and explain various components ofthe model. [8+8] (R05-Nov/Dec 2009)

12. (a) Explain various regions of CMOS inverter transfer characteristics.(b) For a CMOS inverter, calculate the shift in the transfer characteristic curvewhen βn/βp ratio is varied from 1/1 to 10/1. [8+8] (R05- APR/MAY-2008)

13. Compare the relative merits of three different forms of pull up for an invertercircuits. What is the best choice for realization in(a) nMOS technology(b) CMOS technology. [16] (R05- APR/MAY-2008)

14. (a) Derive an equation for Transconductance of an n-channel enhancement MOSFET operating in Active region.(b) For the arrangement shown below plot the on-resistance of M as a function ofVG. Assume Vtn = 0.7 V; W/L = 10; μnCox = 50μA/V2 Note the drain terminal is open. (Figure 1b) (RR-APR/MAY-2007)

15. (a) Find gm and rds for an n-channel transistor with VGS = 1.2V; Vtn = 0.8V; W/L = 10; μnCox = 92μA/V2and VDS = Veff. The out put impedance constant. λ = 95.3 × 10−3V −1(b) Define the term Threshold voltage of MOSFET and explain its significance.[10+6](RR-APR/MAY-2007)

16. (a) Clearly explain the body effect of the MOSFET.(b) Clearly explain about channel length modulation of the MOSFET. [8+8] ((RR-APR/MAY-2007)

17. (a) With neat sketches explain the drain characteristics of an n-channel enhance-ment MOSFET.(b) n-MOS Transistor is operated in the Active region with the following parame-ters VGS = 3.9V ; Vtn = 1V ; W/L = 100; μnCox = 90 μA/V 2Find its drain current and drain source resistance. [8+8] (RR-AUG/SEP-2007)

18. (a) Derive an equation for IDS of an n-channel Enhancement MOSFET operatingin Saturation region.(b) An nMOS transistor is operating in saturation region with the following pa-rameters. VGS = 5V ; Vtn = 1.2V ; W/L = 110; μnCox = 110 μA/V 2.Find Transconductance of the device. [8+8] (RR-AUG/SEP-2007)(RR-Apr/May 2006)

19. (a) Clearly Explain the sub-threshold conduction of the MOSFET.(b) Show that switching speed of an enhancement MOSFET various inversely asthe square of channel length. [8+8] (RR-Apr/May 2006)

20. (a) With neat sketches explain the formation of the inversion layer in n-channelenhancement MOSFET.(b) A PMOS Transistor is operated in the triode region with the following para-meters. VGS = −4.5V ; Vtp = −1V ; VDS = −2.2V ; W/L = 95; μnCox =95 μA/V 2 Find its drain current and drain source resistance. [8+8] (RR-Apr/May 2006)

UNIT-3

1. Draw the stick diagram and layout for(a) NMOS inverter.(b) P-Well CMOS inverter. [8+8] (R07-April 2010)

2. Design a stick diagram and layout diagram for the CMOS logic shown belowY = ((A + B) (C + D))’. [16] (R07-April 2010)

3. (a) Draw the following transistors using lambda based design rulesi. NMOS enhancementii. NMOS depletioniii. PMOS enhancement.(b) Discuss the design rules for wires (both NMOS and CMOS) using lambdabased design rules. [2+2+2+10] (R07-April 2010)

4. a) what is a stick diagram? Draw the stick diagram and layout for a CMOSinverter.b) What are the effects of scaling on Vt?c) What are design rules? Why is metal- metal spacing larger than poly -polyspacing. [8+4+4] (R05-April/May 2009)(R05-AprMay2008)

5. Draw the CMOS representation stick diagram and layout for a two Input EX-NORgate. [16] (R05-April/May 2009)

6. Design a layout diagram for the CMOS logic shown belowY = ( A + B + C)’. [16] (R05-Nov/Dec 2009)

7. Discuss the following with examples with reference to VLSI design(a) Design hierarchy(b) Regularity. [8+8] (R05-Nov/Dec 2009)

8. (a) What is Moore’s law? Explain its relevance with respect to evolution of tech-nology.(b) What are different VLSI technologies available compare their speed/power performance.(c) Why is VLSI design process presented in NMOS only?(d) Discuss the micro electronics evolution. [6+4+2+4] (R05-Nov/Dec 2009)

9. Draw the stick diagram and mask layout for a CMOS two input NOR gate andstick diagram of two input NAND gate. [16] (R05-AprMay2008)

10. Draw the stick diagram and a translated mask layout for nMOS inverter circuit.[16] (R05-AprMay2008)

11. Explain the following(a) Double metal MOS process rules.(b) Design rules for P- well CMOS process. [8+8] (R05-AprMay2008)

11. What is a stick diagram and explain about different symbols used for componentsin stick diagram. [16] (RR-AprMay2007)

12. Design a layout diagram for two input pMOS NAND gate. [16] (RR-AprMay2007)

13. Design a stick diagram for the CMOS logic shown below Y =( (AB + CD))’ [16] (RR-AprMay2007) (RR- Aug/Sep 2007)

14. Explain with suitable examples how design the layout of a gate to maximize per-formance and minimize area. [16] (RR-AprMay2007) )(RR- Aug/Sep 2007)

15. Design a stick diagram for n-MOS Ex-NOR gate. [16] (RR-AprMay2007)(RR- Aug/Sep 2007)

16. Design a layout diagram for CMOS inverter. [16] (RR-AprMay2007) (RR- Aug/Sep 2007)

17. Design a stick diagram for two input p-MOS NAND and NOR gates. [16] (RR-AprMay2007)

18. Design a layout diagram for two input CMOS NOR gate. [16] (RR-AprMay2007)

19. Design a layout diagram for two input nMOS NAND gate. [16] )(RR- Aug/Sep 2007)

20. Design a layout diagram for nMOS inverter. [16] (RR-APR/MAY2006)

21. Explain about the following(a) Lambda - based design rules(b) Double metal process rules. [8+8] (RR-APR/MAY2006)

21. Design a layout diagram for the PMOS logic shown below Y = (AB) + (CD) [16] (RR-APR/MAY2006)

Unit -4

1.Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet resistance Rsn=104 per square and P-channel sheet resistance Rsp = 3.5 × 104 per square. [16] (R07-APR 2010)

2. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-tance on the performance of a VLSI circuit. [16] (R07-APR 2010) (R05-ARR 2009) (R05-APR08)

3. (a) For a 5μm technology,the standard unit of capacitances for metal 1,polysiliconand n-diffusion are 0.0075 Cg, 0.1 Cg and 0.25 Cg respectively. Calculatethe capacitances for area shown in figure 4. Consider same area for calculation.i. metalii. polysiliconiii. n-diffusion

(b) Impliment a 3-input NOR gate in dynamic logic and explain its operation.[8+8] (R07-APR 2010)(R05-ARR 2009)

4. a) Describe the following briefly cascaded inverters as drivers. b) Super buffers. c) BiCMOS drivers. [8+4+4] (R05-ARR 2009)

5. Calculate the rise time and fall time of the CMOS inverter (W/L)n= 6 and (W/L)p=8,K’n =150μ A/V 2, Vtn =0.7V,K’p= 62 μ A/V 2, Vtp=-0.85V , Vtn =3.3V. Total outputcapacitance =150 fF. [16] (R05-ARR 2009)(R05-APR08)

6. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic.(b) In gate logic, compare the geometry aspects between two -input NMOS NANDand CMOS NAND gates. [8+8] (R05-NOV2009)

7. Explain clearly about different capacitances of an nMOS transistor, mentioningtypical values for each of them. [16] (R05-NOV2009)

8. Draw the circuit topology and explain its operation.(a) pseudo- nMOS logic.(b) Clocked CMOS logic.(c) CMOS domino logic.(d) Dynamic CMOS logic. [4+4+4+4] (R05-NOV2009)

9. (a) Explain the concept of sheet resistance and apply it to compute the ON resis-tance (VDD to GND) of an NMOS inverter having pull up to pull down ratioof 4:1, If n channel resistance is Rsn = 104 per square.(b) Calculate the gate capacitance value of 5μm technology minimum size tran-sistor with gate to channel capacitance value is 4 × 10−4pF/μm2. [10+6] (R05-APR08)

10. (a) Define and explain the following:i. Sheet resistance concept applied to MOS transistors and inverters.ii. Standard unit of capacitance.(b) Explain the requirement and functioning of a delay unit. [4+4+8] (R05-APR08)

11. Calculate ON resistance from VDD to GND for the given inverter circuit shown inFigure 5. If n-channel sheet resistance is 2 × 104 per square. [16] (RR-MAY2007) (RR-MAY2007)

12. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-channel sheet resistance Rsn = 10 4 per square and p-channel sheet resistanceRsp = 2.5 × 104 per square. [16] (RR-MAY2007) (RR-MAY2007) (RR-APR 2006)

13. Derive an equation for the propagation delay from input to output of the passtransistor chain shown in Figure 5. [16] (RR-MAY2007)

14. Two nMOS inverters are cascaded to drive a capacitive load CL=16Cg as shown inFigure 5. Calculate the pair delay Vin to Vout in terms of τ for the given data.Inverter -ALP.U= 16λ , WP.U = 2 λ , LP.d = 2 λ , WP.d = 2 λInverter -BLP.U= 2λ , WP.U = 2 λ , LP.d = 2 λ , WP.d = 8 λ [16]

(RR-MAY2007)(RR-APR 2006)

15. Calculate the gate capacitance value of 2μm technology minimum size transistorwith gate to channel capacitance value is 8 × 10−4pF/μm2. [16] (RR-APR 2006)

Unit- 5

1. (a) Draw and explain the schematic of Pseudo-nMOS comparator.(b) Draw and explain the structure of multiplier which computes the partial products in a radix-2 manner. [8+8] (R07- APR 2010)

2. (a) Design a magnitude comparator based on the data path operators.(b) Draw the Schematic and mask layout of array adder used in Booth Multiplierand explain the principle of multiplication in Booth Multiplier. [6+10] (R07- APR 2010)

3. (a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel adder. (b) Design a two input XOR using a ROM. [8+8] (R07- APR 2010)

4. (a) Draw the multiplier array using a square array and explain the operation of multiplication. (b) How is the parity generator designed as a linear column of XOR gates with a tree routing channel and draw the layout of it. [8+8] (R07- APR 2010)

5. a) Explain the CMOS system design based on the control structures with suitableexample.b) What are the different types of Memory elements? Compare them with respectto CMOS design. [8+8] (R05-APR2009)

6. a) Explain the CMOS system design based on the data path operators with asuitable example.b) Draw and explain the basic Memory- chip architecture. [8+8] (R05-APR2009)(R05-nov2009)(R05-APR2008)

7.a) Draw and explain the Booth decode cell used for Booth multiplier. b) Compare different types of CMOS subsystem shifters. [8+8] (R05-APR2009)

8. a) Explain how the partial products are independently computed in parallel multiplier. b) Draw the circuit and layout for ROM and explain how the dynamic powerdissipation is minimized. [8+8] (R05-APR2009)

9. (a) Explain the CMOS system design based on the memory elements with suitableexample.(b) Draw the schematic and logic diagram for a single bit adder and explain itsoperation with truth table. [8+8] )(R05-nov2009)

10. (a) Design a magnitude comparator using data processing elements.(b) Draw the circuit diagram for 4-by-4 barrel shifter using complementary trans-mission gates and also draw the basic cell layout and also explain its principle.[6+10] (R05-nov2009)

11. Explain briefly the CMOS system design based on the data path operators, memoryelements, control structures and I/O cells with suitable examples. [16] (R05-nov2009)

12. (a) Compare the different types of CMOS subsystem Multipliers.(b) Design a schematic for an 8-word × 2-bit NAND ROM that serves a lookuptable to implement a full adder. [8+8] (R05-APR2008)

13. (a) Draw the schematic for tiny XOR gate and explain its operation.(b) Draw the circuit diagram for 4-by-4 barrel shifter using complementary trans-mission gates and explain its shifting operation. [8+8] (R05-APR2008)

UNIT-6

1. (a) Explain the methods of programming of PAL CMOS device.(b) Draw and explain the architecture of an FPGA . [8+8] (R07-APR2010)

2. (a) Draw the typical standard-cell structure showing regular-power cell and explain it. (b) Draw and explain the pseudo-nMOS PLA schematic for full adder and what are the advantages and disadvantages of it. [8+8] (R07-APR2010)(R05-NOV2009)

3. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure.(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8] (R07-APR2010)

4. (a) What are different classes of Programmable CMOS devices? Explain thembriefly.(b) What is the basis for standard-cell? What are basic classes of circuits forLibrary cells? [8+8] (R07-APR2010) (R05-NOV2009)

5. a) Draw a self timed dynamic PLA and what are the advantages of it comparedto footed dynamic PLA.

b) Explain the tradeoffs between using a transmission gate or a tristate buffer toimplement an FPGA routing block. [8+8] (R07-APR 2009)

6. a) Compare the Antifuse and Vialink programmable interconnections for PALdevices.b) What are different typically available SSI Standard-cell types and comparethem. [8+8] (R07-APR 2009)

7. Draw the structure, explain the function and write the applications characteristicsof the following programmable CMOS devices: [16]a) PLAb) PALc) FPGAd) CPLD. (R07-APR 2009)

8. a) Draw the typical standard-cell structure showing low-power cell and explainit.b) Sketch a diagram for two input XOR using PLA and explain its operationwith the help of truth table. (R07-APR 2009)

9. (a) What are the differences between a gate array chip and standard-cell chip?What benefits does each implementation style have?(b) Write the equations for a full adder in SOP form. Sketch a 3-input, 2- outputPLA implementing this logic. [8+8] (R05-NOV2009)

10. Explain about the following gate array based ASICS(a) Channel gate arrays

(b) Channel less gate arrays(c) Structured gate arrays (RR-APR2006)

11. Using PLA Implement JK Flip flop circuit. [16] (RR-APR2006)(RR-SEP2007)

12. With neat sketches explain the architecture of PAL. [16] (RR-APR2006) (RR-APR2007)

13. (a) What are the advantages and disadvantages of the reconfiguration.(b) Mention different advantages of Anti fuse Technology. [8+8] (RR-APR2007) (RR-SEP2007)

UNIT-7

1. (a) Explain how VHDL is developed and where it was used initially.(b) What are the different design capture tools? Explain them briefly. [8+8] (R07-APR2010)

2. (a) What are the advantages of Hardware Description Languages and give someexamples?(b) Explain the different types of simulators used to predict and verify the per-formance of given circuit. [8+8] (R07-APR2010) (R05-APR 2008)

3. (a) What are basic design units of VHDL? Explain them with suitable examples.

(b) Compare the circuit-level and logic-level simulations for CMOS circuits.[8+8] (R07-APR2010)

4. (a) Explain how VHDL is used to simulate and synthesise a CMOS circuit.(b) Write a VHDL program for a Multiplexer with parameterized bit width. [8+8] (R07-APR2010)

5. a) Write a VHDL program for 7-sengment display decoder.b) What are the basic sources of errors in CMOS circuits and how these aretested? Give name of such a simulator. [8+8] (R05-APR2009)

6. a) What are the design styles of VHDL and explain them with suitable examples?b) Explain the method of Timing simulation for CMOS circuits and name suchsimulators. [8+8] (R05-APR2009)

7. a) Explain how a FSM model is described in VHDL with suitable program.b) What is the difference between Design capture tools and design verificationtools? Give some examples of each. [8+8] (R05-APR2009)

8. a) What is the importance of operator precedence in VHDL? Is the AND operationtakes place before OR operation?b) What is mean by Hierarchy in VHDL?Write a program for 4 input multiplexerfrom 2 input multiplexers. [8+8] (R05-APR2009) (R05-NOV 2009)

9. (a) What is the difference between Flop-Flop and Latch? Write a VHDL programfor a latch.(b) Why logic-level simulators are suitable for testing a fast and large CMOScircuits and how to calculate the delay of the gate? [8+8](R05-NOV 2009)

10. (a) Write a VHDL Program for a divide-by-3 counter with suitable state diagram.(b) Compare all available design verification tools. [8+8] (R05-APR 2008)

11. (a) What are the different types of operators used in VHDL? Give some examplesusing this.(b) Compare the Circuit-level, Logic-level, switch-level and Timing simulations.[8+8] (R05-APR 2008)

12. (a) What are the different data types available in VHDL and how they are indi-cated?(b) Write a VHDL program for a 4-bit Counter with Asynchronous reset. [8+8] (R05-APR 2008)

13. What is need for RTL simulation? Clearly explain RTL simulation flow in theASIC design flow and also mention few leading simulation tools. [16] (RR-APR2007)

14. Clearly explain each step of high level design flow of an ASIC. [16] (RR-APR2007) (RR-SEP2007)

15. (a) What are the different constraints that are passed to the synthesis tool in thesynthesis step of the ASIC design and clearly discuss about these constraints.(b) Mention different report files that are generated by the synthesis tool anddiscuss clearly about each report file. [8+8] (RR-APR2007)

16. What is need for RTL simulation? Clearly explain RTL simulation flow in theASIC design flow and also mention few leading simulation tools. [16] (RR-APR2007)

17. With respect to synthesis process explain the following terms.(a) Flattening(b) Factoring.(c) Mapping. [6+5+5] (RR-SEP2007)(RR-APR2006)

18. Explain the following process in the ASIC design flow.(a) Functional gate level verification.(b) Static timing analysis. [8+8] (RR-SEP2007)

19. Explain the following processes in the ASIC design flow.(a) Post - layout timing simulation.(b) Post synthesis simulation. [8+8] (RR-APR2006)

20. What are the inputs that are provided to the synthesis tool? And explain com-pletely about synthesis process in the ASIC design. [16] (RR-APR2006)

UNIT-8

1. (a) Explain the gate level and function level of testing.(b) A sequential circuit with ?n? inputs and ‘m’ storage devices. To test thiscircuit how many test vectors are required.(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6] (R07-APR 2010)(R05-APR2009)

2. (a) Why stuck-at faults occur in CMOS circuits? Explain with suitable logicaldiagram and layout.(b) Draw a schematic for a CMOS edge-sensitive scan-register and also draw somecircuit level diagrams of its implementation. [8+8] (R07-APR2010)(R05-NOV2009)

3. (a) Explain the functionality test of a chip with suitable examples.(b) What are the categories of Design for testability? Explain them briefly. [8+8] ] (R07-APR2010)

4. (a) Explain how function of system can be tested.(b) Explain any one of the method of testing bridge faults.(c) What type of faults can be reduced by improving layout design? [6+5+5] ] (R07-APR2010)

5. a) Explain how the cost of chip can effect with the testing levels,b) Explain how observability is used to test the output of a gate within a largercircuit.c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] )(R05-APR2009) (R05-NOV2009)

6. (a) Explain how controllability and observability are used to test the CMOS cir-cuits.(b) What are the different fault models? Compare them. [8+8] (R05-NOV2009)

7. (a) Explain how an improved layout can be reduced faults in CMOS circuits.(b) Explain how a pseudo random sequence generator may be used to test a 16-bitdata path. How would the outputs be collected and checked. [6+10] (R05-APR2008)

8. (a) compare functionality test and manufacturing test.(b) What type of testing techniques are suitable for the following:i. Memoriesii. Random logiciii. Data path.(c) How IDDQ testing is used to test the bridge faults? [5+6+5] (R05-APR2008)

9. (a) Draw the basic structure of parallel scan and explain how it reduces the longscan chains.(b) Draw the state diagram of TAP Controller and explain how it provides thecontrol signals for test data and instruction register. [8+8] (R05-APR2008)