EC 6112: VLSI DESIGN LABORATORY LIST OF EXPERIMENTS: COMPULSORY EXPERIMENTS: 1. Design of a half adder using the block level entries and simulate it on Active HDL 2. Design of a 3-to-8 decoder using block level entries and simulate it on Active HDL 3. Design of a synchronous counter with the following states and simulate it making the entries through FSM on Active HDL 4. Writing of Code for Full adder using VHDL and its simulation on Active HDL. 5. Design of a 8:1 Multiplexer and its simulation on Active HDL 000 0 000 1 110 0 010 0 010 1 011 0 101 1 100 0 011 1 101 0 100 1 001 1
Transcript
EC 6112: VLSI DESIGN LABORATORY
LIST OF EXPERIMENTS:
COMPULSORY EXPERIMENTS:
1. Design of a half adder using the block level entries and simulate it on Active
HDL
2. Design of a 3-to-8 decoder using block level entries and simulate it on Active
HDL
3. Design of a synchronous counter with the following states and simulate it
making the entries through FSM on Active HDL
4. Writing of Code for Full adder using VHDL and its simulation on Active
HDL.
5. Design of a 8:1 Multiplexer and its simulation on Active HDL
6. Design of a JK flip flop from a D flip flop and its simulation on Active HDL
7. Design of a two input X-OR using CMOS logic (on Cadence Tools)
8. Design of a two input NAND using Pseudo NMOS logic (on Cadence Tools)
9. Design of a Full Adder circuit using TG logic (on Cadence Tools)
10. Design of a common emitter amplifier using an NPN transistor with a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tools)
0000
0001
1100
0100
0101
0110
1011
10000111
1010
1001
0011
11. Design of a common source amplifier using an NMOS transistor and active load for a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tools)
12. Design of a difference amplifier with PMOS current mirror and NMOS input transistors for a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tools)
OPTIONAL EXPERIMENTS :
13. Design of 10-bit shift register and simulate it using active HDL
14. Design of 8:3 encoder and simulate it using Active HDL
15. Design of 8-bit Latch Register and simulate it on Active HDL
16. Design a peripheral circuit for digital Clock and simulate it on Active HDL
17. Design a 416 decoder by using two 24 decoder and simulate it on Active
HDL
18. Design a BCD to excess 3 code converter circuit using SR flip flop and
simulate it using Active HDL
19. Design of a D flip flop with no set-reset input and clocking done to latch at
falling edge (on Cadence Tools)
20. Design of a circuit to compare between two 4-bit numbers for checking
equality using Pseudo NMOS logic (on Cadence Tools)
21. Design of a bi-CMOS NAND gate with NPN transistor acting as a pull down
component (on Cadence Tools)
22. Design of a JK flip flop with asynchronous set-reset and clocking done to
latch at rising edge (on Cadence Tools)
23. Design of a latch using X-gate and hysteresis (without an X-gate in the
feedback loop) (on Cadence Tools)
24. Design of a 8:1 MUX using X-gate (on Cadence Tools)
25. Design of a Full Adder using Current Mode Logic (on Cadence Tools)
26. Design of a 4-bit counter using T-flip flops (on Cadence Tools)
27. Design of a 44 bit adder using CMOS logic
28. Design of the layout of a CMOS inverter using Assura Tools on Cadence
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A HALF ADDER USING THE BLOCK LEVEL ENTRIES AND SIMULATE IT ON ACTIVE HDL
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a half adder using the block level entries and simulate it on Active HDL
SOFTWARE USED:
Active HDL/ Xilinx ISE
THEORY:
A combinational circuit that performs an addition of two bits is called half
adder. For this the circuit needs two binary inputs and two binary outputs. The input
variables designate the augend and addend bits; the output variable produces the sum
and carry.
PROGRAM:
Program for this problem has to be made by the student
TRUTH TABLE: to be obtained by the student
K MAP: : to be obtained by the student
WAVEFORM: to be obtained by the student
RESULT:
PRECAUTIONS:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A 3-TO-8 DECODER USING BLOCK LEVEL ENTRIES AND SIMULATE IT ON ACTIVE HDL
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a 3-to-8 decoder using block level entries and simulate it on Active HDL
SOFTWARE:
Active HDL or Xilinx ISE
THEORY:
Discrete quantities of information are represented in digital systems with binary
codes. A binary code of n bits is capable of representing up to2n distinct elements of
the coded information. A decoder is a combinational circuit that converts binary
information from n input to maximum of 2n unique codes. The purpose of a decoder is
to generate 2n or less minterms of n input variables.
PROGRAM:
Program for this problem has to be made by the student
TRUTH TABLE: to be obtained by the student
K MAP: : to be obtained by the student
WAVEFORM: to be obtained by the student
RESULT:
PRECAUTIONS:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A SYNCHRONOUS COUNTER AND SIMULATE BY MAKING THE ENTRIES THROUGH FSM ON ACTIVE HDL
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a synchronous counter with the following states and simulate it making the entries through FSM on Active HDL
SOFTWARE:
Active HDL or Xilinx ISE
THEORY:
A Sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter. The input pulses called count pulses
may be clock pulses or they may originate from an external source and may occur at
prescribed interval of time or at random. In a counter the sequences of states may
follow a binary count or any other sequences of states.
PROGRAM:Program for this problem has to be made by the student
EXCITATION TABLE: to be drawn by the student
WAVEFORM: to be obtained by the student
0000
0001
1100
0100
0101
0110
1011
10000111
1010
1001
0011
RESULT:
PRECAUTIONS:DEPARTMENT
OFELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
WRITING OF CODE FOR FULL ADDER USING VHDL AND ITS SIMULATION ON ACTIVE HDL
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Writing of Code for Full adder using VHDL and its simulation on Active HDL
SOFTWARE:
Active HDL or Xilinx ISE
THEORY:
A full adder is a combinational circuit that performs a addition of three input bits. For
this the circuit needs three binary inputs and two binary outputs. Two of the input
variables represent two significant bits to be added. The third input represents a carry
from the previous lower significant position. A two-output variable represents the sum
and carry.
PROGRAM:
Program for this problem has to be made by the student
TRUTH TABLE: to be obtained by the student
K MAP: : to be obtained by the student
WAVEFORM: to be obtained by the student
RESULT:
PRECAUTIONS:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A 8:1 MULTIPLEXER ITS SIMULATION ON ACTIVE HDL
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a 8:1 Multiplexer and its simulation on Active HDL
SOFTWARE USED:
Active HDL/ Xilinx ISE
THEORY:
Multiplexing is the transmission of a large number of input signals over a
smaller number of output lines. It’s a combinational circuit that selects one of the
inputs from many input lines determined by the combination of selection inputs and
directs it to a single output line. For n selection lines the number of inputs can be 2n .
PROGRAM:
Program for this problem has to be made by the student
TRUTH TABLE: to be obtained by the student
WAVEFORM: to be obtained by the student
RESULT:
PRECAUTIONS:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A JK FLIP FLOP FROM A D FLIP FLOP AND SIMULATE ON ACTIVE HDL SOFTWARE
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a JK flip flop from a D flip flop and its simulation on Active HDL
SOFTWARE:
Active HDL or Xilinx ISE
THEORY:
A circuit that maintains a binary state indefinitely (as long as power is delivered to the
circuit) until directed by an input signal to switch states is called a flip-flop. The
major differences among various types of Flip-Flop are in the number of inputs they
possess and in the manner in which the inputs affect the binary state. The most
common types of flip-flops are RS, JK, T and D flip-flops.
PROGRAM:
Program for this problem has to be made by the student
TRUTH TABLE: to be obtained by the student
WAVEFORM: to be obtained by the student
RESULT:
PRECAUTIONS:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF TWO INPUT X-OR USING CMOS LOGIC
(ON CADENCE TOOL)
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a two input X-OR using CMOS logic (on Cadence Tools)
PLATFORM:
Software: Cadence Package: IC 5141
THEORY: XOR gate is the heart of digital world. In digital application, most important considerations are delay and power dissipation. There are different types of logic (such as pseudo NMOS, Domino Logic, Current Mode Logic, Pass Transistor logic) for performing same logic function. According to the requirement logic is selected. CMOS logic is one of them. Properly designed XOR gate can be very useful in today’s high-speed digital era.
For two input XOR gate, output related to the inputs according to the following equation
Where A and B are two inputs and Y is the output.
PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library
with your name and attach that library to design library, then create new Cell view under this libray.
3. Click on “add instance” tab and take all components from analog library.
4. For selecting NMOS and PMOS, select NMOS4 and PMOS4 from analog library respectively. Put model name as “trnmos” and “trpmos” respectively. Change aspect ratio according to the requirement.
5. Give input using pin.6. After completing design, check and save the same and execute using
ADE tool according to the instruction given by the instructor.
OBSERVATIONS:
Input rail to rail voltage=4 V
Sl. No. Input 1 (A) Input 2 (B) Output ()
Rise time(tr)
Fall time (tf)
1 0 02 1 03 0 14 1 1
PRECAUTION:
1. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
2. Don’t give input directly. Always assign pin for giving input.3. Don’t switch off machine without properly exiting every operation.4. Shutdown machine properly.
Block diagram:
CMOS Invereter
CMOS NAND gate
CMOS Invereter
CMOS NOR gate
CMOS Invereter
CMOS Invereter
CMOS NAND gate
CMOS Invereter
A
B
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A TWO INPUT NAND USING PSEUDO NMOS LOGIC
(ON CADENCE TOOLS)
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM: Design of a two input NAND using Pseudo NMOS logic (on Cadence Tools)
PLATFORM:
Software: Cadence Package: IC 5141
THEORY: In pseudo-NMOS logic, the load device is a single P-transistor with the gate connected to Vss. Alternatively, the P-load may be connected as a constant current source to provide better process tracking and optimized pull-down sizes. The gain
ratio of the n-driver transistors to p-transistor load has to be selected to yield
sufficient gain to generate consistent high and low logic levels. The design of this style of gate involves ratioed transistors sizes to ensure correct operation. The main problem with the gate is the static power dissipation that occurs whenever the pull-down chain is turned on. PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library with
your name and attach that library to design library, then create new Cell view under this library.
3. Click on “add instance” tab and take all components from analog library. 4. For selecting NMOS and PMOS, select NMOS4 and PMOS4 from analog
library respectively. Put model name as “trnmos” and “trpmos” respectively. Change aspect ratio according to the requirement.
5. Give input using pin.6. After completing design, check and save the same and execute using ADE tool
according to the instruction given by the instructor.
1. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
2. Don’t give input directly. Always assign pin for giving input.3. Don’t switch off machine without properly exiting every operation.4. Shutdown machine properly.
CIRCUIT DIAGRAM:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A FULL ADDER CIRCUIT USING TG LOGIC
(ON CADENCE TOOLS)
BIRLA INSTITUTE OF TECHNOLOGYMESRA, RANCHI
AIM:- Design a Full Adder circuit using TG logic (on Cadence Tools)
Platform:
Software: Cadence Package: IC 5141
THEORY:
A CMOS transmission gate consists of a NMOS and a PMOS connected in parallel. The NMOS is controlled by the signal S, while the PMOS is controlled by the complement S’. When wired in this manner, the pair acts as a good electrical switch between the input and the output variables.
If S=0, the NMOS is off; since S’=1, the PMOS is also off, so that the TG acts as an open switch. For the opposite case both FET’s are on, and the TG provides a good conducting path between input and output. Transmission gates are useful because tey can transmit the entire voltage range [0,VDD].
PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library with
your name and attach that library to design library, then create new Cell view under this libray.
3. Click on “add instance” tab and take all components from analog library. 4. For selecting NMOS and PMOS, select NMOS4 and PMOS4 from analog
library respectively. Put model name as “trnmos” and “trpmos” respectively. Change aspect ratio according to the requirement.
5. Give input using pin.6. After completing design, check and save the same and execute using ADE tool
according to the instruction given by the instructor.
1. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
2. Don’t give input directly. Always assign pin for giving input.3. Don’t switch off machine without properly exiting every operation.4. Shutdown machine properly.
Circuit diagram:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A COMMON EMITTER AMPLIFIER USING AN NPN TRANSISTOR WITH A GAIN OF 50 PLUS AND OFFSET LESS THAN
20% OF SUPPLY RAIL (ON CADENCE TOOLS)
BIRLA INSTITUTE OF TECHNOLOGYMESRA RANCHI
AIM:- Design of a common emitter amplifier using an NPN transistor with a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tools)
PLATFORM:
Software: Cadence Package: IC 5141
THEORY:
The common emitter amplifier is the most popular of all three amplifier connections, since it enjoys both a current and a voltage gain, with the result that it exhibits the greatest power gain. Figure bellow is showing the amplification procedure :
The analysis suggests that small sinusoidal signals, vbe, superimposed on the DC
voltage VBE, will give a sinusoidal collector current, iC, superimposed on the DC
current IC at the Q-point. Depending upon the configuration of the resistors in the
collector, the emitter, and the load, there will be an ideal Q-point for a maximum distortion-free output signal amplitude. Determining these resistor requires constructing an ac loadline.
PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library with
your name and attach that library to design library, then create new Cell view under this libray.
3. Click on “add instance” tab and take all components from analog library. 4. select npn transistor from analog library. Put model name as “trnpn”. 5. Give input using pin.6. After completing design, check and save the same and execute using ADE tool
according to the instruction given by the instructor.
OBSERVATIONS:
PRECAUTIONS:
5. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
6. Don’t give input directly. Always assign pin for giving input.7. Don’t switch off machine without properly exiting every operation.8. Shutdown machine properly.
Circuit diagram:
Sl. No.
Input VPP Input frequency
Output VPP Gain Offset
1234
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A COMMON SOURCE AMPLIFIER USING AN NMOS TRANSISTOR AND ACTIVE LOAD FOR A GAIN OF 50 PLUS AND
OFFSET LESS THAN 20% OF SUPPLY RAIL (ON CADENCE TOOLS)
BIRLA INSTITUTE OF TECHNOLOGYMESRA RANCHI
AIM: Design of a common source amplifier using an NMOS transistor and active load for a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tools)
PLATFORM:
Software: Cadence Package: IC 5141
THEORY:Integrated circuits (IC) are most commonly designed and fabricated
without the use of resistors. This is due to the fact that resistors generally take up most of the area on a chip and increase the cost of the integrated circuit. Since the size of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is so much less than resistors, circuits for IC’s are designed using just MOSFETs that perform the same functions as those with resistors. The use of only MOSFETs results in much higher-density circuits, allowing many functions to be designed and built on a small chip area. MOSFETs can be used to amplify an input signal, to build a current source, or to replace passive resistors in certain applications.
In this experiment, a MOSFET amplifier was constructed that used additional MOSFETs as an active load resistor. The resulting circuit is referred to as a common-source amplifier with active load.
PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library
with your name and attach that library to design library, then create new Cell view under this libray.
3. Click on “add instance” tab and take all components from analog library. 4. select npn transistor from analog library. Put model name as “trnpn”. 5. Give input using pin.6. After completing design, check and save the same and execute using ADE
tool according to the instruction given by the instructor.
OBSERVATIONS:
Sl. No.
Input VPP Input frequency
Active load aspect ratio
NMOS aspect ratio
Output VPP
Gain Offset
1234
PRECAUTION:
1. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
2. Don’t give input directly. Always assign pin for giving input.3. Don’t switch off machine without properly exiting every operation.4. Shutdown machine properly.
Circuit diagram:
DEPARTMENTOF
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL
ON
DESIGN OF A DIFFERENCE AMPLIFIER WITH PMOS CURRENT
MIRROR AND NMOS INPUT TRANSISTORS FOR A GAIN OF 50 PLUS
AND OFFSET LESS THAN 20% OF SUPPLY RAIL
(ON CADENCE TOOLS)
BIRLA INSTITUTE OF TECHNOLOGYMESRA RANCHI
AIM: To design a difference amplifier with PMOS current mirror and NMOS input transistors for a gain of 50 plus and offset less than 20% of supply rail (on Cadence Tool)
PLATFORM:
Software: Cadence Package: IC 5141
THEORY:
The important advantage of differential operation over single ended signaling is higher immunity to environmental noise. Since the common mode level of the two phases is disturbed but the differential output is not corrupted, we say this arrangement “reject” common mode noise.
Other advantages of differential circuits over single ended circuits include simpler biasing and higher linearity.
PROCEDURE:
1. Start Cadence in “icfb &” mode.2. Create new Cell view in your pre created library or first create a library with
your name and attach that library to design library, then create new Cell view under this libray.
3. Click on “add instance” tab and take all components from analog library. 4. select npn transistor from analog library. Put model name as “trnpn”. 5. Give input using pin.6. After completing design, check and save the same and execute using ADE tool
according to the instruction given by the instructor.
OBSERVATIONS:
Sl. No.
Input VPP Input frequency
PMOS aspect ratio
NMOS aspect ratio
Output VPP
Gain Offset
1234
PRECAUTION:
5. Don’t execute “icfb &” without going into “adelabic”. Strictly follow the instruction given by the instructor.
6. Don’t give input directly. Always assign pin for giving input.7. Don’t switch off machine without properly exiting every operation.8. Shutdown machine properly.
