VMM ASIC for the ATLASVMM ASIC for the ATLAS Muon Phase 1 UpgradeMuon Phase 1 Upgrade
Gianluigi De Geronimoa,b, Wenxiang Dingb, Aseem Guptab, George g g g p gIakovidisa, Sorin Martoiuc, Venetios Polychronakosa, Emerson Vernona
a Brookhaven National Laboratory, NY, USAb Stony Brook University, NY, USA
c IFIN‐HH Bucharest, Romania
June 2016 ‐ FEE ‐ Krakow
Outline
• New Small Wheel
• NSW Front‐End Electronics
• The VMM ASICThe VMM ASIC– Analog Front‐End
Digital Back End (Level 0 Processor)– Digital Back‐End (Level‐0 Processor)
• Conclusions
2
ATLAS Muon Spectrometer at LHCmuon barrel stations
ATLAS Detectormuon barrel stations
muon inner stations"small wheels"
muon middle station
3muon outer stations
"endcap"
muon middle station"big wheels"
New Small Wheel• Current small wheel only provide rough tracking and no trigger capability• Current small wheel only provide rough tracking and no trigger capability
Trigger only relies on big wheel → false tracks, significant physics loss
N ll h l (NSW) i i d i i ki hi h• New small wheel (NSW): triggering and precision tracking at high rate
big wheel
small wheelnew small wheel
4
NSW Detector TechnologiesTwo kinds of high‐rate capable large‐area gas detectorsg p g g
4 44 4
sTGCsmall‐strip Thin Gap Chamber
MicroMegasMicro‐Mesh Gaseous structure
• Primary trigger detector (pads/strips) • Primary precision trackerPrimary trigger detector (pads/strips)• Combines pads, strips, wires (~3mm pitch)• Angular resolution < 1 mrad (strips)• Redundant position resolution (strips, wires)4 4 t id l f l l
Primary precision tracker• Strips (~0.5mm pitch)• Position resolution < 100 µm• Redundant triggering4 4 i id l
5
• 4 + 4 outside layers for long lever arm• 400,000 electronics channels
• 4 + 4 inside layers• 2.1 million electronics channels
sTGC Detector• Trigger
• pad signal selects strip region• selected strips sent for trigger
• Tracker• combines strips and wirescombines strips and wires
sTGC Signalwires sandwiched between 2 cathode planesbetween 2 cathode planes
Ion tail currentFE Electronics Requirements
• 1 MHz/channel• Fast processing P=25ns • Recovery < 200 ns (< 1µs at 50pC)
6
• Positive or negative charge• DC or AC coupling• Charge 50pC, linear to 2pC
• Capacitance up to 2nF• Resolution < 1fC at 200pF• Signal tail suppression
MicroMegas Detector
ionization/drift
amplification
MicroMegas Signal
FE Electronics Requirements
7
• Accurate charge & time measurements• Group trigger• Good collection P=100‐200n
• Charge up to 250fC, negative• Capacitance 50‐300 pF• Resolution < 0.5 fC at 200pF
NSW Front‐End Electronics ArchitectureFour ASICs
ART
Four ASICs(1 mixed‐signal, 3 digital)
TDS
VMMTDS
8
ROC
VMM3 Architecture and Functionality
logic
orSETT, SETB
ARTCKART
TDS (ToT TtP PtT PtP 6bADC)64 channels
D1/flagCA shaper
logic
6‐b ADC
10 b ADCpeak
TDS (ToT, TtP, PtT, PtP, 6bADC)CK6B
IN/ ag
D2PDOTDO
12‐b BC
10‐b ADC
8‐b ADCtime4X FIFO
mux
MO
L0
addr.
Gray countlogic
CKTK/L0pulser
trim
bias registersCKTP
tempDAC ENA/softresetprompt
registers CKDT
TKI/BCR/OCRgCKTP prompt
SCK, CSSDI, SDO
TKI/BCR/OCR
SLVS 1.2V CMOSANALOG LVDS bi‐dir
CKBC
9
VMM3 Layout
s
µm Mixed‐signal cessor
Mixed‐signal: ~ 5.2 M transistors tran
sistors
8384
g
L0 procg
: ~ 5.2 M
tL0
~ 15308 µmµ
10L0 processor digitally implemented
Analog Front‐End(simulations)
11
Response to ‐Current vs Cdet
Qdet 2pCGain 0 5mV/fCGain 0.5mV/fC
plitu
deam
p
2pF, 20pF, 200pF, 2nF
Att ti t 2 F 25 t i d ithi 8%
time
• Attenuation at 2nF, 25ns contained within 8%• Peaking time increase at 2nF contained within 6ns
12
sTGC Signal Simulation ‐ Detail
6pC
arge
rent
charge
cha
curr
g~ 50% in 200ns
current~ 25% in 25ns
Simulation of 6pC signal to 1µs
Ab t 25% d 50% f h ll t d i 25 d 200 ti l
time
• About 25% and 50% of charge collected in 25ns and 200ns respectively
13
Response to sTGC‐Currents
delta Qdet 2pC & 6pCC 200 Fe Cdet 200pFGain 0.5mV/fC
amplitu
d
sTGC
tail
• The response to the sTGC current exhibits an increase in peaking time
time
• The response to the sTGC current exhibits an increase in peaking time of about 13ns and a tail extending to some µs – discrimination an issue• No saturation with 6pC sTGC signals up to 6pC (expected average)14
BLH Modified for Tail SuppressionBLH Circuit
low‐frequency filterBLH Circuit
non‐linear stage
signal ref
programmable tail suppressor
• The BLH is programmable: along with the unipolar response mild• The BLH is programmable: along with the unipolar response, mild and strong tail suppressions are available
15
Tail Suppressor with sTGC‐Currents
Qdet 6pCCd t 200pFe Cdet 200pFGain 0.5mV/fC
amplitu
d
strong mildnone
strong
• Impact of the tail suppressor on sTGC‐currents, with a return below
time
Impact of the tail suppressor on sTGC currents, with a return below threshold within 200ns and full baseline return in less than ~ 600ns
16
High Rate Events ‐ DC Coupled Sensor
analog output, Qdet=6pC, 1MHz charge amplifier output
ude
ude dc baseline
amplitu
amplitu
negative chargepositive charge
dc baseline
• A stable baseline can be observed at the analog output
timetime
A stable baseline can be observed at the analog output• For dc‐coupled sensor, a baseline shift occurs at the output of the charge amplifier, with polarity equal to the signal17
High Rate Events ‐ AC Coupled Sensor
analog output, Qdet=6pC, 1MHz charge amplifier output
dc baselineude
ude
positive chargeamplitu
amplitu
negative charge
t ~ RDETCAC
dc baseline
• For ac‐coupled sensor, after the initial baseline shift of the same
timetime
For ac coupled sensor, after the initial baseline shift of the same polarity, a second shift of opposite polarity occurs due to the zero net charge (zero‐area ...) with potential for long‐term saturation18
Additional Front‐End Circuits
• Dynamic discharge circuit (DDC): combines both polarity resets to contain baseline shifts for high‐ratepolarity resets to contain baseline shifts for high rate operation with AC coupled sensors.
F t i it (FRC) id f t di h• Fast recovery circuit (FRC): provides fast discharge for very high charge events to guarantee recovery within ~1µswithin 1µs.
b k l d‐ see backup slides ‐
19
ENC at Maximum Gain
Unipolar ResponseGain 16mV/fCEN
C
positive chargenegative charge
25ns
10k200ns
~10e‐/pF~10e /pF1k
1nF100pF capacitance
20
Digital Back‐End(L l 0 P )(Level‐0 Processor)
Sorin Martoiu, IFIN‐HH Bucharest
21
Level‐0 Processor
BC window
BC counterBC clock
L0 trigger
LAT. FIFO (64)
LAT. FIFO (64)
LAT. FIFO (64)
L0 CH FIFO (16)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16) UILD
L0 SEL
LAT. FIFO (64)
LAT. FIFO (64)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16)
EV BU
BCID FIFO (32)
Latency FIFO takes data from the mixed‐signal front‐end• FIFO designed to accommodate 4 MHz data in a 10 µs latency window• 20‐bit data: threshold, amplitude (ADC), timing (ADC)20 bit data: threshold, amplitude (ADC), timing (ADC)
22
Level‐0 Processor
BC window
BC counterBC clock
L0 trigger
LAT. FIFO (64)
LAT. FIFO (64)
LAT FIFO (64)
L0 CH FIFO (16)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16) UILD
L0 SEL
LAT. FIFO (64)
LAT. FIFO (64)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16)
EV BU
BCID FIFO (32)
At L0 trigger builds BC trigger window and selects data for the L0 CH FIFO• flushes old data• fills non valid data as needed (for simultaneous overflow)• fills non‐valid data as needed (for simultaneous overflow)• builds BCID FIFO
23
Level‐0 Processor
BC window
BC counterBC clock
L0 trigger
LAT. FIFO (64)
LAT. FIFO (64)
LAT FIFO (64)
L0 CH FIFO (16)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16) UILD
L0 SEL
LAT. FIFO (64)
LAT. FIFO (64)
L0 SEL
L0 SEL
L0 CH FIFO (16)
L0 CH FIFO (16)
EV BU
BCID FIFO (32)
B ild tBuilds event• BCID followed by valid data with address• header• event built in < 1µs• event built in < 1µs
Sends data through two data links (DDR, 640MB/s)`24
Conclusions and Future Work• VMM: front end ASIC for NSW in ATLAS Muon P1 upgrade• VMM: front‐end ASIC for NSW in ATLAS Muon P1 upgrade
• programmable options and functions for all pads, strips and wires insTGC and MicroMegas detectors (2.6 million channels total)
• combines mixed‐signal and digital design implementations•moves in the direction of System‐on‐Chip (SoC)• 64 channels, 160kMOSFETs/channel64 channels, 160k MOSFETs/channel• interfaces to 3 digital ASICs (TDS, ART, ROC)• sub‐fC and sub‐ns resolution at 200 pF, 25 ns
l i l i i i i l i l ADC d d h•multiple trigger primitives, multiple ADCs and data paths• VMM3 is being fabricated, aims at pre‐production
CERN and the ATLAS CollaborationNachman Lupu (Technion Haifa Israel) ‐ Lorne Levinson & team (Weizmann Inst Israel)
Acknowledgment
25
Nachman Lupu (Technion Haifa, Israel) ‐ Lorne Levinson & team (Weizmann Inst., Israel)Ken Johns & team (Univ. Arizona, USA) ‐ Jay Chapman & team (Michigan Univ., USA)Paolo Giromini & team (Harvard, USA) ‐ John Hobbs, Chris Bee (Stony Brook, USA)Jon Kotcher, Alessio D’Andragora, Lin Yao, (BNL, USA)
Backup SlidesBackup Slides
26
Path Towards VMM
VMM1 (2012)50 mm²
VMM2 (2014)115 mm²
VMM3 (2016, in fabrication)130 mm²
500k MOSFETs(8k/ch.)•mixed‐signal
h d
> 5M MOSFETs (>80k/ch.)• planned deep re‐design of VMM1•much higher functionality and
l it th VMM1
> 10M MOSFETs (>160k/ch.)• deeply revised front‐end for sTGC• L0 processorSEU l• 2‐phase readout
• no ADCscomplexity than VMM1• continuous fully‐digital readout• ADCs
• SEU‐tolerant• SLVS interface• additional functions• aims at pre‐productionsTGC specifications finalized
27
• aims at pre‐productionsTGC specifications finalized
Analog Front‐EndBLHBLH
bias
test
CA1 CA2 CA3 SH1 SH2 SH3
~ 4mm
• Programmable polarity and injection capacitor• Three‐stage charge amplification with programmable gain• Three‐stage shaping amplifier (DDF) with programmable peaking timeg p g p ( ) p g p g• Programmable baseline stabilizer (BLH)
28
sTGC Signals Specifications"make sure that the signal tails in the cathode readout are properlyincorporated into the simulation"[G. Mikenberg]
"for charges larger than 6 pC thefor charges larger than 6 pC the dead time increases and estimated to reach ~1 usec for 50 pC"[V. Polychronakos]
Design guidelines• accurate tail model• 6pC average
Design guidelines• accurate tail model• 6pC average• 60pCmax• 1MHz• 2nF
• 60pCmax• 1MHz• 2nF• analog recovery as fast as possible• analog recovery as fast as possible
29See also “sTGC analog requirements”: https://edms.cern.ch/document/1536160/1
sTGC Signal Simulation
charge ~ 95% in 12µs6pC
arge
rentg
~ 60% in 1.3µs
µ
cha
curr
Simulation of 6pC signal to 20µscurrent
• About 60% and 95% of charge collected in 1 3µs and 12µs respectively
time
• About 60% and 95% of charge collected in 1.3µs and 12µs respectively
30
Dynamic Discharge Circuit (DDC)negativeReset negativeReset
reset dynamic d h
bias
test
resetdischarge
• The dynamic discharge circuit (DDC) option combines the negative
positive
y g ( ) p g(used in negative charge mode) and positive (used in positive charge mode) reset in a single stabilizing circuit. The pole‐zero cancellation is fully preserved This circuit introduces a small increase in parallel noisefully preserved. This circuit introduces a small increase in parallel noise (~200 e‐ at 200ns).
31
AC Coupling with DDC
analog output, Qdet=6pC, 1MHz charge amplifier output
dc baselineude
ude
positive charge
dc baseline
amplitu
amplitu
negative charge
dc baseline
• For ac‐coupled sensors the charge amplifier output shift is contained
timetime
For ac coupled sensors the charge amplifier output shift is contained by the DDC.
32
Response to Very High Charge
analog output charge amplifierlit
ude
litud
e
Qdet 10pC to 60pC 60pC
poutputam
p
amp
Cdet 200pFGain 0.5mV/fC
60pC10pC
10pC
timetime
• Saturation of the charge amplifier extends to 2µs at 20pC and 6µs
p timetime
Saturation of the charge amplifier extends to 2µs at 20pC and 6µs at 60pC• Similar behavior is obtained for positive charges
33
Fast Recovery from High Charge
Front‐End AmplifierFRC
A B
Th f t i it (FRC) t ti t t t lifi• The fast recovery circuit (FRC) senses saturation state on two amplifier nodes (A, B) and enables a current source connected to the input node34
Response to Very High Charge with FRC
charge amplifieritu
de
itude analog output
Qd 10pC to 60pC60pC
poutput
ampl
ampl
Qdet 10pC to 60pCCdet 200pFGain 0.5mV/fC
60pC10pC10pC
•With the fast recovery circuit enabled, the saturation of the
10pC timetime
With the fast recovery circuit enabled, the saturation of the charge amplifier is reduced to 1.2µs at 20pC and 2µs at 60pC• Similar behavior is obtained for positive charges
35
Input Node Stability at Saturation
analog output charge amplifieritu
de
itude
Qd 10pC to 60pC
pinput
ampl
ampl
Qdet 10pC to 60pCCdet 200pFGain 0.5mV/fC
60pC 40mV
60pC10pC
• At 60pC the input voltage of the charge amplifier exhibits a short
10pC timetime
At 60pC the input voltage of the charge amplifier exhibits a short pulse of ~40mV. The virtual ground is recovered within 2µs• Similar behavior is obtained for positive charges
36
ENC at Minimum Gain
Unipolar ResponseGain 0.5 mV/fC
positive chargenegative charge
25nsENC
200ns
1nF100pF capacitance
37
ENC at Minimum Gain ‐ sfm/sbip
Tail‐Cancellation & Dynamic‐Discharge Response EnabledGain 0.5mV/fC
positive chargenegative charge
25ns
ENC
200ns
1nF100pF capacitance
38
