VO-final

8/4/2019 VO-final

1/140

Easwari Engineering college Department of Electronics and Instrumentation

1

EASWARI ENGINEERING COLLEGE,CHENNAI-600 089.

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

EI 2405 - VLSI LAB MANUAL

SYLLABUS

1. Study of Synthesis tools

Half and full adder.

Decoder 2 x 4, 3 x 8

Priority encoder.

Ripple adder.

4 Bit ripple counter.

Code conversion.

All the above synthesis in three modeling styles - data flow, structural and behavioral

2. Study of Simulation using tools

Half adder.

Multiplexer 2 x 1, 4 x 1

Demultiplexer 1 x 2, 1 x 4

All the above synthesis in three modeling styles - data flow, structural and behavioral

3. Study of Simulation using tools

Flipflop D, T

Priority encoder.

Ripple adder.

4 Bit ripple counter.All the above synthesis in three modeling styles - data flow, structural and behavioral

4. Study of development tool for FPGAs for schematic entry and verilog

Full adder, half adder.

Demultiplexer 1 x 2, 1 x 4.

5. Design and simulation of pipelined serial and parallel adder to add/ subtract 8

number of size, 12 bits each in 2's complement.

6. Place and Root and Back annotation for FPGAs

7. Design and simulation of back annotated verilog files for multiplying two signed, 8 bit

numbers in 2's complement.

8. Study of FPGA board and testing on board LEDs and switches using verilog code.

9. Design a Realtime Clock (2 digits, 7 segments LED displays each for HRS., MTS,

and SECS.) and demonstrate its working on the FPGA board. To display binary number

on the FPGA.

10. Design of traffic light controller using verilog tools .

Movement of vehicles in any direction or pedestrian in any direction.

8/4/2019 VO-final

2/140


2

CYCLE-1

1) Study Of Synthesis Tools-Gate realization2) Half Adder and Full Adder3) Decoder4) Priority Encoder5) Ripple Adder6) 4-bit Ripple counter7) Code conversion8) Study Of Simulation Using Tools for Half adder, Multiplex, De-multiplexer,9) D&T-Flip flop10) Study Of Development Tool For FPGA-Full and Half adder, De-multiplexer

CYCLE-2

11.)Design and Simulation of pipelined serial and parallel adder to add/subtract 8

number of size,12 bits each in 2s complement

12.)Study of place and root and back annotation for FPGAs.

13.) Design and Simulation of back annotated verilog files for multiplying two

signed 8 bit numbers in 2s complement

14.)Design And Testing Onboard Switches And LEDS In FPGA

15.)Design and Implementation of real time clock

16.) Design of traffic light controller using Verilog tool

8/4/2019 VO-final

3/140


3

INTRODUCTION

VLSI DESIGN FLOW

8/4/2019 VO-final

4/140


4

ASIC DESIGN FLOW

8/4/2019 VO-final

5/140


5

Ex No: 1 STUDY OF SYNTHESIS TOOLS

AIM:

To study the Synthesis tools.

THEORY:

Now that you have created the source files, verified the designs behavior with

simulation, and added constraints, you are ready to synthesize and implement the design.

IMPLEMENTING THE DESIGN:

1. Select the counter source file in the Sources in Project window.2. In the Processes for Source window, click the + sign next to Implement Design.

The Translate, Map, and Place & Route processes are displayed. Expand those

processes as well by clicking on the + sign. You can see that there are many sub-

processes and options that can be run during design implementation.

3. Double-click the top level Implement Design process.ISE determines the currentstate of your design and runs the processes needed to pull your design through

implementation. In this case, ISE runs the Translate, Map and PAR processes. Your

design is now pulled through to a placed-and-routed state. This feature is called the

pull through model.

4. After the processes have finished running, notice the status markers in the Processesfor Source window. You should see green checkmarks next to several of the

processes, indicating that they ran successfully. If there are any yellow exclamation

points, check the warnings in the Console tab or the Warnings tab within the

Transcript window. If a red X appears next to a process, you must locate and fix the

error before you can continue.

VERIFICATION OF SYNTHESIS:

Your synthesized design can be viewed as a schematic in the Register Transfer

Level (RTL) Viewer. The schematic view shows gates and elements independent of the

targeted Xilinx device.

8/4/2019 VO-final

6/140


6

1. In the Processes for Source window, double-click View RTL Schematic found in theSynthesize - XST process group. The top level schematic representation of your

synthesized design opens in the workspace.

2. Right-click on the symbol and select Push Into the Selected Instance to view theschematic in detail. The Design tab appears in the Sources in Project window,

enabling you to view the design hierarchy. In the schematic, you can see the design

components you created in the HDL source, and you can push into symbols to

view increasing levels of detail.

3. Close the schematic window.

Fig-1:FLOORPLANNER VIEW - DETAILED VIEW

8/4/2019 VO-final

7/140


7

Fig-2: DESIGN SUMMARY VIEW

RESULT: Thus the synthesis tool was studied.

Ex No: 1. (a) AND GATE REALISATION

AIM:

Realize the AND gate using Verilog.

TOOLS REQUIRED:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

THEORY:

AND Gate is a circuit which performs, one of the basic logical or switching

operation, namely AND operation. It has N inputs (N 2) and one output. Digital signals

are applied at the input terminals A, B, CN. The output is obtained at the output

terminal marked Y and it is also a digital signal. The AND operation is defined as: the

output of an AND gate is 1 if and only if all the inputs are 1. Mathematically, it is written

as

Y = A AND B AND C AND N

= A.B.C N

= ABCN

8/4/2019 VO-final

8/140


8

where A, B, C N are the input variables and Y is the output variable.

The variables are binary, i.e. each variable can assume only one of the possible values, 0

or 1. The binary variables are also referred to as logical variable. The mathematical

equation is known as the Boolean equation or the logical equation of the AND gate. The

term gate is used because of the similarity between the operation of a digital circuit and a

gate. For example, for an AND operation the gate opens (Y = 1) only, when all the inputs

are present.

PROCEDURE:

1. The Verilog Module Source for the AND Gate is written.

2. It is implemented in Model Sim and Simulated.

3. Signals are provided and Output Waveforms are viewed.

TRUTH TABLE

AND GATE

LOGIC DIAGRAM:

AND GATE BEHAVIORLEVEL DESIGN IN VERILOG

//*** AND Gate Behavior Level Design ***//module my_andbehavirvlog (y,a,b);output y;input a,b;

INPUT OUTPUT

A B QN+1

0

0

1

1

0

1

0

1

0

0

0

1

8/4/2019 VO-final

9/140


9

reg y;always @ (a or b)beginif (a == 1)begin

if (b == 1)

y = 1'b 1;else

y = 1'b 0;endelse

y = 1 'b 0;endendmodule

AND GATE IN GATELEVEL DESIGN IN VERILOG

//*** AND Gate in Gate Level Design ***//module my_andgatevlog (y,a,b);output y;

input a,b;and (y,a,b);endmodule

WAVEFORM:

8/4/2019 VO-final

10/140


10

CONCLUSION:

Thus the AND Gate is designed Verilog HDL and the output is verified

Ex No: 1. (b) OR GATE REALISATION

AIM:

Realize the OR gate using Verilog.

TOOLS REQUIRED:



THEORY:

OR Gate is a circuit which performs, one of the basic logical or switching

operation, namely the OR operation. It has N inputs (N 2) and one output. Digital

signals are applied at the input terminals A, B, CN. The output is obtained at the output

terminal marked Y and it is also a digital signal. The OR operation is defined as: the

output of an OR gate is 0 if and only if all the inputs are 0. Mathematically, it is written

as

8/4/2019 VO-final

11/140


11

Y = A OR B OR C ORN

= A+B+C +N

where A, B, C N are the input variables and Y is the output variable.

The variables are binary, i.e. each variable can assume only one of the possible values, 0

or 1. The binary variables are also referred to as logical variable. The mathematical

equation is known as the Boolean equation or the logical equation of the OR gate. The

term gate is used because of the similarity between the operation of a digital circuit and a

gate. For example, for an OR operation the gate closes (Y = 0) only, when all the inputs

are absent.

PROCEDURE:

1. The Verilog Module Source for the OR Gate is written.2. It is implemented in Model Sim and Simulated.3. Signals are provided and Output Waveforms are viewed.

OR GATE:

TRUTH TABLE:

LOGIC DIAGRAM:

PROGRAM:

OR GATE BEHAVIORLEVEL DESIGN IN VERILOG

// *** OR Gate Behavior Level *** //

INPUT OUTPUT

A B QN+1

0

0

1

1

0

1

0

1

0

1

1

1

8/4/2019 VO-final

12/140


12

module my_orbehaviorvlog (y,a,b);output y;input a,b;reg y;always @ (a or b)begin

if (a == 0)begin

if (b == 0)y = 1 'b 0;

elsey = 1 'b 1;

endelse

y = 1 'b1;endendmodule

OR GATE IN GATELEVEL DESIGN IN VERILOG

// *** OR Gate in Verilog *** //

module my_orgatevlog (y,a,b);

output y;

input a,b;

or (y,a,b);endmodule

WAVEFORM:

8/4/2019 VO-final

13/140


13

CONCLUSION:

Thus the OR Gate is designed Verilog HDL and the output is verified.

Ex No: 1. (c) NOT GATE REALISATIONAIM:

Realize the NOT gate using Verilog.

TOOLS REQUIRED:

Synthesis tool: Xilinx ISE.Simulation tool: ModelSim Simulator

THEORY:

NOT Gate is a circuit which performs, the one of the basic logic or Boolean

operation, namely the NOT operation. It has one input and one output. Digital signal is

applied at the input terminal A. The output is obtained at the output terminal marked Y

and it is also a digital signal. The NOT operation is referred to as Inversion or

Complementation. Mathematically, it is written as

Y = NOT A.

= A

where A is the input variable and Y is the output variable. The variables

are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The

binary variables are also referred to as logical variable. The mathematical equation is

8/4/2019 VO-final

14/140


14

known as the Boolean equation or the logical equation of the NOT gate. This is to be read

as Y equals NOT A or Y equals complement of A.

PROCEDURE:

1. The Verilog Module Source for the NOT Gate is written.



TRUTH TABLE:

NOT

LOGIC DIAGRAM:

PROGRAM:

NOT GATE BEHAVIORLEVEL DESIGN IN VERILOG

// *** NOT Gate Behavior Leve *** //

module my_notbehaviorvlog (y,a);

output y;

input a;

reg y;

always @ (a)

begin

if (a == 0)y = 1 'b 1;

else

y = 1 'b 0;

end

endmodule

NOT GATE IN GATELEVEL DESIGN IN VERILOG

INPUT OUTPUT

a y

0

1

1

0

8/4/2019 VO-final

15/140


15

// *** NOT Gate in Gate Level Design *** //

module my_notgate (y,a);

output y;

input a;

not(y,a);

endmoduleWAVEFORM:

CONCLUSION:

Thus the NOT Gate is designed in Verilog HDL and the output is verified.

Ex No: 1. (d) NAND GATE REALISATION

AIM:

Realize the NAND gate using Verilog.

TOOLS REQUIRED:



THEORY:

NAND Gate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operations NOT and AND, namely the NAND operation. It has N

inputs (N 2) and one output. Digital signals are applied at the input terminals A, B,

CN. The output is obtained at the output terminal marked Y and it is also a digital

signal. The NAND operation is defined as: the output of an NAND gate is 0 if and only if

all the inputs are 1. It is the inverse of the AND operation. The NAND gate is known to

be one of the Universal gates. Mathematically, it is written as

Y = A B N

where A, B, C N are the input variables and Y is the output variable. The

variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1.

8/4/2019 VO-final

16/140


16

The binary variables are also referred to as logical variable. The mathematical equation is

known as the Boolean equation or the logical equation of the NAND gate. The term gate

is used because of the similarity between the operation of a digital circuit and a gate. For

example, for an NAND operation the gate closes (Y = 0) only, when all the inputs are

present.

PROCEDURE:

1. The Verilog Module Source for the NAND Gate is written.



TRUTH TABLE:

NAND

LOGIC DIAGRAM:

PROGRAM:

NAND GATE BEHAVIORLEVEL DESIGN IN VERILOG

// *** NAND Gate Behavior Level *** //module my_nandbehaviorvlog (y,a,b);

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

1

1

0

8/4/2019 VO-final

17/140


17

output y;input a,b;reg y;always @ (a or b)beginif ( a==1)

beginif (b==1)

y = 1 'b 0;else

y = 1 'b 1;endelse

y = 1 'b1;endendmodule

NAND GATE IN GATELEVEL DESIGN IN VERILOG

// *** NAND gate in Gate Level *** //

module my_nandgatevlog (y,a,b);

output y;

input a,b;nand (y,a,b);

endmodule

WAVEFORM:

8/4/2019 VO-final

18/140


18

CONCLUSION:

Thus the NAND Gate is designed in Verilog HDL and the output is verified.

8/4/2019 VO-final

19/140


19

Ex No: 1. (e) NOR GATE REALISATIONAIM:

Realize the NOR gate using Verilog.

TOOLS REQUIRED:



THEORY:

NOR Gate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operations NOT and OR, namely the NOR operation. It has N inputs

(N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The

output is obtained at the output terminal marked Y and it is also a digital signal. The

NOR operation is defined as: the output of an

NOR gate is 1 if and only if all the inputs

are 0. It is the inverse of the OR operation. The NOR gate is known to be one of the

Universal gates. Mathematically, it is written as

Y = A +B+ +N




known as the Boolean equation or the logical equation of the NOR gate. The term gate is

used because of the similarity between the operation of a digital circuit and a gate. For

example, for an NOR operation the gate opens (Y = 1) only, when all the inputs are

absent.

PROCEDURE:

1. The Verilog Module Source for the NOR Gate is written.



8/4/2019 VO-final

20/140


20

TRUTH TABLE:

NOR:

LOGIC DIAGRAM:

PROGRAM:

NOR GATE BEHAVIORLEVEL DESIGN IN VERILOG

// *** NOR Gate Behavior Level *** //

module my_norbehaviorvlog (y,a,b);

output y;

input a,b;reg y;

always @ (a or b)

begin

if (a == 0)

begin

if (b == 0)

y = 1 'b 1;

else

y = 1 'b 0;

endelse

y = 1 'b 0;

end

endmodule

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

0

0

0

8/4/2019 VO-final

21/140


21

NOR GATE IN GATELEVEL DESIGN IN VERILOG

// *** NOR Gate in verilog *** //

module my_norgatevlog (y,a,b);

output y;input a,b;

nor (y,a,b);

endmodule

WAVEFORM

CONCLUSION:

Thus the NOR Gate is designed Verilog HDL and the output is verified.

8/4/2019 VO-final

22/140


22

Ex No: 1. (f) XNOR GATE REALISATION

AIM:

Realize the XNOR gate using Verilog.

TOOLS REQUIRED:Synthesis tool: Xilinx ISE.


THEORY:

XNOR Gate or EX-NOR Gate or Exclusive-NOR Gate is a circuit which

performs, the logic or Boolean operation derived from the basic logic operations AND,

OR and NOT or the Universal gates NAND orNOR, namely the XNOR operation. It has

N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B,

CN. The output is obtained at the output terminal marked Y and it is also a digital

signal. The XNOR operation is defined as: the output of an XNOR gate is 1 if all the

inputs are same, whereas the output is 0, if the inputs are not the same. It is the inverse of

the NOR gate. Mathematically, it is written as

Y = A EX-NOR B

= A B




known as the Boolean equation or the logical equation of the XNOR gate. The term gate

is used because of the similarity between the operation of a digital circuit and a gate. For

example, for an XNOR operation the gate opens (Y = 1) only, when all the inputs are not

same.

PROCEDURE:

1. The Verilog Module Source for the XNOR Gate is written.



X

8/4/2019 VO-final

23/140


23

TRUTH TABLE:

XNOR

LOGIC DIAGRAM:

PROGRAM:

XNOR GATE BEHAVIORLEVEL DESIGN IN VERILOG

// *** XNOR Gate Behavior Level *** //

module my_xnorbehaviorvlog (y,a,b);

output y;

input a,b;

reg y;

always @ (a or b)

beginif (a === b)

y = 1 'b 1;

else

y = 1 'b 0;

end

endmodule

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

0

0

1

8/4/2019 VO-final

24/140


24

NOR GATE IN GATELEVEL DESIGN IN VERILOG

// *** XNOR Gate in Gate Level Design *** //

module my_xnorgatevlog (y,a,b);

output y;

input a,b;

xnor (y,a,b);endmodule

WAVEFORM:

CONCLUSION:

Thus the XNOR Gate is designed in Verilog HDL and the output is verified.

8/4/2019 VO-final

25/140


25

Ex No: 2. (a) HALF ADDER REALISATION

AIM:

Realize the half adder using Verilog.

TOOLS REQUIRED:



THEORY:

A combinational circuit that performs the addition of two bits is called a half-

adder. This circuit needs two binary inputs and produces two binary outputs. One of the

input variables designates the augend and other designates the addend. The output

variables produce the sum and the carry.The simplified Boolean functions of the two outputs can be obtained as below:

Sum S = xy + xy

Carry C = xy

Where x and y are the two input variables.

PROCEDURE:

1. The half-adder circuit is designed and the Boolean function is found out.2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

TRUTH TABLE:

HALF ADDER

INPUT OUTPUT

A B SUM CARRY

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

8/4/2019 VO-final

26/140


26

LOGIC DIAGRAM:

PROGRAM:

HALF ADDER DESIGN IN VERILOG

// *** Half Adder *** //

module my_halfadrvlog (s,c,x,y);

output s,c;

input x,y;

xor (s,x,y);

and (c,x,y);

endmodule

HALF ADDER DESIGN IN VERILOG(Behavioral model)

module half_adder(S, C, A, B);

output S, C;

input A, B;

wire S, C, A, B;

assign S = A ^ B;

assign C = A & B;endmodule

WAVEFORM:

CONCLUSION:

Thus the Half Adder is designed in Verilog HDL and the output is verified.

8/4/2019 VO-final

27/140


27

Ex No: 2. (b) FULL ADDER REALISATION

AIM:

Realize the full adder using Verilog.

TOOLS REQUIRED:



THEORY:

A combinational circuit that performs the addition of three bits is called a

half-adder. This circuit needs three binary inputs and produces two binary outputs. One

of the input variables designates the augend and other designates the addend. Mostly, the

third input represents the carry from the previous lower significant position. The output

variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as

below:

Sum S = x y z

Carry C = xy + xz + yz

Where x, y & z are the two input variables.

PROCEDURE:

1. The full-adder circuit is designed and the Boolean function is found out.

2. The Verilog Module Source for the circuit is written.



TRUTH TABLE:

FULL ADDER

INPUT OUTPUT

A B CIN SUM CARRY

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

+ +

8/4/2019 VO-final

28/140


28

LOGIC DIAGRAM:

PROGRAM: FULL ADDER DESIGN IN VERILOG

// *** Full Adder *** //

module my_fuladrvlog (s,c,x,y,z);

output s,c;

input x,y,z;

xor (s,x,y,z);

assign c = ((x & y) | (y & z) | (z & x));

endmodule

WAVEFORM:

CONCLUSION:

Thus the Full Adder is designed Verilog HDL and the output is verified.

8/4/2019 VO-final

29/140


29

Ex No: 3. IMPLEMENTATION OF 2 x 4 and 3 x 8 DECODER

AIM:

To implement 2 x 4 and 3 x 8 Decoder Verilog HDL.

TOOLS REQUIRED:Synthesis tool: Xilinx ISE.


PROCEDURE:

1. Write and draw the Digital logic system.2. Write the Verilog code for above system.3. Enter the Verilog code in Xilinx software.4. Check the syntax and simulate the above verilog code (using ModelSim or

Xilinx) and verify the output waveform as obtained.

LOGIC DIAGRAM:

2 to 4 Decoder:

PROGRAM: 2 TO 4DECODER DESIGN IN VERILOG

// Module Name: Decd2to4

module Decd2to4(i0, i1, out0, out1, out2, out3);

input i0;

input i1;

output out0;

output out1;

output out2;

output out3;

reg out0,out1,out2,out3;

always@(i0,i1)

case({i0,i1})

2'b00: {out0,out1,out2,out3}=4'b1000;

2'b01: {out0,out1,out2,out3}=4'b0100;

2'b10: {out0,out1,out2,out3}=4'b0010;

8/4/2019 VO-final

30/140


30

2'b11: {out0,out1,out2,out3}=4'b0001;

default: $display("Invalid");

endcase

endmodule

Output:

2to4 Decoder

WAVEFORM:

3 TO 8 DECODER REALIZATION IN VERILOG

THEORY:

A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of 2n unique output lines. It performs the reverse operation of

the encoder. If the n-bit decoded information has unused or dont-care combinations, the

decoder output will have fewer than 2n outputs. The decoders are represented as n-to-m

line decoders, where m 2n. Their purpose is to generate the 2n (or fewer) minterms of n

input variables. The name decoder is also used in conjunction with some code converterssuch as BCD-to-seven-segment decoders. Most, if not all, IC decoders include one or

more enable inputs to control the circuit operation. A decoder with an enable input can

function as a de-multiplexer.

INPUT OUTPUT

00

01

10

11

1000

0100

0010

0001

8/4/2019 VO-final

31/140


31

PROCEDURE:

1. The decoder circuit is designed and the Boolean function is found out.




-------INPUT-------- ------------------------ DECIMAL (OUTPUT)---------------------

C B A i1 i2 i3 i4 i5 i6 i7 i8

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

8/4/2019 VO-final

32/140


32

3 to 8 DECODER DESIGN IN VERILOG:

module my_decodr(d,x);output [0:7] d;input [0:2] x;wire [0:2] temp;

not n1(temp[0],x[0]);not n2(temp[1],x[1]);not n3(temp[2],x[2]);and a0(d[0],temp[0],temp[1],temp[2]);and a1(d[1],temp[0],temp[1],x[2]);and a2(d[2],temp[0],x[1],temp[2]);and a3(d[3],temp[0],x[1],x[2]);and a4(d[4],x[0],temp[1],temp[2]);and a5(d[5],x[0],temp[1],x[2]);and a6(d[6],x[0],x[1],temp[2]);and a7(d[7],x[0],x[1],x[2]);endmodule

CONCLUSION:

Thus the logic circuit for the 2 to 4 Decoder and 3 to 8 decoder are designed in

Verilog HDL and the outputs are verified.

8/4/2019 VO-final

33/140


33

Ex No: 4 4 TO 2 ENCODER REALIZATION IN VERILOG

AIM:

Realize the 4 to 2 Encoder in Verilog

TOOLS REQUIRED:


Simulation tool: ModelSim Simulator;

THEORY:

An encoder has 2n (or fewer) input lines and n output lines. The output

lines generate the binary code corresponding to the input value. In encoders, it is assumed

that only one input has a value of 1 at any given time. The encoders are specified as m-to-

n encoders where m 2n.

PROCEDURE:

1. The encoder circuit is designed and the Boolean function is found out.




LOGIC DIAGRAM:

8/4/2019 VO-final

34/140


34

TRUTH TABLE:

I/P 0 I/P1 I/P 2 I/P3 O/P0 O/P1

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

4 TO 2 ENCODER DESIGN IN VERILOG

// *** 4x2 Encoder Behavior Level Realisation *** //module my_encodr2 (y,x);output [0:3] y;input [0:3] x;

reg [0:1] y;always @ (x)case (x)

4'b0001: y = 11;4'b0010: y = 10;4'b0100: y = 01;4'b1000: y = 00;default : $display ("Invalid Input");

endcaseendmodule

8/4/2019 VO-final

35/140


35

WAVEFORM:

CONCLUSION:

Thus the logic circuit for the 4 to 2 encoder is designed in Verilog HDL and the

output is verified.

8/4/2019 VO-final

36/140


36

Ex No: 5 RIPPLE ADDER REALIZATION IN VERILOG

AIM:

To Design Ripple Adder using Verilog.

TOOLS REQUIRED:



THEORY:

The n-bit adder built from n one bit full adders is known as ripple carry

adder because of the carry is computed. The addition is not complete until n-1th adder

has computed its Sn-1 output; that results depends upon ci input, n and so on down the

line, so the critical delay path goes from the 0-bit inputs up through cis to the n-1

bit.(We can find the critical path through the n-bit adder without knowing the exact logic

in the full adder because the delay through the n-bit adder without knowing the exact

logic in the full adder because the delay through the n-bit carry chain is so much longer

than the delay from a and b to s). The ripple-carry adder is area efficient and easy to

design but it is when n is large.It can also be called as cascaded full adder.

The simplified Boolean functions of the two outputs can be obtained as below:

Sum si = ai xor bi xor ciCarry ci+1 = aibi +bi ci +ai ci

Where x, y & z are the two input variables.

PROCEDURE:

1. The ripple carry generator circuit is designed and the Boolean function is

found out.

2. The full-adder circuit is designed and the Boolean function is found out.




8/4/2019 VO-final

37/140


37

VERILOG PROGRAM FOR RIPPLECARRY ADDER:

module ripplecarry_adder(s,cout,a,b,cin); //port listoutput [5:0] s;

output cout;// port declarationinput [5:0] a,b;input cin;wire c0,c1,c2,c3,c4;

// instantiating 1b-ti full addersfulladder_1bit fulladder_1bit_f1(s[0],c0,a[0],b[0],cin);fulladder_1bit fulladder_1bit_f2(s[1],c1,a[1],b[1],c0);fulladder_1bit fulladder_1bit_f3(s[2],c2,a[2],b[2],c1);fulladder_1bit fulladder_1bit_f4(s[3],c3,a[3],b[3],c2);fulladder_1bit fulladder_1bit_f5(s[4],c4,a[4],b[4],c3);fulladder_1bit fulladder_1bit_f6(s[5],cout,a[5],b[5],c4);endmodule

module fulladder_1bit(sum,cout,in1,in2,cin);output cout;output sum;input in1,in2,cin;assign {cout,sum}= in1 + in2 + cin; // through data flow modeling.Endmodule

LOGIC DIAGRAM:

8/4/2019 VO-final

38/140


38

WAVE FORM:

CONCLUSION:

Thus the logic circuit for the ripple carry adder is designed in Verilog HDL and

the output is verified.

8/4/2019 VO-final

39/140


39

Ex No: 6(a) 4 BIT ASYNCHRONOUS RIPPLECOUNTER

REALIZATION IN VERILOG

AIM:

To realize an asynchronous ripple counter in Verilog .

TOOLS REQUIRED:



THEORY:

In a ripple counter, the flip-flop output transition serves as a source for

triggering other flip-flops. In other words, the Clock Pulse inputs of all flip-flops (except

the first) are triggered not by the incoming pulses, but rather by the transition that occurs

in other flip-flops. A binary ripple counter consists of a series connection of

complementing flip-flops (JK or T type), with the output of each flip-flop connected to

the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the LSB

receives the incoming count pulses. All J and K inputs are equal to 1. The small circle in

the Clock Pulse /Count Pulse indicates that the flip-flop complements during a negative-

going transition or when the output to which it is connected goes from 1 to 0. The flip-

flops change one at a time in rapid succession, and the signal propagates through the

counter in a ripple fashion. A binary counter with reverse count is called a binary down-

counter. In binary down-counter, the binary count is decremented by 1 with every input

count pulse.

PROCEDURE:

1. The 4 bit asynchronous ripple counter circuit is designed.




8/4/2019 VO-final

40/140


40

LOGIC DIAGRAM:

STATE TABLE:

TRUTH TABLE FOR JK FLIP-FLOP:

J K Qn+1

0

0

1

1

0

1

0

1

Qn

0

1

Qn

4-BIT ASYNCHRONOUS RIPPLECOUNTER DESIGN IN VERILOG

module my_asyncbincnt (q,qbar,clk,reset);output [0 : 3] q;

output [0 : 3] qbar;input clk,reset;wire [0 : 1] temp;reg high;initialhigh = 1'b1;my_jkffbehaviorvlog ff1 (q[0],qbar[0],high,high,clk,reset);my_jkffbehaviorvlog ff2 (q[1],qbar[1],high,high,q[0],reset);

8/4/2019 VO-final

41/140


41

my_jkffbehaviorvlog ff3 (q[2],qbar[2],high,high,q[1],reset);my_jkffbehaviorvlog ff4 (q[3],qbar[3],high,high,q[2],reset);endmodulemodule my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);output q,qbar;input j,k,clk,reset;

reg q,qbar;always @ (negedge clk or reset)if (~reset)begin

q = 1'b0;qbar = 1'b1;

endelse if (reset)begin

if (j==0 && k ==0)begin

q = q;qbar = qbar;

endelse if ( j== 0 && k ==1)begin

q = 1'b0;qbar = 1'b1;

endelse if (j==1 && k == 0)begin

q = 1'b1;qbar = 1'b0;

endelse if (j ==1 && k ==1)begin

q = ~q;qbar = ~qbar;

endelsebegin

q = 1'bz;qbar = 1'bz;

endend

endmodule;

8/4/2019 VO-final

42/140


42

WAVEFORMS:

IN BINARY

IN DECIMAL

CONCLUSION:

Thus the asynchronous ripple counter is designed in Verilog HDL and the output

is verified.

8/4/2019 VO-final

43/140


43

Ex No:6 (b) 4 BIT SYNCHRONOUS RIPPLECOUNTER

REALIZATION IN VERILOGAIM:

To realize a synchronous ripple counter in Verilog.

TOOLS REQUIRED:



THEORY:

Synchronous counters are distinguished from asynchronous counters in that clock

pulses are applied to the CP inputs of all flip-flops. The common pulse triggers all the

flip-flops simultaneously, rather than one at a time in succession as in asynchronous

counter. The decision whether a flip-flop is to be complemented or not is determined

from the values of the J and K inputs at the time of the pulse. If J = K = 0, the flip-flop

remains unchanged. If J = K = 1, the flip-flop complements. In a synchronous binary

ripple counter, the flip-flop in the lowest-order position is complemented with very pulse.

This means that its J and K inputs must be maintained at logic-1. A flip-flop in any other

position is complemented with a pulse provided all the bits in the lower-order positions

are equal to 1, because the lower-order bits (when all 1s) will change to 0s on the next

count pulse. The binary count dictates the next higher-order bit is complemented.Synchronous binary counters have a regular pattern and can easily be constructed with

complementing flip-flops ( J K or T Type) and gates.

PROCEDURE:

1. The 4 bit synchronous ripple counter circuit is designed.2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

44/140


44

LOGIC DIAGRAM:

STATE TABLE:

TRUTH TABLE FOR JK FLIP-FLOP:

J K Qn+10

0

1

1

0

1

0

1

Qn

0

1

Qn

8/4/2019 VO-final

45/140


45

4-BIT SYNCHRONOUS RIPPLECOUNTER DESIGN IN VERILOG

module my_syncbincnt (q,qbar,load,clk,reset);output [0 : 3] q;output [0 : 3] qbar;input load,clk,reset;

wire [0 : 1] temp;my_jkffbehaviorvlog ff1 (q[0],qbar[0],load,load,clk,reset);my_jkffbehaviorvlog ff2 (q[1],qbar[1],q[0],q[0],clk,reset);and (temp[0],q[0],q[1]);my_jkffbehaviorvlog ff3 (q[2],qbar[2],temp[0],temp[0],clk,reset);and (temp[1],q[2],q[0],q[1]);my_jkffbehaviorvlog ff4 (q[3],qbar[3],temp[1],temp[1],clk,reset);endmodule

module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);output q,qbar;input j,k,clk,reset;reg q,qbar;always @ (negedge clk or reset)if (~reset)begin

q = 1'b0;qbar = 1'b1;

endelse if (reset)begin

if (~clk)begin

if (j==0 && k ==0)beginq = q;qbar = qbar;

endelse if ( j== 0 && k ==1)begin

q = 1'b0;qbar = 1'b1;

endelse if (j==1 && k == 0)begin

q = 1'b1;qbar = 1'b0;endelse if (j ==1 && k ==1)begin


endelse

8/4/2019 VO-final

46/140


46

beginq = 1'bz;qbar = 1'bz;

endend

end

endmodule;

WAVEFORMS:

CONCLUSION:

Thus the synchronous ripple counter is designed in Verilog HDL and the output is

verified.

8/4/2019 VO-final

47/140


47

Ex No: 7(a) CODECONVERSION

BCD TO DECIMAL DECODER REALIZATION IN VERILOG

AIM:

Realize the BCD to Decimal decoder in Verilog.

TOOLS REQUIRED:


Simulation tool: ModelSim Simulator;

THEORY:

A BCD to decimal decoder is a combinational circuit that converts binary

information from n input lines to a maximum of 2n unique output lines. It performs the

reverse operation of the encoder. If the n-bit decoded information has unused or dont-

care combinations, the decoder output will have fewer than 2n outputs. The decoders are

represented as n-to-m line decoders, where m 2n. Their purpose is to generate the 2n

(or fewer) minterms of n input variables. The name decoder is also used in conjunction

with some code converters such as BCD-to-seven-segment decoders. Most, if not all, IC

decoders include one or more enable inputs to control the circuit operation. A decoder

with an enable input can function as a de-multiplexer.

PROCEDURE:

1. The BCD to decimal decoder circuit is designed .2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

48/140


48

TRUTH TABLE:

-------INPUT-------- ------------------------ DECIMAL (OUTPUT)---------------------

X3 X2 X1 X0 D0 D1 D2 D3 D4 D5 D6 D7 D8

0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 1 1 0 0 0 0 0 0 0 0

2 0 0 1 0 0 1 0 0 0 0 0 0 0

3 0 0 1 1 0 0 1 0 0 0 0 0 0

4 0 1 0 0 0 0 0 1 0 0 0 0 0

5 0 1 0 1 0 0 0 0 1 0 0 0 0

6 0 1 1 0 0 0 0 0 0 1 0 0 0

7 0 1 1 1 0 0 0 0 0 0 1 0 0

8 1 0 0 0 0 0 0 0 0 0 0 1 0

9 1 0 0 1 0 0 0 0 0 0 0 0 1

8/4/2019 VO-final

49/140


49

LOGIC DIAGRAM:

PROGRAM:

module bcd(x, d);output[0:9] d;input[0:3] x;

wire [0:3]temp;not n1 (temp[0],x[0]);not n2 (temp[1],x[1]);not n3 (temp[2],x[2]);not n4 (temp[3],x[3]);and a0 (d[0],temp[0],temp[1],temp[2],temp[3]);and a1 (d[1],temp[0],temp[1],temp[2],x[3]);and a2 (d[2],temp[0],temp[1],x[2],temp[3]);and a3 (d[3],temp[0],temp[1],x[2],x[3]);

and a4 (d[4],temp[0],x[1],temp[2],temp[3]);and a5 (d[5],temp[0],x[1],temp[2],x[3]);and a6 (d[6],temp[0],x[1],x[2],temp[3]);and a7 (d[7],temp[0],x[1],x[2],x[3]);and a8 (d[8],x[0],temp[1],temp[2],temp[3]);and a9 (d[9],x[0],temp[1],temp[2],x[3]);

endmodule

X0X1X3 X2

8/4/2019 VO-final

50/140


50

WAVE FORM:

CONCLUSION:

Thus the logic circuit for the BCD to decimal decoder is designed in Verilog HDL

and the output is verified.

8/4/2019 VO-final

51/140


51

Ex No: 7(b) DECIMAL TO BCD ENCODER REALIZATION IN VERILOG

AIM:

Realize the Decimal to BCD encoder in Verilog.

TOOLS REQUIRED:



THEORY:

An encoder is a digital circuit that performs the inverse operation of a decoder.

An encoder 2^n input lines and n output lines. In encoder the output lines generate the

binary code corresponding to the input lines the decimal to BCD encoder, it has ten

input lines and four output lines. Both input and output lines are asserted active low. It is

important to note that there is no input line for decimal zero.

PROCEDURE:

1. The decimal to BCD encoder is designed.

2. The verilog HDL program source code for the circuit is written.

3. It is implemented in Model sim and simulated.

4. Signals are provided and output waveforms are viewed.

8/4/2019 VO-final

52/140


52

TABLE TRUTH

------------------------ DECIMAL (INPUT)--------------------- -------OUTPUT------

i1 i2 i3 i4 i5 i6 i7 i8 i9 D C B A

0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0 0 1

2 0 1 0 0 0 0 0 0 0 0 0 1 0

3 0 0 1 0 0 0 0 0 0 0 0 1 1

4 0 0 0 1 0 0 0 0 0 0 1 0 0

5 0 0 0 0 1 0 0 0 0 0 1 0 1

6 0 0 0 0 0 1 0 0 0 0 1 1 0

7 0 0 0 0 0 0 1 0 0 0 1 1 1

8 0 0 0 0 0 0 0 1 0 1 0 0 0

9 0 0 0 0 0 0 0 0 1 1 0 0 1

8/4/2019 VO-final

53/140


53

LOGIC DIAGRAM:

PROGRAM:

module encod(i1,i2,i3,i4,i5,i6,i7,i8,i9, a,b,c,d);input i1,i2,i3,i4,i5,i6,i7,i8,i9;output a,b,c,d;

or (a,i1,i3,i5,i7,i9);or (b,i2,i3,i6,i7);

or (c,i4,i5,i6,i7);or (d,i8,i9);endmodule

CONCLUSION:

Thus the logic circuit for the decimal to BCD encoder is designed in Verilog HDL

and the output is verified.

8/4/2019 VO-final

54/140


54

Ex No: 7. (c) UNIVERSALCODECONVERTER REALIZATION IN

VERILOG

AIM:

Realize the universal code converter in Verilog.

TOOLS REQUIRED:


Simulation tool: ModelSim Simulator.

THEORY:

The availability of a large variety of codes for the same discrete elements

of information results in the use of different codes by different digital system. It is

sometimes necessary to use the output of one system as the input to another. A

conversion circuit must be inserted between the two systems if each uses different codes

for the same information. Thus, a code converter is a circuit that makes the two systems

compatible even though each uses a different binary code. To convert from binary code A

to binary code B, the input lines must supply the bit combination of elements as specified

by code A and the output lines must generate the corresponding bit combination of code

B. A combinational circuit which performs this transformation by means of logic gates, is

known to be Code Converter.

PROCEDURE:

1. The various code converter circuits are designed and their Booleanfunctions are found out.

2. The Verilog Module Sources for the circuits are written.3. They are implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

55/140


55

LOGIC DIAGRAMS:

BINARY TO BCD CONVERTER

BCD TO BINARYCONVERTER

8/4/2019 VO-final

56/140


56

BCD TO XS3 CONVERTER

XS3 TO BCD CONVERTER

8/4/2019 VO-final

57/140


57

BINARY TO GRAYCONVERTER

GRAY TO BINARY CONVERTER

8/4/2019 VO-final

58/140


58

TRUTH TABLES:

BINARY TO BCD CONVERTER BCD TO BINARYCONVERTER

BCD CODE BINARY CODE

B4 B3 B2 B1 B0 F E C B A

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BINARY CODE BCD CODE

D C B A B4 B3 B2 B1 B0

0

0

0

0

0

0

0

0

11

1

1

1

1

1

1

0

0

0

0

1

1

1

1

00

0

0

1

1

1

1

0

0

1

1

0

0

1

1

00

1

1

0

0

1

1

0

1

0

1

0

1

0

1

01

0

1

0

1

0

1

0

0

0

0

0

0

0

0

00

1

1

1

1

1

1

0

0

0

0

0

0

0

0

11

0

0

0

0

0

0

0

0

0

0

1

1

1

1

00

0

0

0

0

1

1

0

0

1

1

0

0

1

1

00

0

0

1

1

0

0

0

1

0

1

0

1

0

1

01

0

1

0

1

0

1

8/4/2019 VO-final

59/140


59

BCD to XS3 Converter XS3 to BCD Converter

BCD CODE EXCESS 3

CODE

B3 B2 B1 B0 E3 E2 E1 E0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

BINARY TO GRAYCONVERTER GRAY TO BINARY

CONVERTER

BINARY CODE GRAY CODE

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

11

1

1

0

0

0

0

1

1

1

1

0

0

0

0

11

1

1

0

0

1

1

0

0

1

1

0

0

1

1

00

1

1

0

1

0

1

0

1

0

1

0

1

0

1

01

0

1

0

0

0

0

0

0

0

0

1

1

1

1

11

1

1

0

0

0

0

1

1

1

1

1

1

1

1

00

0

0

0

0

1

1

1

1

0

0

0

0

1

1

11

0

0

0

1

1

0

0

1

1

0

0

1

1

0

01

1

0

EXCESS 3

CODE

BCD CODE

E3 E2 E1 E0 B3 B2 B1 B0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

11

1

1

0

0

0

0

1

1

1

1

1

1

1

1

00

0

0

0

0

1

1

1

1

0

0

0

0

1

1

11

0

0

0

1

1

0

0

1

1

0

0

1

1

0

01

1

0

0

0

0

0

0

0

0

0

1

1

1

1

11

1

1

0

0

0

0

1

1

1

1

0

0

0

0

11

1

1

0

0

1

1

0

0

1

1

0

0

1

1

00

1

1

0

1

0

1

0

1

0

1

0

1

0

1

01

0

1

8/4/2019 VO-final

60/140


60

CODECONVERTERS DESIGN IN VERILOG:

// *** Code Converterts Design *** //module my_codeconvertrvlog (op,ip);

output [4 : 0] op;input [4 : 0] ip;reg [4 : 0] op;integer choice;initialchoice = 1'd0;always @ (choice or ip)begincase (choice)

0 :begin

$display ("Enter UR Choice ");$display (" 1'd1 For Binary to BCD");$display (" 1'd2 For BCD to Binary");$display (" 1'd3 For BCD to Excess 3");$display (" 1'd4 For Excess3 to BCD");$display (" 1'd5 For Binary to Gray");$display (" 1'd6 For Gray to Binary");

end1 :

beginop[0] = ip[0];

op[1] = (ip[3] & ip[2] & (~ip[1]) | ((~ip[3]) & ip[1]));op[2] = ((~ip[3]) & ip[2]) | (ip[2] & ip[1]);op[3] = ip[3] & (~ip[2]) & (~ip[1]);op[4] = (ip[3] & ip[2]) | (ip[3] & ip[1]);

end2 :

beginop[0] = ip[0];op[1] = ip[1] ^ ip[4];op[2] = ((~ip[4]) & ip[2]) | (ip[2] & (~ip[1])) | (ip[4] &

(~ip[2]) & ip[1]);op[3] = ((~(ip[4]) & ip[3]) | (ip[4] & (~(ip[3])) & (~ (ip[2]))) |

(ip[4] & (~(ip[3])) & (~ (ip[1]))));op[4] = ((ip[4] & ip[3]) | (ip[4] & ip[2] & ip[1]));end

3 :begin

op[0] = (~(ip[0]));op[1] = (~ (ip[0]^ip[1]));op[2] = ((ip[2])&(~ip[1])&(~ip[0])) |

((~(ip[2])&(ip[0]|ip[1])));

8/4/2019 VO-final

61/140


61

op[3] = ip[3] | (ip[2] & ( ip[0] | ip[1]));op[4] = 1'b 0;

end4 :

beginop[0] = ~(ip[0]);

op[1] = (ip[0]îp[1]);op[2] = (( ( (~(ip[2]))&(~(ip[1])))) | (ip[2]&ip[1]&ip[0]) |

(ip[3] & ip[1] & (~(ip[0]))));op[3] = ( (ip[3]&ip[2]) | (ip[3]&ip[1]&ip[0]));op[4] = 1'b 0;

end5 :

beginop[0] = (ip[1] ^ ip[0]);op[1] = (ip[2] ^ ip[1]);op[2] = (ip[3] ^ ip[2]);op[3] = ip[3];op[4] = 1'b 0;

end6 :

beginop[0] = ((ip[3]îp[2])^(ip[1]îp[0]));op[1] = ip[3]îp[2]îp[1];op[2] = ip[3]îp[2];op[3] = ip[3];op[4] = 1'b 0;

enddefault :

begin $display ("Entered a Wrong Option");$display ("To Know the choices Enter 1'd0");

end

endcaseendendmodule

8/4/2019 VO-final

62/140


62

WAVEFORMS: BINARY TO BCD CONVERTER

8/4/2019 VO-final

63/140


63

BCD TO BINARYCONVERTER

8/4/2019 VO-final

64/140


64

BCD TO XS3 CONVERTER

8/4/2019 VO-final

65/140


65

XS3 TO BCD CONVERTER

8/4/2019 VO-final

66/140


66

BINARY TO GRAYCONVERTER

8/4/2019 VO-final

67/140


67

GRAY TO BINARYCONVERTER

CONCLUSION:

Thus the logic circuit for the universal code converter is designed in Verilog

HDL and the output is verified.

8/4/2019 VO-final

68/140


68

EX.NO : 8 STUDY OF SIMULATION USING TOOLS

AIM:

To study the Simulation tools.

THEORY:

CREATING A TEST BENCH FOR SIMULATION:

In this section, you will create a test bench waveform containing input stimulus

you can use to simulate the counter module. This test bench waveform is a graphical view

of a test bench. It is used with a simulator to verify that the counter design meets both

behavioral and timing design requirements. You will use the Waveform Editor to create a

test bench waveform (TBW) file.

1. Select the counter HDL file in the Sources in Project window.

2. Create a new source by selecting Project _New Source.

3. In the New Source window, select Test Bench Waveform as the source type,

and type test bench in the File Name field.

4. ClickNext.

5. The Source File dialog box shows that you are associating the test bench with

the source file: counter. ClickN

ext.6. Click Finish. You need to set initial values for your test bench waveform in the

Initialize Timing dialog box before the test bench waveform editing window opens.

7. Fill in the fields in the Initialize Timing dialog box using the information

below:

Clock Time High: 20 ns.

Clock Time Low: 20 ns.

Input Setup Time: 10 ns.

Output Valid Delay: 10 ns.

Initial Offset: 0 ns

Global Signals: GSR (FPGA)

Leave the remaining fields with their default values.

8/4/2019 VO-final

69/140


69

8. Click OK to open the waveform editor. The blue shaded areas are associated

with each input signal and correspond to the Input Setup Time in the Initialize Timing

dialog box. In this tutorial, the input transitions occur at the edge of the blue cells located

under each rising edge of the CLOCK input.

Fig 2: Waveform Editor - Test Bench

Fig 3:Waveform Editor -Expected Results

9. In this design, the only stimulus that you will provide is on the D IRECTION

port. Make the transitions as shown below for the DIRECTION port:

Click on the blue cell at approximately the 300 ns clock transition. The signal

switches to high at this point.


switches back to low.

8/4/2019 VO-final

70/140


70


switches to high again.

10. Select File _ Save to save the waveform. In the Sources in Project window,

the TBW file is automatically added to your project.

11. Close the Waveform Editor window.

ADDING EXPECTED RESULTS TO THE TEST BENCH WAVEFORM:

In this step you will create a self-checking test bench with expected outputs that

correspond to your inputs. The input setup and output delay numbers that were entered

into the Initialize Timing dialog when you started the waveform editor are evaluated

against actual results when the design is simulated. This can be useful in the Simulate

Post- Place & Route HDL Model process, to verify that the design behaves as expected in

the target device both in terms of functionality and timing.

To create a self-checking test bench, you can edit output transitions manually, or

you can run the Generate Expected Results process:

1. Select the testbench.tbw file in the Sources in Project window.

2. Double-click the Generate Expected Simulation Results process. This process

converts the TBW into HDL and then simulates it in a background process.

3. The Expected Results dialog box will open. Select Yes to post the results in the

waveform editor.

4. Click the + to expand the COUNT_OUT bus and view the transitions that

correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing dialog

box.

5. Select File _ Save to save the waveform.

6. Close the Waveform Editor.Now that you have a test bench, you are ready to

simulate your design.

SIMULATING THE BEHAVIORAL MODEL (ISE SIMULATOR):

If you are using ISE Base or Foundation, you can simulate your design with the

ISE Simulator. If you wish to simulate your design with a ModelSim simulator, skip this

section and proceed to the Simulating the Behavioral Model (ModelSim) section.

8/4/2019 VO-final

71/140


71

Fig 4:Simulator Processes for Test Bench

Fig 5:Behavioral Simulation in ISE Simulator

To run the integrated simulation processes in ISE:

1. Select the test bench waveform in the Sources in Project window. You can see

the Xilinx ISE Simulator processes in the Processes for Source window.

2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens

and runs the simulation to the end of the test bench.

3. To see your simulation results, select the test bench tab and zoom in on the

transitions. You can use the zoom icons in the waveform view, or right click and select a

zoom command.The ISE window, including the waveform view.

4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is

counting up and down as directed by the stimulus on the DIRECTION port.

8/4/2019 VO-final

72/140


72

5. Close the waveform view window. You have completed simulation of your

design using the ISE Simulator. Skip past the ModelSim section below and proceed to the

Creating and Editing Timing and Area Constraintssection.

SIMULATING THE BEHAVIORAL MODEL (MODELSIM):

If you have a ModelSim simulator installed, you can simulate your design using

the integrated ModelSim flow. You can run processes from within ISE which launches

the installed ModelSim simulator.

To run the integrated simulation processes in ISE:

1.Select the test bench in the Sources in Project window. You can see ModelSim

Simulator processes in the Processes for Source window in Fig 6.

Fig 6: Simulator Processes for Test Bench

8/4/2019 VO-final

73/140


73

Fig 7:Behavioral Simulation in ModelSim

2. Double-click the Simulate Behavioral Model process. The ModelSim simulator

opens and runs your simulation to the end of the test bench.

The ModelSim window, including the waveform, should look like Fig 7.

To see your simulation results, view the Wave window.

1. Right-click in the Wave window and select a zoom command.

2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is

counting up and down as directed by the stimulus on the DIRECTION port.

3. Close the ModelSim window.

8/4/2019 VO-final

74/140


74

Figure: RTL Viewer - Detailed View

RESULT: Thus the stimulation tool was studied.

8/4/2019 VO-final

75/140


75

ExNo:8(a) HALF ADDER REALISATION

AIM:

Realize the half adder using Verilog.

TOOLS REQUIRED:



THEORY:

A combinational circuit that performs the addition of two bits is called a

half-adder. This circuit needs two binary inputs and produces two binary outputs. One of

the input variables designates the augend and other designates the addend. The output

variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as

below:

Sum S = xy + xy

Carry C = xy

Where x and y are the two input variables.

PROCEDURE:

1. The half-adder circuit is designed and the Boolean function is found out.2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

76/140


76

TRUTH TABLE:

HALF ADDER

LOGIC DIAGRAM:

PROGRAM:


// *** Half Adder *** //module my_halfadrvlog (s,c,x,y);output s,c;

input x,y;xor (s,x,y);and (c,x,y);endmodule

INPUT OUTPUT

A B SUM CARRY

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

8/4/2019 VO-final

77/140


77

WAVEFORM:

CONCLUSION:

Thus the Half Adder is designed in Verilog HDL and the output is verified.

8/4/2019 VO-final

78/140


78

Ex No:8(b) MULTIPLEXER REALISATION IN VERILOG

AIM:

Design a 2 to 1 and 4 to 1 multiplexer circuit in Verilog.

TOOLS REQUIRED:

Simulation Tools:

Verilog Xilinx Model Sim;

THEORY:

A digital multiplexer is a combinational circuit that selects binary

information from one of many input lines and directs it to a single output line.

Multiplexing means transmitting a large number of information units over a smaller

number of channels or lines. The selection of a particular input line is controlled by a set

of selection lines. Normally, there are 2n input lines and n selection lines whose bit

combinations determine which input is selected. A multiplexer is also called a data

selector, since it selects one of many inputs and steers the binary information to the

output lines. Multiplexer ICs may have an enable input to control the operation of the

unit. When the enable input is in a given binary state (the disable state), the outputs are

disabled, and when it is in the other state (the enable state), the circuit functions as

normal multiplexer. The enable input (sometimes called strobe) can be used to expand

two or more multiplexerICs to digital multiplexers with a larger number of inputs.

The size of the multiplexer is specified by the number 2n of its input lines and the

single output line. In general, a 2n to 1 line multiplexer is constructed from an n to

2n decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND

gates are applied to a single OR gate to provide the 1 line output.

PROCEDURE:

1. The multiplexer circuit is designed and the Boolean function is found out.




8/4/2019 VO-final

79/140


79

LOGIC DIAGRAM:

4 TO 1 MULTIPLEXER DESIGN IN VERILOG

module my_4to1muxbehavirvlog (y,i,en,sel);output y;input [0 : 3] i;input [0 : 1] sel;input en;reg y;always @ (i or en or sel)beginif (en === 0)begin

case (sel)2'b00 : y = i[0];2'b01 : y = i[1];2'b10 : y = i[2];2'b11 : y = i[3];default : y = 1'bX;endcase

endelse

y = 1'bZ;endendmodule

8/4/2019 VO-final

80/140


80


module mux_using_if(din_0 , // Mux first inputdin_1 , // Mux Second inputsel , // Select inputmux_out // Mux output);//-----------Input Ports---------------input din_0, din_1, sel ;//-----------Output Ports---------------output mux_out;//------------Internal Variables--------reg mux_out;//-------------Code Starts Here---------always @ (sel or din_0 or din_1)begin : MUXif (sel == 1'b0) begin

mux_out = din_0;end else begin

mux_out = din_1 ;end

end

endmodule//End OfModule mux


din_0 , // Mux first inputdin_1 , // Mux Second inputsel , // Select inputmux_out // Mux output);//-----------Input Ports---------------input din_0, din_1, sel ;//-----------Output Ports---------------output mux_out;//------------Internal Variables--------reg mux_out;

//-------------Code Starts Here---------always @ (sel or din_0 or din_1)begin : MUXcase(sel )

1'b0 : mux_out = din_0;1'b1 : mux_out = din_1;

endcaseendendmodule //End Of Module mux

8/4/2019 VO-final

81/140


81

WAVEFORM:

CONCLUSION:

Thus the logic circuit for the 4 to 1 multiplexer is designed in Verilog HDL and

the output is verified.

8/4/2019 VO-final

82/140


82

Ex No:8(c) DE-MULTIPLEXER REALISATION IN VERILOG

AIM:

Design a 4 to 1 de-multiplexer circuit in Verilog.

TOOLS REQUIRED:

Simulation Tools:

Verilog Xilinx Model Sim;

THEORY:

The de-multiplexer performs the reverse operation of a multiplexer. It is a

combinational circuit which accepts a single input and distributes it over several outputs.

The number of output lines is n and the number of select lines is 2n lines. De-

multiplexerICs may have an enable input to control the operation of the unit. When the

enable input is in a given binary state (the disable state), the outputs are disabled, and

when it is in the other state (the enable state), the circuit functions as normal de-

multiplexer. The size of the de-multiplexer is specified by the single input line and the

number 2n of its output lines.

PROCEDURE:

1. The de-multiplexer circuit is designed and the Boolean function is foundout.

2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

83/140


83

LOGIC DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS

I S0 S1 Q0 Q1 Q2 Q3

1

1

1

1

0

0

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

1 TO 2 DE-MULTIPLEXER DESIGN IN VERILOG

module Demux1x2_DF(Out0,Out1,S,In);output Out0,Out1;input S,In;

assign Out0=(~S)&In;assign Out1=S&In;endmodule

8/4/2019 VO-final

84/140


84

1 TO 4 DE-MULTIPLEXER DESIGN IN VERILOG

module my_1to4demuxgatevlog(y,i,en,s);output [0 :3] y;input i,en;input [0 : 1] s;

and (y[0],~en,~s[1],~s[0],i);and (y[1],~en,~s[1],s[0],i);and (y[2],~en,s[1],~s[0],i);and (y[3],~en,s[1],s[0],i);endmodule

or

Verilog code for 1 to 4 demux

module demux(din, s, dout);input din;input [1:0] s;output [3:0] dout;reg [3:0] dout;

always @ (din or s)c 2b01: dout(1)=din;

2b10: dout(2)=din;2b11: dout ase(s)

2b00: dout(0)=din;(3)=din;

endcaseendmodule

8/4/2019 VO-final

85/140


85

WAVEFORM:

CONCLUSION:

Thus the logic circuit for the 1 to 4 de-multiplexer is designed in

Verilog HDL and the output is verified.

8/4/2019 VO-final

86/140


86

Exno:9(a) D FLIP-FLOP REALIZATION IN VERILOG

AIM:

Realize the D Flip-Flop in Verilog

TOOLS REQUIRED:



THEORY:

A flip-flop circuit can maintain a binary state indefinitely (as long as power is

delivered to the circuit) until directed by an input signal to switch states. The basic flip-

flop has two outputs Q and Q. The outputs Q and Q are always complementary. The

flip-flop has two stable states which are known as the 1 state and 0 state. In the 1 state,

the output Q = 1 and hence called Set state. In the 0 state, the output Q = 0 and also

called as Reset or Clear state. The basic flip-flop can be obtained by using NAND or

NOR gates. The basic flip-flop circuit is also called latch, since the information is latched

or locked in this circuit. The basic flip-flop is also called the basic binary memory cell,

since it maintains a binary state as long as power is available. It is often required to set or

reset the basic memory cell in synchronism with a train of pulses known as clock. Such acircuit is referred to as clocked set-reset (S-R) Flip-Flop. In a flip-flop, when the power is

switched on, the state of the circuit is uncertain. It is desired to initially set or reset the

flip-flop, i.e. the initial state of the flip-flop is to be assigned. This is accomplished by

using the direct or asynchronous inputs, referred to as preset and clear inputs.

The uncertainty in the state of an S-R Flip Flop when Sn = Rn = 1 can be

eliminated by ensuring that the inputs S and R are never equal to 1 at the same time. This

is done in the D Flip-Flop. This D Flip-Flop has only two inputs: D and Cp. The D input

goes directly to the S input and its complement is applied to the R input. As long as the

clock pulse input is 0, the D flip-flop cannot change the state regardless of the value of D.

The D input is sampled when CP = 1. If D is 1, the Q output goes to 1, placing the Flip-

Flop in the set state. If D is 0, the output Q goes to 0 and the Flip-Flop switches to clear

8/4/2019 VO-final

87/140


87

or reset state. The D flip-flop is so called because of its ability to hold data into its

internal storage. This type of flip-flop is sometimes called gated D- latch.

PROCEDURE:

1. The D flip-flop circuit is designed and the Boolean function is found out.2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

D FLIP FLOP BEHAVIORLEVEL DESIGN IN VERILOG

module my_dffbehaviorvlog(q,qbar,d,clk,clr);

output q,qbar;input d,clk,clr;reg q,qbar;always @ (clr or posedge clk)begin

if (~clr)begin

q = 1'b0;qbar = 1'b1;

endelsebegin

q = d;assign qbar = ~q;

endendendmodule

D FLIP FLOP GATELEVEL DESIGN IN VERILOG

module my_dffgatevlog (q,qbar,d,clk,clr);

output q,qbar;input d,clk,clr;wire temp1,temp2,temp3,temp4,high;assign high = 1'b1;nand na0 (temp1,d,clk);nand na1 (temp2,~d,clk);nand na2 (temp3,qbar,temp1);nand na3 (temp4,q,temp2);and a0 (q,temp3,clr);and a1 (qbar,temp4,high);endmodule

8/4/2019 VO-final

88/140


88

D FLIP FLOP STRUCTURELEVEL DESIGN IN VERILOG

module my_dffstructvlog (q,qbar,d,clk,clr);output q,qbar;input d,clk,clr;my_srffbehaviorvlog sr1(q,qbar,d,~d,clk,clr);

endmodule// *** SR Flip Flop Behavior Level Design *** //module my_srffbehaviorvlog (q,qbar,s,r,clk,clr);output q,qbar;input s,r,clk,clr;reg q,qbar;always @ (posedge clk or clr)if (clr)beginif (clk)begin

if (s ==0)begin

if(r ==0)begin

q = q; qbar = qbar;endelsebegin

q = 0; qbar = 1;end

endelse

begin if (r ==0)begin q = 1; qbar = 0;endelsebegin

q = 1'bz;qbar = 1'bz;end

endendendelse

begin q = 1'b0;qbar = 1'b1;

endendmodule

8/4/2019 VO-final

89/140


89

EDGE TRIGGERED D FLIP FLOP DESIGN IN VERILOG

module my_dff (q,qbar,d,clk,reset);output q,qbar;input d,clk,reset;reg temp0,temp1,temp2,temp3,q,qbar;

always @ (posedge clk or reset )beginif (reset)beginassign temp0 = !(temp3 && temp1);assign temp1 = !(temp0 && ~clk);assign temp2 = !(temp1 && ~clk && temp3);assign temp3 = ! (temp2 && d);assign q = !(temp1 && qbar);assign qbar = !(temp2 && q);endelsebegindeassign q;deassign qbar;q = 1'b0;qbar = 1'b1;endendendmoduleTRUTH TABLE:

INPUT OUTPUT

STATECLK D QN QN+1

0

0

1

X

X

X

X

0

1

QN

RESET

SET

NO CHANGE

LOGIC DIAGRAM:

8/4/2019 VO-final

90/140


90

WAVEFORMS:

CONCLUSION:

Thus the D flip-flop is realized in Verilog HDL and the output is verified.

8/4/2019 VO-final

91/140


91

Exno:9(b) T FLIP-FLOP REALIZATION IN VERILOG

AIM:

Realize the T Flip-Flop in Verilog

TOOLS REQUIRED:



THEORY:

A flip-flop circuit can maintain a binary state indefinitely (as long as

power is delivered to the circuit) until directed by an input signal to switch states. The

basic flip-flop has two outputs Q and Q. The outputs Q and Q are always

complementary. The flip-flop has two stable states which are known as the 1 state and 0

state. The basic flip-flop can be obtained by using NAND orNOR gates. The basic flip-

flop circuit is also called latch, since the information is latched or locked in this circuit.

The basic flip-flop is also called the basic binary memory cell, since it maintains a binary

state as long as power is available. It is often required to set or reset the basic memory

cell in synchronism with a train of pulses known as clock. Such a circuit is referred to as

clocked set-reset (S-R) Flip-Flop. In a flip-flop, when the power is switched on, the state

of the circuit is uncertain. It is desired to initially set or reset the flip-flop, i.e. the initial

state of the flip-flop is to be assigned. This is accomplished by using the direct orasynchronous inputs, referred to as preset and clear inputs.

In a JK Flip Flop, if J = K, the resulting flip-flop obtained is referred to as a T-

type flip-flop. It has only one input, referred to as T-input. If T = 1, it acts as a toggle

switch, i.e. for every clock pulse, the output Q changes. The designation T comes from

the ability of the flip-flop to toggle, or complement, its state.

PROCEDURE:

1. The T Flip-Flop circuit is designed and the Boolean function is found out.2. The Verilog Module Source for the circuit is written.3. It is implemented in Model Sim and Simulated.4. Signals are provided and Output Waveforms are viewed.

8/4/2019 VO-final

92/140


92

TRUTH TABLE:

LOGIC DIAGRAM:

T FLIP FLOP STRUCTURELEVEL DESIGN IN VERILOG

module my_tffstruct (q,qbar,t,clk,reset);output q,qbar;

input t,clk,reset;my_jkffbehaviorvlog jktot (q,qbar,t,t,clk,reset);endmodulemodule my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);output q,qbar;input j,k,clk,reset;reg q,qbar;always @ (posedge clk or posedge reset)if (reset)begin

q = 1'b0;qbar = 1'b1;

endelsebegin

if (j==0 && k ==0)begin

q = q;qbar = qbar;

end

PREVIOUS

STATE

INPUT OUTPUT

QN T Qn+1

0

0

1

1

0

1

0

1

0

1

1

1

8/4/2019 VO-final

93/140


93

else if ( j== 0 && k ==1)begin

q = 1'b0;qbar = 1'b1;

endelse if (j==1 && k == 0)

beginq = 1'b1;qbar = 1'b0;

endelse if (j ==1 && k ==1)begin


endelsebegin

q = 1'bz;qbar = 1'bz;

endendendmoduleWAVEFORMS:

CONCLUSION:

Thus the T flip-flop is realized in Verilog HDL and the output is verified

8/4/2019 VO-final

94/140

8/4/2019 VO-final

95/140


95

Step 4: Select the corresponding entries for the property names.

Step 5: ClickNew Source

8/4/2019 VO-final

96/140


96

Step 6: Enter the file name and then select Verilog module

Step 7: Define the input and output port names, then click Next for all successive

windows

8/4/2019 VO-final

97/140


97

Step 8: The Verilog file will be created underISE file

Step 9: Double click the Verilog file and enter the logic details and save the file.

8/4/2019 VO-final

98/140


98

Step 10: Double click Synthesize XST for checking the syntax .

Step 11: Right click the half add.v file and select new source, then click implementation

constraints file and enter the file name.

8/4/2019 VO-final

99/140


99

Step 12:.ucf file will be created

Step 13: open the .ucf file and enter the pin location and save the file

8/4/2019 VO-final

100/140


100

Step14: Goto Generate programming file and select Generate PROM,ACE or JTAG file

in the processes window.

Step 15: In Slave Serial mode ,right click and select Add Xilinx Device

8/4/2019 VO-final

101/140


101

Step 16: In the Add Device window select the .bit file to add the device.

8/4/2019 VO-final

102/140


102

Step 17: Connect the RS232 cable between computer and kit. Connect the SMPS to kit

and switch on the kit.

Step 18: Right click the device and select Program to transfer the file to kit.

Step 19: after sucecessful transmission of the programming succeeded will be

displayed

8/4/2019 VO-final

103/140


103

PROGRAM:


// *** Half Adder *** //module my_halfadrvlog (s,c,x,y);output s,c;

input x,y;xor (s,x,y);and (c,x,y);endmodulePROGRAM: FULL ADDER DESIGN IN VERILOG

// *** Full Adder *** //module my_fuladrvlog (s,c,x,y,z);output s,c;input x,y,z;xor (s,x,y,z);assign c = ((x & y) | (y & z) | (z & x));endmodule

1 TO 4 DE-MULTIPLEXER DESIGN IN VERILOGmodule my_1to4demuxgatevlog(y,i,en,s);output [0 :3] y;input i,en;input [0 : 1] s;and (y[0],~en,~s[1],~s[0],i);and (y[1],~en,~s[1],s[0],i);and (y[2],~en,s[1],~s[0],i);and (y[3],~en,s[1],s[0],i);endmodule

RE

SUL

T:Thus the development tool for FPGA for schematic entry and verilog wasstudied

8/4/2019 VO-final

104/140


104

EX NO: 11 DESIGN AND SIMULATION OF PIPELINED SERIAL AND

PARALLEL ADDER TO ADD/SUBTRACT 8 NUMBER OF SIZE,12 BITS EACH

IN 2S COMPLEMENT

SERIAL ADDER:

AIM:

To design, synthesize, simulate pipelined serial and parallel adder to add 8

numbers of 12bit size each in 2s complement and to implement and program the same in

FPGA.

TOOLS REQUIRED:

SOFTWARE:

XILINX ISE 9.1i

HARDWARE:

XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card -I

THEORY:

SERIAL ADDER:

Serial Adder uses a simple adder and constructs the sum sequentially. At a

time t, the Sun is calculated and the carry is stored in a register. At time t+1, the sum uses

carry[t] to calculate a new sum.

Carry [ t + 1] = A [ t +1].B[ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] )

Sum [ t + 1 ] = Carry [ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] + c [ t ] )

+ A [ t + 1

Date post:	07-Apr-2018
Category:	Documents
Upload:	sudhasesh2000
View:	228 times
Download:	0 times

VO-final

Documents