IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010 1719
Voltage-Boosting Converter Based on Charge Pumpand Coupling Inductor With Passive
Voltage ClampingK. I. Hwu, Member, IEEE, and Y. T. Yau, Student Member, IEEE
Abstract—A new voltage-boosting converter, combining acharge pump and a coupling inductor, together with a passivevoltage-clamping circuit which pumps part of the leakage induc-tance energy to the output, is presented herein. Therefore, by doingso, the efficiency tends to be flat between the minimum and ratedloads, which is similar to the behavior of the KY converter. More-over, the implementation of the passive voltage-clamping circuitfor this converter with multiphase is very easy. In this paper, somemathematical derivations are given first, and second, simulatedand experimental results are provided to verify the effectivenessof the proposed voltage-boosting converter topology.
Index Terms—Charge pump, coupling inductor, multiphase,passive voltage-clamping circuit, voltage boosting.
I. INTRODUCTION
THERE ARE many applications with high-voltage sourcesfed, such as the burn-in test plant with energy recycling,
the dc–dc converter used in the car as the prestage of the dc–acconverter, etc. Hence, it is indispensable for low voltage to beboosted to high voltage. In general, the boost or buck-boostconverter is widely used in such applications. However, it is noteasy for such converters to achieve high voltage ratio. In theory,the voltage ratios of these two converters can reach infinity but,in actuality, about four or five, limited by parasitic componenteffect and controller capability. Consequently, if the voltageratio of the converter is desired to be over five, then a two-stageconverter based on the boost or buck-boost converter is utilizedor different converter topologies [1]–[18] are created.
In [1]–[10], the Luo converter and its derivatives are pre-sented, whose voltage lift technique is similar to that of theCuk converter or the single-ended primary inductor converter(SEPIC) converter, based on the energy transfer from oneinductor via the intermediate capacitor and then to the otherinductor. Therefore, the transferred energy is mainly deter-mined by the capacitance, thus causing the current stress onthe capacitor to be serious. In [11] and [12], a voltage-boosting
Manuscript received May 15, 2008; revised September 3, 2009. First pub-lished September 22, 2009; current version published April 14, 2010.
K. I. Hwu is with the Institute of Electrical Engineering, National Taipei Uni-versity of Technology, Taipei 10608, Taiwan (e-mail: [email protected]).
Y. T. Yau is with the Institute of Electrical Engineering, National TaipeiUniversity of Technology, Taipei 10608, Taiwan, and also with the In-dustrial Technology Research Institute, Hsinchu 31040, Taiwan (e-mail:[email protected]).
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2032206
converter with very high voltage ratio also uses a capacitor asan energy-transferring medium, similar to the behavior of theCuk or SEPIC converter, and hence, the current stress on thecapacitor is also serious. In [13], the voltage-boosting converter,specified with input voltage, output voltage, and rated outputcurrent being 24 V, 200 V, and 2 A, respectively, is presented.Such a converter combines the characteristics of the boostconverter and the characteristics of the bootstrap scheme toachieve voltage boosting. The higher the voltage ratio is, themore the number of bootstraps and, hence, the more the numberof diodes and capacitors. However, a surge current occurs asthe energy is transferred via large capacitance, and hence, thevalue of the capacitor cannot be too large and the correspondingequivalent series resistance (ESR) is relatively large. In [14], thevoltage-boosting converter has a voltage ratio of 1/(1 − 2D)in the continuous conduction mode (CCM), where D is theduty cycle of the main switch. Moreover, as compared withthe boost converter, this converter is complicated due to fourswitches required. In [15], the KY converter is presented, butthe maximum voltage ratio of such a converter is only two. Asfor [16]–[18], a coupled-boost converter is presented, whichuses a coupling inductor as an energy-transferring medium.In [18], this converter has the voltage ratio of 1 + nD/(1 − D). However, in this converter, suppressing the voltagespike created due to the leakage inductance of the couplinginductor is taken into account by adding an active voltage-clamping circuit which pumps part of the leakage inductanceenergy to the input. However, for multiphase to be considered,the more the number of phases is, the more the number of activevoltage-clamping circuits.
Consequently, a new voltage-boosting converter, combininga charge pump and a coupling inductor, is presented herein,together with a passive voltage-clamping circuit. There are fourmain merits in this converter. The first is that this converterwith high voltage ratio required is simpler in structure thanany converter mentioned before. The second is that the pri-mary inductor is magnetized under double the input voltage,thereby causing the input current to be reduced and, hence, theefficiency to be improved at light load, which is similar to thebehavior of the KY converter [19]. The third is that the passivevoltage-clamping circuit pumps part of the energy stored in theleakage inductance to the output. The fourth is that, for multi-phase to be considered, if the number of phases is N , then onlyadditional N − 1 diodes are added. However, there is mainlyone demerit in this converter. Since there is one right half-plane
1720 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
Fig. 1. Proposed voltage-boosting converter without leakage inductanceconsidered.
Fig. 2. Proposed voltage-boosting converter with leakage inductanceconsidered.
zero, the corresponding phase margin is reduced, and hence,the high-performance control of this converter is not so easyto obtain. In this paper, some mathematical derivations, andsimulated and experimental results are offered to demonstratethe effectiveness of the proposed voltage-boosting convertertopology.
II. PROPOSED CONVERTER CONFIGURATION
Fig. 1 shows the proposed voltage-boosting converter. Sucha converter contains two cells. One is the charge-pumpingcell, and the other is the inductance-coupling cell. The formerconsists of two MOSFET switches S1 and S2 with two bodydiodes D1 and D2 connected in parallel, respectively, onediode Db, and one capacitor Cb. The latter is comprised of onemain switch S3 with one body diode D3 connected in paralleland one coupling inductor made up of two inductances Lp
and Ls, which are coupled together and put at the primary andsecondary, respectively, with the turn ratio n set to Ns/Np,where Np is the number of turns in the secondary windingand Ns is the number of turns in the primary winding. Theremainder are one output diode Do, one output capacitor Co,and one output resistor Ro.
However, there is a leakage inductance existing in this cou-pling inductor, particularly for the leakage inductance LLK
at the primary, as shown in Fig. 2. Consequently, in Fig. 3,one passive voltage-clamping circuit, containing one inductorLsn, one capacitor Csn, and one diode Dsn, is added to thisconverter, so as to avoid the voltage spike occurring due toLLK and hence destroying the MOSFET switch S3 eternally.
Fig. 3. Proposed voltage-boosting converter with passive voltage-clampingcircuit considered.
Fig. 4. Ideal timing sequence of gate driving signals M1, M2, and M3 todrive S1, S2, and S3, respectively, without blanking times considered.
Moreover, if the multiphase concept is applied to the proposedconverter, for example, N -phase, then the required passivevoltage-clamping circuit is the same as that for the single-phaseconverter except that the number of additional diodes Dsn isN − 1.
III. BASIC OPERATING PRINCIPLES
Before this section is discussed, it is assumed that the voltageacross any MOSFET or diode during the turn-on interval isnegligible, there are no blanking times between S1 and S2, thevoltage across the capacitor Cb is equal to νi, and the operatingmode of this converter is in CCM. As shown in Fig. 4, whereTs is the switching period and the gate driving signals M1, M2,and M3 are used to drive S1, S2, and S3, respectively, the turn-on type of three MOSFET switches is (D, 1 − D, D), where Dis for S1 and S3, 1 − D is for S2, and D is the duty cycle ofthe pulsewidth-modulated (PWM) control signal for S1. Firstof all, the basic operating principles for the proposed converterwithout the passive voltage-clamping circuit are described, andnext, the basic operating principles of the proposed passivevoltage-clamping circuit are illustrated. There are two modesfor the former and two modes for the latter.
A. Basic Operating Principles of Converter
1) Mode 1: In Fig. 5, S1 and S3 are turned on, but S2 isturned off. There are two power flows in this mode. One is from
HWU AND YAU: CONVERTER BASED ON CHARGE PUMP AND COUPLING INDUCTOR WITH VOLTAGE CLAMPING 1721
Fig. 5. Power flow of mode 1 without passive voltage-clamping circuit.
Fig. 6. Power flow of mode 2 without passive voltage-clamping circuit.
the input through S1 via Cb and then to Lp, S3, and the ground.The other is from Co to the ground. Therefore, the voltageacross Lp is the input voltage νi plus the voltage vi across Cb,thereby causing Lp of the coupling inductor to be magnetized.Moreover, Cb is discharged. In addition, Co releases energy intothe output. Hence, the corresponding differential equations are
⎧⎨⎩
Lp∂ip
∂t = 2νi
Co∂νo
∂t = −νo
Ro
ii = ip.
(1)
2) Mode 2: In Fig. 6, S1 and S3 are turned off, but S2 isturned on. There are two power flows in this mode. One isfrom the input through Cb via S2 and then to the ground. Theother is from the input through Db via Ls and then to Do
and the output. Therefore, the voltage across Ls is the inputvoltage νi minus the output voltage νo, thereby causing Ls
of the coupling inductor to be demagnetized. Moreover, Cb ischarged. In addition, Co is energized. Hence, the correspondingdifferential equations are⎧⎨
⎩Ls
∂is
∂t = νi − νo
Co∂νo
∂t = is − νo
Ro
ii = is + ib.
(2)
Based on the basic operating principles of the couplinginductor, (2) can be rewritten to⎧⎪⎨
⎪⎩Lp
∂ip
∂t = 1n (νi − νo)
Co∂νo
∂t = 1n ip − νo
Ro
ii = 1n ip + ib.
(3)
Before we obtain the averaged equations from (1) and (3),there is a symbol 〈x〉 that is used to represent the average
value of the variable x, where x indicates voltage or current,as follows:
〈x〉 =1Ts
Ts∫
0
x dτ. (4)
According to (1), (3), and (4), the average equations can beobtained as
⎧⎪⎨⎪⎩
Lp∂〈ip〉
∂t = (2n−1)d+1n 〈νi〉 − 1−d
n 〈νo〉Co
∂〈νo〉∂t = 1−d
n 〈ip〉 − 〈νo〉Ro
〈ii〉 = (n−1)d+1n 〈ip〉 + (1 − d)〈ib〉
(5)
where d is a variable denoting the duty cycle of the PWMcontrol signal for S1.
Based on the ampere–second balance, 〈ib〉 can be expressedas a function of 〈ip〉 to be
〈ib〉 =d
1 − d〈ip〉. (6)
Hence, by substituting (6) into (5), (5) can be rewritten as⎧⎪⎨⎪⎩
Lp∂〈ip〉
∂t = (2n−1)d+1n 〈νi〉 − 1−d
n 〈νo〉Co
∂〈νo〉∂t = 1−d
n 〈ip〉 − 〈νo〉Ro
〈ii〉 = (2n−1)d+1n 〈ip〉.
(7)
Prior to obtaining the small-signal model from (7), the per-turbation and linearization of (7) are indispensable. First of all,〈x〉 is represented by the corresponding dc quiescent value Xplus the superimposed small ac variation x, with the assumptionthat the ac variation is small in magnitude compared to the dcquiescent value. Let
⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩
〈νi〉 = Vi + νi
d = D + d〈ip〉 = Ip + ip〈νo〉 = Vo + νo
〈ii〉 = Ii + ii
with
⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩
|νi| � Vi
|d| � D|ip| � Ip
|νo| � Vo
|ii| � Ii.
(8)
Next, by substituting (8) into (7), the following are obtained:⎧⎪⎨⎪⎩
Lp∂(Ip+ip)
∂t = (2n−1)(D+d)+1n (Vi + νi) − 1−D−d
n (Vo + νo)Co
∂(Vo+νo)∂t = 1−D−d
n (Ip + ip) − 1R (Vo + νo)
Ii + ii = (2n−1)(D+d)+1n (Ip + ip).
(9)
Based on (9), the quiescent equations can be obtained to be⎧⎪⎪⎨⎪⎪⎩
0 =[
(2n−1)D+1n
]Vi − 1−D
n Vo
0 = 1−Dn Ip − Vo
Ro
Ii = (2n−1)D+1n Ip.
(10)
Hence, the corresponding voltage ratio of the this converter canbe obtained from (10) to be
Vo
Vi=
(2n − 1)D + 11 − D
. (11)
1722 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
Fig. 7. Small-signal model for the proposed converter.
Fig. 8. Ideal timing sequence of gate driving signals M1, M2, and M3 todrive S1, S2, and S3, respectively, with blanking times considered.
On the other hand, with the second-order ac terms neglected,the small-signal equations can be obtained from (9) to be⎧⎪⎪⎨⎪⎪⎩
Lp∂ip
∂t =[
(2n−1)Vi
n + Vo
n
]d − 1−D
n νo +[
(2n−1)D+1n
]νi
Co∂νo
∂t = − Ip
n d + 1−Dn ip − νo
Ro
ii = (2n−1)D+1n ip + (2n−1)Ip
n d.(12)
Hence, the resulting small-signal model for such a converteris shown in Fig. 7 according to (12), where T1 and T2 areideal transformers with turn ratios of 1 : [(2n − 1)D + 1]/nand (1 − D)/n : 1, respectively.
However, in practice, there are blanking times between S1
and S2, as shown in Fig. 8. Hence, there exist additional twomodes. One mode, which is mode 3, locates between modes 1and 2, with a blanking time of td1 considered. The other mode,which is mode 4, locates after mode 2 before mode 1, with ablanking time td2 considered. These two are to be described asfollows.
3) Mode 3: In Fig. 9, S1, S2, and S3 are all turned off, with adelay time of td1 considered. There is only one power flow thatis from the ground through Cb via Ls and then to Do and theoutput. Therefore, the voltage across Ls is the voltage νi acrossCb minus the output νo, thereby causing Ls of the couplinginductor to be demagnetized. Moreover, Cb is discharged. Inaddition, Co is energized.
4) Mode 4: In Fig. 10, S1, S2, and S3 are all turned off,with a delay time of td2 considered. There is only one power
Fig. 9. Power flow of mode 3 without passive voltage-clamping circuit.
Fig. 10. Power flow of mode 4 without passive voltage-clamping circuit.
flow that is from the input through Db via Ls and then to Do
and the output. Therefore, the voltage across Ls is the inputvoltage νi minus the output νo, thereby causing Ls of thecoupling inductor to be demagnetized. Moreover, Cb lies idle.In addition, Co is charged.
B. Operating Principles of Passive Voltage-Clamping Circuit
In this section, the main description focuses on the behaviorof the passive voltage-clamping circuit instead of the behaviorof the main power stage.
1) Mode 1: In Fig. 11, the moment S3 is turned off, and theenergy stored in LLK is released to Csn via Dsn.
2) Mode 2: In Fig. 12, as soon as S3 is turned on, the energystored in Csn is pumped into the output via Lsn and Do.
IV. APPLIED CONTROL METHOD
Fig. 13 shows the proposed overall system block dia-gram for the proposed converter. The one-comparator counter-based PWM control without any analog-to-digital converter
HWU AND YAU: CONVERTER BASED ON CHARGE PUMP AND COUPLING INDUCTOR WITH VOLTAGE CLAMPING 1723
Fig. 11. Power flow of passive voltage-clamping circuit in mode 1.
Fig. 12. Power flow of passive voltage-clamping circuit in mode 2.
based on the field-programmable gate array (FPGA) [20], [21]is employed herein, and the parameters of the proportionalintegral (PI) controller, including the proportional gain kp andthe integral gain ki, are tuned at rated load. In addition, theoutput voltage information after the voltage divider is obtainedthrough the comparator and then sent to FPGA having a systemclock of 100 MHz to create the desired PWM control signals todrive the MOSFET switches after the gate drives.
V. KEY PARAMETER CONSIDERATIONS
Before this section is discussed, there are some specificationsto be given as follows: 1) The rated dc input voltage Vi isset to 5 V; 2) the rated dc output voltage Vo is set to 48 V;3) the rated dc output power Po−rated is set to 48 W; 4) theminimum dc output current Io−min in the boundary conductionmode (BCM) is 0.15 A; 5) switching frequency fs is chosen tobe 195 kHz; 6) the turn ratio Ns/Np of the coupling inductor isset to five; 7) one 1000-μF electrolytic capacitor is chosen forCo; 8) the product names of Db, Dsn, and Do are STPS20L25,3CTQ100, and 3CTQ100, respectively; 9) the product namesof S1, S2, and S3 are PHD96NQ03LT, PHD96NQ03LT, andIRL3705ZS, respectively; 10) the product name of the controlIC is EPIC3T100; 11) PI controller parameters kp and ki areset to 0.25 and 0.0625, respectively; and 12) blanking times td1
and td2 are both set to 100 ns.
A. Design of Main Power Stage
In the main power stage, there are three key parameters tobe designed. One is the value of Cb in the charge-pumping cell,
Fig.13. Overall system block diagram for the proposed converter.
Fig. 14. Current waveforms in BCM. (a) Primary-side current plus secondary-side current, ix. (b) Secondary-side current is.
and the other two are the values of Lp and Ls in the inductance-coupling cell. On the condition that this converter works inBCM, corresponding to the minimum load current Io−min, thepeak value Ip−p of the current flowing through Lp, shown inFig. 14, can be expressed as
Ip−p = nIs−p =2nIo−min
1 − D(13)
where Is−p is the peak value of the current flowing through Ls.Consequently, the minimum energy stored in Lp under BCM
EL−min can be represented as
EL−min =12LpI
2p−p ≥ 1
2ViDTsIp−p. (14)
Based on (13) and (14), the value of Lp can be expressed as
Lp ≥ ViD(1 − D)Ts
2nIo−min. (15)
1724 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
According to the given specifications and (11) and (15), thevalue of Lp is calculated to be larger than 4.3 μH, and eventu-ally, one coupling inductor is chosen with Lp set to 5 μH usingone T106-18 core with five turns and Ls set to 75 μH using thesame core with 20 turns.
Moreover, there are some assumptions used to obtain thevalue of Cb as follows: 1) This converter operates at rated load;2) Cb is charged to Vi in mode 2; 3) the maximum percentageof decreased variation in voltage on Cb in discharge ε is setto 1% in mode 1; 4) the input voltage is an infinite bus, i.e.,the input voltage is kept constant and can be represented asinfinite capacitance which is much larger than the value of Cb;and 5) the converter efficiency η is initially set to 80% at ratedload. It is noted that the efficiency that is assumed to be 80% atrated load is based on the following reason. Since this couplinginductor behavior is similar to the transformer in the flybackconverter and the efficiency of the flyback converter under thetraditional control technique is generally about 80%, this is whythe efficiency of the proposed converter operating at rated loadis roughly chosen to be 80% for the convenience of the designof Cb.
Therefore, in mode 1, the energy Ee is extracted from Vi andCb and can be expressed as
Ee =12Cb
{(2Vi)2 − [(2 − ε)Vi]
2}
=12(4ε − ε2)CbV
2i . (16)
Moreover, in mode 1, the energy Es is sent to the load and canbe represented as
Es =Po−ratedDTs
η. (17)
According to the conservation of energy, Ee is equal to Es, andhence, the value of Cb can be expressed as
Cb ≥2Po−ratedDTs
(4ε − ε2)V 2i η
. (18)
Based on the given specifications and assumptions and (11)and (18), the value of Cb is calculated to be larger than285 μF, and finally, two paralleled 330-μF OSCON capacitorsconnected in parallel with one 22-μF multilayer ceramic capac-itor are selected for Cb to compensate the effect of frequencyon the capacitance and to reduce the ESR.
B. Design of Passive Voltage-Clamping Circuit
There are two key parameters to be designed in the passivevoltage-clamping circuit. One is the value of Csn, and the otheris the value of Lsn. Before doing these, we need to measure thevalue of LLK and set the maximum value of the voltage acrossCsn, Vmax, during the turnoff period for S3 without the voltagespike considered. Hence, based on the following, the minimumvalue of Csn can be obtained as
12CsnV 2
max ≥ 12LLKI2
p−max. (19)
TABLE ICOMPONENT STRESSES
TABLE IICOMPONENT STRESS VALUES
By rearranging (19), the resulting value of Csn can beobtained as
Csn ≥LLKI2
p−max
V 2max
(20)
where Ip−max is the maximum value of the current flowingthrough Lp at rated load and corresponds to the value shownin Table II for S3.
As for the value of Lsn, the relationship between the timerequired for the voltage across Csn to fall from the maximumvalue to zero without the voltage spike considered and theturnoff period for S3 can be expressed as
(1 − D)Ts ≥ 0.5π√
LsnCsn. (21)
By rearranging (21), the resulting value of Lsn can befound to be
Lsn ≤ 4(1 − D)2T 2s
π2Csn. (22)
Based on (22), the measured value of 1.8 μH for LLK , Vmax
set to double the input voltage, and other given and calculatedvalues, the resulting minimum value of Csn is worked out to be1.98 μF, and finally, the value of Csn is set to 2.2 μF; on theother hand, the resulting maximum value of Lsn is figured outto be 1.42 μH, and eventually, the value of Lsn is set to 1 μH.
C. Component Stresses
In this section, the steady-state stresses on the componentsof the proposed converter except the body diodes of MOSFETswitches and the components of the passive voltage-clampingcircuit are tabulated in Table I, on the assumption that the volt-age across any MOSFET or diode during the turn-on intervalis negligible and the voltage across Cb is Vi. As for Table II, itgives the stress value for each component.
In Table I, the symbols from a to i have the followingmeaning.
HWU AND YAU: CONVERTER BASED ON CHARGE PUMP AND COUPLING INDUCTOR WITH VOLTAGE CLAMPING 1725
Fig. 15. Block diagram for efficiency measurement.
Fig. 16. Simulated output voltage during startup.
VI. SIMULATED AND EXPERIMENTAL RESULTS
Before some experimental results are provided, a simulatedresult at startup based on MATLAB/POWERSYS/SIMULINKfor the proposed converter operating under the open loop is pro-vided to verify its feasibility, and after this, some experimentalresults under the closed loop are utilized to demonstrate theeffectiveness of this converter. Moreover, the curve of efficiencyversus load current is provided herein, which is measured basedon Fig. 15 with instrument names added. Fig. 16 shows thesimulated output voltage of the proposed converter under open-loop control during startup. It can be seen that the outputvoltage of this converter can stably rise to the neighborhoodof the prescribed value.
Afterward, some experimental waveforms shown inFigs. 17–23 are provided to verify the performance of theproposed circuit topology. Figs. 17–19 show the PWM gatedriving signals for S3 and S2 and the currents in Lp and Ls,under 15%, 50%, and 100% of the rated load, respectively. It isnoted that the converter under 15% of the rated load operatesin discontinuous conduction mode, which does not correspondto the design specifications. This is because the inductanceis reduced due to the high switching frequency. Figs. 20–22show the gate driving signals for S3 and S2, the voltage onS3, and the voltage on Cb, under 15%, 50%, and 100% ofthe rated load, respectively. It is noted that, the more the loadcurrent, the lower the voltage on S3. As for the voltage spike
Fig. 17. Under 15% of the rated load. (1) Gate driving signal for S3. (2) Gatedriving signal for S2. (3) Current in Lp. (4) Current in Ls.
Fig.18. Under 50% of the rated load. (1) Gate driving signal for S3. (2) Gatedriving signal for S2. (3) Current in Lp. (4) Current in Ls.
Fig. 19. Under the rated load. (1) Gate driving signal for S3. (2) Gate drivingsignal for S2. (3) Current in Lp. (4) Current in Ls.
1726 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
Fig. 20. Under 15% of the rated load. (1) Gate driving signal for S3. (2) Gatedriving signal for S2. (3) Voltage on S3. (4) Voltage on Cb.
Fig. 21. Under 50% of the rated load. (1) Gate driving signal for S3. (2) Gatedriving signal for S2. (3) Voltage on S3. (4) Voltage on Cb.
Fig. 22. Under the rated load. (1) Gate driving signal for S3. (2) Gate drivingsignal for S2. (3) Voltage on S3. (4) Voltage on Cb.
Fig. 23. Efficiency versus load current.
Fig. 24. Photograph of the experimental hardware.
on S3, it is due to the turn-on delay created from the diodeDsn. In addition, the voltage across S3 is larger than doublethe input voltage prescribed. This is because the value of Csn
is reduced due to high frequency or there exists capacitancetolerance in Csn. As mentioned earlier, it is evident that theproposed voltage-boosting converter can stably operate underclosed-loop control. Fig. 23 shows the curve of efficiencyversus load current. It is noted that, unlike the traditionalvoltage-boosting converter, the proposed voltage boostingpossesses an almost flat range of the efficiency from minimumload to rated load. This is because the charge-pumping cell isused. To explain lucidly, the primary inductance of the couplinginductor is magnetized by double the input voltage, therebycausing the input current to be reduced, and this behavior issimilar to the KY converter. Fig. 24 shows the photograph ofthe experimental hardware, which is implemented almost bysurface-mounted devices.
VII. CONCLUSION
A new voltage-boosting converter, combining a charge pumpand a coupling inductor, has been proposed in this paper,together with a passive voltage-clamping circuit. Conclusionsare summarized as follows.
1) This converter with high voltage ratio required is sim-pler in structure than any other converter mentioned inSection I.
HWU AND YAU: CONVERTER BASED ON CHARGE PUMP AND COUPLING INDUCTOR WITH VOLTAGE CLAMPING 1727
2) The primary inductor is magnetized under double theinput voltage, thereby causing the input current to bereduced and, hence, the efficiency to be upgraded at lightload, and this behavior is similar to the KY converter.
3) The passive voltage-clamping circuit pumps part of theenergy stored in the leakage inductance to the output.
4) For the multiphase to be considered, if the number ofphases is N , then only additional N − 1 diodes are added.
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K. I. Hwu (M’06) was born in Taichung, Taiwan, onAugust 24, 1965. He received the B.S. and Ph.D. de-grees in electrical engineering from National TsingHua University, Hsinchu, Taiwan, in 1995 and 2001,respectively.
From 2001 to 2002, he was the Team Leader of thevoltage-regulated module at AcBel Company. From2002 to 2004, he was a Researcher with the Energyand Resources Laboratories, Industrial TechnologyResearch Institute, Hsinchu. He was the Chairmanof the Center for Power Electronics Technology,
National Taipei University of Technology, Taipei, Taiwan, from 2005 to 2006,where he is currently an Assistant Professor in the Institute of ElectricalEngineering. His areas of research interest are power electronics and motordrives. His current research interests focus on converter topology and digitalcontrol.
Dr. Hwu has been a member of the Program Committee of the IEEE AppliedPower Electronics Conference and Exposition since 2005. He has also beena member of the Technical Review Committee of the Bureau of Standards,Metrology, and Inspection since 2005 and the Institution of Engineering andTechnology since 2008.
Y. T. Yau (S’08) was born in Tainan, Taiwan, onNovember 23, 1980. He received the B.S. and M.S.degrees in electrical engineering from Tamkang Uni-versity, Taipei, Taiwan, in 2002 and 2004, respec-tively. He is currently working toward the Ph.D.degree in the Institute of Electrical Engineering,National Taipei University of Technology, Taipei.
For six months in 2002, he was with Acbel Com-pany. He is currently a Researcher in the IndustrialTechnology Research Institute, Hsinchu, Taiwan. Hisresearch interests include power electronics under
