Volume:02/Issue:10/October -2020 Impact Factor- 5.354 UVM … · 2020. 11. 2. · UVM_Monitor: UVM...

e-ISSN: 2582-5208 International Research Journal of Modernization in Engineering Technology and Science Volume:02/Issue:10/October -2020 Impact Factor- 5.354 www.irjmets.com

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www.irjmets.com @International Research Journal of Modernization in Engineering, Technology and Science

UVM BASED TESTBENCH ARCHITECTURE OF SERIAL PERIPHERAL

INTERFACE

Sreemukhi Muddusetty *1

*1Electronics and Communication Engineering, Indian Institute of Information Technology Design and

Manufacturing Kurnool, Andhra Pradesh, India.

ABSTRACT

It is demanded to ensure the provided hardware design works accordingly and deliver expected results. The

functional defects that were identified later would result in the repetition of design steps. So, verification is a

process that saves cost and time. An industry-standard verification methodology is required to get good control

of stimulus generation, functional coverage and etc. UVM is a System Verilog class library that has been

explicitly designed to build and connect modular reusable verification components and test-benches through

object-oriented programming (OOP) features, such as inheritance, and by utilizing override components, which

are allowed by polymorphism. Serial Peripheral Interface (SPI) is a synchronous interface bus commonly used

to send data between microcontrollers and peripherals such as shift registers and sensors. It uses separate

clock and data lines, along with a select line to choose the device to communicate with. SPI’s advantages make it

suitable for applications like reading/writing data to an SD card, or any other application where data transfer

flow is requisite. SPI is designed and verified using Verilog and Universal Verification Methodology (UVM)

respectively to guarantee its functional coverage and design correctness

Keywords: Code Coverage ,Configuration, Factory ,Functional Coverage ,Serial Interface Protocol(SPI),System

Verilog, TLM Connections, UVM phases, UVM reporting, Universal Verification Methodology(UVM).

I. INTRODUCTION

Serial peripheral interface is a synchronous serial communication interface specification used for short-length

communication, essentially in embedded systems. The interface was developed by Motorola in the mid-1980s.

Communication in SPI devices is done in full duplex mode using a master-slave criteria with a single master.

Multiple slave-devices are supported through selection with individual slave select (SS) line. SPI is called a four-

wire serial bus, contrasting with three-wire, two-wire, and one-wire serial buses. SPI is one master and multi

slave communication.

The SPI design is done using Verilog. Verilog was developed to simplify the procedure and make HDL

(Hardware Description Language) more flexible. Today, Verilog is the most well-known HDL used throughout

the semiconductor industry. Verilog generates a level of abstraction that aids hide away the features of its

implementation. Verification of SPI protocol is done using system Verilog based UVM. System Verilog is an

extension of Verilog. System Verilog provides many verification features to verify the design using complex

test-benches and generate random stimuli. System Verilog supports OOPs features which makes verifications of

designs at a suitable higher level of abstraction. System Verilog based Universal Verification Methodology

(UVM) is a standard to make quick development and enables reusability of verification environments

throughout the industry. UVM is derived from Open Verification Methodology (OVM). UVM is a set of class

libraries that uses the syntax of system Verilog. The principal thought supporting UVM is to assist industries

develop reusable, modular test-benches that can be utilized across various projects.

II. DESIGN OF SERIAL PERIPHERAL INTERFACE

SPI protocol is serial communication and operates in full duplex mode. It consists of four wires to transmit and

receive the data serially. The four wires are SCLK (Serial Clock), MISO (Master In Slave Out), MOSI (Master Out

Slave In), SS (Slave Select).

Description of Designed SPI

In SPI the data is transferred bit by bit, we are transferring and receiving 8 bits. Here we are using only one

slave, we should keep the slave select low always. When the data needs to be transferred from master to slave,

the data will be loaded into master shift register which is to be transmitted following clock signal. The data bit


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will be transferred to the shift register of slave through MOSI line. Similarly, all the 8-bit will be transferred into

the slave shift register.

A simple RTL code is developed for both master and slave. In an SPI transfer process, data is simultaneously

shifted out serially known as transmission and shifted in serially known as receiving. SCK (serial clock) line

synchronizes shifting of the information on the existing two serial data lines. Individual selection of slave device

is done by slave select line which is low and the slave devices that are not selected do not interfere with SPI

transmissions and receiving.

III. VERIFICATION METHODOLOGY

In this paper, to verify designed SPI protocol Universal Verification Methodology is used by creating UVM

environment using system Verilog. This includes functional coverage, assertions and required class

components.

Universal Verification Methodology

To use UVM in windows one has to download UVM source files. The basic building blocks of UVM environment

are its components namely UVM sequence item, UVM sequence, UVM sequencer, UVM driver, UVM monitor,

UVM_scoreboard,UVM_environment,UVM_subscriber,UVM_test,UVM_agent.

UVM Architecture

UVM Sequence item: The sequence_item class is written by extending the uvm sequence item, uvm sequence

item inherits from the uvm_object via the uvm_transaction class. This is an object type. The sequence_item have

data fields to generate the stimulus by randomizing it.

UVM_Sequence: Sequences make the main stimuli for verification, from sequence item the variables declared

using rand or randc are randomized in this class. Sequence is written by extending the uvm_sequence. This

send data items to sequencer.


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UVM_Sequencer: Sequencer generates data transactions to driver. Sequencer is written by extending the

uvm_sequencer. The sequencer govern the flow of request and response sequence items between sequence and the driver via TLM ports

UVM_Driver: UVM driver is an active component that drive signals to the interface of the design. Transaction

level objects are obtained from the Sequencer and the UVM driver drives them to the design through an

interface handle. Driver is written by extending the uvm_driver.

UVM_Monitor: UVM monitor captures signals from the design interface and translate it into transaction level

data objects. Active monitor that is present in active agent captures inputs of the design via interface handle

and send the packets to scoreboard via analysis ports. Passive monitor captures output of the design via

interface handle and send to scoreboard via analysis port. Uvm monitor is written by extending uvm_monitor.

UVM_Agent: Agent is a top class that encapsulates driver, sequencer and monitor in general. Active agent is a

top class of sequencer, driver and active monitor. Passive agent is a top class of passive monitor. Entire

connections are done using TLM connections.

UVM_Scoreboard: Scoreboard is written by extending uvm_scoreboard. Active agent and Passive agents are

connected to scoreboard via TLM analysis ports and the design functionality and correctness is checked within

the scoreboard.

UVM_Subscriber: Generally uvm components does not have in built ports for transactions and hence analysis

ports are defined. Subscriber generally consists of cover groups that check the design functionality by sampling

and is connected to active monitor within the environment. Subscriber is written by extending uvm_subscriber.

UVM_Environment: Environment is written by extending uvm_env this consist of multiple agents, scoreboard,

cover groups (subscriber).

UVM_Test: Test is written by extending uvm_test. Test contains environment and other configuration

properties.

Top Module: Top module consists of the test class, DUT and interface. It consists of all verification components

and any assertion are passed in top module of the design.

TLM connections: UVM provides unidirectional ports, exports, and implementation ports for connecting

various components via the TLM interfaces. Analysis ports are used when the components that is to be

connected is the only class in the hierarchy and when to transfer the data packets to many components.

Fig-1


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Compile and Simulation

To compile the design and entire environment the uvm 1.1d library file is downloaded copied to the software

folder. Here Questasim 10.4e is used. The path is set to the library file.

For simulation

To compile and generate coverage report

IV. RESULTS

Transcript results:


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Wave form

Fig-2

Assertion Count

Fig-3

Instance Coverage

Fig-4

Cover groups

Fig-5


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Questa Coverage Report

Fig-6

Fig-7

V. CONCLUSION

In this project, I have designed and verified the functionality of SPI Protocol using system Verilog based

Universal Verification Methodology. The obtained results are discussed in the results section. The main

functionality and operation of Serial Peripheral Interface protocol and details of shift register, signals are

stated. Functional verification of SPI contains the description of verification environment using UVM for the

designed SPI. The verification environment is created according to the SPI design to validate the functionality of

intellectual property.


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ACKNOWLEDGEMENTS

The author wishes to thank Mr. Chand Basha Shaik, Sion Semiconductor PVT LTD for valuable

guidance.

VI. REFERENCES [1] Verilog HDL by Samir Palnitkar Publisher: Prentice Hall PTR (January 15, 1996)

[2] Vadla Siva Prasad, Shaik. Tajmahaboob “Design and implementation of Serial Peripheral Interface”

Volume 5, Issue 04, April -2018.

[3] Chris Spears SYSTEMVERILOG FOR VERIFICATION, Publisher: Springer.

[4] F. Leens, “An Introduction to I2C and SPI Protocols,” IEEE Instrumentation & Measurement Magazine, pp.

8-13, February 2009.

[5] Universal Verification Methodology (UVM) 1.1 User guide by accellera.

[6] Rich Edelman Mentor Graphics Fremont, CA Shashi Bhutada Mentor Graphics, Los Angeles, CA“An

approach to automating UVM testbench writing”.

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