VS5100 SOM Reference Manual€¦ · The SOM provides an ideal building block that easily integrates...

VEST-VS5100-USG-001, REV C

Page 1 APC Proprietary Information March 16, 2016

VS5100 SOM Reference Manual

VEST-VS5100-USG-001

Copyright © 2016 Advanced Products Corporation Pte Ltd. All rights reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written permission of Advanced Products Corporation Pte Ltd.



TABLE OF CONTENTS 1 Overview ................................................................................................................................ 7

1.1 General Information .................................................................................................................. 7 1.2 Feature Summary ...................................................................................................................... 7 1.3 Block Diagram ............................................................................................................................ 8 1.4 List of Acronyms ........................................................................................................................ 8 1.5 Reference Documents ............................................................................................................... 9

2 Main Hardware Components ................................................................................................ 10

2.1 NXP i.MX 6Solo/6DualLite ....................................................................................................... 10 2.1.1 Overview .......................................................................................................................... 10 2.1.2 Features ........................................................................................................................... 10

2.2 Memory ................................................................................................................................... 12 2.2.1 DDR3L SDRAM ................................................................................................................. 12 2.2.2 eMMC Flash Memory ...................................................................................................... 12 2.2.3 On-board I2C EEPROM..................................................................................................... 12

2.3 PMIC ........................................................................................................................................ 12 2.4 Board Variant Configuration Settings ...................................................................................... 13

3 External Interface ................................................................................................................. 14

3.1 CN1 Pin Assignments ............................................................................................................... 15 3.2 CN2 Pin Assignments ............................................................................................................... 21 3.3 CN3 Pin Assignments ............................................................................................................... 28

4 Signal Description Per Block/Instance .................................................................................... 31

4.1 Digital Audio Mux (AudMux) ................................................................................................... 31 4.2 Clock Controller Module (CCM) ............................................................................................... 33 4.3 Enhanced Configurable SPI (ECSPI) ......................................................................................... 33 4.4 10/100-Mbps RMII Ethernet MAC (ENET) ............................................................................... 36 4.5 Enhanced Periodic Interrupt Timer (EPIT) ............................................................................... 37 4.6 Flexible Controller Area Network (FLEXCAN) .......................................................................... 37 4.7 General Purpose Input/Output (GPIO) .................................................................................... 38 4.8 General Purpose Timer (GPT) .................................................................................................. 45 4.9 I2C ............................................................................................................................................ 45 4.10 Image Processing Unit (IPU) .................................................................................................... 46 4.11 LVDS Display Bridge (LDB) ....................................................................................................... 49 4.12 MIPI- Camera Serial Interface Host Ccontroller (MIPI_CSI) .................................................... 50 4.13 Pulse Width Modulation (PWM) ............................................................................................. 50 4.14 System JTAG Controller (SJC)................................................................................................... 51 4.15 Universal Asynchronous Receiver/Transmitter (UART) .......................................................... 52 4.16 Universal Serial Bus Controller (USB) ...................................................................................... 54 4.17 Ultra Secured Digital Host Controller (uSDHC) ........................................................................ 55 4.18 Watchdog Timer (WDOG)........................................................................................................ 58 4.19 PCI Express (PCIe) .................................................................................................................... 59

5 Electrical Specification .......................................................................................................... 60

5.1 Absolute Maximum Characteristics......................................................................................... 60 5.2 operational Characteristics...................................................................................................... 60

5.2.1 Power Supplies ................................................................................................................. 60



5.2.2 Power Consumption ......................................................................................................... 60

6 Layout Recommendations ..................................................................................................... 61

6.1 SOM Board Trace Length ......................................................................................................... 61 6.1.1 Trace Length of CN1 Signals ............................................................................................ 61 6.1.2 Trace Length of CN2 Signals ............................................................................................ 62

6.2 PCI Express Interface Recommendations ................................................................................ 64 6.3 LVDS Recommendations ......................................................................................................... 64 6.4 USB Recommendations ........................................................................................................... 65 6.5 MIPI Recommendations .......................................................................................................... 65 6.6 SD Interface Recommendations .............................................................................................. 65 6.7 CSI Parallel Recommendations ................................................................................................ 65 6.8 PGB Parallel recommendations ............................................................................................... 65 6.9 I2S Recommendations ............................................................................................................. 65 6.10 SPI Interface Recommendations ............................................................................................. 65 6.11 ENET Interface Recomnendations ........................................................................................... 66

7 Environment Specification .................................................................................................... 67

7.1 Temperature Specification ...................................................................................................... 67 7.2 Humidity .................................................................................................................................. 67

8 Mechanical Specifications ..................................................................................................... 68

8.1 Module Dimension .................................................................................................................. 68 8.2 Height On Top .......................................................................................................................... 68 8.3 Height on Bottom .................................................................................................................... 68 8.4 Mechanical Drawing ................................................................................................................ 68

9 Board Options....................................................................................................................... 69

10 Revision History ................................................................................................................ 70

11 Legal Notices ..................................................................................................................... 71



LIST OF TABLES Table 1-1: LIST OF ACRONYMS .................................................................................................................. 9 Table 2-1: GPIO bits Settings ................................................................................................................... 13 Table 2-2: The BOARD VARIANT configuration settings .......................................................................... 13 Table 3-1: CN1 Pin Assignments .............................................................................................................. 21 Table 3-2: CN2 Pin Assignments .............................................................................................................. 28 Table 3-3: CN3 Pin Assignments .............................................................................................................. 29 Table 3-4: VCC_CSI Voltage Level Settings .............................................................................................. 29 Table 3-5: VCC_SD2 Voltage Level Settings ............................................................................................. 29 Table 3-6: VCC_SD3 Voltage Level Settings ............................................................................................. 30 Table 3-7: SOM Board Boot Source Settings ........................................................................................... 30 Table 3-8: Resistors Loading Configurations for SD3 vs. PCIe ................................................................. 30 Table 4-1: External Signals of AUDMUX .................................................................................................. 32 Table 4-2: External Signals of CCM .......................................................................................................... 33 Table 4-3: External Signals of ECSPI 1 ...................................................................................................... 34 Table 4-4: External Signals of ECSPI 2 ...................................................................................................... 35 Table 4-5: External Signals of ECSPI 3 ...................................................................................................... 35 Table 4-6: External Signals of ECSPI 4 ...................................................................................................... 36 Table 4-7: External Signals of ENET ......................................................................................................... 37 Table 4-8: External Signals of EPIT ........................................................................................................... 37 Table 4-9: External Signals of FLEXCAN ................................................................................................... 38 Table 4-10: External Signals of GPiO1 ..................................................................................................... 40 Table 4-11: External Signals of GPIO2 ..................................................................................................... 40 Table 4-12: External Signals of GPIO3 ..................................................................................................... 41 Table 4-13: External Signals of GPIO4 ..................................................................................................... 42 Table 4-14: External Signals of GPIO5 ..................................................................................................... 43 Table 4-15: External Signals of GPIO6 ..................................................................................................... 44 Table 4-16: External Signals of GPIO7 ..................................................................................................... 44 Table 4-17: External Signals of GPT ......................................................................................................... 45 Table 4-18: External Signals of I2C 1 ....................................................................................................... 45 Table 4-19: External Signals of I2C 2 ....................................................................................................... 46 Table 4-20: External Signals of I2C 3 ....................................................................................................... 46 Table 4-21: External Signals of I2C 4 ....................................................................................................... 46 Table 4-22: External Signals of IPU .......................................................................................................... 49 Table 4-23: External Signals of LDB ......................................................................................................... 49 Table 4-24: External Signals of MIPI_CSI ................................................................................................. 50 Table 4-25: External Signals of PWM ...................................................................................................... 51 Table 4-26: External Signals of SJC .......................................................................................................... 52 Table 4-27: External Signals of UART1 .................................................................................................... 53 Table 4-28: External Signals of UART2 .................................................................................................... 53 Table 4-29: External Signals of UART3 .................................................................................................... 54 Table 4-30: External Signals of UART4 .................................................................................................... 54 Table 4-31: External Signals of UART5 .................................................................................................... 54 Table 4-32: External Signals of USB ......................................................................................................... 55 Table 4-33: External Signals of USDHC1 .................................................................................................. 56 Table 4-34: External Signals of USDHC2 .................................................................................................. 58 Table 4-35: External Signals of USDHC3 .................................................................................................. 58 Table 4-36: External Signals of WDOG .................................................................................................... 59 Table 4-37: External Signals of PCIe ........................................................................................................ 59



Table 5-1: Absolute Maximum Characteristics ........................................................................................ 60 Table 5-2: Power Suppliers Requirement ................................................................................................ 60 Table 5-3: VS5100 SOM power consumption ......................................................................................... 60 Table 6-1: Trace Length of CN1 Signals ................................................................................................... 62 Table 6-2: Trace Length of CN2 Signals ................................................................................................... 64 Table 9-1: Board Options and Ordering Part Numbers ........................................................................... 69



LIST OF FIGURES/DIAGRAMS Figure 1-1: VS5100 SOM Board Block Diagram ......................................................................................... 8 Figure 3-1: CN3 Location ......................................................................................................................... 14 Figure 3-2: CN1 and CN2 Locations ......................................................................................................... 14 Figure 3-3: VCC_CSI, VCC_SD2 & VCC_SD3 Voltage Level settings Resistors Location ........................... 30 Figure 8-1: Top View ................................................................................................................................ 68 Figure 8-2: Bottom View .......................................................................................................................... 68



1 OVERVIEW

1.1 GENERAL INFORMATION This document is the hardware reference manual for the VEST VS5100 SOM (System-On-Module) based on the NXP’s i.MX6 ARM® Cortex™-A9 architecture processors. The SOM provides an ideal building block that easily integrates with a wide range of target markets requiring rich multimedia functionality, powerful graphics, and video capabilities, as well as high-processing, compact, cost effective and with low power consumption.

The VS5100 SOM is tested to work in the following operating system environment:

Android

Embedded Linux

1.2 FEATURE SUMMARY NXP i.MX6 processors (Solo/DualLite ARM Cortex-A9 Core, up to 1.0 GHz/Core)

Up to 2GB of DDR3L SDRAM

Up to32GB of eMMC for boot/operating system/application/storage

USB 2.0 OTG (up to 480Mbps), with integrated HS USB PHY

USB 2.0 Host (480Mbps)

LVDS Serial Ports

PCIe V2.0 (shared the pinout with SD3 interface)

Parallel RGB Ports (up to 24bit)

AC97/I2S/SSI, up to 1.4Mbps

MMC/SD/SDIO

I2C

eCSPI

UART

CAN

PWM

MIPI CSI- 2 lanes

Parallel CSI - 12bit

GPIO

On Board 2Kb I2C EEPROM(AT24MAC402-MAHM-T)

10/100 Mbps Ethernet MAC

JTAG– on board 10pin FFC/FPC connector

Single3.3V Input Power Supply



35mm x 50mmForm Factor

2 x100 pin board to board connector

Support boot from eMMC or SD2 (4-bit)

1.3 BLOCK DIAGRAM

Figure 1-1: VS5100 SOM Board Block Diagram

1.4 LIST OF ACRONYMS

Acronyms Abbreviations

ARM Advanced RISC Machine

CAN Controller Area Network

CPU Central Processing Unit

CSI Camera Serial Interface

DDR3L Double Data Rate 3 Low Voltage

eCSPI Enhanced Configurable Serial Peripheral Interface

eMMC Enhanced Multi Media Card

GB Giga Byte



Acronyms Abbreviations

GPIO General Purpose Input Output

I2C Inter-Integrated Circuit

IC Integrated Circuit

JTAG Joint Test Action Group

LCD Liquid Crystal Display

LVDS Low Voltage Differential Signal

MB Mega Byte

Mbps Megabits per second

MHz Mega Hertz

MIPI Mobile Industry CPU Interface

MMC Multi-Media Card

PWM Pulse Width Modulation

PCIe Peripheral Component Interconnect Express

RMII Reduced Media Independent Interface

ROM Read-Only Memory

SD Secure Digital

SDIO Secure Digital Input Output

SDRAM Synchronous Dynamic Random Access Memory

SJC System JTAG Controller

SOM System On Module

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Port

USBOTG Universal Serial Port on the Go

Acronym Abbreviation

VEST Venture Embedded Solutions Technology

APC Advanced Products Corporation Private Limited

ISO International Organization for Standardization

Table 1-1: LIST OF ACRONYMS

1.5 REFERENCE DOCUMENTS

i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors Technical Data (Document Number: IMX6SDLAEC)

i.MX 6Solo/6DualLite Applications Processor Reference Manual (Document Number: IMX6SDLRM)

Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite (Document Number: AN4397)



2 MAIN HARDWARE COMPONENTS

This section summarizes the main hardware building blocks of the SOM

2.1 NXP I.MX 6SOLO/6DUALLITE

2.1.1 Overview The i.MX 6Solo/6DualLite processors represent NXP Semiconductor’s latest achievement in integrated multimedia-focused products.

The processors feature NXP’s advanced implementation of single/dual ARMCortex-A9 core. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32bit DDR3/LVDDR3 memory interface and some other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, display, and camera sensors.

2.1.2 Features The i.MX 6Solo/6DualLite processors are based on ARM Cortex-A9 MPCore Platform, which has the following features:

The i.MX 6Solo supports single ARM Cortex-A9 MPCore (with TrustZone)

The i.MX 6DualLite supports dual ARM Cortex-A9 MPCore (with TrustZone)

The core configuration is symmetric, where each core includes:

- 32 KByte L1 Instruction Cache

- 32 KByte L1 Data Cache

- Private Timer and Watchdog

- Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The ARM Cortex-A9 MPCore complex includes:

General Interrupt Controller with 128 interrupt support

Global Timer

Snoop Control Unit (SCU)

512 KB unified I/D L2 cache:

- Used by one core in i.MX 6Solo

- Shared by two cores in i.MX 6DualLite

The SoC-level memory system consists of the following additional components:

Boot ROM, including HAB (96 KB)

Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

Secure/non-secure RAM (16 KB)

External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards.

32-bit DDR3-800 and LV-DDR3-800



Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):

Displays

One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz)

One LVDS serial ports - up to 165 Mpixels/sec (for example, WUXGA at 60 Hz)

Camera sensors:

One parallel Camera ports (up to 12 bit and up to 240MHz peak)

MIPI CSI-2 Serial port, supporting from 80 Mbps to 1 Gbps speed per data lane. The CSI-2 Receiver core can manage one clock lane and up to two data lanes. Each i.MX 6Solo/6DualLite processor has two lanes.

MMC/SD/SDIO cards

USB:

- One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy

PCI Express Port (PCIe) V2.0 one lane:

- PCI Express (Gen2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Use x1 PHY configuration.

Miscellaneous IPs and interfaces:

- Up to four I2S

- Up to five UARTs, up to 5.0 Mbps each:

Providing RS232 interface

Supporting 9-bit RS485 multidrop mode

- Due to SOC IOMUX limitation, only one of the five UARTs (UART1) supports 8-wire, the rest of four only support 4-wire.

- Up to four eCSPI (Enhanced CSPI)

- Up to four I2C, supporting 400 kbps

- 10/100Mbps Ethernet Controller

- Up to four Pulse Width Modulators (PWM)

- System JTAG Controller (SJC)

- GPIO with interrupt capabilities

- Two Controller Area Network (FlexCAN), 1 Mbps each

- Two Watchdog timers (WDOG)

- Two Clock Controller Module(CCM)

The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers:

Provide PMU, including LDO supplies, for on-chip resources



Use Temperature Sensor for monitoring the die temperature

Support DVFS techniques for low power modes

Use SW State Retention and Power Gating for ARM and MPE

Support various levels of system power modes

Use flexible clock gating control scheme

The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers while having the CPU core relatively free for performing other tasks.

The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators:

VPU - Video Processing Unit

IPUv3H - Image Processing Unit version 3H

GPU3Dv5 - 3D Graphics Processing Unit (OpenGL ES 2.0) version 5

GPU2Dv2 - 2D Graphics Processing Unit (BitBlt)

ASRC - Asynchronous Sample Rate Converter

Note: Please refer the latest i.MX6 datasheet from NXP website for detail

2.2 MEMORY

2.2.1 DDR3L SDRAM The SOM uses two DDR3L SDRAM ICs to support onboard SDRAM memory.

These SDRAM operated at 1.5V voltage level. The SDRAM calibration resistor used on SOM is 240ohm 1% resistor.

Please see Section titled ’Board Options’ for various memory options.

2.2.2 eMMC Flash Memory The SOM has up to 32GB of eMMC Flash memory installed. The eMMC flash can be used for Flash Disk, O.S. run- time-image and the Boot-loader.

eMMC is directly connected to i.MX6 SDHC 4 and operating under 3.3V voltage level. The eMMC Flash memory is physically located on the bottom side of the SOM.

Please see Section titled ’Board Options’ for various eMMC Flash options.

2.2.3 On-board I2C EEPROM The SOM features a 2Kb I2C EEPROM (AT24MAC402-MAHM-T) and this EEPROM is directly connect to I2C2 bus.

2.3 PMIC The SOM uses the NXP PF0200 as a Power Management Integrated Circuit (PMIC) solution. The PF0200 is especially designed for the i.MX6Solo and i.MX6DualLite versions of the i.MX6 family of devices. The PF0200 regulates all power rails required on SOM.



2.4 BOARD VARIANT CONFIGURATION SETTINGS Three GPIO bits are used for different board variant configuration settings. These GPIO bits are either pull up or pull down by 10k resistor. These three bits are:

Signal Name i.MX6 pad name Signal Signal Type Voltage Level Description

BOARD_CFG_1 NANDF_D3 GPIO2_IO03 I 3.3V Board configuration 1

BOARD_CFG_2 NANDF_D2 GPIO2_IO02 I 3.3V Board configuration 2

BOARD_CFG_3 NANDF_CLE GPIO6_IO07 I 3.3V Board configuration 3

Table 2-1: GPIO bits Settings

The BOARD VARIANT configuration settings are:

BOARD VARIANT BOARD_CFG_3 BOARD_CFG_2 BOARD_CFG_1

SDIO Variant 1 1 1

PCIe Variant 1 1 0

Reserved 1 0 1

Reserved 1 0 0

Reserved 0 1 1

Reserved 0 1 0

Reserved 0 0 1

Reserved 0 0 0

Table 2-2: The BOARD VARIANT configuration settings



3 EXTERNAL INTERFACE

The VS5100 SOM uses two 100 pin board to board connectors (CN1 and CN2) for all I/Os connections, and one 10 pin FFC/FPC connector (CN3) for JTAG interface. The location of the connector are shown in the diagram below:

Figure 3-1: CN3 Location

Figure 3-2: CN1 and CN2 Locations

The recommended mating connectors are:

100pin board to board connector: DF40HC-100DS-0.4V(51) or equivalent

10pin FFC/FPC connector: FH12-10S-0.5SV(55) or equivalent

CN3

CN1

CN2



Note:

The i.MX6Solo/6DualLite contains a limited number of pins, most of which have multiple signal options called Muxing. These signal to pin and pin to signal options are selected by the input-output multiplexer called IOMUX.

Below Pin assignments lists the pad names of the chip, the various signals that can be assigned to each of the pads, for more detail please refer the latest i.MX6 datasheet

Pin No. : Pin number on the connector

Pin Name: Pin name on the connector

i.MX 6 pad name: Pad name on i.MX6

Signal: Signal name on the pad

Signal Type: Signal type of this pin

Voltage Level: Voltage level of this pin

Description: Short pin functionality description

3.1 CN1 PIN ASSIGNMENTS

Pin No. Pin Name i.MX6 pad

name

Signal Signal Type Voltage

Level

Description

CN1.1 GND - - Ground 0V GND


CN1.3 CAN1_TX GPIO_7 EPIT1_OUT

FLEXCAN1_TX

UART2_TX_DATA

GPIO1_IO07

I2C4_SCL

- 3.3V Muxing

CN1.4 UART4_RXD KEY_ROW0 ECSPI1_MOSI

AUD5_TXD

UART4_RX_DATA

GPIO4_IO07

- 3.3V Muxing

CN1.5 CAN1_RX GPIO_8 EPIT2_OUT

FLEXCAN1_RX

UART2_RX_DATA

GPIO1_IO08

I2C4_SDA

- 3.3V Muxing

CN1.6 UART4_TXD KEY_COL0 ECSP1_SCLK

AUD5_TXC

UART4_TX_DATA

GPIO4_IO06

- 3.3V Muxing

CN1.7 CAN1_STBY_GPIO13 GPIO_5 CCM_CLKO1

GPIO1_IO05

I2C3_SCL

- 3.3V Muxing




name


Level

Description

CN1.8 UART5_RXD KEY_ROW1 ECSPI1_SS0

AUD5_RXD

UART5_RX_DATA

GPIO4_IO09

SD2_VSELECT

- 3.3V Muxing

CN1.9 CAN2_STBY_GPIO14 GPIO_19 CCM_CLKO1

ECSPI1_RDY

GPIO4_IO05

ENET_TX_ER

- 3.3V Muxing

CN1.10 UART5_TXD KEY_COL1 ECSPI1_MISO

ENET_MDIO

AUD5_TXFS

UART5_TX_DATA

GPIO4_IO08

SD1_VSELECT

- 3.3V Muxing

CN1.11 CAN2_TX KEY_COL4 FLEXCAN2_TX

USB_OTG_OC

UART5_RTS_B

GPIO4_IO14

- 3.3V Muxing


CN1.13 CAN2_RX KEY_ROW4 FLEXCAN2_RX

USB_OTG_PWR

UART5_CTS_B

GPIO4_IO15

3.3V Muxing

CN1.14 LVDS0_TX3_N LVDS0_TX3_N LVDS0_DATA3_N Differential 2.5V LVDS

differential

pair3

negative

CN1.15 GPIO12 GPIO_17 GPIO7_IO12 - 3.3V Muxing

CN1.16 LVDS0_TX3_P LVDS0_TX3_P LVDS0_DATA3_P Differential 2.5V LVDS

differential

pair3

positive

CN1.17 CSI_EN GPIO_2 GPIO1_IO02

SD2_WP

- 3.3V Muxing


CN1.19 CSI_MCLK GPIO_0 CCM_CLKO1

ASRC_EXT_CLK

EPIT1_OUT

GPIO1_IO00

USB_H1_PWR

- 3.3V Muxing

CN1.20 LVDS0_CLK_N LVDS0_CLK_N LVDS0_CLK_N Differential 2.5V LVDS

differential

clock

negative


CN1.22 LVDS0_CLK_P LVDS0_CLK_P LVDS0_CLK_P Differential 2.5V LVDS

differential

clock

positive




name


Level

Description

CN1.23 CSI0_PIXCLK CSI0_PIXCLK IPU1_CSI0_PIXCLK

GPIO5_IO18

- VCC_CSI1 Muxing


CN1.25 CSI0_STROBE CSI0_DATA_EN IPU1_CSI0_DATA_EN

GPIO5_IO20

- VCC_CSI1 Muxing


differential

pair2

negative

CN1.27 CSI0_VSYNCH CSI0_VSYNC IPU1_CSI0_VSYNC

GPIO5_IO21

- VCC_CSI1 Muxing


differential

pair2

positive

CN1.29 CSI0_HSYNCH CSI0_MCLK IPU1_CSI0_HSYNC

CCM_CLKO1

GPIO5_IO19

- VCC_CSI1 Muxing




differential

pair1

negative

CN1.33 CSI0_DAT8_GPIO25 CSI0_DAT8 IPU1_CSI0_DATA08

ECSPI2_SCLK

I2C1_SDA

GPIO5_IO26

- VCC_CSI1 Muxing


differential

pair1

positive


ECSPI2_MOSI

I2C1_SCL

GPIO5_IO27

- VCC_CSI1 Muxing



AUD3_RXC

ECSPI2_MISO

UART1_TX_DATA

GPIO5_IO28

- VCC_CSI1 Muxing


differential

pair0

negative




name


Level

Description


AUD3_RXFS

ECSPI2_SS0

UART1_RX_DATA

GPIO5_IO29

- VCC_CSI1 Muxing


differential

pair0

positive

CN1.41 CSI0_DAT12 CSI0_DAT12 IPU1_CSI0_DATA12

UART4_TX_DATA

GPIO5_IO30

- VCC_CSI1 Muxing



UART4_RX_DATA

GPIO5_IO31

- VCC_CSI1 Muxing

CN1.44 AUD3_TXC CSI0_DAT4 IPU1_CSI0_DATA04

ECSPI1_SCLK

AUD3_TXC

GPIO5_IO22

- VCC_CSI1 Muxing


CN1.46 AUD3_TXD CSI0_DAT5 IPU1_CSI0_DATA05

ECSPI1_MOSI

AUD3_TXD

GPIO5_IO23

- VCC_CSI1 Muxing


UART5_TX_DATA

GPIO6_IO00

- VCC_CSI1 Muxing

CN1.48 AUD3_TXFS CSI0_DAT6 IPU1_CSI0_DATA06

ECSPI1_MISO

AUD3_TXFS

GPIO5_IO24

- VCC_CSI1 Muxing


UART5_RX_DATA

GPIO6_IO01

- VCC_CSI1 Muxing

CN1.50 AUD3_RXD CSI0_DAT7 IPU1_CSI0_DATA07

ECSPI1_SS0

AUD3_RXD

GPIO5_IO25

- VCC_CSI1 Muxing


UART4_RTS_B

GPIO6_IO02

- VCC_CSI1 Muxing

CN1.52 AUD_MCLK_GPIO24 NANDF_CS2 CCM_CLKO2

GPIO6_IO15

- 3.3V Muxing


UART4_CTS_B

GPIO6_IO03

- VCC_CSI1 Muxing




name


Level

Description



UART5_RTS_B

GPIO6_IO04

- VCC_CSI1 Muxing

CN1.56 USB_OTG_DN USB_OTG_DN USB_OTG_DN Differential 3.0V USB OTG

data

negative


UART5_CTS_B

GPIO6_IO05

- VCC_CSI1 Muxing

CN1.58 USB_OTG_DP USB_OTG_DP USB_OTG_DP Differential 3.0V USB OTG

data

positive


CN1.60 USB_OTG_ID GPIO_1 WDOG2_B

USB_OTG_ID

PWM2_OUT

GPIO1_IO01

SD1_CD_B

3.3V Muxing

CN1.61 BT_Pin1 EIM_DA4 SRC_BOOT_CFG04 - 3.3V Boot Select

14

CN1.62 USB_OTG_OC EIM_D21 ECSPI4_SCLK

USB_OTG_OC

GPIO3_IO21

I2C1_SCL

- 3.3V Muxing

CN1.63 BT_Pin3 EIM_DA6 SRC_BOOT_CFG06 - 3.3V Boot Select

34

CN1.64 USB_OTG_PWR_EN EIM_D22 ECSPI4_MISO

USB_OTG_PWR

GPIO3_IO22

- 3.3V Muxing

CN1.65 RESET PMIC PWRON - Input

(68K pull up)

3.0V Reset


CN1.67 CPU_PWR_BUTTON ONOFF SRC_ONOFF Input

(100K pull

up)

3.0V Power

on/off

CN1.68 USBHUB_nRST KEY_ROW2 ECSPI1_SS2

FLEXCAN1_RX

SD2_VSELECT

GPIO4_IO11

- 3.3V Muxing


CN1.70 USB_HOST_PWR_EN KEY_COL2 ECSPI1_SS1

FLEXCAN1_TX

ENET_MDC

GPIO4_IO10

- 3.3V Muxing

CN1.71 CSI_CLK0M CSI_CLK0M CSI_CLK0_N Differential 2.5V MIPI CSI

differential

clock

negative




name


Level

Description

CN1.72 USB_HOST_OC EIM_D30 IPU1_CSI0_DATA03

UART3_CTS_B

GPIO3_IO30

USB_H1_OC

- 3.3V Muxing

CN1.73 CSI_CLK0P CSI_CLK0P CSI_CLK0_P Differential 2.5V MIPI CSI

differential

clock

positive

CN1.74 USB_HOST_DP USB_H1_DP USB_H1_DP Differential 3.0V USB Host

data

positive

CN1.75 CSI_D0M CSI_D0M CSI_DATA0_N Differential 2.5V MIPI CSI

differential

data0

negative

CN1.76 USB_HOST_DN USB_H1_DN USB_H1_DN Differential 3.0V USB Host

data

negative

CN1.77 CSI_D0P CSI_D0P CSI_DATA0_P Differential 2.5V MIPI CSI

differential

data0

positive



CN1.80 I2C2_SCL KEY_COL3 I2C2_SCL Output

(4.7K pull

up)

3.3V I2C2_SCL

CN1.81 CSI_D1M CSI_D1M CSI_DATA1_N Differential 2.5V MIPI CSI

differential

data1

negative

CN1.82 I2C2_SDA KEY_ROW3 I2C2_SDA Bidirectional

(4.7K pull

up)

3.3V I2C2_SDA

CN1.83 CSI_D1P CSI_D1P CSI_DATA1_P Differential 2.5V MIPI CSI

differential

data1

positive

CN1.84 I2C4_SCL NANDF_WP_B GPIO6_IO09

I2C4_SCL

- 3.3V Muxing

CN1.85 I2C3_SDA GPIO_6 I2C3_SDA

GPIO1_IO06

SD2_LCTL

- 3.3V Muxing

CN1.86 I2C4_SDA NANDF_CS3 GPIO6_IO16

I2C4_SDA

- 3.3V Muxing

CN1.87 I2C3_SCL GPIO_3 I2C3_SCL

CCM_CLKO2

GPIO1_IO03

USB_H1_OC

- 3.3V GND




name


Level

Description

CN1.88 USB_HOST_VBUS USB_H1_VBUS USB_H1_VBUS Input 4.4-

5.25V

Primary

supply for

the 3V

regulator

CN1.89 CARRIER_PWR_ON - - Output 3.3V Carrier

board

power on

control

signal, high

active

CN1.90 USB_OTG_VBUS USB_OTG_VBUS USB_OTG_VBUS Input 4.4-

5.25V

Primary

supply for

the 3V

regulator



CN1.93 ENET_REF_CLK_50M GPIO_16 ENET_REF_CLK

SD1_LCTL

GPIO7_IO11

I2C3_SDA

- 3.3V Muxing

CN1.94 SOM_3V3 - - Input 3.3V Power







Table 3-1: CN1 Pin Assignments



name


Level

Description


(default)

(resistor

configurable5)

PCIE_RXM PCIE_RXM PCIE_RX_N Differential 2.5V PCIe

differential

receive line

negative

(resistor

configurable5)





name


Level

Description

CN2.3 SD3_CLK SD3_CLK SD3_CLK

UART2_RTS_B

FLEXCAN1_RX

GPIO7_IO03

- VCC_SD33

Muxing

(default)

(resistor

configurable5)

PCIE_RXP PCIE_RXP PCIE_RX_P Differential 2.5V PCIe

differential

receive line

positive

(resistor

configurable5)

CN2.4 SD2_CLK SD2_CLK SD2_CLK

AUD4_RXFS

GPIO1_IO10

- VCC_SD22

Muxing

CN2.5 SD3_CMD SD3_CMD SD3_CMD

UART2_CTS_B

FLEXCAN1_TX

GPIO7_IO02

- VCC_SD33

Muxing

(default)

(resistor

configurable5)

GND - - Ground 0V GND

(resistor

configurable5)

CN2.6 SD2_CMD SD2_CMD SD2_CMD

AUD4_RXC

GPIO1_IO11

- VCC_SD22

Muxing

CN2.7 SD3_DATA0 SD3_DAT0 SD3_DATA0

UART1_CTS_B

FLEXCAN2_TX

GPIO7_IO04

- VCC_SD33

Muxing

(default)

(resistor

configurable5)

PCIE_TXM PCIE_TXM PCIE_TX_N Differential/0.1

uF AC coupling

2.5V PCIe

differential

transmit line

negative

(resistor

configurable5)


AUD4_RXD

GPIO1_IO15

- VCC_SD22

Muxing


UART1_RTS_B

FLEXCAN2_RX

GPIO7_IO05

- VCC_SD33

Muxing

(default)

(resistor

configurable5)

PCIE_TXP PCIE_TXP PCIE_TX_P Differential/0.1

uF AC coupling

2.5V PCIe

differential

transmit line

positive

(resistor

configurable5)




name


Level

Description


AUD4_TXFS

GPIO1_IO14

- VCC_SD2 Muxing


GPIO7_IO06

- VCC_SD33

Muxing

(default)

(resistor

configurable5)


(resistor

configurable5)


AUD4_TXD

GPIO1_IO13

- VCC_SD22

Muxing


UART3_CTS_B

GPIO7_IO07

- VCC_SD33

Muxing

(default)

(resistor

configurable5)

PCIE_CLK1_N CLK1_N XTALOSC_CLK1_N Differential 2.5V PCIe

differential

clock

negative

(resistor

configurable5)


AUD4_TXC

GPIO1_IO12

- VCC_SD22

Muxing

CN2.15 SD3_CD_B NANDF_D0 GPIO2_IO00 - 3.3V Muxing

(default)

(resistor

configurable5)

PCIE_CLK1_P CLK1_P XTALOSC_CLK1_P Differential 2.5V PCIe

differential

clock

positive

(resistor

configurable5)

CN2.16 SD2_CD_B GPIO_4 GPIO1_IO04

SD2_CD_B

- 3.3V Muxing



CN2.19 GPIO7 SD1_CLK SD1_CLK

GPT_CLKIN

GPIO1_IO20

- 3.3V Muxing

CN2.20 GPIO1 NANDF_D4 SD2_DATA4

GPIO2_IO04

- 3.3V Muxing




name


Level

Description

CN2.21 GPIO8 SD1_DAT0 SD1_DATA0

GPIO1_IO16

- 3.3V Muxing


GPIO2_IO05

- 3.3V Muxing

CN2.23 GPIO9_PWM3 SD1_DAT1 SD1_DATA1

PWM3_OUT

GPT_CAPTURE2

GPIO1_IO17

- 3.3V Muxing


GPIO2_IO06

- 3.3V Muxing

CN2.25 GPIO10_PWM2 SD1_DAT2 SD1_DATA2

GPT_COMPARE2

PWM2_OUT

WDOG1_B

GPIO1_IO19

WDOG1_RESET_B_D

EB

- 3.3V Muxing


GPIO2_IO07

- 3.3V Muxing

CN2.27 GPIO11 EIM_D31 IPU1_CSI0_DATA02

UART3_RTS_B

GPIO3_IO31

USB_H1_PWR

- 3.3V Muxing

CN2.28 GPIO5 NANDF_RB0 GPIO6_IO10 - 3.3V Muxing

CN2.29 BACKLIGHT_EN EIM_BCLK GPIO6_IO31 - 3.3V Muxing

CN2.30 GPIO6_PWM4 SD1_CMD SD1_CMD

PWM4_OUT

GPT_COMPARE1

GPIO1_IO18

- 3.3V Muxing

CN2.31 DISP0_PWM SD1_DAT3 SD1_DATA3

GPT_COMPARE3

PWM1_OUT

WDOG2_B

GPIO1_IO21

WDOG2_RESET_B_D

EB

- 3.3V Muxing



CN2.34 UART1_RTS_GPIO

16

EIM_D20 ECSPI4_SS0

UART1_RTS_B

GPIO3_IO20

EPIT2_OUT

- 3.3V Muxing

CN2.35 DISP0_CLK DI0_DISP_CL

K

IPU1_DI0_DISP_CLK

GPIO4_IO16

- 3.3V Muxing

CN2.36 UART1_CTS_GPIO

15

EIM_D19 ECSPI1_SS1

UART1_CTS_B

GPIO3_IO19

EPIT1_OUT

- 3.3V Muxing




name


Level

Description

CN2.37 DISP0_HSYNCH DI0_PIN2 AUD6_TXD

GPIO4_IO18

- 3.3V Muxing

CN2.38 UART1_TXD SD3_DAT7 UART1_TX_DATA

GPIO6_IO17

- VCC_SD33

Muxing

CN2.39 DISP0_VSYNCH DI0_PIN3 AUD6_TXFS

GPIO4_IO19

- 3.3V Muxing

CN2.40 UART1_RXD SD3_DAT6 UART1_RX_DATA

GPIO6_IO18

- VCC_SD33

Muxing

CN2.41 DISP0_CNTRST DI0_PIN4 AUD6_RXD

SD1_WP

GPIO4_IO20

- 3.3V Muxing

CN2.42 UART3_RTS EIM_EB3 ECSPI4_RDY

UART3_RTS_B

UART1_RI_B

GPIO2_IO31

-

(200K pull

down)

3.3V Muxing

(this pin

must be low

during boot

up)

CN2.43 DISP0_DRDY DI0_PIN15 AUD6_TXC

GPIO4_IO17

- 3.3V Muxing

CN2.44 UART3_CTS EIM_D23 UART3_CTS_B

UART1_DCD_B

GPIO3_IO23

- 3.3V Muxing



CN2.47 DISP0_DAT0 DISP0_DAT0 IPU1_DISP0_DATA00

ECSPI3_SCLK

GPIO4_IO21

- 3.3V Muxing

CN2.48 UART3_TXD EIM_D24 ECSPI4_SS2

UART3_TX_DATA

ECSPI1_SS2

ECSPI2_SS2

AUD5_RXFS

UART1_DTR_B

GPIO3_IO24

- 3.3V Muxing


ECSPI3_MOSI

GPIO4_IO22

- 3.3V Muxing

CN2.50 UART3_RXD EIM_D25 ECSPI4_SS3

UART3_RX_DATA

ECSPI1_SS3

ECSPI2_SS3

GPIO3_IO25

AUD5_RXC

UART1_DSR_B

- 3.3V Muxing


ECSPI3_MISO

GPIO4_IO23

- 3.3V Muxing




name


Level

Description

CN2.52 UART2_RTS_GPIO

18

EIM_D29 ECSPI4_SS0

UART2_RTS_B

GPIO3_IO29

- 3.3V Muxing


ECSPI3_SS0

GPIO4_IO24

- 3.3V Muxing

CN2.54 UART2_CTS_GPIO

17

EIM_D28 I2C1_SDA

ECSPI4_MOSI

UART2_CTS_B

GPIO3_IO28

- 3.3V Muxing


ECSPI3_SS1

GPIO4_IO25

- 3.3V Muxing

CN2.56 UART2_RXD EIM_D27 IPU1_CSI0_DATA00

UART2_RX_DATA

GPIO3_IO27

- 3.3V Muxing


ECSPI3_SS2

AUD6_RXFS

GPIO4_IO26

- 3.3V Muxing

CN2.58 UART2_TXD EIM_D26 IPU1_CSI0_DATA01

UART2_TX_DATA

GPIO3_IO26

- 3.3V Muxing


ECSPI3_SS3

AUD6_RXC

GPIO4_IO27

- 3.3V Muxing

CN2.60 GND Ground 0V GND


ECSPI3_RDY

GPIO4_IO28

- 3.3V Muxing

CN2.62 SPI_SCLK_GPIO21 EIM_CS0 ECSPI2_SCLK

GPIO2_IO23

- 3.3V Muxing


CN2.64 SPI_MOSI_GPIO20 EIM_CS1 ECSPI2_MOSI

GPIO2_IO24

- 3.3V Muxing


PWM1_OUT

WDOG1_B

GPIO4_IO29

- 3.3V Muxing

CN2.66 SPI_MISO_GPIO19 EIM_OE ECSPI2_MISO

GPIO2_IO25

- 3.3V Muxing


PWM2_OUT

WDOG2_B

GPIO4_IO30

- 3.3V Muxing




name


Level

Description

CN2.68 SPI_SS0_GPIO22 EIM_RW ECSPI2_SS0

GPIO2_IO26

- 3.3V Muxing


GPIO4_IO31

- 3.3V Muxing

CN2.70 SPI_SS1_GPIO23 EIM_LBA ECSPI2_SS1

GPIO2_IO27

- 3.3V Muxing


GPIO5_IO05

- 3.3V Muxing

CN2.72 PHY_REST_B ENET_REF_CL

K

GPIO1_IO23 - 3.3V Muxing


GPIO5_IO06

- 3.3V Muxing

CN2.74 PHY_INT_B EIM_WAIT GPIO5_IO00 - 3.3V Muxing


AUD5_RXFS

GPIO5_IO07

- 3.3V Muxing

CN2.76 GND Ground 0V GND


AUD5_RXC

GPIO5_IO08

- 3.3V Muxing

CN2.78 ENET_RX_ER ENET_RX_ER USB_OTG_ID

ENET_RX_ER

GPIO1_IO24

- 3.3V Muxing


ECSPI1_SS1

ECSPI2_SS1

GPIO5_IO09

- 3.3V Muxing

CN2.80 ENET_TX_EN ENET_TX_EN ENET_TX_EN

GPIO1_IO28

I2C4_SCL

- 3.3V Muxing


CN2.82 ENET_CRS_DV ENET_CRS_D

V

ENET_RX_EN

GPIO1_IO25

- 3.3V Muxing


ECSPI2_MOSI

AUD5_TXC

GPIO5_IO10

- 3.3V Muxing



ECSPI2_MISO

AUD5_TXD

GPIO5_IO11

- 3.3V Muxing

CN2.86 ENET_MDIO ENET_MDIO ENE_MDIO

GPIO1_IO22

- 3.3V Muxing




name


Level

Description


ECSPI2_SS0

AUD5_TXFS

AUD4_RXFS

GPIO5_IO12

- 3.3V Muxing

CN2.88 ENET_MDC ENET_MDC ENET_MDC

GPIO1_IO31

- 3.3V Muxing


ECSPI2_SCLK

AUD5_RXD

AUD4_RXC

GPIO5_IO13

- 3.3V Muxing



ECSPI1_SCLK

AUD4_TXC

GPIO5_IO14

- 3.3V Muxing

CN2.92 ENET_RXD0 ENET_RXD0 ENET_RX_DATA0

GPIO1_IO27

- 3.3V Muxing


ECSPI1_MOSI

AUD4_TXD

GPIO5_IO15

- 3.3V Muxing

CN2.94 ENET_RXD1 ENET_RXD1 ENET_RX_DATA1

GPIO1_IO26

- 3.3V Muxing


ECSPI1_MISO

AUD4_TXFS

GPIO5_IO16

- 3.3V Muxing

CN2.96 ENET_TXD0 ENET_TXD0 ENET_TX_DATA0

GPIO1_IO30

- 3.3V Muxing


ECSPI1_SS0

AUD4_RXD

GPIO5_IO17

- 3.3V Muxing

CN2.98 ENET_TXD1 ENET_TXD1 ENET_TX_DATA1

GPIO1_IO29

I2C4_SDA

- 3.3V Muxing


CN2.10

0







name


Level

Description

CN3.1 JTAG_VREF - - Output 3.3V Power

CN3.2 JTAG_nTRST JTAG_TRSTB JTAG_TRSTB Input

(47K pull

up)

3.3V No Muxing

CN3.3 JTAG_TDI JTAG_TDI STAG_TDI Input

(47K pull

up)

3.3V No Muxing

CN3.4 JTAG_TMS JTAG_TMS JTAG_TMS Input

(47K pull

up)

3.3V No Muxing

CN3.5 JTAG_TCK JTAG_TCK JTAG_TCK Input

(47K pull

up)

3.3V No Muxing


CN3.7 JTAG_TDO JTAG_TDO JTAG_TDO Output 3.3V No Muxing

CN3.8 JTAG_nSRST POR_B SRC_POR_B Input 3.3V System reset

CN3.9 JTAG_DE - - Output 3.3V Through 10K to 3.3V

power



Notes:

1. The VCC_CSI voltage level default is 1.8V, it’s configurable by resistor R4, R34 and R40.

VCC_CSI Voltage Level R4 R34 R40

1.8V(default) Populate Non-populate Non-populate

2.8V Non-populate Populate Non-populate

3.3V Non-populate Non-populate Populate

Table 3-4: VCC_CSI Voltage Level Settings

2. The VCC_SD2 voltage level default is 3.3V, it’s configurable by resistor R9, R37 and R45.

VCC_SD2 Voltage Level R9 R37 R45

1.8V Populate Non-populate Non-populate


3.3V(default) Non-populate Non-populate Populate

Table 3-5: VCC_SD2 Voltage Level Settings

3. The VCC_SD3 voltage level default is 3.3V, it’s configurable by resistor R12, R72 and R78.

VCC_SD3 Voltage Level R12 R72 R78



1.8V Populate Non-populate Non-populate


3.3V(default) Non-populate Non-populate Populate

Table 3-6: VCC_SD3 Voltage Level Settings

Figure 3-3: VCC_CSI, VCC_SD2 & VCC_SD3 Voltage Level settings Resistors Location

4. The SOM board support boot from serial downloader or eMMC or SD2 (4-bit) by the configuration of BT_Pin1 and BT_Pin3.

Serial Downloader eMMC SD2(4-bit)

BT_Pin1 0 1 1

BT_Pin3 1 1 0

Table 3-7: SOM Board Boot Source Settings

5. The SD3 and PCIe interface are shared same pinout of CN2:1, CN2:3, CN2:5, CN2:7, CN2:9, CN2:11, CN2:13 and CN2:15, its resistor configurable and the default is SD3 interface.

Populated Non-populated

SD3 Interface (default) R81,R82,R83,R84,R85,R86,R87,R88 R89,R90,R91,R92,R93,R94,R95,R96

PCIe Interface R89,R90,R91,R92,R93,R94,R95,R96 R81,R82,R83,R84,R85,R86,R87,R88

Table 3-8: Resistors Loading Configurations for SD3 vs. PCIe

R4

R40

R34

R9

R45

R37

R78

R72

R12



4 SIGNAL DESCRIPTION PER BLOCK/INSTANCE

This chapter describes in detail the external interfaces per block/instance, referring to the default SOM pin names.

SIGNAL:

Signal name on the block/instance

PIN NO. :

Pin number on the connector

PIN NAME:

Pin name on the connector

I.MX6 PAD NAME:

Pad name on iMXi.MX6

SIGNAL TYPE:

I – In

O - Out

I/O – Input/output

DESCRIPTION:

Short pin functionality description

4.1 DIGITAL AUDIO MUX (AUDMUX) The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnected device for voice, audio, and synchronous data routing between Synchronous Serial Interface Controller (SSI) and audio/voice codec’s (also known as coder-decoders) peripheral serial interfaces.

The following table describes the external signals of AUDMUX:

Signal Pin No.

Pin Name i.MX6 pad name

Signal Type

Voltage Level

Description

AUD3_RXC CN1.37 CSI0_DAT10_GPIO27 CSI0_DAT10 I/O VCC_CSI Receive clock signal

AUD3_RXD CN1.50 AUD3_RXD CSI0_DAT7 I/O VCC_CSI Data receive signal

AUD3_RXFS CN1.39 CSI0_DAT11_GPIO28 CSI0_DAT11 I/O VCC_CSI Receive frame sync signal

AUD3_TXC CN1.44 AUD3_TXC CSI0_DAT4 I/O VCC_CSI Transmit clock signal

AUD3_TXD CN1.46 AUD3_TXD CSI0_DAT5 I/O VCC_CSI Data transmit signal

AUD3_TXFS CN1.48 AUD3_TXFS CSI0_DAT6 I/O VCC_CSI Transmit frame sync signal

AUD4_RXC CN2.89 DISP0_DAT19 DISP0_DAT19 I/O 3.3V Receive clock signal

CN2.6 SD2_CMD SD2_CMD I/O VCC_SD2

AUD4_RXD CN2.97 DISP0_DAT23 DISP0_DAT23 I/O 3.3V Data receive signal



Signal Pin No.


Signal Type

Voltage Level

Description

CN2.8 SD2_DATA0 SD2_DAT0 I/O VCC_SD2

AUD4_RXFS CN2.87 DISP0_DAT18 DISP0_DAT18 I/O 3.3V Receive frame sync signal

CN2.4 SD2_CLK SD2_CLK I/O VCC_SD2

AUD4_TXC CN2.91 DISP0_DAT20 DISP0_DAT20 I/O 3.3V Transmit clock signal


AUD4_TXD CN2.93 DISP0_DAT21 DISP0_DAT21 I/O 3.3V Data transmit signal


AUD4_TXFS CN2.95 DISP0_DAT22 DISP0_DAT22 I/O 3.3V Transmit frame sync signal



CN2.50 UART3_RXD EIM_D25 I/O 3.3V

AUD5_RXD CN2.89 DISP0_DAT19 DISP0_DAT19 I/O 3.3V Data receive signal

CN1.8 UART5_RXD KEY_ROW1 I/O 3.3V


CN2.48 UART3_TXD EIM_D24 I/O 3.3V

AUD5_TXC CN2.83 DISP0_DAT16 DISP0_DAT16 I/O 3.3V Transmit clock signal

CN1.6 UART4_TXD KEY_COL0 I/O 3.3V

AUD5_TXD CN2.85 DISP0_DAT17 DISP0_DAT17 I/O 3.3V Data transmit signal

CN1.4 UART4_RXD KEY_ROW0 I/O 3.3V

AUD5_TXFS CN2.87 DISP0_DAT18 DISP0_DAT18 I/O 3.3V Transmit frame sync signal

CN1.10 UART5_TXD KEY_COL1 I/O 3.3V


AUD6_RXD CN2.41 DISP0_CNTRST DI0_PIN4 I/O 3.3V Data receive signal


AUD6_TXC CN2.43 DISP0_DRDY DI0_PIN15 I/O 3.3V Transmit clock signal

AUD6_TXD CN2.37 DISP0_HSYNCH DI0_PIN2 I/O 3.3V Data transmit signal

AUD6_TXFS CN2.39 DISP0_VSYNCH DI0_PIN3 I/O 3.3V Transmit frame sync signal

Table 4-1: External Signals of AUDMUX



4.2 CLOCK CONTROLLER MODULE (CCM) The Clock Control Module (CCM) generates and controls clocks to the various modules in the design and manages low power modes. This module uses the available clock sources to generate the clock roots.

The following table describes the external signals of CCM:

Signal Pin No.


Signal Type

Voltage Level

Description

CCM_CLKO1 CN1.19 CSI_MCLK GPIO_0 O 3.3V Observability clock 1 output

CN1.29 CSI0_HSYNCH CSI0_MCLK VCC_CSI

CN1.7 CAN1_STBY_GPIO13 GPIO_5 3.3V


CCM_CLKO2 CN1.87 I2C3_SCL GPIO_3 O 3.3V Observability clock 2 output

CN1.52 AUD_MCLK_GPIO24 NANDF_CS2 3.3V

Table 4-2: External Signals of CCM

4.3 ENHANCED CONFIGURABLE SPI (ECSPI)

The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex, synchronous, four-wire serial communication block.

The ECSPI contains a 64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer (TXFIFO). With data FIFOs, the ECSPI allows rapid data communication with fewer software interrupts.

The following table describes the external signals of ECSPI 1:

Signal Pin No.


Signal Type

Voltage Level

Description

ECSPI1_MISO CN1.48 AUD3_TXFS CSI0_DAT6 I/O VCC_CSI Master data in; slave data out

CN2.95 DISP0_DAT22 DISP0_DAT22 3.3V

CN1.10 UART5_TXD KEY_COL1 3.3V

ECSPI1_MOSI CN1.46 AUD3_TXD CSI0_DAT5 I/O VCC_CSI Master data out; slave data in


CN1.4 UART4_RXD KEY_ROW0 3.3V

ECSPI1_RDY CN1.9 CAN2_STBY_GPIO14 GPIO_19 I 3.3V SPI data ready signal

ECSPI1_SCLK CN1.44 AUD3_TXC CSI0_DAT4 I/O VCC_CSI SPI clock signal



ECSPI1_SS0 CN1.50 AUD3_RXD CSI0_DAT7 I/O VCC_CSI Chip select signal




Signal Pin No.


Signal Type

Voltage Level

Description

CN1.8 UART5_RXD KEY_ROW1 3.3V

ECSPI1_SS1 CN2.79 DISP0_DAT15 DISP0_DAT15 I/O 3.3V Chip select signal

CN2.36 UART1_CTS_GPIO15 EIM_D19 3.3V

CN1.70 USB_HOST_PWR_EN KEY_COL2 3.3V

ECSPI1_SS2 CN2.48 UART3_TXD EIM_D24 I/O 3.3V Chip select signal

CN1.68 USBHUB_nRST KEY_ROW2 3.3V

ECSPI1_SS3 CN2.50 UART3_RXD EIM_D25 I/O 3.3V Chip select signal

Table 4-3: External Signals of ECSPI 1


Signal Pin No.


Signal Type

Voltage Level

Description

ECSPI2_MISO CN1.37 CSI0_DAT10_GPIO27 CSI0_DAT10 I/O VCC_CSI Master data in; slave data out


CN2.66 SPI_MISO_GPIO19 EIM_OE 3.3V

ECSPI2_MOSI CN1.35 CSI0_DAT9_GPIO26 CSI0_DAT9 I/O VCC_CSI Master data out; slave data in


CN2.64 SPI_MOSI_GPIO20 EIM_CS1 3.3V

ECSPI2_SCLK CN1.33 CSI0_DAT8_GPIO25 CSI0_DAT8 I/O VCC_CSI SPI clock signal


CN2.62 SPI_SCLK_GPIO21 EIM_CS0 3.3V

ECSPI2_SS0 CN1.39 CSI0_DAT11_GPIO28 CSI0_DAT11 I/O VCC_CSI Chip select signal


CN2.68 SPI_SS0_GPIO22 EIM_RW 3.3V


CN2.70 SPI_SS1_GPIO23 EIM_LBA 3.3V



Signal Pin No.


Signal Type

Voltage Level

Description





Signal Pin No.


Signal Type

Voltage Level

Description

ECSPI3_MISO CN2.51 DISP0_DAT2 DISP0_DAT2 I/O 3.3V Master data in; slave data out

ECSPI3_MOSI CN2.49 DISP0_DAT1 DISP0_DAT1 I/O 3.3V Master data out; slave data in

ECSPI3_RDY CN2.61 DISP0_DAT7 DISP0_DAT7 I 3.3V SPI data ready signal

ECSPI3_SCLK CN2.47 DISP0_DAT0 DISP0_DAT0 I/O 3.3V SPI clock signal







Signal Pin No.


Signal Type

Voltage Level

Description

ECSPI4_MISO CN1.64 USB_OTG_PWR_EN EIM_D22 I/O 3.3V Master data in; slave data out

ECSPI4_MOSI CN2.54 UART2_CTS_GPIO17 EIM_D28 I/O 3.3V Master data out; slave data in

ECSPI4_RDY CN2.42 UART3_RTS EIM_EB3 I 3.3V SPI data ready signal

ECSPI4_SCLK CN1.62 USB_OTG_OC EIM_D21 I/O 3.3V SPI clock signal

ECSPI4_SS0 CN2.34 UART1_RTS_GPIO16 EIM_D20 I/O 3.3V Chip select signal

CN2.52 UART2_RTS_GPIO18 EIM_D29 3.3V




Signal Pin No.


Signal Type

Voltage Level

Description



4.4 10/100-MBPS RMII ETHERNET MAC (ENET) The MAC-NET core, in conjunction with a 10/100 MAC, implements layer 3 network acceleration functions. These functions are designed to accelerate the processing of various common networking protocols which compliant with the IEEE802.3-2002 standard.

The following table describes the external signals of ENET:

Signal Pin No.


Signal Type

Voltage Level

Description

ENET_MDC CN2.88 ENET_MDC ENET_MDC O 3.3V Output clock provides a timing reference to the PHY for data transfers on the MDIO signal.


ENET_MDIO CN2.86 ENET_MDIO ENET_MDIO I/O 3.3V Transfers control information between the external PHY and the media-access controller. Data is synchronous to MDC. This signal is an input after reset


ENET_REF_CLK CN1.93 ENET_REF_CLK_50M GPIO_16 I/O 3.3V In RMII mode, this signal is the reference clock for receive, transmit, and the control interface

ENET_RX_DATA0 CN2.92 ENET_RXD0 ENET_RXD0 I/O 3.3V Contains the Ethernet input data transferred from the PHY to the media-access controller when RX_EN is asserted.

ENET_RX_DATA1 CN2.94 ENET_RXD1 ENET_RXD1 I/O 3.3V Contains the Ethernet input data transferred from the PHY to the media-access controller when RX_EN is asserted.

ENET_RX_EN CN2.82 ENET_CRS_DV ENET_CRS_DV I 3.3V Asserting this input indicates the PHY has valid nibbles present on the RMII. RX_EN must remain asserted from the first recovered nibble of the frame through to the last nibble. Asserting RX_EN must start no later than the SFD and exclude and EOF. In RMII mode, this pin also generates the CRS signal.

ENET_RX_ER CN2.78 ENET_RX_ER ENET_RX_ER I 3.3V When asserted with RXDV, indicates the PHY detects an error in the current frame

ENET_TX_DATA0 CN2.96 ENET_TXD0 ENET_TXD0 I/O 3.3V Serial output Ethernet data. Only valid during TX_EN assertion

ENET_TX_DATA1 CN2.98 ENET_TXD1 ENET_TXD1 I/O 3.3V Serial output Ethernet data. Only valid during TX_EN assertion



Signal Pin No.


Signal Type

Voltage Level

Description

ENET_TX_EN CN2.80 ENET_TX_EN ENET_TX_EN O 3.3V Indicates when valid nibbles are present on the RMII. This signal is asserted with the first nibble of a preamble and is deasserted before then first TX_CLK following the final nibble of the frame

ENET_TX_ER CN1.9 CAN2_STBY_GPIO14 GPIO_19 O 3.3V When asserted for one of more clock cycles while TXEN is also asserted, PHY sends one or more illegal symbols

Table 4-7: External Signals of ENET

4.5 ENHANCED PERIODIC INTERRUPT TIMER (EPIT) EPIT is a 32-bit set-and-forget timer that is capable of providing precise interrupts at regular intervals with minimal processor intervention. EPIT begins counting after it is enabled by software.

The following table describes the external signals of EPIT:

Signal Pin No.


Signal Type

Voltage Level

Description

EPIT1_OUT CN2.36 UART1_CTS_GPIO15 EIM_D19 O 3.3V Output 1 pin at chip boundary for indicating the occurrence of an output compare event through a specified transition.

CN1.19 CSI_MCLK GPIO_0 3.3V

CN1.3 CAN1_TX GPIO_7 3.3V

EPIT2_OUT CN2.34 UART1_RTS_GPIO16 EIM_D20 O 3.3V Output 2 pin at chip boundary for indicating the occurrence of an output compare event through a specified transition.

CN1.5 CAN1_RX GPIO_8 3.3V

Table 4-8: External Signals of EPIT

4.6 FLEXIBLE CONTROLLER AREA NETWORK (FLEXCAN) The Flexible Controller Area Network (FLEXCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. The CAN protocol was primarily designed to be used as a vehicle serial data bus meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN module is a full implementation of the CAN protocol specification, which supports both standard and extended message frames. 64 Message Buffers are supported.

The following table describes the external signals of FLEXCAN:

Signal Pin No.


Signal Type

Voltage Level

Description

FLEXCAN1_RX CN1.5 CAN1_RX GPIO_8 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


CN2.3 SD3_CLK SD3_CLK VCC_SD3



Signal Pin No.


Signal Type

Voltage Level

Description

FLEXCAN1_TX CN1.3 CAN1_TX GPIO_7 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


CN2.5 SD3_CMD SD3_CMD VCC_SD3

FLEXCAN2_RX CN1.13 CAN2_RX KEY_ROW4 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.

CN2.9 SD3_DATA1 SD3_DAT1 VCC_SD3

FLEXCAN2_TX CN1.11 CAN2_TX KEY_COL4 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


Table 4-9: External Signals of FLEXCAN

4.7 GENERAL PURPOSE INPUT/OUTPUT (GPIO) The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts.

The following table describes the external signals of GPIO1:

Signal Pin No. Pin Name i.MX6 pad name Signal Type Voltage Level Description

GPIO1_IO00 CN1.19 CSI_MCLK GPIO_0 I/O 3.3V -

GPIO1_IO01 CN1.60 USB_OTG_ID GPIO_1 I/O 3.3V -

GPIO1_IO02 CN1.17 CSI_EN GPIO_2 I/O 3.3V -

GPIO1_IO03 CN1.87 I2C3_SCL GPIO_3 I/O 3.3V -

GPIO1_IO04 CN2.16 SD2_CD_B GPIO_4 I/O 3.3V -

GPIO1_IO05 CN1.7 CAN1_STBY_GPIO13 GPIO_5 I/O 3.3V -




GPIO1_IO06 CN1.85 I2C3_SDA GPIO_6 I/O 3.3V -

GPIO1_IO07 CN1.3 CAN1_TX GPIO_7 I/O 3.3V -

GPIO1_IO08 CN1.5 CAN1_RX GPIO_8 I/O 3.3V -

GPIO1_IO10 CN2.4 SD2_CLK SD2_CLK I/O VCC_SD2 -

GPIO1_IO11 CN2.6 SD2_CMD SD2_CMD I/O VCC_SD2 -

GPIO1_IO12 CN2.14 SD2_DATA3 SD2_DAT3 I/O VCC_SD2 -




GPIO1_IO16 CN2.21 GPIO8 SD1_DAT0 I/O 3.3V -

GPIO1_IO17 CN2.23 GPIO9_PWM3 SD1_DAT1 I/O 3.3V -

GPIO1_IO18 CN2.30 GPIO6_PWM4 SD1_CMD I/O 3.3V -

GPIO1_IO19 CN2.25 GPIO10_PWM2 SD1_DAT2 I/O 3.3V -

GPIO1_IO20 CN2.19 GPIO7 SD1_CLK I/O 3.3V -

GPIO1_IO21 CN2.31 DISP0_PWM SD1_DAT3 I/O 3.3V -

GPIO1_IO22 CN2.86 ENET_MDIO ENET_MDIO I/O 3.3V -

GPIO1_IO23 CN2.72 PHY_REST_B ENET_REF_CLK I/O 3.3V -

GPIO1_IO24 CN2.78 ENET_RX_ER ENET_RX_ER I/O 3.3V -

GPIO1_IO25 CN2.82 ENET_CRS_DV ENET_CRS_DV I/O 3.3V -

GPIO1_IO26 CN2.94 ENET_RXD1 ENET_RXD1 I/O 3.3V -

GPIO1_IO27 CN2.92 ENET_RXD0 ENET_RXD0 I/O 3.3V -

GPIO1_IO28 CN2.80 ENET_TX_EN ENET_TX_EN I/O 3.3V -




GPIO1_IO29 CN2.98 ENET_TXD1 ENET_TXD1 I/O 3.3V -

GPIO1_IO30 CN2.96 ENET_TXD0 ENET_TXD0 I/O 3.3V -

GPIO1_IO31 CN2.88 ENET_MDC ENET_MDC I/O 3.3V -

Table 4-10: External Signals of GPiO1



GPIO2_IO00 CN2.15 SD3_CD_B NANDF_D0 I/O 3.3V -

GPIO2_IO04 CN2.20 GPIO1 NANDF_D4 I/O 3.3V -




GPIO2_IO23 CN2.62 SPI_SCLK_GPIO21 EIM_CS0 I/O 3.3V -

GPIO2_IO24 CN2.64 SPI_MOSI_GPIO20 EIM_CS1 I/O 3.3V -

GPIO2_IO25 CN2.66 SPI_MISO_GPIO19 EIM_OE I/O 3.3V -

GPIO2_IO26 CN2.68 SPI_SS0_GPIO22 EIM_RW I/O 3.3V -

GPIO2_IO27 CN2.70 SPI_SS1_GPIO23 EIM_LBA I/O 3.3V -

GPIO2_IO31 CN2.42 UART3_RTS EIM_EB3 I/O 3.3V -

Table 4-11: External Signals of GPIO2



GPIO3_IO19 CN2.36 UART1_CTS_GPIO15 EIM_D19 I/O 3.3V -

GPIO3_IO20 CN2.34 UART1_RTS_GPIO16 EIM_D20 I/O 3.3V -

GPIO3_IO21 CN1.62 USB_OTG_OC EIM_D21 I/O 3.3V -




GPIO3_IO22 CN1.64 USB_OTG_PWR_EN EIM_D22 I/O 3.3V -

GPIO3_IO23 CN2.44 UART3_CTS EIM_D23 I/O 3.3V -

GPIO3_IO24 CN2.48 UART3_TXD EIM_D24 I/O 3.3V -

GPIO3_IO25 CN2.50 UART3_RXD EIM_D25 I/O 3.3V -

GPIO3_IO26 CN2.58 UART2_TXD EIM_D26 I/O 3.3V -

GPIO3_IO27 CN2.56 UART2_RXD EIM_D27 I/O 3.3V -

GPIO3_IO28 CN2.54 UART2_CTS_GPIO17 EIM_D28 I/O 3.3V -

GPIO3_IO29 CN2.52 UART2_RTS_GPIO18 EIM_D29 I/O 3.3V -

GPIO3_IO30 CN1.72 USB_HOST_OC EIM_D30 I/O 3.3V -

GPIO3_IO31 CN2.27 GPIO11 EIM_D31 I/O 3.3V -




GPIO4_IO05 CN1.9 CAN2_STBY_GPIO14 GPIO_19 I/O 3.3V -

GPIO4_IO06 CN1.6 UART4_TXD KEY_COL0 I/O 3.3V -

GPIO4_IO07 CN1.4 UART4_RXD KEY_ROW0 I/O 3.3V -

GPIO4_IO08 CN1.10 UART5_TXD KEY_COL1 I/O 3.3V -

GPIO4_IO09 CN1.8 UART5_RXD KEY_ROW1 I/O 3.3V -

GPIO4_IO10 CN1.70 USB_HOST_PWR_EN KEY_COL2 I/O 3.3V -

GPIO4_IO11 CN1.68 USBHUB_nRST KEY_ROW2 I/O 3.3V -

GPIO4_IO14 CN1.11 CAN2_TX KEY_COL4 I/O 3.3V -

GPIO4_IO15 CN1.13 CAN2_RX KEY_ROW4 I/O 3.3V -

GPIO4_IO16 CN2.35 DISP0_CLK DI0_DISP_CLK I/O 3.3V -

GPIO4_IO17 CN2.43 DISP0_DRDY DI0_PIN15 I/O 3.3V -

GPIO4_IO18 CN2.37 DISP0_HSYNCH DI0_PIN2 I/O 3.3V -

GPIO4_IO19 CN2.39 DISP0_VSYNCH DI0_PIN3 I/O 3.3V -

GPIO4_IO20 CN2.41 DISP0_CNTRST DI0_PIN4 I/O 3.3V -

GPIO4_IO21 CN2.47 DISP0_DAT0 DISP0_DAT0 I/O 3.3V -

















GPIO5_IO00 CN2.74 PHY_INT_B EIM_WAIT I/O 3.3V -

















GPIO5_IO18 CN1.23 CSI0_PIXCLK CSI0_PIXCLK I/O VCC_CSI -

GPIO5_IO19 CN1.29 CSI0_HSYNCH CSI0_MCLK I/O VCC_CSI -

GPIO5_IO20 CN1.25 CSI0_STROBE CSI0_DATA_EN I/O VCC_CSI -

GPIO5_IO21 CN1.27 CSI0_VSYNCH CSI0_VSYNC I/O VCC_CSI -

GPIO5_IO22 CN1.44 AUD3_TXC CSI0_DAT4 I/O VCC_CSI -

GPIO5_IO23 CN1.46 AUD3_TXD CSI0_DAT5 I/O VCC_CSI -

GPIO5_IO24 CN1.48 AUD3_TXFS CSI0_DAT6 I/O VCC_CSI -

GPIO5_IO25 CN1.50 AUD3_RXD CSI0_DAT7 I/O VCC_CSI -

GPIO5_IO26 CN1.33 CSI0_DAT8_GPIO25 CSI0_DAT8 I/O VCC_CSI -




GPIO5_IO30 CN1.41 CSI0_DAT12 CSI0_DAT12 I/O VCC_CSI -














GPIO6_IO09 CN1.84 I2C4_SCL NANDF_WP_B I/O 3.3V -

GPIO6_IO10 CN2.28 GPIO5 NANDF_RB0 I/O 3.3V -

GPIO6_IO15 CN1.52 AUD_MCLK_GPIO24 NANDF_CS2 I/O 3.3V -

GPIO6_IO16 CN1.86 I2C4_SDA NANDF_CS3 I/O 3.3V -

GPIO6_IO17 CN2.38 UART1_TXD SD3_DAT7 I/O VCC_SD3 -

GPIO6_IO18 CN2.40 UART1_RXD SD3_DAT6 I/O VCC_SD3 -

GPIO6_IO31 CN2.29 BACKLIGHT_EN EIM_BCLK I/O 3.3V -




GPIO7_IO02 CN2.5 SD3_CMD SD3_CMD I/O VCC_SD3 -

GPIO7_IO03 CN2.3 SD3_CLK SD3_CLK I/O VCC_SD3 -





GPIO7_IO11 CN1.93 ENET_REF_CLK_50M GPIO_16 I/O 3.3V -

GPIO7_IO12 CN1.15 GPIO12 GPIO_17 I/O 3.3V -




4.8 GENERAL PURPOSE TIMER (GPT) The GPT has a 32-bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or/and falling edge. The GPT can also generate an event on the DO_CMPOUTn pins and an interrupt when the timer reaches a programmed value. The GPT has a 12-bit prescaler, which provides a programmable clock frequency derived from multiple clock sources.

The following table describes the external signals of GPT:

Signal Pin No.


Signal Type

Voltage Level

Description

GPT_CAPTURE2 CN2.23 GPIO9_PWM3 SD1_DAT1 I 3.3V Input pin for a capture event for Input Capture Channel 2.

GPT_CLKIN CN2.19 GPIO7 SD1_CLK I 3.3V Input pin for an external clock that the counter can be operated at.

GPT_COMPARE1 CN2.30 GPIO6_PWM4 SD1_CMD O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 1.

GPT_COMPARE2 CN2.25 GPIO10_PWM2 SD1_DAT2 O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 2.

GPT_COMPARE3 CN2.31 DISP0_PWM SD1_DAT3 O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 3.

Table 4-17: External Signals of GPT

4.9 I2C The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol.

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C standard allows additional devices to be connected to the bus for expansion and system development.

The following table describes the external signals of I2C 1:


I2C1_SCL CN1.35 CSI0_DAT9_GPIO26 CSI0_DAT9 I/O VCC_CSI Serial clock

CN1.62 USB_OTG_OC EIM_D21 3.3V

I2C1_SDA CN1.33 CSI0_DAT8_GPIO25 CSI0_DAT8 I/O VCC_CSI Serial data

CN2.54 UART2_CTS_GPIO17 EIM_D28 3.3V

Table 4-18: External Signals of I2C 1





I2C2_SCL CN1.80 I2C2_SCL KEY_COL3 O (4.7K pull up)

3.3V Serial clock

I2C2_SDA CN1.82 I2C2_SDA KEY_ROW3 I/O (4.7K pull up)

3.3V Serial data




I2C3_SCL CN1.87 I2C3_SCL GPIO_3 I/O 3.3V Serial clock


I2C3_SDA CN1.85 I2C3_SDA GPIO_6 I/O 3.3V Serial data

CN1.93 ENET_REF_CLK_50M GPIO_16 3.3V



Signal Pin No. Pin Name i.MX6 pad name

Signal Type Voltage Level

Description

I2C4_SCL CN2.80 ENET_TX_EN ENET_TX_EN I/O 3.3V Serial clock


CN1.84 I2C4_SCL NANDF_WP_B 3.3V

I2C4_SDA CN1.86 I2C4_SDA NANDF_CS3 I/O 3.3V Serial data

CN2.98 ENET_TXD1 ENET_TXD1 3.3V



4.10 IMAGE PROCESSING UNIT (IPU) The IPU is planned to be a part of the video and graphics subsystem in an application processor.

The goal of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device.

The following table describes the external signals of IPU:



Signal Pin No.


Signal Type

Voltage Level Description

IPU1_CSI0_DATA00 CN2.56 UART2_RXD EIM_D27 I 3.3V -

IPU1_CSI0_DATA01 CN2.58 UART2_TXD EIM_D26 I 3.3V -

IPU1_CSI0_DATA02 CN2.27 GPIO11 EIM_D31 I 3.3V -

IPU1_CSI0_DATA03 CN1.72 USB_HOST_OC EIM_D30 I 3.3V -

IPU1_CSI0_DATA04 CN1.44 AUD3_TXC CSI0_DAT4 I VCC_CSI -

IPU1_CSI0_DATA05 CN1.46 AUD3_TXD CSI0_DAT5 I VCC_CSI -

IPU1_CSI0_DATA06 CN1.48 AUD3_TXFS CSI0_DAT6 I VCC_CSI -

IPU1_CSI0_DATA07 CN1.50 AUD3_RXD CSI0_DAT7 I VCC_CSI -

IPU1_CSI0_DATA08 CN1.33 CSI0_DAT8_GPIO25 CSI0_DAT8 I VCC_CSI -




IPU1_CSI0_DATA12 CN1.41 CSI0_DAT12 CSI0_DAT12 I VCC_CSI -








IPU1_CSI0_DATA_EN CN1.25 CSI0_STROBE CSI0_DATA_EN I VCC_CSI -

IPU1_CSI0_HSYNC CN1.29 CSI0_HSYNCH CSI0_MCLK I VCC_CSI -



Signal Pin No.


Signal Type


IPU1_CSI0_PIXCLK CN1.23 CSI0_PIXCLK CSI0_PIXCLK I VCC_CSI -

IPU1_CSI0_VSYNC CN1.27 CSI0_VSYNCH CSI0_VSYNC I VCC_CSI -

IPU1_DISP0_DATA00 CN2.47 DISP0_DAT0 DISP0_DAT0 I 3.3V -






















Signal Pin No.


Signal Type






IPU1_DI0_DISP_CLK CN2.35 DISP0_CLK DI0_DISP_CLK I 3.3V -

Table 4-22: External Signals of IPU

4.11 LVDS DISPLAY BRIDGE (LDB) The LVDS Display Bridge (LDB) connects the IPU (Image Processing Unit) to an External LVDS Display Interface.

The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS interface.

The following table describes the external signals of LDB:


Signal Type

Voltage Level

Description

LVDS0_CLK_N CN1.20 LVDS0_CLK_N LVDS0_CLK_N O 2.5V LVDS differential clock negative

LVDS0_CLK_P CN1.22 LVDS0_CLK_P LVDS0_CLK_P O 2.5V LVDS differential clock positive

LVDS0_DATA0_N CN1.38 LVDS0_TX0_N LVDS0_TX0_N O 2.5V LVDS differential pair0 negative

LVDS0_DATA0_P CN1.40 LVDS0_TX0_P LVDS0_TX0_P O 2.5V LVDS differential pair0 positive







Table 4-23: External Signals of LDB



4.12 MIPI- CAMERA SERIAL INTERFACE HOST CCONTROLLER (MIPI_CSI) CSI-2 is a high performance serial interconnect bus for mobile applications connecting camera sensors to the host system.

The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPID-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor.

The following table describes the external signals of MIPI_CSI:


Signal Type

Voltage Level

Description

CSI_CLK0_N CN1.71 CSI_CLK0M CSI_CLK0M I 2.5V MIPI CSI differential clock negative

CSI_CLK0_P CN1.73 CSI_CLK0P CSI_CLK0P I 2.5V MIPI CSI differential clock positive

CSI_DATA0_N CN1.75 CSI_D0M CSI_D0M I 2.5V MIPI CSI differential data0 negative

CSI_DATA0_P CN1.77 CSI_D0P CSI_D0P I 2.5V MIPI CSI differential data0 positive

CSI_DATA1_N CN1.81 CSI_D1M CSI_D1M I 2.5V MIPI CSI differential data1 negative

CSI_DATA1_P CN1.83 CSI_D1P CSI_D1P I 2.5V MIPI CSI differential data1 positive

Table 4-24: External Signals of MIPI_CSI

4.13 PULSE WIDTH MODULATION (PWM) The Pulse Width Modulation (PWM) has a 16-bit counter, and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bitresolution and a 4 x 16 data FIFO.

The following table describes the external signals of PWM:

Signal Pin No.


Signal Type

Voltage Level

Description

PWM1_OUT CN2.31 DISP0_PWM SD1_DAT3 O 3.3V This is the PWM1 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.




PWM2_OUT CN2.67 DISP0_DAT9 DISP0_DAT9 O 3.3V This is the PWM2 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

CN1.60 USB_OTG_ID GPIO_1 3.3V

CN2.25 GPIO10_PWM2 SD1_DAT2 3.3V

PWM3_OUT CN2.23 GPIO9_PWM3 SD1_DAT1 O 3.3V This is the PWM3 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

PWM4_OUT CN2.30 GPIO6_PWM4 SD1_CMD O 3.3V This is the PWM4 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

Table 4-25: External Signals of PWM

4.14 SYSTEM JTAG CONTROLLER (SJC) The System JTAG Controller (SJC) provides debug and test control with the maximum security.

The following table describes the external signals of SJC:

Signal Pin No.



Description

JTAG_TCK CN3.5 JTAG_TCK JTAG_TCK (47K pull up)

3.3V Test Clock (TCK). This is used to synchronize the test logic and includes an internal pull-up resistor

JTAG_TDI CN3.3 JTAG_TDI JTAG_TDI (47K pull up)

3.3V Test Data Input (TDI). Serial test instruction and data are received through the test data input (TDI) pin. TDI is sampled on the rising edge of TCK and includes an internal pull up resistor



Signal Pin No.



Description

JTAG_TDO CN3.7 JTAG_TDO JTAG_TDO O 3.3V Test Data Output (TDO). The serial output for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK

JTAG_TMS CN3.4 JTAG_TMS JTAG_TMS (47K pull up)

3.3V Test Mode Select (TMS). This is used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and includes an internal pull up resistor

JTAG_TRSTB CN3.2 JTAG_nTRST JTAG_TRSTB (47K pull up)

3.3V Test Reset (TRST). This is used to asynchronously initialize the test controller. The TRST pin has an internal pull up resistor

Table 4-26: External Signals of SJC

4.15 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter and an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility.

UART supports NRZ encoding format, RS485 compatible 9-bit data format and IrDA-compatible infrared slow data rate (SIR) format.

The following table describes the external signals of UART1:


Signal Type


UART1_CTS_B CN2.36 UART1_CTS_GPIO15 EIM_D19 O 3.3V Clear to send


UART1_DCD_B CN2.44 UART3_CTS EIM_D23 I/O 3.3V Data carrier detected

UART1_DSR_B CN2.50 UART3_RXD EIM_D25 I/O 3.3V Data set ready

UART1_DTR_B CN2.48 UART3_TXD EIM_D24 I/O 3.3V Data terminal ready

UART1_RI_B CN2.42 UART3_RTS EIM_EB3 I/O 3.3V Ring indicator

UART1_RTS_B CN2.34 UART1_RTS_GPIO16 EIM_D20 I 3.3V Request to send


UART1_RX_DATA CN1.39 CSI0_DAT11_GPIO28 CSI0_DAT11 I VCC_CSI




Signal Type


CN2.40 UART1_RXD SD3_DAT6 VCC_SD3 Serial / infrared data receive

UART1_TX_DATA CN1.37 CSI0_DAT10_GPIO27 CSI0_DAT10 O VCC_CSI Serial / infrared data transmit

CN2.38 UART1_TXD SD3_DAT7 VCC_SD3

Table 4-27: External Signals of UART1



Signal Type


UART2_CTS_B CN2.54 UART2_CTS_GPIO17 EIM_D28 O 3.3V Clear to send

CN2.5 SD3_CMD SD3_CMD VCC_SD3

UART2_RTS_B CN2.52 UART2_RTS_GPIO18 EIM_D29 I 3.3V Request to send

CN2.3 SD3_CLK SD3_CLK VCC_SD3

UART2_RX_DATA CN2.56 UART2_RXD EIM_D27 I 3.3V Serial / infrared data receive


UART2_TX_DATA CN2.58 UART2_TXD EIM_D26 O 3.3V Serial / infrared data transmit





Signal Type


UART3_CTS_B CN2.44 UART3_CTS EIM_D23 O 3.3V Clear to send

CN1.72 USB_HOST_OC EIM_D30 3.3V


UART3_RTS_B CN2.42 UART3_RTS EIM_EB3 I 3.3V Request to send

CN2.27 GPIO11 EIM_D31 3.3V

UART3_RX_DATA CN2.50 UART3_RXD EIM_D25 I 3.3V Serial / infrared data receive



UART3_TX_DATA CN2.48 UART3_TXD EIM_D24 O 3.3V Serial / infrared data transmit




Signal Type


UART4_CTS_B CN1.53 CSI0_DAT17 CSI0_DAT17 O VCC_CSI Clear to send

UART4_RTS_B CN1.51 CSI0_DAT16 CSI0_DAT16 I VCC_CSI Request to send

UART4_RX_DATA CN1.4 UART4_RXD KEY_ROW0 I 3.3V Serial / infrared data receive

CN1.43 CSI0_DAT13 CSI0_DAT13 VCC_CSI

UART4_TX_DATA CN1.6 UART4_TXD KEY_COL0 O 3.3V Serial / infrared data transmit





Signal Type


UART5_CTS_B CN1.57 CSI0_DAT19 CSI0_DAT19 O VCC_CSI Clear to send

CN1.13 CAN2_RX KEY_ROW4 3.3V

UART5_RTS_B CN1.55 CSI0_DAT18 CSI0_DAT18 I VCC_CSI Request to send

CN1.11 CAN2_TX KEY_COL4 3.3V

UART5_RX_DATA CN1.8 UART5_RXD KEY_ROW1 I 3.3V Serial / infrared data receive


UART5_TX_DATA CN1.10 UART5_TXD KEY_COL1 O 3.3V Serial / infrared data transmit



4.16 UNIVERSAL SERIAL BUS CONTROLLER (USB) The USB controller block provides high performance USB functionality that conforms to the Universal Serial Bus Specification, Rev. 2.0, and the On-The-Go and Embedded Host Supplement to the USB Revision2.0 Specification.



The following table describes the external signals of USB:


Signal Type

Voltage Level

Description

USB_H1_DN CN1.76 USB_HOST_DN USB_H1_DN I/O 3.0V DN host 1 signal

USB_H1_DP CN1.74 USB_HOST_DP USB_H1_DP I/O 3.0V DP host 1 signal

USB_H1_OC CN1.72 USB_HOST_OC EIM_D30 I 3.3V Host 1 external input for VBUS over current detection

CN1.87 I2C3_SCL GPIO_3 3.3V

USB_H1_PWR CN1.19 CSI_MCLK GPIO_0 O 3.3V To control power switch to supply VBUS voltage

CN2.27 GPIO11 EIM_D31 3.3V

USB_OTG_DN CN1.56 USB_OTG_DN USB_OTG_DN I/O 3.0V DN OTG signal

USB_OTG_DP CN1.58 USB_OTG_DP USB_OTG_DP I/O 3.0V DP OTG signal

USB_OTG_ID CN1.60 USB_OTG_ID GPIO_1 I 3.3V ID signal

CN2.78 ENET_RX_ER ENET_RX_ER 3.3V

USB_OTG_OC CN1.62 USB_OTG_OC EIM_D21 I 3.3V OTG external input for VBUS over current detection

CN1.11 CAN2_TX KEY_COL4 3.3V

USB_OTG_PWR CN1.13 CAN2_RX KEY_ROW4 O 3.3V To control power switch to supply VBUS voltage

CN1.64 USB_OTG_PWR_EN EIM_D22 3.3V

Table 4-32: External Signals of USB

4.17 ULTRA SECURED DIGITAL HOST CONTROLLER (USDHC) The Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host system and the SD/SDIO/MMC cards.

The uSDHC acts as a bridge, passing host bus transactions to the SD/SDIO/MMC cards by sending commands and performing data accesses to/from the cards.

It handles the SD/SDIO/MMC protocols at the transmission level.

The following table describes the external signals of USDHC1:



Signal Pin No.


Signal Type

Voltage Level

Description

SD1_CD_B CN1.60 USB_OTG_ID GPIO_1 I 3.3V Card detection pin If not used (for the embedded memory), tie low to indicate there is a card attached.

SD1_CLK CN2.19 GPIO7 SD1_CLK O 3.3V Clock for MMC/SD/SDIO card

SD1_CMD CN2.30 GPIO6_PWM4 SD1_CMD I/O 3.3V CMD line connect to card

SD1_DATA0 CN2.21 GPIO8 SD1_DAT0 I/O 3.3V DATA0 line

SD1_DATA1 CN2.23 GPIO9_PWM3 SD1_DAT1 I/O 3.3V DATA1 line

SD1_DATA2 CN2.25 GPIO10_PWM2 SD1_DAT2 I/O 3.3V DATA2 line

SD1_DATA3 CN2.31 DISP0_PWM SD1_DAT3 I/O 3.3V DATA3 line

SD1_LCTL CN1.93 ENET_REF_CLK_50M GPIO_16 O 3.3V LED control used to drive an external LED Active high Fully controlled by the driver Optional output

SD1_VSELECT CN1.10 UART5_TXD KEY_COL1 O 3.3V IO power voltage selection signal

SD1_WP CN2.41 DISP0_CNTRST DI0_PIN4 I 3.3V Card write protect detect

If not used (for the embedded memory), tie low to indicate it's not write protected.

Table 4-33: External Signals of USDHC1


Signal Pin No.


Signal Type

Voltage Level

Description

SD2_CD_B CN2.16 SD2_CD_B GPIO_4 I 3.3V Card detection pin If not used (for the embed memory), tie low to indicate there is a card attached.



Signal Pin No.


Signal Type

Voltage Level

Description

SD2_CLK CN2.4 SD2_CLK SD2_CLK O VCC_SD2 Clock for MMC/SD/SDIO card

SD2_CMD CN2.6 SD2_CMD SD2_CMD I/O VCC_SD2 CMD line connect to card

SD2_DATA0 CN2.8 SD2_DATA0 SD2_DAT0 I/O VCC_SD2 DATA0 line




SD2_DATA4 CN2.20 GPIO1 NANDF_D4 I/O 3.3V DATA4 line




SD2_LCTL CN1.85 I2C3_SDA GPIO_6 O 3.3V LED control used to drive an external LED Active high Fully controlled by the driver Optional output

SD2_VSELECT CN1.8 UART5_RXD KEY_ROW1 O 3.3V IO power voltage selection signal




Signal Pin No.


Signal Type

Voltage Level

Description

SD2_WP CN1.17 CSI_EN GPIO_2 I 3.3V Card write protect detect

If not used (for the embedded memory), tie low to indicate it's not write protected.



Signal Pin No.


Signal Type

Voltage Level

Description

SD3_CLK CN2.3 SD3_CLK SD3_CLK O VCC_SD3 Clock for MMC/SD/SDIO card

SD3_CMD CN2.5 SD3_CMD SD3_CMD I/O VCC_SD3 CMD line connect to card






4.18 WATCHDOG TIMER (WDOG) The Watchdog Timer (WDOG) protects against system failures by providing a method by which to escape from unexpected events or programming errors.

Once the WDOG is activated, it must be serviced by the software on a periodic basis. If servicing does not take place, the timer times out. Upon timeout, the WDOG asserts the internal system reset signal, WDOG_RESET_B_DEB to the System Reset Controller (SRC).

The following table describes the external signals of WDOG:

Signal Pin No.


Signal Type

Voltage Level

Description

WDOG1_B CN2.25 GPIO10_PWM2 SD1_DAT2 I/O 3.3V This signal will power down the chip.


WDOG1_RESET_B_DEB CN2.25 GPIO10_PWM2 SD1_DAT2 O 3.3V This signal is a reset source for the chip.

WDOG2_B CN2.31 DISP0_PWM SD1_DAT3 I/O 3.3V



CN2.67 DISP0_DAT9 DISP0_DAT9 3.3V This signal will power down the chip.

CN1.60 USB_OTG_ID GPIO_1 3.3V

WDOG2_RESET_B_DEB CN2.31 DISP0_PWM SD1_DAT3 O 3.3V This signal is a reset source for the chip.

Table 4-36: External Signals of WDOG

4.19 PCI EXPRESS (PCIE) The PCIe support both the 5Gbps data rate of the PCI Express Gen 2.0 specification as well as being backwords compatible to the 2.5Gbps Gen 1.1 specification.

PCIe includes the following cores:

PCI Express Dual Mode (DM) core

PCI Express Root Complex (RC) core

PCI Express Endpoint (EP) core

The PCIe signals shared pinout of CN2:1, CN2:3, CN2:5, CN2:7, CN2:9, CN2:11, CN2:13 and CN2:15 with SD3 interface, its resistor configurable and the default is SD3 interface.

The following table describes the external signals of PCIe:

Signal Pin No.



Description

PCIE_RX_N CN2.1 PCIE_RXM PCIE_RXM I 2.5V PCIe differential receive line negative

PCIE_RX_P CN2.3 PCIE_RXP PICE_RXP I 2.5V PCIe differential receive line positive

PCIE_TX_N CN2.7 PCIE_TXM PCIE_TXM O/0.1uF AC coupling

2.5V PCIe differential transmit line negative

PCIE_TX_P CN2.9 PCIE_TXP PCIE_TXP O/0.1uF AC coupling

2.5V PCIe differential transmit line positive

PCIE_CLK_N CN2.13 PCIE_CLK1_N CLK1_N O 2.5V PCIe differential clock negative

PCIE_CLK_P CN2.15 PCIE_CLK1_P CLK1_P O 2.5V PCIe differential clock positive

Table 4-37: External Signals of PCIe



5 ELECTRICAL SPECIFICATION

5.1 ABSOLUTE MAXIMUM CHARACTERISTICS Minimum Maximum Unit

Main Power Supply, DC-IN -0.3 3.6 V

Table 5-1: Absolute Maximum Characteristics

5.2 OPERATIONAL CHARACTERISTICS

5.2.1 Power Supplies The VS5100 SOM is designed to be driven with a single +3.3VDC input power.

Minimum Typical Maximum Unit

Voltage of Input Power 3.135 3.3 3.465 V

Current of Input Power 1.5 A

Table 5-2: Power Suppliers Requirement

Note: Power Rating applies for both i.MX 6Solo and 6DualLite

5.2.2 Power Consumption The VS5100 SOM power consumption is measured in i.MX6Solo/DualLite carrier board while running different power scripts under Android 4.2.2.

No. Power Script Power Script Operation Imax(A) @ 3.3V Input

1 Power Script 1 LVDS/RGB– Play video

Audio – Headphone in

USB – Keyboard and Mouse

1.05A (Solo)

1.08A (DualLite)

2 Power Script 2 LVDS/RGB– Play video

Audio – Headphone in

Ethernet – Ping test

CPU – Run Stability TEST Utility

1.12A (Solo)

1.15A (DualLite)

3 Standby OS is in idle mode 0.079A (Solo)

0.079A (DualLite)

Table 5-3: VS5100 SOM power consumption

Note: Power consumption is measured in particular condition and it may vary platform to platform based on board configuration. Depending upon board configuration, overall system design and cooling mechanism, customer may need to choose the appropriate heat solution.



6 LAYOUT RECOMMENDATIONS

This chapter provides recommendations to assist design engineers with the correct layout of their SOM based systems.

6.1 SOM BOARD TRACE LENGTH

Length matching is needed to be considered for each groups of the high speed signals. The trace lengths of each SOM board signals are listed below. The designer of the carrier board needs to take note of the trace length on the SOM when performing system signals length matching.

6.1.1 Trace Length of CN1 Signals

Pin No. Pin Name Trace Length

(unit: mil)


(unit: mil)

CN1.1 GND CN1.2 GND

CN1.3 CAN1_TX 622.17 CN1.4 UART4_RXD 441.97

CN1.5 CAN1_RX 583.96 CN1.6 UART4_TXD 375.14

CN1.7 CAN1_STBY_GPIO13 557.41 CN1.8 UART5_RXD 485.32

CN1.9 CAN2_STBY_GPIO14 567.82 CN1.10 UART5_TXD 446.63

CN1.11 CAN2_TX 518.24 CN1.12 GND

CN1.13 CAN2_RX 463.9 CN1.14 LVDS0_TX3_N 268.81

CN1.15 GPIO12 425.74 CN1.16 LVDS0_TX3_P 268.22

CN1.17 CSI_EN 358.92 CN1.18 GND

CN1.19 CSI_MCLK 448.93 CN1.20 LVDS0_CLK_N 363.63

CN1.21 GND CN1.22 LVDS0_CLK_P 360.01

CN1.23 CSI0_PIXCLK 556.82 CN1.24 GND

CN1.25 CSI0_STROBE 514.42 CN1.26 LVDS0_TX2_N 277.3

CN1.27 CSI0_VSYNCH 530.19 CN1.28 LVDS0_TX2_P 277.12

CN1.29 CSI0_HSYNCH 514.01 CN1.30 GND

CN1.31 GND CN1.32 LVDS0_TX1_N 358.73

CN1.33 CSI0_DAT8_GPIO25 510.21 CN1.34 LVDS0_TX1_P 358.52

CN1.35 CSI0_DAT9_GPIO26 521.88 CN1.36 GND

CN1.37 CSI0_DAT10_GPIO27 523.4 CN1.38 LVDS0_TX0_N 284.47

CN1.39 CSI0_DAT11_GPIO28 523.5 CN1.40 LVDS0_TX0_P 284.85

CN1.41 CSI0_DAT12 520.18 CN1.42 GND

CN1.43 CSI0_DAT13 514.95 CN1.44 AUD3_TXC 285.63

CN1.45 GND CN1.46 AUD3_TXD 210.3

CN1.47 CSI0_DAT14 527.61 CN1.48 AUD3_TXFS 312.87

CN1.49 CSI0_DAT15 539.76 CN1.50 AUD3_RXD 274.64




(unit: mil)


(unit: mil)

CN1.51 CSI0_DAT16 551.41 CN1.52 AUD_MCLK_GPIO24 1208.79

CN1.53 CSI0_DAT17 543.15 CN1.54 GND

CN1.55 CSI0_DAT18 540.08 CN1.56 USB_OTG_DN 581.64

CN1.57 CSI0_DAT19 526.67 CN1.58 USB_OTG_DP 581.9

CN1.59 GND CN1.60 USB_OTG_ID 600.48

CN1.61 BT_Pin1 CN1.62 USB_OTG_OC 827.19

CN1.63 BT_Pin2 CN1.64 USB_OTG_PWR_EN 986.59

CN1.65 RESET CN1.66 GND

CN1.67 CPU_PWR_BUTTON CN1.68 USBHUB_nRST 835.99

CN1.69 GND CN1.70 USB_HOST_PWR_EN 1006.14

CN1.71 CSI_CLK0M 391.96 CN1.72 USB_HOST_OC 876.98

CN1.73 CSI_CLK0P 392.06 CN1.74 USB_HOST_DP 698.31

CN1.75 CSI_D0M 381.3 CN1.76 USB_HOST_DN 698.34

CN1.77 CSI_D0P 381.83 CN1.78 GND

CN1.79 GND CN1.80 I2C2_SCL

CN1.81 CSI_D1M 386.31 CN1.82 I2C2_SDA

CN1.83 CSI_D1P 386.2 CN1.84 I2C4_SCL 867.6

CN1.85 I2C3_SDA 728.15 CN1.86 I2C4_SDA 911.94

CN1.87 I2C3_SCL 852.34 CN1.88 USB_HOST_VBUS

CN1.89 CARRIER_PWR_ON CN1.90 USB_OTG_VBUS

CN1.91 GND CN1.92 GND

CN1.93 ENET_REF_CLK_50M 740.2 CN1.94 SOM_3V3

CN1.95 GND CN1.96 SOM_3V3

CN1.97 SOM_3V3 CN1.98 SOM_3V3

CN1.99 SOM_3V3 CN1.100 SOM_3V3

Table 6-1: Trace Length of CN1 Signals

6.1.2 Trace Length of CN2 Signals


(unit: mil)


(unit: mil)

CN2.1 GND CN2.2 GND

PCIE_RXM 2212.7

CN2.3 SD3_CLK 1538.62 CN2.4 SD2_CLK 465.95

PCIE_RXP 2212.79




(unit: mil)


(unit: mil)

CN2.5 SD3_CMD 1501.82 CN2.6 SD2_CMD 448.92

GND

CN2.7 SD3_DATA0 1506.16 CN2.8 SD2_DATA0 419.63

PCIE_TXM 2215.66


PCIE_TXP 2214.78


GND


PCIE_CLK1_N 2223.59

CN2.15 SD3_CD_B 971.69 CN2.16 SD2_CD_B 1510.54

PCIE_CLK1_P 2224.42


CN2.19 GPIO7 577.36 CN2.20 GPIO1 627.88

CN2.21 GPIO8 598.74 CN2.22 GPIO2 713.39

CN2.23 GPIO9_PWM3 622.84 CN2.24 GPIO3 845.09

CN2.25 GPIO10_PWM2 605.02 CN2.26 GPIO4 745.69

CN2.27 GPIO11 555.82 CN2.28 GPIO5 841.06

CN2.29 BACKLIGHT_EN 751.81 CN2.30 GPIO6_PWM4 676.24

CN2.31 DISP0_PWM 740.92 CN2.32 GND

CN2.33 GND CN2.34 UART1_RTS_GPIO16 591.28

CN2.35 DISP0_CLK 667.99 CN2.36 UART1_CTS_GPIO15 396.08

CN2.37 DISP0_HSYNCH 346.52 CN2.38 UART1_TXD 1314.46

CN2.39 DISP0_VSYNCH 595.65 CN2.40 UART1_RXD 1226.3

CN2.41 DISP0_CNTRST 332.15 CN2.42 UART3_RTS 488.26

CN2.43 DISP0_DRDY 660.46 CN2.44 UART3_CTS 456.49


CN2.47 DISP0_DAT0 632.42 CN2.48 UART3_TXD 474.46

CN2.49 DISP0_DAT1 639.68 CN2.50 UART3_RXD 467.68

CN2.51 DISP0_DAT2 578.1 CN2.52 UART2_RTS_GPIO18 573.87

CN2.53 DISP0_DAT3 645 CN2.54 UART2_CTS_GPIO17 455.87

CN2.55 DISP0_DAT4 658.31 CN2.56 UART2_RXD 509.88

CN2.57 DISP0_DAT5 569.08 CN2.58 UART2_TXD 595.48

CN2.59 DISP0_DAT6 569.85 CN2.60 GND




(unit: mil)


(unit: mil)

CN2.61 DISP0_DAT7 571.63 CN2.62 SPI_SCLK_GPIO21 542.88

CN2.63 GND CN2.64 SPI_MOSI_GPIO20 451.73

CN2.65 DISP0_DAT8 595.09 CN2.66 SPI_MISO_GPIO19 457.78

CN2.67 DISP0_DAT9 575.09 CN2.68 SPI_SS0_GPIO22 636.01

CN2.69 DISP0_DAT10 628.44 CN2.70 SPI_SS1_GPIO23 512.04

CN2.71 DISP0_DAT11 608.68 CN2.72 PHY_REST_B 299.98

CN2.73 DISP0_DAT12 569.3 CN2.74 PHY_INT_B 384.84

CN2.75 DISP0_DAT13 676.37 CN2.76 GND

CN2.77 DISP0_DAT14 572.41 CN2.78 ENET_RX_ER 739.79

CN2.79 DISP0_DAT15 669.03 CN2.80 ENET_TX_EN 733.97

CN2.81 GND CN2.82 ENET_CRS_DV 721.87

CN2.83 DISP0_DAT16 671.26 CN2.84 GND

CN2.85 DISP0_DAT17 568.23 CN2.86 ENET_MDIO 413

CN2.87 DISP0_DAT18 573.17 CN2.88 ENET_MDC 452.32

CN2.89 DISP0_DAT19 643.55 CN2.90 GND

CN2.91 DISP0_DAT20 644.56 CN2.92 ENET_RXD0 720.42

CN2.93 DISP0_DAT21 710.69 CN2.94 ENET_RXD1 737.31

CN2.95 DISP0_DAT22 589.75 CN2.96 ENET_TXD0 711.12

CN2.97 DISP0_DAT23 658.75 CN2.98 ENET_TXD1 719.02


Table 6-2: Trace Length of CN2 Signals

6.2 PCI EXPRESS INTERFACE RECOMMENDATIONS

Use the following recommendations for PCI Express interface:

PCIe differential pairs should have a differential impedance of 85Ω +/- 10%.

Each differential pair should be length matched to +/- 5 mils

Match the signals with respect to PCIE_CLK (clock signal) +/- 50mils

6.3 LVDS RECOMMENDATIONS

Use the following recommendations for the LVDS:

LVDS differential pairs should have a differential impedance of 100Ω +/- 10%.


Match the signals with respect to LVDS_CLK (clock signal) +/- 100mils



6.4 USB RECOMMENDATIONS

Use the following recommendations for the USB:

The differential pairs should have a differential impedance of 90Ω +/- 10%.


6.5 MIPI RECOMMENDATIONS

Use the following recommendations for the MIPI:

The differential pairs should have a differential impedance of 100Ω +/- 10%.


Match the signals with respect to CSI_CLK (clock signal) +/- 25mils

6.6 SD INTERFACE RECOMMENDATIONS

Use the following recommendations for the SD interface:

Match the signals with respect to SDx_CLK (clock signal) +/- 75mils.

6.7 CSI PARALLEL RECOMMENDATIONS

Use the following recommendations for the CSI parallel interface:

Match the signals with respect to CSI0_PIXCLK (clock signal) +/- 50mils.

6.8 PGB PARALLEL RECOMMENDATIONS

Use the following recommendations for the RGB parallel interface:

Match the signals with respect to Disp0_CLK (clock signal) +/- 100mils.

6.9 I2S RECOMMENDATIONS

Use the following recommendations for the I2S interface:

Match the signals with respect to AUD3_TXC (clock signal) +/- 100mils.

6.10 SPI INTERFACE RECOMMENDATIONS

Use the following recommendations for the SPI interface:

Match the signals with respect to SPI_CLK (clock signal) +/- 100mils.



6.11 ENET INTERFACE RECOMNENDATIONS

Use the following recommendations for the ENET interface:

Match the signals with respect to ENET_REF_CLK_50M (clock signal) +/- 100mils.



7 ENVIRONMENT SPECIFICATION

7.1 TEMPERATURE SPECIFICATION The VS5100 SOM has 2 product variants with operating temperature from 5℃to 50℃ and storage temperature from -20℃ to 70℃.For detail, please refer to Section 9 Board Options.

7.2 HUMIDITY Operating: 10% to 90% (Non-condensing)

Non-operating: 5% to 95% (Non-condensing)



8 MECHANICAL SPECIFICATIONS

8.1 MODULE DIMENSION 35mm x 50mm

8.2 HEIGHT ON TOP Maximum 3.0mm (without printed circuit board)

Height is depending on CPU cooler/heat spreader (optional; subjected to final product application)

8.3 HEIGHT ON BOTTOM Maximum approximately 1.3mm (without printed circuit board)

8.4 MECHANICAL DRAWING

Unit: INCH [MM] , Tolerance: +/- 0.1mm

Figure 8-1: Top View

Figure 8-2: Bottom View



9 BOARD OPTIONS

Part No. CPU CPU Grade SDRAM eMMC Operating Temperature

Storage Temperature

Remark

VS603SAC2F i.MX6 Solo, 1.0GHz

Commercial 512MB 4GB 5°C to 50°C -20°C to 70℃ I2C EEPROM unpopulated

VS603UAC2F i.MX6 DualLite, 1.0GHz

Commercial 512MB 4GB 5°C to 50°C -20°C to 70℃ I2C EEPROM unpopulated

VS603SAC2F-1 i.MX6 Solo, 1.0GHz

Commercial 512MB 4GB 5°C to 50°C -20°C to 70℃ I2C EEPROM populated

VS603UAC2F-1 i.MX6 DualLite, 1.0GHz

Commercial 512MB 4GB 5°C to 50°C -20°C to 70℃ I2C EEPROM populated

Table 9-1: Board Options and Ordering Part Numbers

More variants of SOM (with Industrial and Automotive Processor options) are available. Please contact your sales representative for more information.



10 REVISION HISTORY

Version Date Released

Changes

0.1.0 24 Feb, 2016 Preliminary Release

0.2.0 26 Feb, 2016 Changing document type to Reference Manual (USG)

A 1 Mar, 2016 Bumped major revision to A

B 14 Mar, 2016 Added new part numbers for SOM with EEPROM installed

C 16 Mar, 2016 Changed the SOM family name from VS6x to VS5100



11 LEGAL NOTICES

The signed agreement between Purchaser and APC will govern the sale and purchase of APC’s Venture Embedded Solutions Technology (“VEST”) products (“Products”). In the event that no agreement has been concluded, APC’s terms and conditions of supply will apply.

Testing and other quality control techniques are used to the extent that APC deems necessary to support its warranty.

Except where required by law, specific testing of all parameters of each Product is not necessarily performed.

Purchaser must provide adequate design and operating safeguards to minimize inherent or procedural and technical risks associated with Purchaser products and applications. Purchaser is solely responsible for its selection and use of APC Products. APC assumes no liability for applications assistance, Purchaser product design or any incompatibility of the Product with Purchaser product.

Products supplied by APC are not designed, intended or authorized for use in life support, life sustaining, medical systems or devices, aircraft navigation, nuclear, or other applications, including, but not limited to, public transportation operating systems, in which the failure of such Products could reasonably be expected to result in personal injury, loss of life or severe property or environmental damage. Purchaser acknowledges that use of APC’s Products in such product applications is understood to be fully at the risk of Purchaser and that Purchaser is responsible for verification and validation of the suitability of APC’s Products in such applications. Purchaser agrees that APC is not and shall not be liable, in whole or in part, for any claim or damage arising from use in such applications. Purchaser agrees to indemnify, defend and hold APC harmless from and against any and all claims, damages, losses, costs, expenses and liabilities arising out of or in connection with any such use or application.

APC retains all rights to all proprietary intellectual property in the Products and associated manufacturing processes and has the right to file for and obtain intellectual property protection for same.

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