VSC8490-17 Datasheet Dual Channel WAN/LAN/Backplane ......VMDS-10505 VSC8490-17 Datasheet Revision...

VSC8490-17 DatasheetDual Channel WANLANBackplane RXAUIXAUI toSFP+KR 10 GbE SerDes PHY with IntelliSectrade and

VeriTimetrade

VMDS-10505 40 1118

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copy2018 Microsemi a wholly owned subsidiary of Microchip Technology Inc All rights reserved Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation All other trademarks and service marks are the property of their respective owners

Microsemi makes no warranty representation or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications Any performance specifications are believed to be reliable but are not verified and Buyer must conduct and complete all performance and other testing of the products alone and together with or installed in any end-products Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi It is the Buyerrsquos responsibility to independently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided ldquoas is where isrdquo and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or anything described by such information Information provided in this document is proprietary to Microsemi and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice

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VMDS-10505 VSC8490-17 Datasheet Revision 40 i

Contents

1 Revision History 111 Revision 41 112 Revision 40 113 Revision 20 1

2 Overview 221 Major Applications 322 Features and Benefits 5

3 Functional Descriptions 631 Data Path Overview 7

311 Ingress Operation 7312 Egress Operation 7313 Interface Data Rates 8

32 Physical Medium Attachment (PMA) 8321 VScope Input Signal Monitoring Integrated Circuit 8

33 WAN Interface Sublayer (WIS) 10331 Operation 10332 Section Overhead 12333 Line Overhead 18334 SPE Pointer 23335 Path Overhead 26336 Defects and Anomalies 32337 Interrupt Pins and Interrupt Masking 33338 Overhead Serial Interfaces 34339 Pattern Generator and Checker 37

34 10G Physical Coding Sublayer (64B66B PCS) 38341 Control Codes 38342 Transmit Path 39343 Receive Path 39344 PCS Standard Test Modes 40

35 1G Physical Coding Sublayer 4136 IEEE 1588 Block Operation 41

361 IEEE 1588 Block 42362 IEEE 1588v2 One-Step End-to-End Transparent Clock 44363 IEEE 1588v2 Transparent Clock and Boundary Clock 45364 Enhancing IEEE 1588 Accuracy for CE Switches and MACs 46365 MACsec Support 46366 Supporting One-Step Boundary ClockOrdinary Clock 46367 Supporting Two-Step Boundary ClockOrdinary Clock 48368 Supporting One-Step End-to-End Transparent Clock 50369 Supporting One-Step Peer-to-Peer Transparent Clock 533610 Supporting Two-Step Transparent Clock 573611 Calculating OAM Delay Measurements 593612 Supporting Y1731 One-Way Delay Measurements 593613 Supporting Y1731 Two-Way Delay Measurements 613614 Device Synchronization for IEEE 1588 Support 633615 Time Stamp Update Block 643616 Analyzer 673617 Time Stamp Processor 873618 Time Stamp FIFO 883619 Serial Time Stamp Output Interface 89

VMDS-10505 VSC8490-17 Datasheet Revision 40 ii

3620 Rewriter 903621 Local Time Counter 913622 Serial Time of Day 933623 Programmable Offset for LTC Load Register 953624 Adjustment of LTC Counter 953625 Pulse per Second Output 963626 Resolution 973627 Loopbacks 973628 Accessing 1588 IP Registers 98

37 MACsec Block Operation 98371 MACsec Architecture 98372 MACsec Target Applications 101373 Formats Transforms and Classification 103374 MACsec Integration in PHY 105375 MACsec Pipeline Operation 106376 Debug Fault Code in FCS 126377 Capture FIFO 129378 Flow Control Buffer 130379 Media Access Control 134

38 Flow Control Buffers 13739 Rate Compensating Buffers 137310 Loopback 137311 Cross-Connect (Non-Hitless Operation) 138312 Host-Side Interface 140

3121 RXAUI Interoperability 141313 Clocking 141

3131 PLL 1413132 Reference Clock 1423133 Synchronous Ethernet Support 143

314 Operating Modes 1433141 10G LAN with 1588 and MACsec 1433142 10G LAN with 1588 1443143 10G LAN 1443144 10G WAN with 1588 and MACsec 1443145 10G WAN with 1588 1453146 10G WAN 1453147 1 GbE with 1588 and MACsec 1463148 1 GbE with 1588 and MACs 1463149 1 GbE 147

315 Management Interfaces 1473151 MDIO Interface 1473152 SPI Slave Interface 1483153 Two-Wire Serial (Slave) Interface 1513154 Two-Wire Serial (Master) Interface 1533155 Push Out SPI Master Interface 1543156 GPIO 1543157 JTAG 157

4 Registers 158

5 Electrical Specifications 15951 DC Characteristics 159

511 DC Inputs and Outputs 159512 Reference Clock 160

52 AC Characteristics 160521 Receiver Specifications 160

VMDS-10505 VSC8490-17 Datasheet Revision 40 iii

522 Transmitter Specifications 164523 Timing and Reference Clock 168524 Two-Wire Serial (Slave) Interface 169525 MDIO Interface 170526 Synchronous Time-of-Day LoadSave Timing 171527 SPI Slave Interface 172

53 Operating Conditions 17354 Stress Ratings 174

6 Pin Descriptions 17561 Pin Diagram 17562 Pin Identifications 17563 Pins by Function 176

7 Package Information 19771 Package Drawing 19772 Thermal Specifications 19873 Moisture Sensitivity 199

8 Design Considerations 20081 1588 bypass switch should not be activated on the fly 20082 Low-power mode and SerDes calibration 20083 Low-power mode should not be enabled when failover switching is enabled 20084 Flow control with failover switching 20085 XAUI BIST Checker Compatibility 20086 SPI bus speeds 20087 GPIO as TOSI 20088 10GBASE-KR auto negotiation and training 20089 Loopbacks in 10G WAN mode 200810 10100M mode not supported 201811 Limited access to registers during failover cross-connect mode 201812 Limited auto negotiation support in 1G mode 201813 Limited 1G status reporting 201814 Timestamp errors due to IEEE 1588 reference clock interruption 201815 RXCKOUT squelching 201

9 Ordering Information 202

VMDS-10505 VSC8490-17 Datasheet Revision 40 iv

FiguresFigure 10 VSC8490-17 Block Diagram 3Figure 11 SFPSFP+ Application 4Figure 12 Backplane Equalization Application 4Figure 13 1588 Transparent Clock Line Card End-to-End PHY Application 4Figure 14 1588 Boundary Clock Line Card Application 5Figure 15 10GBASE-KR Output Driver 9Figure 16 KR Test Pattern 9Figure 17 WIS Transmit and Receive Functions 11Figure 18 WIS Frame Structure 11Figure 19 STS-192cSTM-64 Section and Line Overhead Structure 12Figure 20 Path Overhead Octets 12Figure 21 Primary Synchronization State Diagram 14Figure 22 Secondary Synchronization State Diagram 15Figure 23 16-bit Designations within Payload Pointer 24Figure 24 Pointer Interpreter State Diagram 25Figure 25 TOSI Timing Diagram 35Figure 26 ROSI Timing Diagram 37Figure 27 PCS Block Diagram 38Figure 28 64B66B Block Formats 40Figure 29 IEEE 1588 Architecture 42Figure 30 IEEE 1588 Block Diagram 43Figure 31 1588 Transparent Clock Line Card End-to-End PHY Application 44Figure 32 Transparent Clock and Boundary Clock Line Card Application 45Figure 33 1588 Boundary Clock Line Card Application 46Figure 34 One-Step E-nd-to-End Boundary Clock 47Figure 35 Two-Step End-to-End Boundary Clock 49Figure 36 One-Step End-to-End Transparent Clock Mode A 51Figure 37 One-Step End-to-End Transparent Clock Mode B 52Figure 38 Delay Measurements 54Figure 39 One-Step Peer-to-Peer Transparent Clock Mode B 57Figure 40 Two-Step End-to-End Transparent Clock 58Figure 41 Y1731 1DM PDU Format 59Figure 42 Y1731 One-Way Delay 60Figure 43 Y1731 DMM PDU Format 61Figure 44 Y1731 Two-Way Delay 62Figure 45 RFC6374 DMMDMR OAM PDU Format 63Figure 46 Draft-bhh DMMDMR1DM OAM PDU Formats 63Figure 47 PTP Packet Encapsulations 65Figure 48 OAM Packet Encapsulations 65Figure 49 TSU Block Diagram 66Figure 50 Analyzer Block Diagram 67Figure 51 Type II Ethernet Basic Frame Format 70Figure 52 Ethernet Frame with SNAP 70Figure 53 Ethernet Frame with VLAN Tag and SNAP 70Figure 54 Ethernet Frame with VLAN Tags and SNAP 70Figure 55 PBB Ethernet Frame Format (No B-Tag) 70Figure 56 PBB Ethernet Frame Format (1 B-Tag) 70Figure 57 MPLS Label Format 73Figure 58 MPLS Label Stack within an Ethernet Frame 73Figure 59 MPLS Labels and Control Word 73Figure 60 IPv4 with UDP 75Figure 61 IPv6 with UDP 76Figure 62 ACH Header Format 76Figure 63 ACH Header with Protocol ID Field 76Figure 64 IPSec Header Format 77

VMDS-10505 VSC8490-17 Datasheet Revision 40 v

Figure 65 IPv6 with UDP and IPSec 77Figure 66 PTP Frame Layout 80Figure 67 OAM 1DM Frame Header Format 81Figure 68 OAM DMM Frame Header Format 81Figure 69 OAM DMR Frame Header Format 81Figure 70 RFC6374 DMMDMR OAM PDU Format 82Figure 71 G81131draft-bhh DMMDMR1DM OAM PDU Format 82Figure 72 Serial Time StampFrame Signature Output 90Figure 73 Preamble Reduction in Rewriter 91Figure 74 Local Time Counter LoadSave Timing 92Figure 75 Standard PPS and 1PPS with TOD Timing Relationship 93Figure 76 ToD Octet Waveform 94Figure 77 MACsec Architecture 99Figure 78 Secure Enterprise Infrastructure and WAN 101Figure 79 Secure Carrier Ethernet Connection 102Figure 80 Secure Mobile Backhaul with IEEE 1588 102Figure 81 Untagged Ethernet 103Figure 82 Standard MACsec Transform of Untagged Ethernet 103Figure 83 Single-Tagged Ethernet 103Figure 84 Standard MACsec Transform of Single-Tagged Ethernet 103Figure 85 Dual-Tagged Ethernet 104Figure 86 Standard MACsec Transform of Dual-Tagged Ethernet 104Figure 87 Single-Tagged Ethernet 104Figure 88 MACsec Transform to Single Tag Bypass 104Figure 89 Dual-Tagged Ethernet 104Figure 90 MACsec Transform to Single and Dual Tag Bypass 105Figure 91 EoMPLS with One Label 105Figure 92 Standard and Advanced MACsec Transform 105Figure 93 EoMPLS with Two Labels 105Figure 94 Standard and Advanced MACsec Transform 105Figure 95 MACsec in PHY 106Figure 96 MACsec Egress Data Flow 108Figure 97 MACsec Ingress Data Flow 108Figure 98 VLAN Tag Bypass Format 115Figure 99 EoMPLS Header Bypass Format 116Figure 100 Capture FIFO Layout 129Figure 101 Line Back-Pressure by Remote Link Partner 131Figure 102 Host Back-Pressure by Remote Link Partner 132Figure 103 Advanced Flow Control Handling 133Figure 104 MAC Block Diagram 134Figure 105 Host-Side and Line-Side Loopbacks 138Figure 106 Cross-Connect Configuration 140Figure 107 Host-Side IO Interface 141Figure 108 10G LAN with 1588 and MACsec 143Figure 109 10G LAN with 1588 144Figure 110 10G LAN 144Figure 111 10G WAN with 1588 and MACsec 145Figure 112 10G WAN with 1588 145Figure 113 10G WAN 146Figure 114 1 GbE with 1588 and MACsec 146Figure 115 1 GbE with 1588 and MACs 146Figure 116 1 GbE 147Figure 117 SPI Single Register Read 149Figure 118 SPI Multiple Register Reads 150Figure 119 SPI Multiple Register Writes 150Figure 120 SPI Read Following Write 150Figure 121 SPI Write Following Read 150Figure 122 SPI Slave Default Mode 151Figure 123 SPI Slave Fast Mode 151

VMDS-10505 VSC8490-17 Datasheet Revision 40 vi

Figure 124 Two-Wire Serial Bus Reset Sequence 152Figure 125 Two-Wire Serial Slave Register Address Format 152Figure 126 Two-Wire Serial Write Instruction 153Figure 127 Two-Wire Serial Read Instruction 153Figure 128 SFI Datacom Sinusoidal Jitter Tolerance 161Figure 129 XAUI Receiver Input Sinusoidal Jitter Tolerance 163Figure 130 SFI Transmit Differential Output Compliance Mask 165Figure 131 XAUI Output Compliance Mask 167Figure 132 XREFCK to Data Output Jitter Transfer 169Figure 133 Two-Wire Serial Interface Timing 170Figure 134 Timing with MDIO Sourced by STA 171Figure 135 Timing with MDIO Sourced by MMD 171Figure 136 LoadSave AC Timing 172Figure 137 SPI Interface Timing 172Figure 138 3-Pin Push-Out SPI Timing 173Figure 139 Pin Diagram 175Figure 140 Package Drawing 198

VMDS-10505 VSC8490-17 Datasheet Revision 40 vii

TablesTable 141 Interface Data Rates 8Table 142 Section Overhead 12Table 143 Framing Parameter Description and Values 14Table 144 Line Overhead Octets 18Table 145 K2 Encodings 21Table 146 SONETSDH Pointer Mode Differences 23Table 147 H1H2 Pointer Types 24Table 148 Concatenation Indication Types 24Table 149 Pointer Interpreter State Diagram Transitions 25Table 150 STS Path Overhead Octets 26Table 151 Path Status (G1) Byte for RDI-P Mode 29Table 152 Path Status (G1) Byte for ERDI-P Mode 29Table 153 RDI-P and ERDI-P Bit Settings and Interpretation 29Table 154 PMTICK Counters 31Table 155 Defects and Anomalies 32Table 156 TOSIROSI Addresses 35Table 157 Control Codes 38Table 158 Flows Per Engine Type 68Table 159 Ethernet Comparator Next Protocol 69Table 160 Comparator ID Codes 69Table 161 Ethernet Comparator (Next Protocol) 71Table 162 Ethernet Comparator (Flow) 71Table 163 MPLS Comparator Next Word 74Table 164 MPLS Comparator Per-Flow 74Table 165 MPLS Range_UpperLower Label Map 74Table 166 Next MPLS Comparator 75Table 167 Next-Protocol Registers in OAM-Version of MPLS Block 75Table 168 Comparator Field Summary 78Table 169 IPACH Next-Protocol Comparison 78Table 170 IPACH Comparator Flow Verification Registers 79Table 171 PTP Comparison 82Table 172 PTP Comparison Common Controls 84Table 173 PTP Comparison Additions for OAM-Optimized Engine 84Table 174 Frame Signature Byte Mapping 85Table 175 Frame Signature Address Source 85Table 176 LTC Time LoadSave Options 94Table 177 Output Pulse Frequencies 96Table 178 Standard MACsec Frame Combinations 103Table 179 Advanced MACsec Frame Combinations 104Table 180 MACsec Tag Parsing Checks 110Table 181 Match Criteria and Maskable Bits 112Table 182 Egress SA Flow Actions 113Table 183 Ingress SA Flow Actions 114Table 184 Transform Record Format (Non-XPN) 117Table 185 Context Control Word Fields 118Table 186 Transform Record Format (XPN) 118Table 187 Egress SA Counters 122Table 188 Egress Global Counters 122Table 189 Ingress SA Counters 123Table 190 Ingress Global Counters 123Table 191 Egress Per-User Global Counters 123Table 192 IEEE 8021AE Correlation 124Table 193 Ingress Per-User Global Counters 124Table 194 FCS Fault Codes 127Table 195 Ingress Global Stat Event Vector Format 127

VMDS-10505 VSC8490-17 Datasheet Revision 40 viii

Table 196 Ingress SA Stat Event Vector Format 127Table 197 Egress Global Stat Event Vector Format 128Table 198 Egress SA Stat Event Vector Format 128Table 199 Host-Side Loopbacks 137Table 200 Line-Side Loopbacks 138Table 201 Failover and Broadcasting Modes 139Table 202 RXAUI Interoperability 141Table 203 Supported Reference Clock Frequencies 141Table 204 XREFCK Frequency Selection 142Table 205 Supported Clock Rates and Modes 142Table 206 MDIO Port Addresses Per Channel 148Table 207 SPI Slave Instruction Bit Sequence 149Table 208 GPIO Functions 155Table 209 JTAG Instructions and Register Codes 157Table 210 LVTTL Input and PushPull Output DC Characteristics 159Table 211 LVTTLOD Input and Open-Drain Output DC Characteristics 159Table 212 Reference Clock DC Characteristics 160Table 213 Line-Side 10G Receiver Input (SFI Point D 995328G) AC Characteristics 160Table 214 Line-Side SONET 10G Input Jitter AC Characteristics 162Table 215 Host-Side RXAUI Receiver AC Characteristics 162Table 216 Host-Side XAUI Receiver AC Characteristics 162Table 217 Line-Side 125 Gbps SFI Input AC Characteristics 163Table 218 Host-Side 125 Gbps (1000BASE-KX) Receiver Input AC Characteristics 164Table 219 Line-Side 10G Transmitter Output (SFI Point B) AC Characteristics 164Table 220 Transmitter SFP+ Direct Attach Copper Output AC Characteristics 165Table 221 10 Gbps Transmitter 10GBASE-KR AC Characteristics 165Table 222 Line-Side SONET 10G Output Jitter AC Characteristics 166Table 223 Near-end RXAUI Transmitter Output AC Characteristics 166Table 224 Far-end RXAUI Transmitter Output AC Characteristics 166Table 225 Far-end XAUI Transmitter Output AC Characteristics 167Table 226 Line-Side 125 Gbps SFI Output AC Characteristics 168Table 227 Host-Side Transmitter 1000BASE-KX AC Characteristics 168Table 228 Reference Clock AC Characteristics 168Table 229 Two-Wire Serial Interface AC Characteristics 169Table 230 MDIO Interface AC Characteristics 170Table 231 Clock Output AC Characteristics 171Table 232 LoadSave Setup and Hold Timing AC Characteristics 171Table 233 SPI Slave Interface AC Characteristics 172Table 234 3-Pin Push-Out SPI AC Characteristics 173Table 235 Recommended Operating Conditions 173Table 236 Stress Ratings 174Table 237 Pin Identifications 176Table 238 Thermal Resistances 199Table 239 Ordering Information 202

Revision History

VMDS-10505 VSC8490-17 Datasheet Revision 40 1

1 Revision History

The revision history describes the changes that were implemented in the document The changes are listed by revision starting with the most current publication

11 Revision 41Revision 41 was published in September 2018 In revision 41 of this document the registers were attached For more information see Registers page 158

12 Revision 40Revision 40 was published in November 2017 The following is a summary of the changes in revision 40 of this document

bull Low-voltage transistor-to-transistor logic (LVTTL) updated to low-voltage transistor-to-transistor logic with open-drain output (LVTTLOD) where appropriate

bull The two-wire serial slave interface register address illustrations and 24-bit addressing scheme details were updated For more information see Two-Wire Serial (Slave) Interface page 151

bull Line-side 10G receiver input AC characteristics were updated For more information see Table 73 page 160

bull Conditions for transmitter SFP+ direct attach copper output AC characteristics were updated For more information see Table 80 page 165

bull Reference clock AC characteristics were updated For more information see Table 88 page 168bull The SPI interface timing diagram was updated For more information see Figure 128 page 172bull Some pin description information was updated For more information see Pins by Function

page 176bull Moisture sensitivity level (MSL) was corrected from 2 to 4 For more information see Moisture

Sensitivity page 199

13 Revision 20Revision 20 was published in September 2017 It was the first publication of this document

Overview

2 Overview

The VSC8490-17 device is a dual-port 10G1G WANLANBackplane RXAUIXAUI to SFP+KR 10 GbE SerDes PHY with VeriTimetrade and Intellisectrade It supports IEEE 8021AE IEEE 8023ae and IEEE 1588v2

The VSC8490-17 is an IEEE 1588v2-compliant dual-channel device for timing-critical applications It is also well suited for optical module copper Twinax cable and backplane applications with support for a wide variety of protocols including 10 GbE LAN 10 Gb WAN and 1 Gb Legacy Ethernet

The VSC8490-17 device offers a seamless integration between IEEE 1588v2 and the MACsec engine with no loss of precision The MACsec functionality in the VSC8490-17 device supports the IEEE 8021AE 128256-bit MACsec protocols to meet the security requirements for protecting data traversing Ethernet LANs such as input classification frame encryptiondecryption performance and latency monitoring

VeriTimetrade is Microsemirsquos patent-pending timing technology that delivers the industryrsquos most accurate IEEE 1588v2 timing implementation for Ethernet transceivers The IEEE 1588v2 timing integrated in the VSC8490-17 device is the most reliable and lowest-cost method of implementing the timing accuracy to maintain existing timing-critical capabilities during the migration from TDM to packet-based architectures Complete Y1731 OAM performance monitoring capabilities master slave boundary and transparent clock configurations and sophisticated classifications (including UDP IPv4 IPv6 packets and VLAN and MPLS-TP encapsulation) are also supported

The VSC8490-17 device meets the SFP+ limiting and linear SRLRERZR220MMF host requirements in accordance with the SFF-8431 specifications It also compensates for electrical and optical impairments in SFP+ applications along with imperfections of the PCB and connectors

The VSC8490-17 device provides a complete suite of BIST functionality including line and client loopbacks along with pattern generation and error detection Highly flexible clocking options support LAN and WAN operation using single 15625 MHz reference clock rate inputs for seamless Synchronous Ethernet support The VSC8490-17 device also includes a failover switching capability for protection routing along with selectable lane ordering

The serial side supports 125 Gbps and various 10 Gbps modes Each channel consists of a receiver (Rx) and a transmitter (Tx) subsection Three programmable reference clock inputs (XREFCK SREFCK and WREFCK) support the various modes along with clock and data recovery (CDR) in the Rx and Tx subsections of all channels

The following illustration shows a high-level block diagram for the VSC8490-17 device

Overview

Figure 1 bull VSC8490-17 Block Diagram

21 Major Applicationsbull Multiple-port RXAUIXAUI to SFISFP+ line cards or network interface controllers

SD6G

XGXS 1G PCS

SD6G

XAUI

RXA

UI

1 Gb

E

XAUI

RXA

UI

1 Gb

E

XGXS

Host

MAC

Host

MAC

MDI

OTw

o-W

ire S

eria

l Sla

veSP

ITw

o-W

ire S

eria

l Mas

ter

FC

Rate

Com

pBu

ffers

FC

Rate

Com

pBu

ffers

Line

MAC Line

MAC

WIS

SFP

SFP+

SFP

SFP+

HostClient

Line

WIS

Switc

h

1588

MACsec MACsec

1G PCS

10G

PCS

10G

PCS

1G PCS

SD6G

SD10

G

SD10

G

2 times

10G

2 times

1G

2x

2 times

62

5G2x

4 times

31

25G

2x 1

times 1

25G4

21

SPI

MDI

OTw

o-W

ire S

eria

lTw

o-W

ire S

eria

l

42

1

Host

LC-

PLL

Cloc

king

Net

wor

k fo

r Tim

ing

and

Retim

ing

Inclu

ding

Syn

cE S

uppo

rtLi

ne L

C-PL

L

Overview

bull Carrier Ethernet networks requiring 1588v2 timingbull Secure data center-to-data center interconnectsbull 10 GbE switch cards router cards and NICsIn addition the VSC8490-17 device has the following MACsec-enabled applications

bull Secure access connectionsbull Secure client and access connectionsbull Secure connections across a LANbull Secure data center interconnections across a WANbull IEEE 1588 time-stamping on a MACsec portThe following illustrations show the various applications for the VSC8490-17 device

Figure 2 bull SFPSFP+ Application

Figure 3 bull Backplane Equalization Application

Figure 4 bull 1588 Transparent Clock Line Card End-to-End PHY Application

Dual10 GbE

MACNIC

10 GbE Line Card or NIC

VSC8490-17

2 times 10G2 times 1G

RXAUIXAUI

10 G

bE

SFPSFP+XFP24

24SFPSFP+XFP

Dual10 GbE

MACNIC

VSC8490-17

RXAUIXAUI

10 G

bE

SFPSFP+XFP24

24SFPSFP+XFP

Linecard ControlProcessor

Ethernet Port

Ethernet Line Card

MAC PacketProcessing

Ethernet Line Card

MACPacketProcessing

Ethernet Line Card

FabricAdapter

System Card

System ControlProcessor

Fabric

Ethernet Port

1G SerDes PHY

MAC orSwitch

10G SerDes PHY

Overview

Figure 5 bull 1588 Boundary Clock Line Card Application

22 Features and BenefitsThe main features of the VSC8490-17 device are as follows

bull IEEE 1588v21731 OAM precision timing support at 1G and 10Gbull Compliant to IEEE 8023ae and SFF-8431 electrical (SFI) specificationsbull IEEE 8021AE MACsec with 128-bit and 256-bit encryption supportbull 995 Gbps WAN 103125 Gbps LAN and 125 Gbps Ethernet supportbull Supports all standard SFP+ applicationsbull Adaptive receive equalization with programmable multitap transmit pre-emphasisbull Extended WIS supportbull MDIO SPI and two-wire serial slave management interfacesbull Failover switching for protection routing along with selectable lane ordering (non-hitless switching)bull VScopetrade input signal monitoring integrated circuitbull Host-side and line-side loopbacks with BIST functionsbull IO programmability for lane swap invert amplitude slew pre-emphasis and equalizationbull Optional forward error correction (FEC)bull Flexible clocking options for Synchronous Ethernet supportbull Passive copper cable compliant to SFF-8431 is supported for minimum transmission costbull Pin-friendly with VSC8488-15

Ethernet Port

Ethernet Line Card

MACPacketProcessing

System Card

FabricEthernet Port1G

SerDes PHY10G

SerDes PHY

BoundaryClock

Functional Descriptions

3 Functional Descriptions

This section describes the functional aspects of the VSC8490-17 device including the functional block diagram operating modes and major functional blocks

The VSC8490-17 device host-side interface is either four-lane XAUI two-lane RXAUI or one-lane 1 GbE The line-side interface is 10G SFP+ or 1 GbE SFP

Each lane has the following main sections

bull PMAThe PMA section contains the high-speed serial IO interfaces an input equalization circuit a KR-compliant output buffer and a SerDes Additionally the PMA also generates all the line-side clocks including the clocks required for Synchronous Ethernet applications

bull WISThe WIS section contains the framing and de-framing circuits and control and status registers to convert the data to be IEEE 8023ae WIS-compliant

bull 10G PCS The 10G PCS section is composed of the PCS transmit PCS receive block synchronization and BER monitor processes The PCS functions can be further broken down into encode or decode scramble or descramble and gearbox functions as well as various test and loopback modes

bull 1G PCS The 1G PCS section describes the 1000BASE-XSGMII coding and auto-negotiation processes There are two instances per channel one for the host and one for the line

bull IEEE 1588The IEEE 1588 section contains the local time counter analyzer time stamp FIFO and rewriter to support both 1-step and 2-step clock timing and to perform 1588 frame detection time stamp appending header removal and frame processing

bull MACsecThe MACsec section supports IEEE 8021AE MACsec which defines a set of protocols to meet the security requirements for protecting data traversing Ethernet LANs Tasks performed include input classification latency monitoring frame encryption and decryption and performance monitoring

bull MACThe MAC block frames data for transmission over the network before passing the frame to the physical layer interface where it is transmitted as a stream of bits In 10G mode MAC is only enabled along with MACsec In 1G mode MAC can be enabled with or without MACsec

bull FIFOThe FIFO section contains a rate-compensating FIFO between the line rate and the host rate

bull Flow Control BufferThe flow control buffer performs rate compensation between the host and line interfaces when the MACs are enabled

bull Cross ConnectThe cross connect connects one port to the adjacent port to enable routing dataclock to and from port 1 and 0 This cross connect only supports broadcasting from PMA to XAUI but NOT from XAUI to PMA The failover supported by this cross connect is not hitless

bull XGXSThe XGXS implements the PHY XGXS referenced in IEEE 8023 Clause 47 and contains a 10GBASE-X PCS as defined in Clause 48 It provides the necessary translation between the external XAUI interface and the on-chip XGMII interface In addition to standard 4-lane XAUI it also supports 2-lane RXAUIDDR-XAUI

bull XAUIRXAUIThe XAUI and RXAUI section contains the parallel XAUIRXAUI IO interface and a SerDes

bull KRThe KR driver includes programmable equalization accomplished by a three-tap finite impulse response (FIR) structure Three-tap delays are achieved by three flip-flops clocked by a high-speed serial clock (10 GHz in 10G mode 1 GHz in 1G mode)

bull LoopbackThe loopback sections describe the different loopbacks available in the VSC8490-17 device including system and network loopbacks The various loopbacks enhance the engineering debugging and manufacturing testing capability

bull ManagementThe management section contains the status and configuration registers and the serial management interface logic to access them

31 Data Path OverviewThe following sections provide data path information for the VSC8490-17 device Ingress and egress data flow is relative to the line-side interface

311 Ingress OperationData is received by the line-side interface (SFP+1 GbE) processed by core logic and transmitted from the host-side interface (XAUIRXAUI1 GbE) in the ingress (or line-side receive) data path

High-speed serial data is received by the PMA Data can be equalized and is delivered to the clock recovery unit (CRU) The received serial data must be a 66B64B encoded ethernet frame at 103125 Gbps in 10G LAN mode a SONETSDH STS-192c frame at 9953 Gbps in 10G WAN mode or 8B10B encoded data at 125 Gbps in 1 GbE mode

In 10G WAN mode the CRU data is processed by the WIS where 66B64B encoded ethernet data is extracted from SONETSDH STS-192c frames and overhead bytes are processed The extracted payload data is then processed by the 10G PCS In 10G LAN mode the CRU data is processed by a 10G PCS In 1G mode the CRU data is processed by the line-side 1G PCS The 1G10G PCS data can be optionally processed by the IEEE 1588 MACsec and two MAC logic blocks

In 10G LAN and WAN modes data from the core is 8B10B encoded by the XGXS logic and serialized in the host-side SerDes The host interface can be configured as a XAUI interface where four lanes of 3125 Gbps data is transmitted or as a RXAUI interface where two lanes of 625 Gbps data is transmitted Data is transmitted on XAUI lanes 0 and 2 when the host interface is configured to be RXAUI

In 1 GbE mode data from the core is 8B10B encoded by the host-side 1G PCS logic and serialized in the host-side SerDes 125 Gbps data is transmitted from the host interface on either XAUI lane 0 or 3 When 1 GbE data is transmitted from XAUI lane 0 data received by the host interface must enter on lane 0 When 1 GbE data is transmitted from XAUI lane 3 data received by the host interface must enter on lane 3

312 Egress OperationData is received by the host-side interface (XAUIRXAUI1 GbE) processed by core logic and transmitted from the line-side interface (SFP+1 GbE) in the egress (or line-side transmit) data path

The host-side interface can be configured to receive XAUI or RXAUI data when in 10G LAN or 10G WAN modes Data enters the part on XAUI lanes 0 and 2 when using the RXAUI interface The host-side interface receives 1 GbE data when the VSC8490-17 device is in the 1G operating mode XAUI lane 0 or lane 3 may be selected to receive the 125 Gbps data at the host interface When receiving data on XAUI lane 0 1 GbE data will be transmitted from XAUI lane 0 in the ingress data path When receiving data on XAUI lane 3 1 GbE data will be transmitted from XAUI lane 3 in the ingress data path

In 10G mode a clock is recovered from each lane of XAUIRXAUI data in the host-side SerDes The data is 8B10B decoded and lane aligned in the XGXS logic then optionally processed by the IEEE 1588 MACsec and two MAC logic blocks The data is then 66B64B encoded by the 10G PCS logic The data is serialized by the PMA in 10G LAN mode and transmitted from the line interface at 103125 Gbps When the WIS logic is enabled in 10G WAN mode a SONETSDH STS-192c frame is created using the 66B64B encoded data as the frames payload The WIS data is serialized by the PMA and transmitted from the line interface at 9953 Gbps

In 1G mode a clock is recovered from 1 GbE data in the host-side SerDes The data is 8B10B decoded by the host-side 1G PCS then optionally processed by the IEEE 1588 MACsec and two logic blocks

The data is 8B10B encoded by the line-side 1G PCS logic serialized by the PMA and transmitted from the line interface at 125 Gbps

313 Interface Data RatesThe following table shows the interface data rates supported by the VSC8490-17 device

32 Physical Medium Attachment (PMA)The VSC8490-17 PMA section consists of a receiver (Rx) and a transmitter (Tx) subsection The receiver accepts data from the serial data input RXIN and sends the parallel data to the WIS 10G PCS or 1G PCS block A data rate clock also accompanies the parallel data The transmitter accepts parallel data from the WIS or PCS block and transmits at serial data output TXOUT A loopback at the data path is also provided connecting the Rx and the Tx subsection

Serial data is pre-equalized in the input buffer and clock and data are recovered in the deserializer which provides 32-bit data A demux then deserializes the data into a parallel core data interface A PLL in the Rx subsection is used as reference for clock and data recovery Locked to the incoming datastream a lane sync signal is derived from the PLL clock which may be used for source synchronous data transmission to one or multiple transmitters

The Tx subsection is made up of the serializer the output buffer and the PLL The high-speed serial stream is forwarded to a 3-tap filter output buffer The PLL in the Tx subsection is used to generate the high-speed clock used in the serializer

To support different data rates a frequency synthesizer inside the Rx and Tx subsection takes the reference clock input XREFCK and generates all necessary clock rates

The PMA also has two fully programmable clock outputs TXCKOUT and RXCKOUT that may be used to output various clock domains from the PMA For more information about the reference clock see Reference Clock page 142

321 VScope Input Signal Monitoring Integrated CircuitThe VScopetrade input signal monitoring integrated circuit displays the input signal before it is digitized by the CDR The two primary configurations are as follows

bull Unity Gain Amplifier monitors the 10 Gbps input signals before signal processing and equalizationVScope input signal monitoring integrated circuit acts as a virtual scope to effectively observe the received data signal before it has been processed The autonomous adaptive filter taps must first be disabled and the front-end receiver must be set for operation as a linear unity gain amplifier In this mode all DFE taps are set to zero This mode does not require an adaptive algorithm

bull Link Monitor provides the link marginVScope input signal monitoring integrated circuit enables design engineers and system developers to monitor signals remotely without disrupting the data integrity of a live data path By monitoring the health of a given link (optical or electrical) various types of signal degradation can be identified and corrected

Note The VScope input signal monitoring integrated circuit feature is only available in the 10G operation mode

Table 1 bull Interface Data Rates

Operating Mode Line-Side Datarate (Gbps) Host-Side Interface Host-Side Datarate (Gbps)10G LAN 1 times 103125 XAUI 4 times 3125

10G LAN 1 times 103125 RXAUI 2 times 625

10G WAN 1 times 995328 XAUI 4 times 3125

10G WAN 1 times 995328 RXAUI 2 times 625

1 GbE 1 times 125 1 GbE 1 times 125

3211 10GBASE-KR Output DriverThe high-speed output driver includes programmable equalization accomplished by a three-tap finite impulse response (FIR) structure The three-tap delays are achieved by three flip-flops clocked by a high-speed serial clock as shown in the following illustration Coefficients C(ndash1) C(0) and C(+1) adjust the pre-cursor main-cursor and post-cursor of the output waveform The coefficients are independently adjusted by control bits The bits for each coefficient are decoded in a thermometer fashion to achieve linear coefficient adjustment The three delayed data streams after being properly strength adjusted by their coefficients are summed by a summing amplifier The output driver meets the requirements defined in IEEE 8023ap Clause 72

Figure 6 bull 10GBASE-KR Output Driver

The final output stage has 50 Ω back-termination with inductor peaking The output slew rate is controlled by adjusting the effectiveness of the inductors

The test pattern for the transmitter output waveform is the square wave test pattern with at least eight consecutive 1s The following illustration shows the transmitter output waveform test based on voltages V1 through V6 ∆V2 and ∆V5

Figure 7 bull KR Test Pattern

T T T

C ndash1 C 0

decode

KR_COEFF_Cndash1

decode

KR_COEFF_C0

DIN

CKIN

C +1

decode

KR_COEFF_C+1

SummingJunction

decode

KR_SLEW[30]

Slew Control

TXOUTP

TXOUTN

VDD18TX

50 Ω50 Ω

0 V

V1

V2

V3

V4

V5

V6

∆|V2

∆|V5

t1 t1 + T t1 + 2T t2 - 2T t2 - T t2 t2 + 2T t2 + 2T t3 - 2T t3 - T t3

The output waveform is manipulated through the state of the coefficient C(-1) C(0) and C(+1)

33 WAN Interface Sublayer (WIS)The WAN interface sublayer (WIS) is defined in IEEE 8023ae Clause 50 The VSC8490-17 WIS block is fully compliant with this specification The VSC8490-17 offers additional controls ports and registers to allow integration into a wider array of SONETSDH equipment

In addition to the SONETSDH features addressed by WIS as defined by IEEE most SONETSDH framersmappers contain additional circuitry for implementing operation administration maintenance and provisioning (OAMampP) These framersmappers also support special features to enable compatibility with legacy SONETSDH solutions Because the VSC8490-17 WIS leverages Microsemirsquos industry leading framermapper technology it contains suitable features for standard SONETSDH equipment This includes the transmitreceive overhead serial interfaces (TOSIROSI) commonly used for network customization and OAMampP support for SONETSDH errors not contained in the WIS standard support for common legacy SONETSDH implementations and SONETSDH jitter and timing quality

331 OperationWAN mode is enabled by asserting 2x00070 (SPIMDIOTWS) or wis_ctrl2wan_mode Status register bit 1xA1013 (SPIMDIOTWS) or Vendor_Specific_PMA_Status_2WAN_ENABLED_status indicates whether WAN mode is enabled or not The Rx and Tx paths both have WAN mode enabled or disabled It is not possible to have WAN mode in the Tx path enabled while the Rx path is disabled or vice versa

The transmit portion of the WIS does the following

bull Maps data from the PCS through the WIS service interface and to the SONETSDH synchronous payload envelope (SPE)

bull Generates path line and section overhead octetsbull Scrambles the framebull Transmits the frame to the PMA service interfaceThe receive portion of the WIS does the following

bull Receives data from the PMA service interfacebull Delineates octet and frame boundariesbull Descrambles the framebull Processes section line and path overhead information that contain alarms and parity errorsbull Interprets the pointer fieldbull Extracts the payload for transmittal to the PCS through the WIS service interfaceThe following illustration shows the WIS block diagram

Figure 8 bull WIS Transmit and Receive Functions

The following illustration shows the WIS frame structure

Figure 9 bull WIS Frame Structure

The following illustration shows the positions of the section and line overhead octets within the WIS frame

TRANSM IT P AYLO AD MAP P ING

GENERATE P ATH O VERH EAD amp FIXED

STU FF

CO MP U TE B3 (B IP-8)

CO MP U TE B2 (B IP-N )

GENERATE L IN E O VERHEAD

GEN ERATE SECT IO N O VERHEAD

X 7 + X 6 + 1SCRAMBLER

W IS S e rv ice Inte rfa ce tx_ d a ta -u n itlt 1 50 gt rx _ d a ta-u n itlt 1 5 0 gt

PM A S e rv ice Inte rfa ce tx _ d a ta-g ro u plt 1 5 0 gt s y n c_ b itslt 1 50 gt

TR AN SM IT P R O C ESS

R EC EIVE P R O C ESS

P RO CESS P ATH

DEFECTS

P RO CESS L INE

DEFECTS

RECEIVE P AYLO AD MAP P IN G

P RO CESS PATH O VERH EAD

CHECK B3 (B IP-8)

P RO CESS H1 H2 PO INTER

P RO CESS LINE O VERH EAD

CH ECK B2 (B IP-N )

P RO CESS SECTIO N O VERH EAD

CHECK B1 (B IP-8)

X 7 + X 6 + 1DESCRAMBLER

IN S ER T P A T H O V ER H EA D amp F IX ED S T U FF

IN S ERT L IN E O V ER H EA D

IN S ER T S EC T IO N

O V ER H EA D

RE M O V E P A T H O V ER H EA D amp F IX ED S T U FF

RE M O V E L IN E O V ERH EA D

REM O V E S ECT IO N

O V ER H EA D

63 Octets 16 640 Octets

Payload958464 Gbs

Fixe

d Stu

ffin

g

Path

Ove

rhea

d

16 704 Octets576 Octets

LineOverhead

Pointer

SectionOverhead

Figure 10 bull STS-192cSTM-64 Section and Line Overhead Structure

The following illustration shows the path overhead octet positions

Figure 11 bull Path Overhead Octets

332 Section OverheadThe section overhead portion of the SONETSDH frame supports frame synchronization a tandem connection monitor (TCM) known as the Section Trace a high-level parity check and some OAMampP octets The following table lists each of the octets including their function specification and related information

The VSC8490-17 device provides a mechanism to transmit a static value as programmed by the MDIO interface However by definition MDIO is not fast enough to alter the octet on a frame-by-frame basis

Table 2 bull Section Overhead

Overhead Octet FunctionIEEE 8023ae WIS Usage

Recommended Value WIS Extension

A1 Frame alignment Supported 0xF6 Register (EWIS_TX_A1_A2) TOSI and ROSI access

A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 J0(C1)

Z0(C1)

B1

D1

H1

B2

D4

D7

D10

S1

H1

B2 B2

H1

Bytes reserved for national use

B2

H1

B2

H1

B2

H1

576 Octets

9Octets

E1

D2

H2

K1

D5

D8

D11

Z2

M0 M1 Z2

H2 H2 H2 H2 H2

F1

D3

H3

K2

D6

D9

D12

E2

Bytes undefinedunused by IEEE8023ae

H3 H3 H3 H3 H3

J1

B 3

C 2

G 1

F2

H 4

Z 3 F 3

Z 4 K 3

N 1

N in eO c te ts

3321 Frame Alignment (A1 A2)The SONETSDH protocol is based upon a frame structure that is delineated by the framing octets A1 and A2 The framing octets are defined to be 0xF6 and 0x28 respectively In the transmit direction all 192 A1 octets are sourced from the TX_A1 (EWIS_TX_A1_A2TX_A1) register while the A2 octets are sourced from the TX_A2 (EWIS_TX_A1_A2TX_A2) register

In the receive direction the frame aligner monitors the input bus from the PMA and performs word alignment The frame alignment architecture is composed of a primary and secondary state machine The selected frame alignment and synchronization pattern have implications on the tolerated input BER The higher the input BER the less likely the frame boundary can be found The chances of finding the frame boundary are improved by reducing the number of A1A2 bytes required to be detected (using a smaller pattern width) According to the WIS specification the minimum for all parameters allows a signal with an error tolerance of 10-12 to be framed

A2 Frame alignment Supported 0x28 Register (EWIS_TX_A1_A2) TOSI and ROSI access

J0 Section trace Specified value For more information see Section Trace (J0) page 17

A 1-byte 16-byte or 64-byte trace message can be sent using registers WIS_Tx_J0_Octets_1_0 to WIS_Tx_J0_Octets_15_14 EWIS_TX_MSGLEN or EWIS_Tx_J0_Octets_17_16 to EWIS_Tx_J0_Octets_63_62 and received using registers WIS_Rx_J0_Octets_1_0 to WIS_Rx_J0_Octets_15_14 EWIS_RX_MSGLEN and EWIS_Rx_J0_Octets_17_16 to EWIS_Rx_J0_Octets_63_62 TOSI and ROSI access

Z0 Reserved for section growth

Unsupported 0xCC Register EWIS_TX_Z0_E1 TOSI and ROSI access

B1 Section error monitoring (Section BIP-8)

Supported Bit interleaved parity - 8 bits as specified in T1416

Using the TOSI the B1 byte can be masked for test purposes For each B1 mask bit that is cleared to 0 on the TOSI interface the transmitted bit is left unchanged For each B1 mask bit that is set to 1 on the TOSI interface the transmitted bit is inverted

Using the ROSI the B1 error locations can be extracted Periodically latched counter (EWIS_B1_ERR_CNT1-EWIS_B1_ERR_CNT0) is available

E1 Orderwire Unsupported 0x00 Register EWIS_TX_Z0_E1 TOSI and ROSI access

F1 Section user channel

Unsupported 0x00 Register EWIS_TX_F1_D1 TOSI and ROSI access

D1-D3 Section data communications channel (DCC)

Unsupported 0x00 Register EWIS_TX_F1_D1 to EWIS_TX_D2_D3 TOSI and ROSI access

Table 2 bull Section Overhead (continued)

The following illustration shows the primary synchronization state diagram

Figure 12 bull Primary Synchronization State Diagram

The following table lists the variables for the primary state diagram The variables are reflected in registers EWIS_RX_FRM_CTRL1 and EWIS_RX_FRM_CTRL2 that can be alternately reconfigured

Table 3 bull Framing Parameter Description and Values

Name DescriptionIEEE 8023ae Parameter

IEEE 8023ae Range Range Default

Sync_Pattern width Sequence of f consecutive A1s followed immediately by a sequence of f consecutive A2s If f = 2 Sync_Pattern is A1A1A2A2

f 2 to 192 0 to 16ExceptionsIf f = 0 Sync_Pattern is A1 + 4 MSBs of A2If f = 1 Sync_Pattern is A1A1A2

2

Hunt_Pattern width Sequence of i consecutive A1s

i 1 to 192 1 to 16 4

Presync_Pattern A1 width Presync_Pattern consists of a sequence of j consecutive A1s followed immediately by a sequence of k consecutive A2s

j 16 to 190 1 to 16If set to 0 behaves as if set to 1If set to 17 to 31 behaves as if set to 16

16

HUNT

sync_start FALSEin_HUNT TRUE

A1_ALIGN

FALSEin_HUNT

PRESYNC

sync_start TRUE

SYNC

sync_start FALSE

power_on = TRUE + signal_fail = TRUE

found_Hunt = FALSE

found_Presync = FALSE

bad_sync_cnt = 1

bad_sync_cnt = n

found_Hunt = TRUE

found_Presync = TRUE

bad_sync_cnt = m

The following illustration shows the secondary synchronization state diagram

Figure 13 bull Secondary Synchronization State Diagram

3322 Loss of Signal (LOS)WIS_STAT3LOS alarm status is a latch-high register back-to-back reads provide both the event as well as status information The LOS event also asserts register EWIS_INTR_PEND1LOS_PEND until read This event can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_1LOS_MASKA and EWIS_INTR_MASKB_1LOS_MASK

There is no hysteresis on the LOS detection and so it is recommended to have the system software to implement a sliding window to check on the LOS before qualifying the presence of a signal As an alternative Rx_LOS can be used from the optical module (through LOPC) to qualify the input signal In

k 16 to 192 0 to 160 means only 4 MSB of A2 are usedIf set to 17 to 31 behaves as if set to 16

16

SYNC state entry Number of consecutive frame boundaries needed to be found after entering the PRESYNC state in order to enter the SYNC state

m 4 to 8 1 to 15If set to 0 behaves as if set to 1

4

SYNC state exit Number of consecutive frame boundary location errors detected before exiting the SYNC state

n 1 to 8 1 to 15If set to 0 behaves as if set to 1

4

Table 3 bull Framing Parameter Description and Values (continued)

DELAY_1

power_on = TRUE + reset = TRUE + signal_fail = TRUE

in_HUNT = TRUE

sync_start = TRUE

WAIT

good_sync_cnt 0bad_sync_cnt 0octet_cnt 0

DELAY_2

FOUND

bad_sync_cnt 0good_sync_cnt ++octet_cnt 0

MISSED

good_sync_cnt 0bad_sync_cnt ++octet_cnt 0

in_HUNT = FALSE octet_cnt = 155520 found_Sync = FALSE

in_HUNT = FALSE octet_cnt = 155520 found_Sync = TRUE

in_HUNT = FALSE octet_cnt = (155520+fndashk) found_Sync = TRUE

in_HUNT = FALSE octet_cnt = (155520+fndashk) found_Sync = FALSE

UCT UCT

addition to using analog detection digital detection such as PCS_Rx_Fault is recommended to determine if the input signal is good

When the near-end device experiences LOS it is possible to automatically transmit a remote defect indication (RDI-L) to the far-end for notification purposes The EWIS_RXTX_CTRLTXRDIL_ON_LOS if asserted overwrites the outgoing K2 bits with the RDI-L code In the receive path it is possible to trigger an AIS-L state (alarm assertion plus forcing the payload to an all ones state) upon a detection of an LOS condition This is accomplished by asserting EWIS_RXTX_CTRLRXAISL_ON_LOS

3323 Loss of Optical Carrier (LOPC)The input pin LOPC can be used by external optic components to directly assert the loss of optical power to the physical media device Any change in level on the LOPC input asserts register EWIS_INTR_PEND2LOPC_PEND until read The current status of the LOPC input pin can be read in register EWIS_INTR_STAT2LOPC_STAT The LOPC input can be active high or active low by setting the Vendor_Specific_LOPC_ControlLOPC_state_inversion_select bit appropriately The LOPC_PEND bit can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_2LOPC_MASKA and EWIS_INTR_MASKB_2LOPC_MASKB

When the near-end device experiences LOPC it is possible to automatically transmit a remote defect indication (RDI-L) to the far-end to notify it of a problem The EWIS_RXTX_CTRLTXRDIL_ON_LOPC register bit if asserted overwrites the outgoing K2 bits with the RDI-L code In the receive path it is possible to force the receive framer into an LOF state thereby squelching subsequent alarms and invalid payload data processing This is accomplished by asserting EWIS_RX_ERR_FRC1RXLOF_ON_LOPC Similar to the LOF condition forced upon an LOPC the EWIS_RXTX_CTRLRXAISL_ON_LOPC can force the AIS-L alarm assertion plus force the payload to an all ones state to indicate to the PCS the lack of valid data upon an LOPC condition

3324 Severely Errored Frame (SEF)Upon reset the VSC8490-17 device Rx WIS enters the out-of-frame (OOF) state with both the severely errored frame (SEF) and loss of frame (LOF) alarms active The SEF state is terminated when the framer enters the SYNC state The framer enters the SYNC state after EWIS_RX_FRM_CTRL2SYNC_ENTRY_CNT plus 1 consecutive frame boundaries are identified An SEF state is declared when the framer enters the out-of-frame (OOF) state The frame changes from the SYNC state to the OOF state when EWIS_RX_FRM_CTRL2SYNC_EXIT_CNT consecutive frames with errored frame alignment words are detected The SEF alarm condition is reported in WIS_STAT3SEF This register latches high providing a combination of interrupt pending and status information within consecutive reads

An additional bi-stable interrupt pending bit SEF_PEND (EWIS_INTR_PEND1SEF_PEND) is provided to propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits SEF_MASKA (EWIS_INTR_MASKA_1SEF_MASKA) and SEF_MASKB (EWIS_INTR_MASKB_1SEF_MASKB)

3325 Loss of Frame (LOF)An LOF occurs when an out-of-frame state persists for an integrating period of EWIS_LOF_CTRL1LOF_T1 frames To provide for the case of intermittent OOFs when not in the LOF state the integrating timer is not reset to zero until an in-frame condition persists continuously for EWIS_LOF_CTRL1LOF_T2 frames The LOF state is exited when the in-frame state persists continuously for EWIS_LOF_CTRL2LOF_T3 frames The LOF state is indicated by the WIS_STAT3LOF register being asserted This register latches high providing a combination of pending and status information over consecutive reads

An additional bi-stable interrupt pending bit EWIS_INTR_PEND1LOF_PEND is provided to propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_1LOF_MASKA and EWIS_INTR_MASKB_1LOF_MASKB

When the near-end device experiences an LOF condition it is possible to automatically transmit a remote defect indication (RDI-L) to the far end to notify it of a problem The EWIS_RXTX_CTRLTXRDIL_ON_LOF if asserted overwrites the outgoing K2 bits with the RDI-L code

In the receive path it is possible to force a AIS-L state (alarm assertion plus forcing the payload to an all ones state) upon a detection of an LOF condition This is accomplished by asserting EWIS_RXTX_CTRLRXAISL_ON_LOF

3326 Section Trace (J0)The J0 octet often carries a repeating message called the Section Trace message The default transmitted message length is 16 octets whose contents are defined in WIS_TXJ0 (WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14) If no active message is being broadcast a default section trace message is transmitted This section trace message consists of 15 octets of zeros and a header octet formatted according to Section 5 of ANSI T1269-2000 The header octet for the 15-octets of zero is 0x89 The default values of WIS_TXJ0 (WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14) do not contain the 0x89 value of the header octet so software must write this value

The J0 octet in the receive direction is assumed to be carrying a 16-octet continuously-repeating section trace message The message is extracted from the incoming WIS frames and stored in WIS_RXJ0 (WIS_Rx_J0_Octets_1_0-WIS_Rx_J0_Octets_15_14) The WIS receive process does not delineate the message boundaries thus the message might appear rotated between new frame alignment events

The VSC8490-17 device supports two alternate message types a single repeating octet and a 64-octet message The message type can be independently selected for the transmit and receive direction The transmit direction is configured using EWIS_TX_MSGLENJ0_TXLEN while EWIS_RX_MSGLENJ0_RX_LEN configures the receive path

When the transmit direction is configured for a 64-octet message the first 16 octets are programmed in WIS_TXJ0 (WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14) while the 48 remaining octets are programmed in EWIS_TXJ0 (EWIS_Tx_J0_Octets_17_16-EWIS_Tx_J0_Octets_63_62) Likewise the first 16 octets of the receive message are stored in WIS_RXJ0 (WIS_Rx_J0_Octets_1_0-WIS_Rx_J0_Octets_15_14) while the other 48 octets are stored in EWIS_RXJ0 (EWIS_Rx_J0_Octets_17_16-EWIS_Rx_J0_Octets_63_62) The receive message is updated every 125 micros with the recently received octet Any persistency or message matching is expected to take place within the station manager

3327 Reserved for Section Growth (Z0)The WIS standard does not support the Z0 octet and requires transmission of 0xCC in the octet locations A different Z0 value can be transmitted by configuring EWIS_TX_Z0_E1TX_Z0 The TX_Z0 default is 0xCC

3328 ScramblingDescramblingThe transmit signal (except for row 1 of the section overhead) is scrambled according to the standards when register bit EWIS_TXCTRL2SCR is asserted which is the default state When deasserted the scrambler is disabled

The receive signal descrambler is enabled by default The descrambler can be bypassed by deasserting register bit EWIS_RX_CTRL1DSCR_ENA

Enabling loopback H4 and turning off the WIS scrambler and descrambler may yield an interesting data point when debugging board setups The CRU in the ingress PMA path would not have enough edge transitions in the data to reliably recover the clock if the chip were receiving non-scrambled data The same would be true for any far-end device connected to the egress PMA if the scrambler were turned off The WIS scrambler and descrambler should be left on under normal operating conditions

3329 Section Error Monitoring (B1)The B1 octet is a bit interleaved parity-8 (BIP-8) code using even parity calculated over the previous STS-192c frame post scrambling The computed BIP-8 is placed in the following outgoing SONET frame before scrambling

In the receive direction the incoming frame is processed and a BIP-8 is calculated The calculated value is then compared with the B1 value received in the following frame The difference between the calculated and received octets are accumulated into the WIS_B1_CNT register This counter rolls over after the maximum count This counter is cleared upon device reset

The EWIS_B1_ERR_CNT1 and EWIS_B1_ERR_CNT0 registers provide a count of the number of received B1 parity errors This register is updated with the internal count value upon a PMTICK condition after which the internal counter is reset to zero When the counter is nonzero the EWIS_INTR_PEND2B1_NZ_PEND event register is asserted until read A non-latch high version of this event EWIS_INTR_STAT2B1_NZ_STAT is also available This event can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_2B1_NZ_MASKA and EWIS_INTR_MASKB_2B1_NZ_MASKB

The B1_ERR_CNT can optionally be configured to increment on a block count basis a maximum increment of 1 per errored frame regardless of the number of errors received This mode is enabled by asserting EWIS_CNT_CFGB1_BLK_MODE

33210 Section Orderwire (E1)The WIS standard does not support the E1 octet and requires transmission of 0x00 in the octet location A different E1 value can be transmitted by configuring EWIS_TX_Z0_E1TX_E1 (whose default is 0x00)

33211 Section User Channel (F1)The WIS standard does not support the F1 octet and requires transmission of 0x00 in the octet location A different F1 value can be transmitted by configuring EWIS_TX_F1_D1TX_F1 (whose default is 0x00)

33212 Section Data Communication Channel (DCC-S)The WIS standard does not support the DCC-S octets and requires transmission of 0x00 in the octet locations Different DCC-S values can be transmitted by configuring EWIS_TX_F1_D1TX_D1 EWIS_TX_D2_D3TX_D2 and EWIS_TX_D2_D3TX_D3 (all of which default to 0x00)

33213 Reserved National and Unused OctetsThe VSC8490-17 device transmits 0x00 for all reserved national and unused overhead octets

333 Line OverheadThe line overhead portion of the SONETSDH frame supports pointer interpretation a per channel parity check protection switching information synchronization status messaging far-end error reporting and some OAMampP octets

The VSC8490-17 device provides a mechanism to transmit a static value as programmed by the MDIO interface However by definition MDIO is not fast enough to alter the octet on a frame-by-frame basis The following table lists each of the octets including their function specification and related information

Table 4 bull Line Overhead Octets

Overhead Octet FunctionIEEE 8023ae WIS Usage Recommended Value WIS Extension

H1-H2 Pointer Specified value SONET modeSTS-1 0x62 0x0ASTS-n 0x93 0xFF SDH modeSTS-1 0x6A 0x0ASTS-n 0x9B 0xFF

Registers EWIS_TX_C2_H1TX_H1 and EWIS_TX_H2_H3TX_H2 TOSI and ROSI access

H3 Pointer action Specified value 0x00 Register EWIS_TX_H2_H3TX_H3 TOSI and ROSI access

B2 Line error monitoring (line BIP-1536)

Supported BIP-8 as specified in T1416

Using the TOSI the B2 bytes can be masked for test purposes For each B2 mask bit that is cleared to 0 on the TOSI interface the transmitted bit is left unchanged For each B2 mask bit that is set to 1 on the TOSI interface the transmitted bit is inverted Using the ROSI the B2 error locations can be extracted Periodically latched counter (EWIS_B1_ERR_CNT1-EWIS_B1_ERR_CNT0) is available

K1 K2 Automatic protection switch (APS) channel and line remote defect identifier (RDI-L)

Specified value For more information about K2 coding see Table 5 page 21

Register Registers EWIS_TX_G1_K1TX_K1 and EWIS_TX_K2_F2TX_K2 TOSI and ROSI access

D4-D12 Line data communications channel (DCC)

Unsupported 0x00 Registers EWIS_TX_D4_D5 and EWIS_TX_D6_H4 TOSI and ROSI access

S1 Synchronization messaging

Unsupported 0x0F Register EWIS_TX_S1_Z1TX_S1 TOSI and ROSI access

Z1 Reserved for Line growth

Unsupported 0x00 Register EWIS_TX_S1_Z1TX_Z1 TOSI and ROSI access

M0M1 STS-1N line remote error indication (REI)

M0 unsupported M1 supported

0x00number of detected B2 errors in the receive path as specified in T1416

TOSI and ROSI access The VSC8490-17 device supports a mode that uses only M1 to back report REI-L (EWIS_MODE_CTRREI_MODE = 0) and another mode which uses both M0 and M1 to back report REI-L (EWIS_MODE_CTRREI_MODE = 1) For more information see Line Error Monitoring (B2) page 20

E2 Orderwire Unsupported 0x00 Register EWIS_TX_Z2_E2TX_E2 TOSI and ROSI access

Unsupported 0x00 Register EWIS_TX_Z2_E2TX_Z2 TOSI and ROSI access

Table 4 bull Line Overhead Octets (continued)

3331 Line Error Monitoring (B2)The B2 octet is a BIP-8 value calculated over each of the previous STS-1 channels excluding the section overhead and pre-scrambling As the B2 octet is calculated on an STS-1 basis there are 192 B2 octets within an STS-192STM-64 frame Each of the 192 calculated BIP-8 octets are then placed in the outgoing SONETSDH frame

Note For SONET mode when the number of errors detected in the B2 octet of a receive frame is greater than 255 the total count of detected errors is transmitted in more than one frame Even when no B2 errors are detected in subsequent frames the number of detected B2 errors going into an accumulator will be limited to 255 if more than 255 errors are detected in a frame The Tx framer pulls the REI-L count out of the accumulator when REI-L is transmitted to be compliant with T1-105

In the receive direction the incoming frame is processed a per STS-1 BIP-8 is calculated (excluding section overhead and after descrambling) and then compared to the B2 value in the following frame Errors are accumulated in the WIS_B2_CNT1 and WIS_B2_CNT0 registers This counter is non-saturating and so rolls over after its maximum count The counter is cleared only on device reset

An additional 32-bit B2 error counter is provided in B2_ERR_CNT (EWIS_B2_ERR_CNT1 and EWIS_B2_ERR_CNT0) which is a saturating counter and is latched and cleared based upon a PMTICK event Errors are accumulated from the previous PMTICK event When the counter is nonzero the EWIS_INTR_PEND2B2_NZ_PEND event register is asserted until read A non-latch high version of this event is available in EWIS_INTR_STAT2B2_NZ_STAT This event can propagate an interrupt to either WIS_INTA or WIS_INTB based on mask enable bits EWIS_INTR_MASKA_2B2_NZ_MASKA and EWIS_INTR_MASKB_2B2_NZ_MASKB

It is possible that two sets of B2 bytes (from two SONETSDH frames) are received by the Rx WIS logic in a period of time when only one M0M1 octet is transmitted In this situation one of the two B2 error counts delivered to the Tx WIS logic is discarded This situation occurs when the receive data rate is faster than the transmit data rate Similarly when the transmit data rate is faster than the receive data rate a B2 error count is not available for REI-L insertion into the M0M1 octets of the transmitted SONETSDH frame A value of zero is transmitted in this case This behavior is achieved by using a FIFO to transfer the detected B2 error count from the receive to transmit domains

A FIFO overflow or underflow condition is not considered an error Instead it is recovered from gracefully as described above A FIFO overflow or underflow eventually occurs unless the transmit and receive interfaces are running at the same average data rate Because the received and transmitted frames can differ by at most 40 ppm (plusmn20 ppm) and still meet the industry standards this ldquosliprdquo can happen no more often than once every 31 seconds

3332 APS Channel and Line Remote Defect Identifier (K1 K2)The K1 and K2 octets carry information regarding automatic protection switching (APS) and line remote defect identifier (RDI-L) The K1 octet and the most significant five bits of the K2 octet contain the APS channel information The transmitted values can be configured at EWIS_TX_G1_K1TX_K1 and EWIS_TX_K2_F2TX_K2 The default values of all zeros are compliant with the WIS standard

The three least significant bits within the K2 octet carry the RDI-L encoding as defined by section 741 of ANSI T1416-1999 and as shown in the following table

Although the transmission of RDI-L is not explicitly defined within the WIS standard the VSC8490-17 device allows the automatic transmission of RDI-L upon the detection of LOPC LOS LOF or AIS-L conditions These features are enabled by asserting TXRDIL_ON_LOPC TXRDIL_ON_LOS TXRDIL_ON_LOF and TXRDIL_ON_AISL in register EWIS_RXTX_CTRL

Note The RDI-L code of 110 is transmitted by the DUT only when Rx AIS-L is asserted For example if AIS-L is detected by the DUT for five continuous frames in the Rx direction then the RDI-L code is transmitted for five frames in the Tx direction (not 20 frames as stated in the ANSI T1105 specification)

The VSC8490-17 device can force a RDI-L condition independent of the K2 transmit value by asserting EWIS_TXCTRL2FRC_TX_RDI Likewise a AIS-L condition can be forced by asserting EWIS_TXCTRL2FRC_TX_AISL If both conditions are forced the AIS-L value is transmitted

In the receive direction the RDI-L alarm (K2[68] = 110 using SONET nomenclature) and the AIS-L alarm (K2[68] = 111 using SONET nomenclature) are not asserted until the condition persists for a programmable number of contiguous frames This value is programmable at EWIS_RX_ERR_FRC1APS_THRES and is typically set to values of 5 or 10 The AIS-L is detected by the receiver after the programmable number of frames is received and results in the reporting of AIS-P

The WIS standard defines WIS_STAT3RDIL and WIS_STAT3AISL as a read-only latch-high register so a read of a one in this register indicates that an error condition occurred since the last read A second

read of the register provides the current status of the event as to whether the alarm is currently asserted EWIS_INTR_PEND1RDIL_PEND and EWIS_INTR_PEND1AISL_PEND assert whenever the RDI-L or AIS-L state changes (assert or deassert) These interrupts have associated mask enable bits (EWIS_INTR_MASKA_1RDIL_MASKA EWIS_INTR_MASKB_1RDIL_MASKB EWIS_INTR_MASKA_1AISL_MASKA and EWIS_INTR_MASKB_1AISL_MASKB) which if enabled propagate an interrupt to the WIS_INTAB pins

Table 5 bull K2 Encodings

Indicator K2 Value for Bits 6 7 8 InterpretationRDI-L 110 Remote error indication

For the receive process an RDI-L defect occurs after a programmable number of RDI-L signals are received in contiguous frames and is terminated when no RDI-L is received for the same number of contiguous framesAn RDI-L can be forced by asserting EWIS_RX_ERR_FRC1FRC_RX_RDILFor the transmit process the WIS standard does not indicate when or how to transmit RDI-L VSC8490-17 provides the option of transmitting K2 by programming it through the TOSI by programming it using the K2_TX MDIO register or by programming it based on the contents of the K2_TX register with bits 6 7 and 8 modified depending on the status of the following LOPC LOS LOF AIS-L and their associated transmit enable bits enable bits TXRDIL_ON_LOPC TXRDIL_ON_LOS TXRDIL_ON_LOF and TXRDIL_ON_AISL in register EWIS_RXTX_CTRL

AIS-L 111 Alarm indication signal (line)For the receive process this is detected based on the settings of the K2 byte When AIS-L is detected the WIS link status is down and WIS_STAT3AISL is set high This also contributes to errored second (ES) and severally errored second (SES) reportsFor standard WIS operation this is never transmitted

Idle (normal)

000 Unless RDI-L exists the standard WIS transmits idle

For test purposes the VSC8490-17 device can induce a RDI-L condition in the receive direction independent of the received K2 value by asserting EWIS_RX_ERR_FRC1FRC_RX_RDIL Likewise a AIS-L condition can be forced in the receive direction by asserting EWIS_RX_ERR_FRC1FRC_RX_AISL

3333 Line Data Communications Channel (D4 to D12)The WIS standard does not support Line Data Communications Channel (L-DCC) octets (D4-D12) and recommends transmitting 0x00 within these octets The D4-D12 transmitted values can be programmed in registers EWIS_TX_D4_D5 - EWIS_TX_D12_Z4 The register defaults are all 0x00 The receive L-DCC octets are only accessible through the ROSI port

3334 STS-1N Line Remote Error Indication (M0 and M1)The M0 and M1 octets are used for back reporting the number of B2 errors received known as remote error indication (REI-L) The value in this octet comes from the B2 error FIFO as discussed with the B2 octet The WIS standard does not support the M0 octet and recommends transmitting 0x00 in place of the M0 octet However the WIS standard supports the M1 octet in accordance with T1416

Two methods for back-reporting exist and are controlled by EWIS_TXCTRL2SDH_TX_MODE Because a single frame can contain up to 1536 B2 errors while the M1 byte alone can only back report a maximum of 255 errors a discrepancy exists When G707_2000_REIL is deasserted only the M1 byte is used and a maximum of 255 errors are back-reported When G707_2000_REIL is asserted two octets per frame are used for back reporting- the M1 octet and the M0 octet (not the first STS-1 octet but the second STS-1 octet) In this mode a total of 1536 errors can be back-reported per frame

In the receive direction the VSC8490-17 device detects and accumulates errors according to the EWIS_MODE_CTRLREI_MODE setting The VSC8490-17 device deviates from the G707 standard by not interpreting REI-L values greater than 1536 as zero The WIS standard defines a 32-bit REI-L counter in registers WIS_REIL_CNT1 and WIS_REIL_CNT0 This counter is non-saturating and so rolls over after its maximum count The counter is cleared only on device reset

An additional 32-bit REI-L counter is provided in registers EWIS_REIL_CNT1 and EWIS_REIL_CNT0 which is a saturating counter and is latched and cleared based upon a PMTICK event Errors are accumulated since the previous PMTICK event When the counter is nonzero the EWIS_INTR_PEND2REIL_NZ_PEND event register is asserted until read A non-latch high version of this event (EWIS_INTR_STAT2REIL_NZ_STAT) is also available This event can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_2REIL_NZ_MASKA and EWIS_INTR_MASKB_2REIL_NZ_MASKB

The REIL_ERR_CNT can optionally be configured to increment on a block count basis a maximum increment of 1 per errored frame regardless of the number of errors received This mode is enabled by asserting EWIS_CNT_CFGREIL_BLK_MODE

3335 Synchronization Messaging (S1)The S1 octet carries the synchronization status message and provides synchronization quality measures of the transmission link in the least significant 4 bits The WIS standard does not support the S1 octet and requires the transmission of a 0x0F within the S1 octet A value other than 0x0F can be programmed in TX_S1 (2xE61F)

3336 Reserved for Line Growth (Z1 and Z2)The WIS standard does not support the Z1 or Z2 octets and requires the transmission of 0x00 in their locations Different Z1 and Z2 values can be transmitted by programming the values at EWIS_TX_S1_Z1TX_Z1 and EWIS_TX_Z2_E2TX_Z2 respectively

3337 Orderwire (E2)The WIS standard does not support the E2 octet and recommends transmitting 0x00 in place of the E2 octet A value other than 0x00 can be transmitted by programming the intended value at EWIS_TX_Z2_E2TX_E2

334 SPE PointerThe H1 and H2 octets are used as a pointer within the SONETSDH frame to locate the beginning of the path overhead and the beginning of the synchronous payload envelope (SPE) Within SONETSDH the SPE can begin anywhere within the payload area However IEEE 8023ae specifies that a transmitted SPE must always be positioned solely within a single SONETSDH frame The constant pointer value of 522 decimal (0x20A) must be contained in the first channelrsquos H1 and H2 octets Together these conditions result in the H1 and H2 octets being 0x62 and 0x0A respectively These are the default values of EWIS_TX_C2_H1TX_H1 and EWIS_TX_H2_H3TX_H2 Programming these registers with alternate values does not alter the positioning of the SPE but it might induce a loss of pointer (LOP-P) at the far-end or at least prevent the far-end from extracting the proper payload Furthermore the WIS standard specifies the frame structure be a concatenated payload For this reason the H1 and H2 octets in channels 2 through 192 contain the concatenation indicator

The VSC8490-17 device supports forcing the loss of pointer (LOP-P) and path alarm indication signal (AIS-P) state

The WIS standard specifies that a 0times00 be transmitted in the H3 octet An alternate value can be transmitted by programming EWIS_TX_H2_H3TX_H3

The WIS specification does not limit the pointer position within the receive SONETSDH frame to allow interoperability to other SONETSDH equipment In addition to supporting the required SONET pointer rules the VSC8490-17 device pointer interpreter optionally supports SDH pointers This is selectable using the EWIS_MODE_CTRLRX_SS_MODE bit The following table shows the differences between SONET and SDH modes

The H1 and H2 octets combine to form a word with several fields as shown in Figure 14 page 24

3341 Bit Designations within Payload PointerThe N bits [1512] carry a new data flag (NDF) This mechanism allows an arbitrary change in the location of the payload NDF is indicated by at least three out of the four N bits matching the code lsquo1001rsquo (NDF enabled) Normal operation is indicated by three out of the four N bits matching the code lsquo0110rsquo (normal NDF)

The last ten bits of the pointer word (D bits and I bits) carry the pointer value The pointer value has a range from 0 to 782 that indicates the offset between the first byte after the H3 byte and the first byte of the SPE

The SS bits are located in bits 11 and 10 and are unused in SONET mode In SDH mode these bits are compared with pattern lsquo10rsquo and the pointer is considered invalid if it does not match

Because the VSC8490-17 device only supports concatenated frames only the first pair of bytes (H1 H2) are called the primary pointer and have a normal format The

rest of the H1H2 bytes contain the concatenation indication (CI) The format for the CI is NDF enabled with a pointer value of all ones

Table 6 bull SONETSDH Pointer Mode Differences

SONET SDHSS bits are ignored by the device pointer interpreter and not used

SS bits are set to 10 and are checked by the device pointer interpreter to determine the pointer type

All 192 bytes of H1 and H2 are checked by the pointer interpreter to determine the pointer type

The first 64 bytes are checked by the pointer interpreter to determine the pointer type (first Au-4 of an AU-4-64c)

Uses lsquo8 out of 10rsquo GR-253-core objective incrementdecrement rule

Uses majority detect incrementdecrement rule

Figure 14 bull 16-bit Designations within Payload Pointer

3342 Pointer TypesThe VSC8490-17 device supports five different pointer types as described in the following table A normal pointer indicates the current pointer a new data flag indicates a new pointer location and an AIS pointer indicates AIS The pointer increment and pointer decrement mechanism adjusts the frequency offset between the frame overhead and SPE A pointer increment is indicated by a normal NDF that has the currently accepted pointer with the I bits inverted A pointer decrement is indicated by a normal NDF that has the currently accepted pointer with D bits inverted

3343 Pointer Adjustment RuleThe VSC8490-17 device pointer interpreter adjusts the current pointer value according to rules listed in Section 916 of ANSI T1105-1995 In addition no incrementdecrement is accepted for at least three frames following an incrementdecrement or NDF operation

3344 Pointer IncrementDecrement Majority RulesIn SONET mode the pointer interpreter uses more restrictive GR-253-CORE objective rules as follows

bull An increment is indicated by eight or more bits matching non-inverted D bits and inverted I bitsbull A decrement is indicated by eight or more bits matching non-inverted I bits and inverted D bitsIn SDH mode the majority rules are

bull An increment is indicated by three or more inverted I bits and two or fewer inverted D bitsbull A decrement is indicated by three or more inverted D bits and two or fewer inverted I bitsbull If three or more D bits are inverted and three or more I bits are inverted no action is taken

Table 7 bull H1H2 Pointer Types

Pointer Type nnnn Value Pointer Value SS bitsNormal Three out of the four bits

matching 01100 to 782 Matching in SDH mode

ignored in SONET mode

New data flag (NDF) Three out of the four bits matching 1001

0 to 782 Matching in SDH mode ignored in SONET mode

AIS pointer 1111 1111 1111 11 11

Pointer increment Three out of the four bits matching 0110

Current pointer with I bits inverted

Matching in SDH mode ignored in SONET mode

Pointer decrement Three out of the four bits matching 0110

Current pointer with D bits inverted

Table 8 bull Concatenation Indication Types

Pointer Type nnnn Value Pointer Value SS bitsNormal concatenation indication Three out of the four

bits matching 10011111 1111 11 Matching in SDH mode

AIS concatenation indication Pointer value nnnn value and SS bits are the same as the AIS pointer

Invalid concatenation indication Any other concatenation indication other than normal CI or AIS CI

DIDI

01234567

DIDID

H1 H2

15 1314 10 9 812 11

N N N N S S I

3345 Pointer Interpretation StatesThe pointer interpreter algorithm for state transitions can be modeled as a finite state machine with three states as shown in the following illustration The three states are normal (NORM) loss of pointer (LOP) and alarm indication state (AIS)

Figure 15 bull Pointer Interpreter State Diagram

The conditions for transitions between these states are summarized in the following table

3346 Valid Pointer Definition for Interpreter State Diagram TransitionsDuring an AIS state only an AIS pointer is a valid pointer In NORM state several definitions of ldquovalid pointerrdquo for purpose of LOP detection are possible according to GR-253-CORE The VSC8490-17 device follows the GR-253-CORE intended definition but adds a single normal pointer that exactly matches the current valid pointer value

Any change in the AIS state is reflected in the alarm bit WIS_STAT3AISP This latch-high register reports both the event and status information in consecutive reads The EWIS_INTR_PEND1AISP_PEND bit remains asserted until read This event can propagate an interrupt to either WIS_INTA or WIS_INTB

Table 9 bull Pointer Interpreter State Diagram Transitions

Transitions States Description Required Persistencea NORM NORM

AIS NORM ltH1gtltH2gt=ltEEEESSPPgtltPPPPPPPPgt NDF enabled with pointer in range (0 to 782) SS bit match (if enabled)

1 frame

b NORM NORMLOP NORM AIS NORM

ltH1gtltH2gt=ltDDDDSSPPgtltPPPPPPPPgt NDF disabled (NORM pointer) with the same pointer value in range (0 to 782) SS bit match (if enabled)

3 frames

c NORM AIS LOP AIS

ltH1gtltH2gt=lt11111111gtlt11111111gt AIS pointer (0xFFFF)

3 frames

d NORM LOPAIS LOP

Anything other than transitions b and c or NDF enabled (transition a) or AIS pointer when not in AIS state or NORM pointer when not in NORM state or NORM pointer with pointer value not equal to current or incrementdecrement or CONC pointer or SS bit mismatch (if comparison is enabled)

8 frames

e Justification Valid increment or decrement indication 1 frame

a b e

NORM

LOP AIS

b

d

c

a b

based on mask enable bits EWIS_INTR_MASKA_1AISP_MASKA and EWIS_INTR_MASKB_1AISP_MASKB

Similarly any change in the LOP state is reflected in the alarm bit WIS_STAT3LOPP This latch-high register reports both the event and status information in consecutive reads The EWIS_INTR_PEND1LOPP_PEND bit remains asserted until read This event can propagate an interrupt to either WIS_INTA or WIS_INTB based upon the mask enable bits EWIS_INTR_MASKA_1LOPP_MASKA and EWIS_INTR_MASKB_1LOPP_MASKB

335 Path OverheadThe path overhead portion of the SONETSDH frame supports an end-to-end trace identifier a payload parity check a payload type indicator a status indicator and a user channel The following table lists each of the octets including their function

Note The VSC8490-17 device provides a mechanism to transmit a static value as programmed by the MDIO interface However by definition MDIO is not fast enough to alter the octet on a frame-by-frame basis Extended WIS TOSI and ROSI do not support path overhead

Table 10 bull STS Path Overhead Octets

Overhead Octet Function

IEEE 8023ae WIS Usage

J1 Path trace message Specified value For more information see Overhead Octet (J1) page 27

A 1- 16- or 64-byte trace message can be sent using registers (EWIS_TX_MSGLENJ1_TXLEN WIS_Tx_J1_Octets_1_0-WIS_Tx_J1_Octets_15_14 and EWIS_Tx_J1_Octets_17_16-EWIS_Tx_J1_Octets_63_62) and received using registers (EWIS_RX_MSGLENJ1_RX_LEN WIS_Rx_J1_Octets_1_0-WIS_Rx_J1_Octets_15_14 EWIS_Rx_J1_Octets_17_16-EWIS_Rx_J1_Octets_63_62)TOSI and ROSI access

B3 Path error monitoring (path BIP-8)

Both SONET and SDH mode B3 calculation is supported

C2 Path signal label Specified value 0x1A Register (EWIS_TX_C2_H1TX_C2)Supports persistency and mismatch detection (EWIS_MODE_CTRLC2_EXP)

G1 Path status Supported As specified in T1416

Ability to select between RDI-P and ERDI-P formats

F2 Path user channel Unsupported 0x00 Register (EWIS_TX_K2_F2TX_F2)

H4 Multiframe indicator Unsupported 0x00 Register (EWIS_TX_D6_H4TX_H4)

Z3-Z4 Reserved for path growth

Unsupported 0x00 Register (EWIS_TX_D9_Z3TX_Z3 EWIS_TX_D12_Z4TX_Z4)

N1 Tandem connection maintenance and path data channel

Unsupported 0x00 Register (EWIS_TX_N1TX_N1)TOSI and ROSI access

3351 Overhead Octet (J1)The J1 transmitted octet contains a 16-octet repeating path trace message whose contents are defined in WIS Tx J1s (WIS_Tx_J1_Octets_1_0-WIS_Tx_J1_Octets_15_14) If no active message is being broadcast a default path trace message is transmitted consisting of 15 octets of zeros and a header octet formatted according to Section 5 of ANSI T1269-2000 The header octet for the 15-octets of zero is 0x89 The default values of WIS Tx J1s do not contain the 0x89 value of the header octet thus software must write this value

By default the J1 octet in the receive direction is assumed to be carrying a 16-octet continuously repeating path trace message The message is extracted from the incoming WIS frames and presented in WIS Rx J1s (WIS_Rx_J1_Octets_1_0-WIS_Rx_J1_Octets_15_14) The WIS receive process does not delineate the message boundaries thus the message might appear rotated between new frame alignment events

When the transmit direction is configured for a 64-octet message the first 16 octets are programmed in WIS_Tx_J1_Octets_1_0-WIS_Tx_J1_Octets_15_14 while the 48 remaining octets are programmed in EWIS_Tx_J1_Octets_17_16-EWIS_Tx_J1_Octets_63_62 Likewise the first 16-octets of the receive message are stored in J1_RXMSG (WIS_Rx_J1_Octets_1_0-WIS_Rx_J1_Octets_15_14) while the other 48 octets are stored in EWIS_Rx_J1_Octets_17_16-EWIS_Rx_J1_Octets_63_62 The receive message is updated every 125 micros with the recently received octet Any persistence or message matching is expected to take place within the station manager

3352 STS Path Error Monitoring (B3)The B3 octet is a bit interleaved parity-8 (BIP-8) code using even parity calculated over the previous STS-192c SPE before scrambling The computed BIP-8 is placed in the B3 byte of the following frame before scrambling

In the receive direction the incoming frame is processed and a B3 octet is calculated over the received frame The calculated value is then compared with the B3 value received in the following frame The difference between the calculated and received octets are accumulated in block (maximum increment of 1 per errored frame) fashion into a B3 error register WIS_B3_CNT This counter is non-saturating and so rolls over The counter is cleared upon a device reset

An additional 32-bit B3 error counter is provided at B3_ERR_CNT (EWIS_B3_ERR_CNT1 and EWIS_B3_ERR_CNT0) a saturating counter that is latched and cleared based upon a PMTICK event Errors are accumulated starting from the previous PMTICK event When the counter is nonzero the EWIS_INTR_PEND2B3_NZ_PEND event register is asserted until read A non-latch high version of this event EWIS_INTR_STAT2B3_NZ_STAT is also available This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2B3_NZ_MASKA and EWIS_INTR_MASKB_2B3_NZ_MASKB

The B3_ERR_CNT may optionally be configured to increment on a block count basis a maximum increment of 1 per errored frame regardless of the number of errors received The EWIS_CNT_CFGB3_BLK_MODE control bit if asserted places the B3_ERR_CNT counter in block increment mode

It is possible that two sets of B3 bytes (from two SONETSDH frames) are received by the Rx WIS logic in a period of time when only one G1 octet is transmitted In this situation one of the two B3 error counts delivered to the Tx WIS logic is discarded This situation occurs when the receive data rate is faster than the transmit data rate Similarly when the transmit data rate is faster than the receive data rate a B3 error count is not available for REI-P insertion into the G1 octets of the transmitted SONETSDH frame A value of zero is transmitted in this case This behavior is achieved by using a FIFO to transfer the detected B3 error count from the receive to transmit domains

3353 STS Path Signal Label and Path Label Mismatch (C2)The C2 octet contains a value intended to describe the type of payload carried within the SONETSDH frame The WIS standard calls for a 0x1A to be transmitted This is the default value of EWIS_TX_C2_H1TX_C2

As specified in T1416 a path label mismatch (PLM-P) register WIS_STAT3PLMP event occurs when the C2 octet in five consecutive frames contain a value other than the expected one The expected value is set in EWIS_MODE_CTRLC2_EXP whose default value 0x1A is compliant with the WIS standard

When a value of 0x00 is accepted (received for five or more consecutive frames) the unequipped path pending (EWIS_INTR_PEND2UNEQP_PEND) event is asserted until read A non-latch high version of this event (EWIS_INTR_STAT2UNEQP_STAT) is also available This event can propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2UNEQP_MASKA and EWIS_INTR_MASKB_2UNEQP_MASKB

If the accepted value is not an unequipped label (0x00) and it differs from the programmed expected value EWIS_MODE_CTRLC2_EXP then a path label mismatch (WIS_STAT3PLMP) is asserted Similarly the EWIS_INTR_PEND1PLMP_PEND event is asserted until read This event can propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_1PLMP_MASKA and EWIS_INTR_MASKB_1PLMP_MASKB

Although PLMP is not a path level defect it does cause a change in the setting of one of the ERDI-P codes For more information see Table 13 page 29

3354 Remote Path Error Indication (G1)The most significant four bits of the G1 octet are used for back reporting the number of B3 block errors received at the near-end This is typically known as path remote error indication (REI-P) The value in this octet comes from the B3 error FIFO The WIS standard defines a 16-bit REI-P counter register WIS_REIP_CNT The WIS standard defines this counter to operate as a block counter as opposed to an individual errored bit counter This counter is non-saturating and so rolls over after its maximum count The counter does not clear upon a read but instead only upon reset as defined in the WIS specification When the counter is nonzero the EWIS_INTR_PEND2REIP_PEND event register is asserted until read A non-latch high version of this event EWIS_INTR_STAT2REIP_STAT is also available This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2REIP_MASKA and EWIS_INTR_MASKB_2REIP_MASKB respectively

An additional 32-bit REI-P counter is provided at REIP_ERR_CNT (EWIS_REIP_CNT1 and EWIS_REIP_CNT0) which is a saturating counter and is latched and cleared based upon a PMTICK event Errors are accumulated since the previous PMTICK event When the counter is nonzero the EWIS_INTR_PEND2REIP_NZ_PEND event register is asserted until read A non-latch high version of this event (EWIS_INTR_STAT2REIP_NZ_STAT) is also available This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2REIP_NZ_MASKA and EWIS_INTR_MASKB_2REIP_NZ_MASKB respectively

The REIP_ERR_CNT may optionally be configured to increment on a block count basis a maximum increment of 1 per errored frame regardless of the number of errors received This mode is enabled by asserting EWIS_CNT_CFGREIP_BLK_MODE

3355 Path Status (G1)In addition to back-reporting the far-end B3 BIP-8 error count the G1 octet carries status information from the far-end device known as path remote defect indicator (RDI-P) T1416 allows either support of 1-bit RDI-P or 3-bit ERDI-P but indicates ERDI-P is preferred The VSC8490-17 device supports both modes and may be independently configured for the Rx and Tx directions by configuring EWIS_MODE_CTRLRX_ERDI_MODE and EWIS_TXCTRL2ERDI_TX_MODE ERDI-P is the default for both directions

The following tables show the different structures for this octet

Enhanced RDI is defined for SONET-based systems as listed in GR-253-CORE (Issue 3) reproduced here in the following table and as a possible enhancement of SDH-based systems (G707Y1322 (102000) Appendix VII (not an integral part of that recommendation))

In the receive direction with EWIS_MODE_CTRLRX_ERDI_MODE = 0 an RDI-P defect is the occurrence of the RDI-P signal in ten contiguous frames An RDI-P defect terminates when no RDI-P signal is detected in ten contiguous frames An RDI-P event asserts EWIS_INTR_PEND2FERDIP_PEND until read A non-latch high version of the far-end RDI-P status can be found in EWIS_INTR_STAT2FERDIP_STAT This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2FERDIP_MASKA and EWIS_INTR_MASKB_2FERDIP_MASKB

When EWIS_MODE_CTRLRX_ERDI_MODE = 1 an ERDI-P defect is the occurrence of any one of three ERDI-P signals in ten contiguous frames An ERDI-P defect terminates when no ERDI-P signal is detected in ten contiguous frames

Table 11 bull Path Status (G1) Byte for RDI-P Mode

G1 REI (B3) RDI-P Reserved Spare1 2 3 4 5 6 7 8

Remote Error Indicator count from B3 (0ndash8 value)

Remote Defect indicator

Set to 00 by transmitter

Ignored by receiver

Table 12 bull Path Status (G1) Byte for ERDI-P Mode

G1 REI (B3) ERDI-P Spare1 2 3 4 5 6 7 8

Enhanced Remote Defect Indicator (see following table)

Ignored by receiver

Table 13 bull RDI-P and ERDI-P Bit Settings and Interpretation

G1 Bits 5 6 and 7Priority of ERDI-P Codes Trigger Interpretation

000011 Not applicable No defects No RDI-P defect

100111 Not applicable Path alarm indication signal (AIS-P) The remote device sends all ones for H1 H2 H3 and the entire STS SPEPath loss of pointer (LOP-P)

One-bit RDI-P defect

001 4 No defects No ERDI-P defect

010 3 Path label mismatch (PLM-P) Path loss of code group delineation (LCD-P)

ERDI-P payload defect

101 1 Path alarm indication signal (AIS-P) The remote device sends all ones for H1 H2 H3 and entire STS SPEPath loss of pointer (LOP-P)

ERDI-P server defect

110 2 Path unequipped (UNEQ-P) The received C2 byte is 0x00Path trace identifier mismatch (TIM-P) This error is not automatically generated but can be forced using MDIO

ERDI-P connectivity defect

The 010 code triggers the latch high register bit WIS_STAT3FEPLMP_LCDP It also asserts EWIS_INTR_PEND1FEPLMP_LCDP_PEND until read This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_1FEPLMP_LCDP_MASKA and EWIS_INTR_MASKB_1FEPLMP_LCDP_MASKB respectively

The 101 code triggers the latch high register bit WIS_STAT3FEAISP_LOPP It also asserts EWIS_INTR_PEND1FEAISP_LOPP_PEND until read This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_1FEAISP_LOPP_MASKA and EWIS_INTR_MASKB_1FEAISP_LOPP_MASKB respectively

The 110 code asserts the EWIS_INTR_PEND2FEUNEQP_PEND until read A non-latch-high version of this register (EWIS_INTR_STAT2FEUNEQP_STAT) is also available This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2FERDIP_MASKA and EWIS_INTR_MASKB_2FERDIP_MASKB respectively

3356 Path User Channel (F2)The WIS standard does not support the F2 octet and recommends transmitting 0x00 in place of the F2 octet A value other than 0x00 may be transmitted by programming the intended value at EWIS_TX_K2_F2TX_F2

3357 Multi-frame Indicator (H4)The WIS standard does not support the H4 multi-frame octet and recommends transmitting 0x00 in place of the H4 octet A value other than 0x00 may be transmitted by programming the intended value at EWIS_TX_D6_H4TX_H4

3358 Reserved for Path Growth (Z3-Z4)The WIS standard does not support the Z3-Z4 octets and recommends transmitting 0x00 in their place A value other than 0x00 may be transmitted by programming the intended value at EWIS_TX_D9_Z3TX_Z3 and EWIS_TX_D12_Z4TX_Z4 respectively

3359 Tandem Connection MaintenancePath Data Channel (N1)The WIS standard does not support the N1 octet and recommends transmitting 0x00 in place of the N1 octet A value other than 0x00 may be transmitted by programming the intended value at EWIS_TX_N1TX_N1

33510 Loss of Code Group DelineationAfter the overhead is stripped the payload is passed to the PCS If the PCS block loses synchronization and cannot delineate valid code groups the PCS passes a loss of code group delineation (LCD-P) alarm to the WIS This alarm triggers the latch high register bit WIS_STAT3LCDP It also asserts EWIS_INTR_PEND1LCDP_PEND until read This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_1LCDP_MASKA and EWIS_INTR_MASKB_1LCDP_MASKB respectively

The WIS specification calls for a LCD-P defect persisting continuously for more than 3 ms to be back reported to the far-end Upon device reset a LCD-P is back reported until the PCS signals that valid code groups are being delineated The LCD-P defect deasserts (and is not back reported) after the condition is absent continuously for at least 1 ms

33511 Reading Statistical CountersThe VSC8490-17 device contains several counters that may be read using the MDIO interface For each error count there are two sets of counters The first set is the standard WIS counter implemented according to IEEE 8023ae and the second set is for statistical counts using PMTICK

To read the IEEE 8023ae counters the station manager must read the most significant register of the 32-bit counter first This read action latches the internal error counter value into the MDIO readable registers A subsequent read of the least significant register does not latch new values but returns the value latched at the time of the most significant register read

It may be difficult to get a clear picture of the timeframes in which errors were received because the IEEE 8023ae counters are independently latched The PMTICK counters are all latched together thereby providing a complete snapshot in time When PMTICK is asserted the internal error counter values are copied into their associated registers and the internal counters are reset

There are three methods of asserting PMTICK

bull The station manager may asynchronously assert EWIS_PMTICK_CTRLPMTICK_FRC to latch the values at a given time regardless of the EWIS_PMTICK_CTRLPMTICK_ENA setting

bull The VSC8490-17 device may be configured to latch and clear the statistical counters at a periodic interval as determined by the timer (count) value in EWIS_PMTICK_CTRLPMTICK_DUR In this mode the EWIS_PMTICK_CTRLPMTICK_SRC must be configured for internal mode and the EWIS_PMTICK_CTRLPMTICK_ENA bit must be asserted The receive path clock is used to drive the PMTICK counter thus the periodicity of the timer can vary during times of loss of lock and loss of frame

bull The VSC8490-17 device may be configured to latch and clear the statistical counters at the occurrence of a rising edge detected at a GPIO pin configured as a PMTICK input pin In this mode the EWIS_PMTICK_CTRLPMTICK_SRC bit must be deasserted and the EWIS_PMTICK_CTRLPMTICK_ENA must be asserted Corresponding GPIO must be configured as the PMTICK input pin

Regardless of EWIS_PMTICK_CTRLPMTICK_SRC when the PMTICK event occurs the EWIS_INTR_PEND2PMTICK_PEND is asserted until read This event may propagate an interrupt to either WIS_INTA or WIS_INTB based on the mask enable bits EWIS_INTR_MASKA_2PMTICK_MASKA and EWIS_INTR_MASKB_2PMTICK_MASKB respectively

Given the size of the error counters and the maximum allowable error counts per frame care must be taken in the frequency of polling the registers to ensure accurate values All PMTICK counters saturate at their maximum values

Both individual and block mode accumulation of B1 B2 and B3 error indications are supported and selectable using the control bits EWIS_CNT_CFGB1_BLK_MODE EWIS_CNT_CFGB2_BLK_MODE and EWIS_CNT_CFGB3_BLK_MODE In individual accumulation mode 0 the counter is incremented for each bit mismatch between the calculated B1 B2 andor B3 error and the extracted B1 B2 andor B3 In block accumulation mode 1 the counter is incremented only once for any nonzero number of bit mismatches between the calculated B1 B2 andor B3 and the extracted B1 B2 andor B3 (maximum of one error per frame)

Table 14 bull PMTICK Counters

Counter Name Description Registers

Maximum Increase Count Per Frame

Maximum Increase Count Per Second

Time Until Overflow

B1_ERR_CNT B1 section error count EWIS_B1_ERR_CNT1 EWIS_B1_ERR_CNT0

8 64000 67109

B2_ERR_CNT B2 line error count EWIS_B2_ERR_CNT1EWIS_B2_ERR_CNT0

1536 12288000 350

B3_ERR_CNT B3 path error count EWIS_B3_ERR_CNT1EWIS_B3_ERR_CNT0

8 64000 67109

EWIS_REIP_CNT Far-end B3 path error count EWIS_REIP_CNT1 EWIS_REIP_CNT0

8 64000 67109

EWIS_REIL_CNT Far-end B2 line error count EWIS_REIL_CNT1 EWIS_REIL_CNT0

1536 12288000 350

336 Defects and AnomaliesAll defects and anomalies listed in the following table can be forced and masked by the user The VSC8490-17 device does not automatically generate TIM-P but does support forcing defects using MDIO

Table 15 bull Defects and Anomalies

Defect or Anomaly Description Type Force Bit Status BitFar-end PLM-P or LCD-P

These two errors are indistinguishable when reported by the far-end through the G1 octet (ERDI-P) because the far-end reports both PLM-P and LCD-P with the same error code

Far-end defect EWIS_RX_ERR_FRC2FRC_RX_FE_PLMP

WIS_STAT3FEPLMP_LCDP

Far-end AIS-P or LOP-P

These two errors are indistinguishable when reported by the far-end through the G1 octet (ERDI-P) because the far-end reports both AIS-P and LOP-P with the same error code

Far-end defect EWIS_RX_ERR_FRC2FRC_RX_FE_AISP

WIS_STAT3FEAISP_LOPP

PLM-P Path label mismatch The detection and reporting of the PLM-P defect follows section 75 of ANSI T1416-1999

Near-end defect propagated to PCS

EWIS_RX_ERR_FRC2FRC_RX_PLMP

WIS_STAT3PLMP

AIS-L Generated on LOPC LOS LOF if enabled by EWIS_RXTX_CTRLRXAISL_ON_LOPC EWIS_RXTX_CTRLRXAISL_ON_LOS EWIS_RXTX_CTRLRXAISL_ON_LOF or when forced by user

Near-end defect The AIS-L defect is only processed and reported by the WIS Receive process it is never transmitted by the WIS Transmit process according to IEEE 8023ae

EWIS_RX_ERR_FRC1FRC_RX_AISLWIS_STAT3AISL

AIS-P Path alarm indication signal Near-end defect propagated to PCS

EWIS_RX_ERR_FRC1FRC_RX_AISP

WIS_STAT3AISP

LOP-P Path loss of pointer Nine consecutive invalid pointers result in loss of pointer detection See Figure 15 page 25 for the pointer interpreter state machine

EWIS_RX_ERR_FRC1FRC_RX_LOP

WIS_STAT3LOPP

LCD-P Path loss of code group delineation See Table 13 page 29 This is also reported to the far-end if it persists for at least 3 ms

Near-end defect EWIS_RX_ERR_FRC2FRC_LCDP

WIS_STAT3LCDP

LOPC Loss of optical carrier alarm This is an input from the XFP modulersquos loss of signal output The polarity can be inverted for use with other module types This defect can be used independently or in place of LOS

Near-end defect EWIS_RX_ERR_FRC1FRC_LOPC

EWIS_INTR_STAT2LOPC_STAT

337 Interrupt Pins and Interrupt MaskingThe VSC8490-17 device generates interrupts for each defect and anomaly The interrupts for the BIP error counts (B1 B2 and B3 counters) and the interrupts for the far-end error counts (REI-L and REI-P)

LOS The PMA circuitry detects a loss of signal (LOS) defect if the input signal falls below the assert threshold When a PMA LOS is declared the framer is held in reset to prevent it from looking for a frame boundary

Near-end defect EWIS_RX_ERR_FRC1FRC_LOS

WIS_STAT3LOS

SEF Severely errored frame Generated when device cannot frame to A1 A2 pattern SEF indicates synchronization process is not in the SYNC state as defined by the state diagram of IEEE 8023ae clause 5042

EWIS_RX_ERR_FRC2FRC_RX_SEF

WIS_STAT3SEF

LOF Generated when SEF persists for 3 ms Terminated when no SEF occurs for 1 ms to 3 ms

Near-end defect EWIS_RX_ERR_FRC2FRC_RX_LOF

WIS_STAT3LOF

B1 PMTICK error count is nonzero

BIP-N(S) - 32-bit near-end section BIP error counter is nonzero

Near-end anomaly

EWIS_RX_ERR_FRC2FRC_RX_B1

EWIS_INTR_STAT2B1_NZ_STAT

BIP-N(L) - 32-bit near-end line BIP error counter is nonzero

Near-end anomaly

BIP-N(P) - 32-bit near-end path BIP error counter is nonzero

Near-end anomaly

REI-L Line remote error indicator octet is nonzero Far-end BIP-N(L)

Far-end anomaly

EWIS_RX_ERR_FRC2FRC_RX_REIL

EWIS_INTR_STAT2REIL_STAT

REI-L PMTICK error count is nonzero

Line remote error indicator is nonzero Far-end BIP-N(L)

Far-end anomaly

EWIS_RX_ERR_FRC2FRC_REIL

EWIS_INTR_STAT2REIL_NZ_STAT

RDI-L Line remote defect indicator Far-end defect EWIS_RX_ERR_FRC1FRC_RX_RDIL

WIS_STAT3RDIL

REI-P Path remote error indicator octet is nonzero Far-end BIP-N(P)

Far-end anomaly

EWIS_RX_ERR_FRC2FRC_RX_REIP

EWIS_INTR_STAT2REIP_STAT

REI-P PMTICK error count is nonzero

Path remote error indicator Far-end BIP-N(P) Far-end anomaly

EWIS_RX_ERR_FRC2FRC_REIP

EWIS_INTR_STAT2REIP_NZ_STAT

UNEQ-P Unequipped path Near-end defect EWIS_RX_ERR_FRC2FRC_RX_UNEQP

EWIS_INTR_STAT2UNEQP_STAT

Far-end UNEQ-P

Far-end unequipped path Far-end defect EWIS_RX_ERR_FRC2FRC_RX_FE_UNEQP

EWIS_INTR_STAT2FEUNEQP_STAT

Table 15 bull Defects and Anomalies (continued)

Defect or Anomaly Description Type Force Bit Status Bit

are generated when the PMTICK counters become nonzero Mask enable bits propagate the interrupt pending event to GPIO pins configured as WIS_INTA and WIS_INTB Each event may be optionally masked for each WIS_INTAB pin

The WIS_INTA and WIS_INTB signals are routed off-chip through GPIO pins Many specialized functions share the GPIO pins The WIS_INTA and WIS_INTB signals do not go to dedicated pins

For each defect or anomaly defined in IEEE 8023ae the VSC8490-17 device supports the standard WIS register In addition the VSC8490-17 device supports another set of registers in the WIS Vendor Specific area These registers provide a STATUS bit to indicate the current real-time status of the event a PENDING bit to indicate if the STATUS bit has changed state and two mask enable bits for each interrupt pin (WIS_INTA and WIS_INTB) The STATUS bit is set if and only if the interrupt currently exists This STATUS bit does not latch

The defects and anomalies are constructed in a hierarchy such that lower order alarms are squelched when higher order events are detected For more information about the dependencies between squelches and events see the WIS interrupt registers

338 Overhead Serial InterfacesThe VSC8490-17 device includes provisions for off-chip processing of the critical SONETSDH transport overhead 9-bit words through two independent serial interfaces The transmit overhead serial interface (TOSI) is used to insert 9-bit words into the transmit frames and the receive overhead serial interface (ROSI) is used to recover the 9-bit words from the received frames Each interface consists of three pins a clock output a frame pulse output and a data input (Tx) output (Rx) These IO are LVTTL compatible for easy connection to an external device such as an FPGA

Note Extended WIS TOSI and ROSI do not support path overhead bytes

The TOSI ROSI signals are routed off-chip through GPIO pins If the ROSITOSI interfaces are to be used there are no GPIO pins left in the design for any other functionmdashloss-of-lock for Sync-E applications activity LED drivers WIS_interrupts or two-wire serial (slave) interface

All references to TCLKOUT TFPOUT TDAIN RCLKOUT RFPOUT and RDAOUT are the TOSIROSI signals routed through GPIO pins

3381 Transmit Overhead Serial Interface (TOSI)The TOSI port enables the user to individually program 222 separate 9-bit words in the SONETSDH overhead The SONETSDH frame rate is 8 kHz as signaled by the frame pulse (TFPOUT) signal The TOSI port is clocked from a divided-down version of the WIS transmit clock made available on TCLKOUT To provide a more standard clock rate 9-bit dummy words are added per frame resulting in a clock running at one five-hundred-twelfth of the line rate (or 1944 MHz) For each 9-bit word the external device indicates the desire to transmit that byte by using an enable indicator bit (EIB) that is appended to the beginning of the 9-bit word If EIB = 0 the data on the serial interface is ignored for that overhead 9-bit word If EIB = 1 the serial interface data takes precedence over the value generated within the VSC8490-17 device The EIB is present before the 9-bit dummy words too however its value has no effect as the 9-bit dummy words are ignored within the device The first EIB bit should be transmitted by the external device on the first rising edge of TCLKOUT after TFPOUT as shown in the following illustration The data should be provided with the most significant bit (MSB) first After reception of the TOSI data for a complete frame the values are placed in the overhead for the next transmitted frame

Figure 16 bull TOSI Timing Diagram

Some 9-bit words are error masks such that the transmitted 9-bit word is the XOR of the TOSI 9-bit word and the pre-defined value within the chip if the EIB is enabled This feature is best used for test purposes only

The order of the 9-bit word required by the TOSI port is summarized in the following table where the number of registers is the number of bytes on the serial interface and the number of bytes is the number of STS channels on which the byte is transmitted For H1 and H2 pointers bytes 2 to 192 are concatenation indication bytes consistent with STS-192c frames There are not 192 different point locations as in STS-192 frames

Table 16 bull TOSIROSI Addresses

Byte Name9-Bit Word

TOSIROSI Byte Order

Number of Registers

Number of Bytes Type

Frame boundary A1 0 1 192 Programmable byte that is identical for all locations

Section trace J0 2 1 1 Programmable byte

Section growth Z0 3 1 191 Programmable byte that is identical for all locations

Dummy byte 4 1 1 Programmable byte

Section BIP-8 B1 5 1 1 TOSI inserts error mask ROSI extracts XOR of B1 value and received data

Orderwire E1 6 1 1 Programmable byte

Section user channel F1 7 1 1 Programmable byte

Dummy byte 8 1 1 Programmable bytes

Section DCC 1 D1 9 1 1 Programmable byte

Pointer 1 H1 13 1 1 Programmable byte affecting the first H1 byte

Padding Dummy Bits

A1EIB

A1Bit 1

A1Bit 2

A1Bit 3TDAIN

TFPOUT

TCLKOUT

Pointer action H3 15 1 192 Programmable byte that is identical for all locations

Line BIP-8 B2 17 to 208 192 192 TOSI inserts error mask for each byte ROSI extracts XOR of B2 value and received data for each byte

Automatic protection switching (APS) channel and remote defect indicator (RDI)

K1 209 1 1 Programmable byte

Line DCC 4 D4 212 1 1 Programmable byte

Synchronization message

S1 224 1 1 Programmable byte

Growth 1 Z1 225 1 191 Programmable byte that is identical for all locations

Growth 2 Z2 226 1 190191 Programmable byte that is identical for all locations dependent upon 2xEC4012

STS-1 REI-L M0 227 1 1 Programmable byte

STS-N REI-L M1 228 1 1 Programmable byte

Orderwire 2 E2 229 1 1 Programmable byte

Table 16 bull TOSIROSI Addresses (continued)

Byte Name9-Bit Word

TOSIROSI Byte Order

Number of Registers

3382 Receive Overhead Serial Interface (ROSI)The ROSI port extracts the same 222 overhead 9-bit words from the SONETSDH frame and consists of the clock output (RCLKOUT) frame pulse output (RFPOUT) and data output (RDAOUT) The ROSI port is clocked from a divided-down version of the WIS receive clock and is valid during in-frame conditions only As with the TOSI port 9-bit dummy words are provided each frame period resulting in a 1944 MHz RCLKOUT frequency For each 9-bit word including the 9-bit dummy words an extra 0 bit is added at the beginning of each byte so that the TOSI and ROSI clock rates are identical The first stuff bit for each frame is transmitted by RDAOUT on the first rising edge of RCLKOUT after the frame pulse (RFPOUT) as shown in the following illustration

Because the receive path overhead can be split across two frames the VSC8490-17 device buffers the overhead for an additional frame time so that a complete path overhead is presented Table 16 page 35 outlines the order for each of the 9-bit words presented on the ROSI port With the exception of the M0M1 9-bit words the extracted 9-bit words are from the first channel position In place of parity and error 9-bit words the VSC8490-17 device outputs the result of an XOR between the calculated BIP and the received value Therefore a count of ones within each of the BIP 9-bit words should correspond with the internal error accumulators The following illustration shows the functional timing for the ROSI port

Figure 17 bull ROSI Timing Diagram

339 Pattern Generator and CheckerThe VSC8490-17 device implements the square wave PRBS31 and mixed-frequency test patterns as described in section 5038 of IEEE 8023ae as well as the test signal structure (TSS) and continuous identical digits (CID) pattern

The square wave pattern is selected asserting WIS_CTRL2TEST_PAT_SEL and the generator is enabled by asserting WIS_CTRL2TEST_PAT_GEN When WIS_CTRL2TEST_PAT_SEL is deasserted the mixed frequency test pattern is selected The square wave frequency is configured according to EWIS_TXCTRL2SQ_WV_PW The WIS_CTRL2TEST_PAT_ANA bit is used to enable the test pattern checker in the receive path The checker does not operate on square wave receive traffic Error counts from the mixed frequency pattern are presented in the SONETSDH BIP-8 counters B1_CNT WIS_B1_CNT WIS_B2_CNT and WIS_B3_CNT

The VSC8490-17 device supports the PRBS31 test pattern as reflected in WIS_STAT2PRBS31_ABILITY The transmittergenerator is enabled by asserting

Padding dummy bytes 231 to 269

39 No function

Byte Name9-Bit Word

TOSIROSI Byte Order

Number of Registers

RCLKOUT

RFPOUT

RDAOUTPadding

Dummy Bitslsquo0rsquo

StuffA1

Bit 1A1

Bit 2A1

Bit 3

WIS_CTRL2TEST_PRBS31_GEN while the receiverchecker is enabled by asserting WIS_CTRL2TEST_PRBS31_ANA Because the mixed frequencysquare wave test patterns have priority over the PRBS31 pattern WIS_CTRL2TEST_PAT_GEN must be disabled for the PRBS31 test pattern to be sent Error counts from the PRBS31 checker are available in WIS_TSTPAT_CNT This register does not roll over after reaching its maximum count and is cleared after every read operation Two status bits are available from the PRBS checker The EWIS_PRBS31_ANA_STATPRBS31_ERR bit indicates whether the error counter is nonzero The EWIS_PRBS31_ANA_STATPRBS31_ANA_STATE bit if asserted indicates that checker is synchronized and actively checking received bits For test purposes the PRBS generator can inject single bit errors By asserting EWIS_PMTICK_CTRLPMTICK_SRC a single bit error is injected resulting in three bit errors being detected within the checker The value of three comes from the specification which indicates one error should be detected for each tap within the checker

34 10G Physical Coding Sublayer (64B66B PCS)The 10G physical coding sublayer (PCS) is defined in IEEE 8023ae Clause 49 It is composed of the PCS transmit PCS receive block synchronization and BER monitor processes The PCS functions can be further broken down into encode or decode scramble or descramble and gearbox functions as well as various test and loopback modes

The PCS is responsible for transferring data between the XAUI clock domain and the WISPMA clock domain In addition the PCS encodes and scrambles the data for efficient transport across the given medium

The following illustration provides a block diagram of the 10G PCS block

Figure 18 bull PCS Block Diagram

341 Control CodesThe VSC8490-17 device supports the use of all control codes and ordered sets necessary for 10 GbE and 10 GFC operation The following table lists the control characters notation and control codes

Table 17 bull Control Codes

Control CodesControl Character Notation1

XGMII Control Code

10-G BASE-R Control Code

10-G BASE-R O Code

8b10b Code2 Idle I 0x07 0x00

K280 or K283 or K285 Start S 0xfb

Buffer 64LAN 64b66b Encoder and Scrambler

66 6664 Gear Box66 64

Buffer 64LAN 64b66b Decoder and Descrambler

66 6664 Gear Box 64

Tx PCS and EPCS

Rx PCS and EPCS

MAC

158

8XG

XS

WIS

PM

A

342 Transmit PathIn the transmit direction the PCS accepts data from the XGXS interface which runs off the XAUI recovered clock and transfers the data onto the PMA transmit clock domain through the rate-disparity compensating FIFO Based on the FIFOrsquos fill level idle characters are added or removed as needed

Once in the PMA clock domain the de-serialized XAUI input data (64-bit) is checked for validity Transmitted data is handled according to IEEE 8023ae Clause 49

The characters are then processed in a two-step manner First the 64 bits are encoded and a 2-bit header is calculated to form a single 66-bit block The two header bits are used for block delineation and classification The only valid header codes are 01 to indicate a payload of all data octets and 10 to indicate the presence of one or more control characters within the payload To maintain a DC balanced signal on the serial line the 64-bit encoded payload is scrambled using a self-synchronizing scrambler that implements the polynomial G(x) = 1 + x39 + x58 The header bits are not scrambled as they are already DC balanced For debug purposes the scrambler can be disabled by deasserting SCR_DIS (3x80059)

The 66-bit blocks are then passed to the PMA through a 6664 gearbox The gearbox merely feeds the 66-bit data into the WISPMArsquos 64-bit data path

343 Receive PathIn the receive direction the PCS accepts data from the WISPMA block and reformats it for transmission to the XGXS interface Because of the data path width mismatches between the WISPMA and the PCS a 6466 gearbox is needed The gearbox also performs block synchronizationalignment based upon the 2-bit synchronization header When the receive logic receives 64 continuous valid sync headers the BLOCK_LOCK (3x002115) bit is asserted This bit is a latch-low bit therefore a second read of the bit returns the current status If 16 invalid block sync headers are detected within a 125 micros period the

Encoded by block type field

K277 Terminate T 0xfd

K297 Error E 0xfe

0x1e K307 Sequence ordered_set

Q 0x9c

Encoded by block type field plus O code

0x0 K284 Reserved 0 R 0x1c

0x2d K280 Reserved 1 0x3c

0x33 K281 Reserved 2 A 0x7c

0x4b K283 Reserved 3 K 0xbc

0x55 K285 Reserved 4 0xdc

0x66 K286 Reserved 5 0xf7

0x78 K237 Signal ordered_set3

Fsig 0x5c

0xF K282

1 The codes for A K and R are used on the XAUI interface to signal idle2 For information only The 8b10b code is specified in Clause 36 Usage of the 8b10b code for 10 Gbps operation

is specified in Clause 43 Reserved for INCITS T11 - 10 GFC micros

Table 17 bull Control Codes (continued)

Control Codes (continued)

Control Character Notation1

XGMII Control Code

10-G BASE-R O Code

PCS_HIGHBER (3x002114) bit is asserted This bit is a latch-high bit and therefore a second read of the bit returns the current status

Once block synchronization is achieved the occurrence of errored blocks are accumulated in the PCS_ERRORED_BLOCKS (3x002170) counter An errored block is one that has one or more of the following defects

bull The sync field has a value of 00 or 11bull The block type field contains a reserved value (for more information see Table 17 page 38)bull Any control character contains an incorrect value bull Any O code contains an incorrect value bull The set of eight XGMII characters does not have a corresponding block format shown in the

following illustrationFigure 19 bull 64B66B Block Formats

Valid blocks recover their original payload data by being descrambled The descrambler is the same polynomial used by the transmitter For test purposes the descrambler may be disabled by asserting DSCR_DIS (3x800510) The data is checked for valid characters and sequencing

The data is passed from the PMAWIS clock domain to the XAUI clock domain through a FIFO Based upon the FIFOrsquos fill level idle characters are added or removed as needed

344 PCS Standard Test ModesThe PCS block offers all of the standard defined test pattern generators and analyzers In addition the VSC8490-17 device supports a 64-bit static user pattern and the optional PRBS31 pattern Two error counters are available Each is a saturating counter that is cleared upon a read operation The first PCS_ERR_CNT is located in the IEEE Standard area while the 32-bit PCS_VSERR_CNT_0PCS_VSERR_CNT_1 is located in the vendor specific area

The IEEE specification defines two test pattern modes a square wave generator and a pseudo-random test pattern The square wave generator is enabled by first selecting the square wave pattern by asserting PCS_TSTPAT_SEL and then enabling the test pattern generator PCS_TSTPAT_GEN The period of the square wave can be controlled in terms of bit times by writing to PCS_SQPW There is no associated square wave checker within the VSC8490-17 device

The pseudo-random test pattern is selected by deasserting PCS_TSTPAT_SEL The pseudo-random test pattern contains two data modes When PCS_TSTDAT_SEL is deasserted the pseudo-random

Input Data Sync Block Payload

Bit Position

Data Block Format

0 1 2 65

D0 D1 D2 D3D4 D5 D6 D7

Control Block Formats

C0 C1 C2 C3C4 C5 C6 C7

C0 C1 C2 C3O4 D5 D6 D7

C0 C1 C2 C3S4 D5 D6 D7

O0 D1 D2 D3D4 D5 D6 D7

O0 D1 D2 D3O4 D5 D6 D7

S0 D1 D2 D3D4 D5 D6 D7

O0 D1 D2 D3C4 C5 C6 C7

T0 C1 C2 C3C4 C5 C6 C7

D0 T1 C2 C3C4 C5 C6 C7

D0 D1 T2 C3C4 C5 C6 C7

D0 D1 D2 T3C4 C5 C6 C7

D0 D1 D2 D3T4 C5 C6 C7

D0 D1 D2 D3D4 T5 C6 C7

D0 D1 D2 D3D4 D5 T6 C7

D0 D1 D2 D3D4 D5 D6 T7

01

10

D0 D1 D2 D3 D4 D5 D6 D7

BlockTypeField

0x1e

0x2d

0x33

0x66

0x55

0x78

0x4b

0x87

0x99

0xaa

0xb4

0xcc

0xd2

0xe1

0xff

C0

D1

D0

C6

C3

C4 C5 C6C1 C2

C1

D2

C2

D1

C2

D3

D2

C3

O0

D4

O0

D3

O4

C4

D5

C5

D4

D6

C6

D5

C7

D7

C7

D6

pattern is a revolving series of four blocks with each block 128-bits in length The four blocks are the resultant bit sequence produced by the PCS scrambler when pre-loaded with the following seeds

bull PCS_SEEDA_0 PCS_SEEDA_1 PCS_SEEDA_2 PCS_SEEDA_3bull PCS_SEEDA invertbull PCS_SEEDB_0 PCS_SEEDB_1 PCS_SEEDB_2 PCS_SEEDB_3bull PCS_SEEDB invertThe pattern generator is enabled by asserting PCS_TSTPAT_GEN while the analyzer is enabled by asserting PCS_TSTPAT_ANA Errors are accumulated in the clear-on-read saturating counter PCS_ERR_CNT In pseudo-random pattern mode the error counter counts the number of errored blocks

Support for the optional PRBS31 pattern is indicated by PRBS31_pattern_testing_ability register whose default is high The PRBS31 test generator is selected by asserting PCS_PRBS31_GEN while the checker is enabled by asserting PCS_PRBS31_ENA IEEE standards specify that the error counter should increment for each linear feedback shift register (LFSR) tap that a bit is in error Therefore a single bit error increments the counter by three because there are three taps in the PRBS31 polynomial

The user-defined 64-bit static pattern can be written to PCS_USRPAT registers and enabled by asserting PCS_USRPAT_ENA and PCS_TSTPAT_GEN Enabling the user-defined pattern enables both the generator and analyzer

35 1G Physical Coding SublayerThe 1G physical coding sublayer (PCS) implements 1000BASE-X as specified by IEEE 8023 Clause 36 and auto-negotiation as specified by IEEE 8023 Clause 37 It provides for the encoding (and decoding) of GMII data octets to (and from) ten-bit code-groups (8B10B) for communication with the underlying PMA It also manages link control and the auto-negotiation process

In addition to these standard 1000BASE-X functions the 1G PCS also includes a conversion function that maps the standard GMII data to (and from) an internal XGMII-like interface This allows the processing core to be largely agnostic to whether a channel is operating in 1G or 10G operation

36 IEEE 1588 Block OperationThe VSC8490-17 device uses a second generation IEEE 1588 engine that is backward compatible with the earlier version of VeriTimetrade (the Microsemi IEEE 1588 time stamping engine) both stand alone and in combination with MACsec) It is also compatible with the IEEE 1588 operations supported in Microsemi CE switches The following list shows the new features of the Microsemi second generation IEEE 1588

bull MACsec supportbull Higher time stamp accuracy and resolutionbull Automatic clear enables after system time is read or writtenbull Ability to load or extract the current system time in serial formatbull Full 48-bit math support for incoming correction fieldbull Ability to add or subtract fixed offset from system time to synchronize between slavesbull Independent control and bypass for each direction of IEEE 1588bull Support to extract frame signature in an IPv6 framebull MPLS-TP OAM support in third analyzer engine bull Special mode where all frames traversing the system can be time stampedThe unique architecture of the MACsec and the second generation IEEE 1588 block combination provides for the lowest latency and maximum throughput on the channel The following illustration shows a block diagram of the IEEE 1588 architecture in the VSC8490-17 device

Figure 20 bull IEEE 1588 Architecture

The following sections list some of the major IEEE 1588 applications

361 IEEE 1588 BlockThe IEEE 1588 engine may be configured to support one-step and two-step clocks as well as Ethernet and MPLS OAM delay measurement It detects the IEEE 1588 frames in both the Rx and Tx paths creates a time stamp processes the frame and updates them It can add a 3032-bit Rx time stamp to the 4-bytes reserved field of the PTP packet It can also modify the IEEE 1588 correction field and update the CRC of changed frames There are local time counters (reference for all time stamps) that can be preloaded and adjusted though the register interface

A local time counter is used to hold the local time for Rx and Tx paths A small FIFO delays frames to allow time for processing and modification An analyzer detects the time stamp frames (PTP and OAM) and a time stamp block calculates the new correction field The rewriter block replaces the correction field with an updated one and checkscalculates the CRC For the Tx path a time stamp FIFO saves Tx event time stamp plus frame identifier for use in some modes

The IEEE 1588 enginersquos registers and time stamps are accessible through the MDIO or 4-pin SPI To overcome the MDIO or 4-pin SPI speed limitations the dedicated ldquopush-outrdquo style SPI output bus can be used for faster or large amounts of time stamp reads This SPI output is used to push out time stamp information to an external device only and does not provide readwrite to the registers of the IEEE 1588 engine or registers of other blocks in the VSC8490-17 device In addition there is a LOADSAVE pin that

LTC0

deconstructor

constructor

tsprewriter

delay fifo

Engine0

Engine1

Engine2

analyzer

Proc0

registers

Proc1 config

EgressProcessor 0

constructor

deconstructor

tsprewriter

delay fifo

Engine0

Engine1

Engine2

analyzer

IngressProcessor 0

EgressProcessor1

IngressProcessor1

Time stamp

LTC1

1588 instance

PHY 0 PHY 1

MAC 0 MAC 1

1588 instance

is used to load the time in the PHYs and to ensure that all the PHYs are in sync The local time counter may come from any one of the following sources

bull Data path clock (varies according to mode)bull 250 MHz from host-side PLLbull External clock (125 MHz or 250 MHz) from CLK1588PN pinsThe local time counters contain two counters nanosecond_counter and second_counter The 1 PPS (pulse per second signal) output pin can be used for skew monitoring and adjustment The following illustration shows an overview of a typical system using IEEE 1588 PHYs The LOADSAVE and 1 PPS pins are signals routed to the GPIO pins The following illustration shows how the PHY is embedded in a system

Figure 21 bull IEEE 1588 Block Diagram

The system card has to drive the REFCLK (125 MHz or 250 MHz timetick clock) to all the PHYs including the VSC8490-17 device The system clock may need local frequency conversion to match the required reference clock frequency The system clock may be locked to a PRC by SyncE or by IEEE 1588 If locked by IEEE 1588 the central CPU recovers the PTP timing and adjusts the frequency of the system clock to match the PTP frequency If the system clock is free running the central CPU must calculate the frequency offset between the system clock and the synchronized IEEE 1588 clock and program the PHYs to make internal adjustments

The system card also provides a sync pulse to all PHYs including the VSC8490-17 device to the LOADSAVE pin This signal is used to load the time to the PHYs and to ensure that all the PHYs are in sync This may just be a centrally divided down system clock that gives a pulse at fixed time intervals The delay from the source of the signal to each PHY must be known and taken into account when writing in the load time in the PHYs

The VSC8490-17 device supports a vast variety of IEEE 1588 applications In simple one-step end-to-end transparent clock applications the VSC8490-17 device can be used without any central CPU involvement (except for initial configuration) The IEEE 1588 block inside the VSC8490-17 device forwards Sync and Delay_req frames with automatic updates to the Correction field

In other applications the VSC8490-17 device enhances the performance by working with a central processor that runs the IEEE 1588 protocol The VSC8490-17 device performs the accurate time stamp operations needed for all the different PTP operation modes For example at startup in a boundary clock application the central CPU receives PTP sync frames that are time stamped by the ingress PHY and recovers the local time offset from the PTP master using the PTP protocol It then sets the save bit in the VSC8490-17 device connected to the PTP master and later reads the saved time The central CPU loads the expected time (time of the next LOADSAVE pulse corrected by the offset to the recovered PTP time) into the PHY and sets the save bit It checks that the time offset is 0 If not it makes small adjustments to the time in the PHY by issuing add 1 ns or subtract 1 ns commands to the VSC8490-17 device through MDIO until the time matches the PTP master A save command is issued to the PHY connected to the PTP master and reads the saved time The central CPU then writes the saved time plus the sync pulse interval plus any sync pulse latency variation (trace length difference compared to the

Ethernet Port

Ethernet Line Card

MACPacketProcessing

System Card

System 1588Control

Processor

PHY

Optional frequency conversion

RefClk Timing Card

TimingCard

10G PHY

1 PPS Sync

RefClk

PHY connected to the PTP master) to the other PHYs and sets the load bit in these VSC8490-17 devices

The preceding sequence may be completed in several steps Not all PHYs need to be loaded at once The central CPU sets the save bit in all PHYs and reads back the values They should all save the same value

The central CPU continuously detects if the system time drifts off compared to the recovered PTP time If needed it can adjust each PHY for any known skew between PHYs without affecting the operation of the device It can program the PHYs including the VSC8490-17 device to automatically add 1 ns or subtract 1 ns at specific time intervals

362 IEEE 1588v2 One-Step End-to-End Transparent ClockThe timestamp block is located in PHYs and MACs with integrated PHYs that are placed on line cards If Microsemi 1588 PHYs are used on all ports that support IEEE 1588 one-step end-to-end transparent clocks the rest of the system does not need to be 1588-aware and there is no CPU maintenance needed once the system is set up

As all the PHYs in a system can be configured the same way the system supports failover of 1588 masters without any CPU intervention

This solution works for both blade systems and pizza boxes where the devices placed on the system side of the PHYs donrsquot need to be 1588-aware This allows an easy migration path for systems that do not support IEEE 1588 as this feature can be added by replacing existing PHYs with Microsemi 1588 PHYs on all ports

Unique advantages for implementing IEEE 1588-2008 include

bull When several VSC8490-17 devices or Microsemi PHYs with integrated IEEE 1588 time stamping blocks are used on all ports within the system that support IEEE 1588 one-step E2E TC the rest of the system does not need to be IEEE 1588 aware and there is no CPU maintenance needed once the system is set up

bull As all the PHYs in a system can be configured the same way it supports fail-over of IEEE 1588 masters without any CPU intervention

bull VSC8490-17 and other Microsemi PHYs with integrated IEEE 1588 time stamping blocks also work for pizza box solutions where the switchrouter can be upgraded to support IEEE 1588 E2E TC

Requirements for the rest of the system are

bull Delivery of a synchronous global timetick clock (or reference clock) to ensure that the ldquolocal timerdquo for all PHYs in the system progresses at the same rate

bull Delivery of a global timetick load to synchronize the local time counters in each PHYbull CPU access to each PHY to set up the required configuration This can be through MDIO two-wire

slave or 4-pin SPIThe following illustration shows a diagram for the transparent clock line card application

Ethernet Port

Ethernet Line Card

MACPacketProcessing

Ethernet Line Card

FabricAdapter

System Card

Fabric

Ethernet Port

1G SerDes PHY

MAC orSwitch

10G SerDes PHY

363 IEEE 1588v2 Transparent Clock and Boundary ClockThis is the same system as described previously with the addition of a central IEEE 1588 engine (Boundary Clock) The IEEE 1588 engine is most likely a CPU system possibly together with hardware support functions to generate Sync frames (for BC and ordinary clock masters) The switchfabric needs to have the ability to redirect (and copy) PTP frames to the IEEE 1588 engine for processing

This system uses a central 1588 engine most likely a CPU system together with hardware support functions to generate sync frames (for boundary clock and ordinary clock masters) The switch fabric needs to have the ability to redirect (and copy) PTP frames to the 1588 engine for processing This system also works for pizza boxes

Figure 23 bull Transparent Clock and Boundary Clock Line Card Application

This solution also works for pizza boxes To ensure that blade redundancy works the PHYs for the redundant blades must have the same 1588-in-the-PHY configuration

bull Delivery of a synchronous global timetick clock (or reference clock) to the PHYsbull Delivery of a global timetick load that synchronizes the local time counters in each portbull CPU access to each PHY to set up the required configuration For one-step support this can be

MDCMDIO For two-step support a higher speed CPU interface (such as the SPI) might be required (depending on the number of time stamps that are required to be read by the CPU) In blade systems it might be required to have a local CPU on the blade that collects the information and sends it to the central IEEE 1588 engine by means of the control plane or the data plane In advanced MACSwitch devices this might be an internal CPU

bull Fabric must be able to detect IEEE 1588 frames and redirect them to the central IEEE 1588 engineThe same solution can also be used to add Y1731 delay measurement support This does not require a local CPU on the blade but the fabric must be able to redirect OAM frames to a localcentral OAM processor

The following illustration shows a diagram for the boundary clock line card application

Ethernet Port

Ethernet Line Card

MACPacketProcessing

System Card

PHY1G

PHY

BoundaryClock

364 Enhancing IEEE 1588 Accuracy for CE Switches and MACsConnecting VSC8490-17 or other Microsemi PHYs that have integrated IEEE 1588 time stamping in front of the CE Switches and MACs improves the accuracy of the IEEE 1588 time stamp calculation This is due to the clock boundary for the XAUI and SGMIIQSGMII interface It will also add support for one-step TC and BC on the Jaguar-1 family of devices

365 MACsec SupportMACsec is required when the physical link between two MACs must provide secure communication MACsec PHYs such as the VSC8490-17 device are connected with CE switches to provide secure communication PTP and OAM frames are recognizable only before or after encryption meaning that the MACsec block must precede the IEEE 1588 block from the line inward

Even though MACsec introduces large delay variation because of the insertionremoval of the MACsec header on all encrypted frames the VSC8490-17 device provides the same accuracy with MACsec enabled as without In all other aspects the IEEE 1588 operation is as described in previous sections

366 Supporting One-Step Boundary ClockOrdinary ClockIn one-step boundary clock the BC device acts as an ordinary clock slave on one port and as master on the other ports On the master ports Sync frames are transmitted from the IEEE 1588 engine that holds the Origin time stamp These frames will have the correction field or the full Tx time stamp updated on the way out though the PHY

Master ports also receive Delay_req from the slaves and respond with Delay_resp messages The Delay_req messages are time stamped on ingress through the PHY and the IEEE 1588 engine receives the Delay_req frame and generates a Delay_resp message The Delay_resp messages are not event messages and are passed though the PHY as any other frame

The port configured as slave receives Sync frames from its master The Sync frames have a Rx time stamp added in the PHY and forwarded to the IEEE 1588 engine

The IEEE 1588 engine also generates Delay_req frames that are sent on the port configured as slave port Normally the transmit time for the Delay_req frames (t3) is saved in a time stamp FIFO in the PHYs but when using Microsemi IEEE 1588 PHYs a slight modification can be made to the algorithm to remove the CPU processing overhead of reading the t3 time stamp

To modify the algorithm the IEEE 1588 engine should send the Delay_req message with a software generated t3 value in the origin time stamp the sub-second value of the t3 time stamp in the reserved bytes of the PTP header and a correction field of 0 The software generated t3 time stamp should be within a second before the actual t3 time The Egress PHY should then be configured to perform E2E TC egress operation meaning calculate the ldquoresidence timerdquo from the inserted t3 time stamp to the actual t3 time and insert this value in the correction field of the frame When the local IEEE 1588 engine receives the corresponding Delay_resp frame back it can use the software generated t3 value because the correction field of the Delay_resp frame contains a value that compensates for the actual t3 transmission time

Ethernet Port

Ethernet Line Card

MACPacketProcessing

System Card

SerDes PHY10G

SerDes PHY

BoundaryClock

Boundary clocks and ordinary clocks must also reply to Pdelay_req messages just as P2P TC using the same procedure for the P2P TC For more information see Supporting One-Step Peer-to-Peer Transparent Clock page 53

Figure 25 bull One-Step E-nd-to-End Boundary Clock

3661 IngressEach time the PCSPMA detects the start of a frame it sends a pulse to the time stamp block which saves the value of the Local_Time received from the Local Time counter In the time stamp block the programmed value in the local_correction register is subtracted from the saved time stamp The local_correction register is programmed with the fixed latency from the measurement point to the place that the start of frame is detected in the PCSPMA logic The time stamp block also contains a register that can be programmed with the known link asymmetry This value is added or subtracted from the correction field depending on the frame type

When the frame leaves the PCSPMA block it is loaded into a small FIFO block that delays and stores the frame data for a few clock cycles to allow for later modifications of the frame The data is also copied to the analyzer block that parses the incoming frame to detect whether it is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain that the system is operating on If so it signals to the ingress time stamp block in the PHY which action to perform (Write) It also delivers the write offset and data size (location of the four reserved bytes in the PTP header 4 bytes wide) to the rewriter block in the PHY

If the analyzer detects that the frame is not matched it signals to the time stamp block and the rewriter block to ignore the frame (NOP) which allows it to pass unmodified and flushes the saved time stamp in the time stamp block

If the time stamp block gets the Write action it delivers the value of the calculated time stamp for the frame to the rewriter block and the rewriter block adds this time stamp (ns part of it) to the four reserved bytes in the frame and recalculates FCS

The rewriter block takes data out of the FIFO block continuously and feeds it to the system side PCSPMA block using a counter to keep track of the byte positions of the frame When the rewriter block receives a signal from the time stamp block to rewrite a specific position in the frame (that information comes from the analyzer block) it overwrites the position with the data from the time stamp block and

Packet processing and Switching

Engine recovers frequency from Sync frames and controls

1588 frequencyPTP Sync Frame

Correction Field = AReserved bytes = RxTimestamp +

Peer Delay

PTP Pdelay_req FrameCorrection Field = C

PTP Sync FrameOriginTime = F

Correction Field = E

PTP delay_req FrameCorrection Field = C

(TxTimestamp saved in FIFO)

PTP Sync or Delay_req FrameCorrection Field = A

Reserved bytes = RxTimestamp

PTP Sync FrameOriginTime = TxTimestamp

PTP Sync Or Delay_req FrameCorrection Field = AReserved Bytes = 0

PTP Sync FrameOrigin Time = F

IEEE 1588 PHY

Central IEEE 1588

Engine (CPU)

replaces the FCS of the frame The rewriter also checks the original FCS of the frame to ensure that a frame that is received with a bad FCS and then modified by the rewriter is also sent out with a bad FCS This is achieved by inverting the new FCS If the frame is an IPv4 frame the rewriter ensures that the IP checksum is 0 If the frame is IPv6 the rewriter keeps track of the modifications done to the frame and modifies a couple of bytes placed at the end of the PTP frame (for this specific purpose) so that the IP checksum stays correct

The following full calculations are performed

bull Sync frames Reserved_bytes = (Raw_Timestamp_ns ndash Local_correction) Correction field = Original Correction field + Asymmetry

bull Delay_req frames Reserved_bytes = (Raw_Timestamp_ns ndash Local_correction)

3662 EgressWhen a frame is received from the system side PCSPMA block it is loaded into a FIFO block that delays and stores the frame data for a few clock cycles to allow for later modifications of the frame The data is also copied to the analyzer block that parses the incoming frame to detect whether it is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain that the system is operating on

If the egress analyzer of the PHY detects that the frame is a IEEE 1588 Sync frame belonging to the PTP domain(s) of the system it signals to the egress time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the Tx time stamp inside the frame 10 bytes wide) to the rewriter

If the egress analyzer detects that the frame is a IEEE 1588 Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write Save) It also delivers the write offset and data size (location of the Tx time stamp inside the frame 10 bytes wide) to the rewriter It also outputs up to 16 bytes of frame identifier to the Tx time stamp FIFO to be saved along with the Tx time stamp The frame identifier bytes are selected information from the frame configured in the analyzer

If the time stamp block gets the (Write Save) action it delivers the calculated time stamp and signals to the time stamp FIFO block that it must save the time stamp along with the frame identifier data it received from the analyzer block

The Tx time stamp FIFO block contains a buffer memory It simply stores the Tx time stamp values that it receives from the time stamp block together with the frame identifier data it receives from the analyzerblock and has a CPU interface that allows the IEEE 1588 engine to read out the time stamp sets (Frame identifier + New Tx time stamp)

bull Sync frames OriginTimestamp = (Raw_Timestamp + Local_correction)bull Delay_req frames OriginTimestamp = (Raw_Timestamp + Local_correction) Correction

field = Original Correction field + Asymmetry

367 Supporting Two-Step Boundary ClockOrdinary ClockTwo-step clocks are used in systems that cannot update the correction field on-the-fly and this requires more CPU processing than one-step

Each time a Tx time stamp is sent in a frame the IEEE 1588 engine reads the actual Tx transmission time from the time stamp FIFO and issues a follow-up message containing this time stamp Even though the VSC8490-17 device supports one-step operation thereby eliminating the need to run in two-step mode support for this mode is provided for networks that include two-step-only implementations

Figure 26 bull Two-Step End-to-End Boundary Clock

3671 IngressIf the ingress analyzer in the PHY detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the four reserved bytes in the PTP header 4 bytes wide) to the rewriter

If the time stamp block gets the Write action it delivers the calculated time stamp to the rewriter block and the rewriter block adds this time stamp (ns part of it) to the four reserved bytes in the frame and recalculates FCS

Note When secure timing delivery is required (when using IPsec authentication for instance) the four reserved bytes must be reverted back to 0 before performing integrity check

bull Sync frames Reserved_bytes = (Raw_Timestamp ndash Local_correction)Correction field = Original Correction field + Asymmetry

bull Delay_req frames Reserved_bytes = (Raw_Timestamp ndash Local_correction)

3672 EgressIf the egress analyzer detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write Save) The analyzer outputs up to 15 bytes of frame identifier to the Tx time stamp FIFO to be saved along with the Tx time stamp The frame identifier must include at a minimum the sequenceId field so the CPU can match the time stamp with the follow-up frame

If the time stamp block gets the Write Save action it delivers the calculated time stamp to the time stamp FIFO and signals to the time stamp FIFO block that it must save the time stamp along with the frame identified data it received from the analyzer block

bull Sync frames FIFO = (Raw_Timestamp + Local_correction)

1588 frequency

PTP Sync Or Delay_req FrameCorrection Field = A

Correction Field = E(TxTimestamp saved in FIFO)

Central IEEE 1588

Engine (CPU)

IEEE 1588 PHY

bull Delay_req frames FIFO = (Raw_Timestamp + Local_correction)Correction field = Original Correction field ndash Asymmetry

368 Supporting One-Step End-to-End Transparent ClockEnd-to-end transparent clocks add the residence time (the time it takes to traverse the system from the input to the output port(s)) to all Sync and Delay_req frames It does not need to have any knowledge of the actual time but if it is not locked to the frequency of the IEEE 1588 time it will produce an error that is the ppm difference in frequency times the residence time

When the TC is frequency-locked by means of IEEE 1588 or other methods (SyncE) the error is only caused by sampling inaccuracies

The VSC8490-17 device supports a number of different transparent clock modes that can be divided into two main modes as follows

bull Mode A Subtracts the ingress time stamp at ingress and adds the egress time stamp at egress This mode can run in a number of sub-modes depending on the format of the time stamp that is subtracted or added

bull Mode B Saves the ingress time stamp in the reserved bytes of the PTP header (just as is done in BC and ordinary clock modes) and performs the residence time calculation at the egress PHY where the calculated residence time is added to the correction field of the PTP frame

Mode B is recommended because it has a number of advantages including the option to support TC and BC operation in the same system and on the same traffic and the ease of implementing syntonized TC operation

When an E2E TC recovers frequency using IEEE 1588 and is using Mode A it must either have a PHY with IEEE 1588 time stamping Mode A support or another way of adding the local time to the correction field placed in front of the IEEE 1588 engine The IEEE 1588 engine is then able to receive Sync frames and adjust the local frequency to match the IEEE 1588 time

If using Mode B the IEEE 1588 engine can recover the frequency directly from the Sync frames because it can extract the ingress time stamp directly from the frames The frequency adjustment can be done by adjusting the time counter in each PHY or by adjusting the global Timetick clock

Figure 27 bull One-Step End-to-End Transparent Clock Mode A

When the system works in one-step E2E TC mode Sync and Delay_req frames must be forwarded through the system and the residence time = (Egress time stamp ndash Ingress time stamp) must be added to the correction field in the frame before it leaves the system

The following sections describe the operation in Modes A and B

3681 Ingress (Mode A)If the analyzer detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Subtract) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the time stamp block gets the Subtract action it subtracts the time stamp converted to ns from the original correction field of the frame and outputs the value to the rewriter block

As a result the frame is sent towards the system with a correction field containing the value Original Correction field ndash Rx time stamp (converted to ns)

bull Sync frames Internal Correction field = Original Correction field ndash (Raw_Timestamp_ns ndashLocal_correction) + Asymmetry

bull Delay_req frames Internal Correction field = Original Correction field ndash (Raw_Timestamp_ns ndashLocal_correction)

Central IEEE 1588

Engine (CPU)

PTP Sync or Delay_Req FrameCorrection Field = A ndash RxTimestamp

PTP Sync or Delay_Req FrameCorrection Field =

A ndash RxTimestamp + TxTimestamp

PTP Sync or Delay_Req FrameCorrection Field = A

IEEE 1588 PHY

3682 Egress (Mode A)The egress side works that same way as ingress but the analyzer is set up to add the active_timestamp to the correction field

If the analyzer detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Add) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is not matched it signals the time stamp block and the rewriter block to ignore the frame (let it pass unmodified and flush the saved time stamp in the time stamp block)

If the time stamp block gets the Add action it adds the current value of the active_timestamp to the value of the correction field received from the analyzer and outputs the value to the rewriter block

When the rewriter block receives a signal from the analyzer block to rewrite a specific position in the frame it overwrites the position with the data received from the time stamp block and replaces the FCS of the frame The rewriter also checks the original FCS of the frame and ensures that a frame that is received with a bad FCS and then modified by the rewriter is also sent out with a bad FCS This is achieved by inverting the new FCS

bull Sync frames Correction field = Internal Correction field + (Raw_Timestamp_ns + Local_correction)bull Delay_req frames Correction field = Internal Correction field + (Raw_Timestamp_ns +

Local_correction) ndash AsymmetryFigure 28 bull One-Step End-to-End Transparent Clock Mode B

3683 Ingress (Mode B)In ingress mode B all calculations are performed at the egress port

A ndash RxTimestamp + TxTimestampReserved bytes = 0

PTP Sync or Delay_Req FrameCorrection Field = AReserved Bytes = 0

PTP Sync FrameCorrection Field = A

Reserved bytes = RxTimestampPTP Sync or Delay_Req FrameCorrection Field = A

Reserved bytes = RxTimestampEngine recovers frequency

from Sync frames and controls 1588 frequency

IEEE 1588 PHY

Central IEEE 1588

Engine (CPU)

On the ingress side when the analyzer detects Sync or Delay_req frames it adds the Rx time stamp to the four reserved bytes in the PTP frame

bull Sync frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correction Correction field = Original Correction field + Asymmetry

bull Delay_req frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correction

3684 Egress (Mode B)All calculations are done at the egress side When the analyzer detects Sync or Delay_req frames it performs the following calculation

bull Correction field = Original Correction field + Tx time stamp ndash Rx time stampThe value of the Rx time stamp is extracted from four reserved bytes in the PTP header The four reserved bytes are cleared back to 0 before transmission

The result is that every Sync and Delay_req frame that belongs to the PTP domain(s) and is configured as one-step E2E TC in the system will exit the system with a correction field that contains the following

bull Correction field = Original correction field + Tx time stamp ndash Rx time stampAll this is done without any interaction with a CPU system other than the initial setup There is no bandwidth expansion Standard switchingrouting tunneling can be done between the ingress and egress PHY provided that the analyzers in the ingress PHY and egress PHY are set up to catch the Sync and Delay_req on both If the PTP Sync and Delay_req frames are modified inside the system the egress analyzer must be able to detect the egress Sync and Delay_req frames otherwise the egress Sync and Delay_req frames will have an incorrect correction field

bull Sync frames Correction field = Original Correction field + (Raw_Timestamp_ns + Local_correction) ndash Reserved_bytes

bull Delay_req frames Correction field = Original Correction field + (Raw_Timestamp_ns + Local_correction) ndash Reserved_bytes ndash Asymmetry

369 Supporting One-Step Peer-to-Peer Transparent ClockWhen a Sync frame traverses a P2P TC the correction field is updated with both the residence time and the calculated path delay on the port that the Sync frame came in on

3691 Peer Link Delay MeasurementIn P2P TC the P2P TC device actively sends and receives Pdelay_req and Pdelay_resp messages and calculates the path delays to each neighbor node in the PTP network The following illustration shows the delay measurements

Figure 29 bull Delay Measurements

To calculate the path delays on a link the IEEE 1588 engine (located somewhere in the system) generates Pdelay_req messages on all ports When transmitted the actual Tx time stamp (t3) is saved for the CPU to read

When a P2P TC BC or OC receives a Pdelay_req frame it saves the Rx time stamp (t4) and generates a Pdelay_resp frame which adds t5 ndash t4 to the correction field copied from the received Pdelay_req frame where t5 is the time that the Pdelay_resp leaves the port (t5)

When a P2P TC receives the Pdelay_resp frame it saves the Rx time stamp (t6) and then calculates the path delay as (t6 ndash t3 ndash the correction field of the frame)2 The time stamp corrections are combined into a single formula as follows

bull Path delay = (t6 ndash (t3 + (t5 ndash t4))2 = (t6 ndash t3 ndash t5 + t4)2 = ((t4 ndash t3) + (t6 ndash t5))2The two path delays are divided by two but in such a way as to cancel out any timing difference between the two devices

A slight modification can be made to the algorithm to remove the CPU processing overhead of reading the t3 time stamp To modify the algorithm the IEEE 1588 engine should send the Pdelay_req message with a software generated t3 value in the origin time stamp the sub-second value of the t3 time stamp in the reserved bytes of the PTP header and a correction field of 0 The software generated t3 time stamp should just be within a second before the actual t3 time The egress PHY should then be configured to perform E2E TC egress operation meaning calculate the ldquoresidence timerdquo from the inserted t3 time stamp to the actual t3 time and insert this value in the correction field of the frame When the IEEE 1588 engine receives the corresponding Pdelay_resp frame back it can use the software generated t3 value as the correction field of the Pdelay_resp frame will contain a value that compensates for the actual t3 transmission time

A P2P TC adds the calculated one-way path delay to the ingress correction field and this ensures that the time stamp + correction field in the egress Sync frames is accurate and a slave connected to the P2P TC only needs to add the link delay from the TC to the slave

Timestamps known by slave

t2

t3

t6

t2t1 t2t3

t6t3 t4 t5 t6

Slave time

Master time

Sync

Follow_Up

Pdelay_RespPdelay_Resp_Follow_Up

t1

t4

t5

Pdelay_Req

t-ms

t-sm

S- OCS- BC -MGrandmaster-M

The following sections describe both the standard and modified methods for taking P2P measurements As with E2E TC operations the VSC8490-17 device also supports the different TC modes mode A (with different time stamp formats) and mode B Mode B is also the preferred method to implement P2P TC

3692 Ingress Mode AIf the analyzer detects that the frame is a IEEE 1588 Sync frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (subtract_p2p) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a IEEE 1588 Pdelay_req or Pdelay_resp frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the reserved 4 bytes in the PTP header that is used to save the ns part of the Rx time stamp 4 bytes wide) to the rewriter

If the time stamp block gets the subtract_p2p action it subtracts the value in the ingress time stamp from the correction_field data adds the configured path delay value and delivers the result to the rewriter block

If the time stamp block gets the Write action it outputs the value of the ingress time stamp register to the rewrite block and the rewriter block writes the sub-second value to the reserved bytes in the PTP header

bull Sync frames Internal Correction field = Original Correction field ndash (Raw_Timestamp_ns ndash Local_correction) + Path_delay + Asymmetry

bull Pdelay_req frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correctionbull Pdelay_resp frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correction

Correction Field = Original Correction field + Asymmetry

3693 Egress Mode AIf the analyzer detects that the frame is a IEEE 1588 Sync frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Add) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a IEEE 1588 Pdelay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Sub_add) along with the original correction field of the frame (will have the value of 0) and the time stamp extracted from the reserved bytes It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the user prefers to use to use the normal t3 handling where the t3 time stamp is saved in a time stamp FIFO the following configuration should be used If the analyzer detects that the frame is a IEEE 1588 Pdelay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write Save) along with the original correction field of the frame (will have the value of 0) It also delivers the write offset and data size (0- No data is actually written into the frame) to the rewriter In addition it outputs the field that holds the frame identifier (sequenceId from the PTP header) to the time stamp FIFO to save along with the Tx time stamp

If the analyzer detects that the frame is a IEEE 1588 Pdelay_resp frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Sub_add) along with the original correction field of the frame (will have the value of the CF received from the Pdelay_req frame) and the time stamp extracted from the reserved bytes It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is not matched it signals to the time stamp block and the rewriter block to ignore the frame (let it pass unmodified and flush the saved time stamp in the time stamp block)

bull Sync frames Correction field = Internal Correction field + (Raw_Timestamp_ns + Local_correction)

bull Pdelay_req frames Correction field = Internal Correction field + (Raw_Timestamp_ns + Local_correction) ndash Reserved_bytes ndash Asymmetry

bull Pdelay_resp frames Correction field = Original Correction field + (Raw_Timestamp_ns + Local_correction) ndash Reserved_bytes

3694 Ingress Mode BIf the analyzer detects that the frame is a IEEE 1588 Sync frame belonging to the PTP domain(s) of system it signals to the time stamp block which action to perform (subtract_p2p) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a IEEE 1588 Pdelay_req frame belonging to the PTP domain(s) of system it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the reserved 4 bytes in the PTP header used to save the ns part of the Rx time stamp 4 bytes wide) to the rewriter

If the analyzer detects that the frame is a IEEE 1588 Pdelay_resp frame belonging to the PTP domain(s) of system it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the reserved 4 bytes in the PTP header used to save the ns part of the Rx time stamp 4 bytes wide) to the rewriter

If the time stamp block gets the Subtract_p2p action it subtracts the value in the active_timestamp_ns_p2p register from the correction_field data and outputs the value on the New_Field bus to the Rewriter block

If the time stamp block gets the Write action it outputs the value of the active_timestamp_ns register on the New_field bus to the Rewriter block

bull Pdelay_req frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correctionbull Pdelay_resp frames Reserved_bytes = Raw_Timestamp_ns ndash Local_correction + Asymmetry

3695 Egress Mode BIf the analyzer detects that the frame is a IEEE 1588 Sync frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Add) along with the correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a IEEE 1588 Pdelay_req frame belonging to the PTP domain(s) of system it signals to the time stamp block which action to perform (Write Save) along with the original correction field of the frame (will have the value of 0) It also delivers the write offset and data size (0- No data is actually written into the frame) to the rewriter In addition it outputs the field that holds the frame identifier (sequenceId from the PTP header) to the time stamp FIFO to save along with the Tx time stamp

If the analyzer detects that the frame is a IEEE 1588 Pdelay_resp frame belonging to the PTP domain(s) of system it signals to the time stamp block which action to perform (Add - this requires that the IEEE 1588 engine has subtracted the Rx time stamp from the correction field) along with the original correction field of the frame It also delivers the write offset and data size (location of the correction field inside the frame 8 bytes wide) to the rewriter

If the time stamp block gets the Write Save action it outputs the value of the active_timestamp_ns register on the New_field bus to the Rewriter block and sets the save_timestamp bit

If the time stamp block gets the Add action it adds the correction field value to the value in the active_timestamp_ns register and outputs the value on the New_Field bus to the Rewriter block

The Tx time stamp FIFO block contains an (implementation specific) amount of buffer memory It simply stores the Tx time stamp values that it receives from the time stamp block together with the frame

identifier data it receives from the Analyzer block and has a CPU interface that allows the IEEE 1588 engine to read out the time stamp sets (Frame identifier + New Tx time stamp)

bull Sync frames Correction field = Internal Correction field + (Raw_Timestamp_ns + Local_correction)bull Pdelay_req frames FIFO = Raw_Timestamp_ns + Local_correction ndash Asymmetrybull Pdelay_resp frames Correction field = Internal Correction field +

(Raw_Timestamp_ns + Local_correction)Figure 30 bull One-Step Peer-to-Peer Transparent Clock Mode B

3610 Supporting Two-Step Transparent ClockIn two-step transparent clocks the Rx and Tx time stamps are saved for the IEEE 1588 engine to read and the follow-up message is redirected to the IEEE 1588 engine so that it can update the correction field with the residence time

Even though two-step transparent clocks can be used with this architecture it is also possible to process the frames in the same manner as a one-step TC because the slaves are required to take both the correction fields from the Sync frames and the follow-up frames into account This significantly reduces the CPU load for the TC The following illustration shows two-step transparent clock normal operation

1588 frequencyPTP Sync FrameCorrection Field = A

Reserved bytes = RxTimestamp + Peer Delay

PTP Pdelay_reqresp FrameCorrection Field = B

Reserved Bytes = RxTimestamp

PTP Pdelay _resp FrameCorrection Field = D

(D = B ndash RxTimestamp )

PTP Pdelay_resp FrameCorrection Field = D + TxTimestamp

PTP Pdelay_resp FrameCorrection Field = D

(D = B ndash RxTimestamp)

PTP Pdelay_reqresp FrameCorrection Field = BReserved Bytes = 0

(TxTimestamp saved in FIFO )

PTP Sync FrameCorrection Field =

A ndash RxTimestamp + TxTimestamp+ Peer Delay

Reserved bytes = 0

PTP Sync FrameCorrection Field = AReserved Bytes = 0

IEEE 1588 PHY

Central IEEE 1588

Engine (CPU)

Central IEEE 1588

Engine (CPU)

Central IEEE 1588

Engine (CPU)

Figure 31 bull Two-Step End-to-End Transparent Clock

36101 IngressIf the analyzer detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write) The analyzer also delivers the write offset and data size to the rewriter (four reserved bytes in the PTP header which will be passed out on the egress port of the system) A changed reserved value may be significant in security protection This method allows the frames to be copied to the IEEE 1588 engine so that it can extract the Rx time stamp and knows that it needs to read the Tx time stamps to be ready for the follow up message It is also possible to save the Rx time stamp value along with the Tx time stamp in the Tx time stamp FIFO

If the time stamp block gets the Write action it outputs the current time stamp to the rewriter and the rewriter writes the ns part of the time stamp into the reserved bytes and recalculates FCS

36102 EgressIf the analyzer detects that the frame is a IEEE 1588 Sync or Delay_req frame belonging to the PTP domain(s) of the system it signals to the time stamp block which action to perform (Write Save) The analyzer also delivers the write offset and data size (but as nothing is to be overwritten the values will be 0) to the rewriter The analyzer outputs 10 bytes of frame identifier to the Tx time stamp FIFO to be saved along with the Tx time stamp The frame identifier must include at minimum the sequenceId field so the CPU can match the time stamp with the follow-up frame The analyzer also outputs the offset for the reserved fields in the PTP header to the rewriter so that the rewriter field is reset to 0 and the temporary Rx time stamp value is cleared

1588 frequency

PTP Sync Or Delay_req FrameCorrection Field = AReserved bytes = 0

TxTimestamp and RxTimestamp in FIFO

IEEE 1588 PHY

Central IEEE 1588

Engine (CPU)

If the time stamp block gets the Write Save action it outputs the current time stamp value to the rewriter (and time stamp FIFO) and sets the save_timestamp bit The time stamp FIFO block saves the New_field data along with the frame identifier data it received from the analyzer block The frame identifier data that is saved can contain the reserved field in the PTP header that was written with the Rx time stamp so that the CPU now can read the set of Tx and Rx time stamp from the Tx time stamp FIFO

bull Sync frames FIFO = Raw_Timestamp_ns + Local_correction (reserved_bytes containing the Rx time stamp saved together with Tx time stamp)

bull Delay_req frames FIFO = Raw_Timestamp_ns + Local_correction ndash Asymmetry (reserved_bytes containing the Rx time stamp saved together with Tx time stamp)

3611 Calculating OAM Delay MeasurementsFrame delay measurements can be made as one-way and two-way delay measurements Microsemi recommends that the delay measurement be measured before the packets enter the queues if the purpose is to measure the delay for different priority traffic but it can be used with time stamping in the PHY to measure the delay through the network devices placed in the path between the measurement points

The function is mainly an on-demand OAM function but it can run continuously

3612 Supporting Y1731 One-Way Delay MeasurementsOne-way delay measurements require that the two peers are synchronized in time When they are not synchronized only frame delay variations can be measured

The MEP periodically sends out 1DM OAM frames containing a TxTimeStampf value in IEEE 1588 format

The receiver notes the time of reception of the 1DM frame and calculates the delay

Figure 32 bull Y1731 1DM PDU Format

1 For one-way delay measurements both MEPs must support IEEE 1588 and be in sync2 1DM frame is generated by the CPU but with an empty Tx time stamp3 The frame is transmitted by the initiating MEP4 The 1DM frame is classified as an outgoing 1DM frame by the egress PHY and the PHY rewrites the

frame with the time as TxFCf5 The receiving PHY classifies the incoming 1DM frame and writes the receive time stamp in reserved

place (RxTimeStampf)6 The frame is received by the peer MEP7 The frame is forwarded to the CPU that can calculate the delay

MEL Version (0) OpCode (1DM=45) Flags (0) TLV Offset (16)

End TLV (0)

Reserved for 1DM receiving equipment (0)(for RxTimeStampf)

TxTimeStampf

1

5

9

13

17

21

1 2 3 48 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

Figure 33 bull Y1731 One-Way Delay

36121 IngressIf the analyzer detects that the frame is a Y1731 1DM PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) The analyzer also delivers the write offset and data size (location of the RxTimeStampf location in the frame 8 bytes wide) to the rewriter

If the time stamp block gets the Write action it delivers the time stamp to the rewriter block and the rewriter block adds this time stamp to the reserved bytes in the frame and recalculates FCS

The following calculation is performed for 1DM frames

bull RxTimeStampf = (Raw_Timestamp ndash Local_correction)

36122 EgressIf the analyzer detects that the frame is a Y1731 1DM PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the TxTimeStampf location in the frame 8 bytes wide) to the rewriter

bull TxTimeStampf = (Raw_Timestamp + Local_correction)

Y1731 1DM MessageTxTimeStampf = ARxTimeStampf = 0

Y1731 1DM MessageTimeStampsf = A

RxTimeStampf = RxTimestamp

Y1731 1DM MessageTimeStampsf = 0

RxTimeStampf = 0

Y1731 1DM MessageTimeStampsf = TxTimestamp

RxTimeStampf = 0

RxTimeStampf = 0 Central Y1731 Engine (CPU)

IEEE 1588 PHY

3613 Supporting Y1731 Two-Way Delay MeasurementsWhen performing two-way delay measurements the initiating MEP transmits DMM frames containing a TxTimeStampf value The receiving MEP replies with a DMR frame that is the same as the DMM frame but with destination and source MAC address swapped and with a different OAMPDU opcode

When the DMR frame is received back at the initiating MEP the time of reception is noted and the total delay is calculated

As an option it is allowed to include two additional time stamps in the DMR frame RxTimeStampf and TxTimeStampb These contain the time that the DMM page is received for processing and the time the responding DMR reply is sent back both in IEEE 1588 format

Including these time stamps allows for the exclusion of the processing time in the peer MEP but it does not require that the two MEPs are synchronized

Figure 34 bull Y1731 DMM PDU Format

In that case the following frame flow is needed (two-way delay measurement)

1 DMM frame is generated by the CPU (initiating MEP) but with an empty Tx time stamp2 In the egress PHY the DMM frame is classified as an outgoing DMM frame from the MEP and the

PHY rewrites the frame with the time as TxTimeStampf3 In the ingress PHY the frame is classified as an incoming DMM belonging to the MEP and the

RxTimeStampf in the frame is written (the frame has a reserved space for this)4 The DMM frame is forwarded to the MEP (CPU)5 The CPU processes the frame (swaps SADA MAC addresses modifies the opcode to DMT) and

sends out a DMT frame6 The outgoing DMT frame is detected in the egress PHY and the TxTimeStampb is written into the

frame7 In the ingress PHY the frame is classified as an incoming DMT belonging to the MEP and the

RxTimeStampb in the frame in written (the frame has a reserved space for this)8 The frame is forwarded to the CPU that can calculate the delays

MEL Version (0) OpCode (DMM=47) Flags (0) TLV Offset (32)

End TLV (0)

Reserved for DMM receiving equipment (0)(for RxTimeStampf)

TxTimeStampf

1

5

9

13

17

21

25

29

33

37

1 2 3 48 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

Reserved for DMR (0)(for TxTimeStampb)

Reserved for DMR receiving equipment (0)

Figure 35 bull Y1731 Two-Way Delay

36131 IngressIf the analyzer detects that the frame is a Y1731 DMM PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the RxTimeStampf location in the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a Y1731 DMT PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the RxTimeStampf location in the frame 8 bytes wide) to the rewriter

The following calculations are performed

bull DMM frames RxTimeStampf = (Raw_Timestamp ndash Local_correction)bull DMR frames RxTimeStampb = (Raw_Timestamp ndash Local_correction)

36132 EgressIf the analyzer detects that the frame is a Y1731 DMM PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the TxTimeStampf location in the frame 8 bytes wide) to the rewriter

If the analyzer detects that the frame is a Y1731 DMT PDU frame belonging to the MEP it signals to the time stamp block which action to perform (Write) It also delivers the write offset and data size (location of the TxTimeStampb location in the frame 8 bytes wide) to the rewriter

If the time stamp block gets the Write action it delivers the time stamp to the rewriter block and the rewriter block adds the time stamp to the reserved bytes in the frame and recalculates FCS as follows

bull DMM frames TxTimeStampf = (Raw_Timestamp + Local_correction)

Y1731 DMM MessageTxTimeStampf = ARxTimeStampf = 0TxTimeStampb = 0RxTimeStampb = 0

Y1731 DMM MessageTxTimeStampf = A

RxTimeStampf = RxTimestampTxTimeStampb = 0RxTimeStampb = 0

Y1731 DMR MessageTxTimeStampf = BRxTimeStampf = CTxTimeStampb = 0RxTimeStampb = 0

Y1731 DMR MessageTxTimeStampf = BRxTimeStampf = C

TxTimeStampb = TxTimestampRxTimeStampb = 0

Y1731 DMR MessageTxTimeStampf = DRxTimeStampf = ETxTimeStampb = F

RxTimeStampb = RxTimestamp

Y1731 DMR MessageTxTimeStampf = DRxTimeStampf = ETxTimeStampb = FRxTimeStampb = 0

Y1731 DMM MessageTxTimeStampf = 0RxTimeStampf = 0TxTimeStampb = 0RxTimeStampb = 0

Y1731 DMM MessageTxTimeStampf = TxTimestamp

RxTimeStampf = 0TxTimeStampb = 0RxTimeStampb = 0

RxTimeStampb = RxTimestampIEEE 1588

PHY

IEEE 1588 PHY

Central Y1731 Engine (CPU)

bull DMR frames TxTimeStampb = (Raw_Timestamp + Local_correction)

36133 Supporting MPLS-TP One-Way and Two-Way Delay MeasurementsMPLS-TP one- and two-way delay measurement are defined in RFC6374 (G81132) and G81131 (draft-bhh) These mechanisms are similar to the ones described for Y1731 Ethernet OAM delay measurement except for the encapsulations The following illustrations show the PDU formats

Figure 36 bull RFC6374 DMMDMR OAM PDU Format

Figure 37 bull Draft-bhh DMMDMR1DM OAM PDU Formats

3614 Device Synchronization for IEEE 1588 SupportIt is important to keep all the local clock blocks synchronized to the accurate time over a complete system To maintain ns accuracy the signal routing and internal signal delays must be taken into account when configuring a system

The architecture described in this document assumes that there is a global synchronous clock available in the system If the system is a telecom system where the system is locked to a PRC the system clock can be adjusted to match the PRC meaning that once locked the frequency of the system clock ensures that the local clocks are progressing (counting) with the accurate frequency This system clock can be locked to the PRC using IEEE 1588 SyncE SDH or by other means

ETH (1)

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

padding

FCS

DMM

DM

R O

AM P

DUs

141822B

481216B

4B

8B

(variable size)

4B

(1) 0 1 or 2 VLAN tags(2) Up to 4 MPLS labels

ETH (1)

DMMDMR

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

End TLV indicator

FCS

DM

MD

MR

OAM

PDU

s

141822B

481216B

4B

8B

1B

4B

ETH (1)

1DM

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

End TLV indicator

FCS

1DM

OA

M P

DUs

141822B

481216B

4B

8B

4B

1B

A global timing signal must also be distributed to all the devices This could be a 1 pps pulse or another slow synchronization pulse like a 4 kHz synchronization frequency It can also just be a one-shot pulse The system CPU can load each local counter with the time value that happens next time the synchronization pulse goes high (+ the known delay of the synchronization pulse traces) It can also just load the same approximate time value into all the local clock blocks (again + the known delay of the synchronization pulse traces) and load them in parallel Then the local time can be adjusted to match the actual time by adjusting the local clock blocks using the plusmn1 ns function

If the Save signal is triggered synchronously on all PHYs of the system software can read the saved time stamp in each PHY and correct the time accordingly On a blade with multiple PHYs it is possible to connect the 1588_PPS_1 pin on one PHY to the 1588_LOAD_SAVE pin on the next PHY If the routing delay (both internal chip delay and trace delay) is known Microsemi recommends that the value saved in the next PHYs correspond to this delay

If the global system clock is not synchronous the PPM offset between system clock and the IEEE 1588 time progress can be calculated This PPM offset can be used to calculate how many local-time-clocks is takes to reach a time offset of 1 ns and this value can be programmed into each local time block The CPU still need to keep track of the smaller PPM offset and adjust the local time blocks with plusmn writes when necessary

By measuring the skew between the 1 pps test output from each PHY it is possible to measure the nominal correction values for the time counters in a system These can be incorporated into the software of the system Variations from system to system and temperature variations should be minimized by design

3615 Time Stamp Update BlockThe IEEE 1588 block is also called the Time Stamp Update block (TSU) and supports the implementation of IEEE 1588v2 and ITU-T Y1731 in PHY hardware by providing a mechanism for time stamp update (PTP) and time stamping (OAM)

The TSU block works with other blocks to identify PTPOAM messages process these messages and insert accurate time stamp updatestime stamps where necessary For IEEE 1588 timing distribution the VSC8490-17 device supports ordinary clocks boundary clocks end-to-end transparent clocks and peer-to-peer transparent clocks in a chassis based IEEE 1588 capable system One-step and two-step processing is also supported For details on the timing protocol refer to IEEE 1588v2 For OAM details refer to ITU-T Y1731 and G81131G81132 The TSU block implements part of the functionality required for full IEEE 1588 compliance

The IEEE 1588 protocol has four different types of messages that require action by the TSU Sync Delay_req Pdelay_req and Pdelay_resp These frames may be encapsulated in other protocols several layers deep The processor is able to detect PTP messages within these other protocols The supported encapsulations are as follows

bull Ethernetbull UDP over IPv4bull UDP over IPv6bull MPLSbull Pseudo-wiresbull PBB and PBB-TE tunnelsOAM frames for delay measurement (1DM DMM and DMR) with the following supported encapsulations

bull Ethernet (Y1731 Ethernet OAM)bull Ethernet in MPLS pseudo-wires (Y1731 Ethernet OAM)bull MPLS-TP (G81131 (~draft-bhh-mpls-tp-oam-y1731) and G81132 (RFC6374))The following illustration shows an overview of the supported PTP encapsulations Note that the implementation is flexible so encapsulations not defined here may also be covered

Figure 38 bull PTP Packet Encapsulations

The following illustration shows the same overview of the supported encapsulations with the focus on OAM

Figure 39 bull OAM Packet Encapsulations

There is one TSU per channel in the VSC8490-17 device The TSU detects and updates up to three different encapsulations of PTPOAM Non-matching frames are transferred transparently This includes IFG preamble and SFD For all frames there is no bandwidth expansionshrink

Once these frames are detected in the receive path they are stamped with the ingress time and forwarded for further PTPOAM processing In the transmit path the correction field of the appropriate PTP message (or the Rx and Tx fields of the OAM frame) is updated with the correct time stamp A local time counter is maintained to provide the time stamps Implementation of some of the IEEE 1588 protocol requires interaction with the TSU block over the CPU interface and external processing

The system has an ingress processor egress processor and a local time counter The ingress and egress processing logic blocks are identical except that the time stamp FIFO is only required in the egress direction because the CPU needs to know the actual time stamps of some of the transmitted PTP

E T H 1

E T H 2

IP U D P

P T P P T PP T P

P B B E T H

IP U D P

P T PP T P

P W E

E T H 2

IP U D P

P T PP T P

IP -M P L S

M P L S

M A C -in -M A C U n tagged T aggedP B (Q - in -Q )

d ra ft -ie t f -t ic toc-1588 ove rm p ls

d ra f t -ie t f- t ic toc-1588ove rm p ls

ACHPWEETH

ETH1

ETH2

ACH(RFC-5718)

Y 1731 OAM Y1731 OAM

ETH2

Y1731 OAM

MPLS

MAC -in-MACUntagged TaggedPB (Q-in-Q)

PBB

G81131(~draft-bhh-mpls-tp-oam-y1731)

G 81132 (RFC6374)

frames The CPU reads the time stamps and any associated frame information out of the time stamp FIFO The FIFO saves the generated time stamps along with information that uniquely identifies the frame to be read out by the CPU

The ingress and egress processing blocks run on the same clock as the data paths for the corresponding directions The local time counter is the primary reference clock for the system and it maintains the local reference time used by the TSU logic It should be synchronized by an external entity The block provides a method to load and view its value when the 1588_LOAD_SAVE pin is asserted The block also provides a one pulse-per-second output signal with a programmable duty cycle The local time counter runs at several clock frequencies

The following illustration shows the block diagram of the TSU

Figure 40 bull TSU Block Diagram

In both directions the input data from the PHY layer is first fed to an SOF detect block Data is then fed to both the programmable time-delay FIFO and the analyzer The FIFO delays the data by the time needed to complete the operations necessary to update the PTP frame That is the data is delayed to the input of the rewriter so that the rewriter operations are known when the frame arrives This includes the analyzer and time stamp processor blocks functions

The analyzer block checks the data stream and searches for PTPOAM frames When one is detected it determines the appropriate operations to be performed based on the operating mode and the type of frame detected

Note The analyzer blocks of two channels share configuration registers and have identical setups

The time stamp block waits for an SOF to be detected captures a time stamp from the local time counter and builds the new time stamp that is to be written into the PTPOAM frame Captured time stamps can be read by the CPU

The rewriter block handles the actual writing of the new time stamp into the PTPOAM frame It is also able to clear parts of the frame such as the UDP checksum if required or it can update the frame to

SOF detect

DataData

Analyzer

Cntrl

FIFO Rewriter

Time stamp

Data

Corr_TS

Ingress processor

SOF detect

DataData

Analyzer

Cntrl

FIFORewriter

Time stamp

Data

Corr_TS

Egress processor

Time stamp FIFO Sign

TS

Local Time Counter

1 PPS

Egress timing domain

Ingress timing domainAdapt

Adapt

Egress predictor

Ingress predictor

Serial time

stamps

LoadSave

External

ensure that the UDP checksum is correct (for IPv6 PTP frames) The block also calculates the new FCS to be written to the PTP frame after updating the fields with the new time stamp

The VSC8490-17 device has variable latency in the PCS block These variations are predicted and used to compensatemaximize the accuracy of the IEEE 1588 time stamp logic

If the time stamp update function is not used the block can be bypassed When the TSU is bypassed the block can be configured and then enabled and taken out of bypass mode The change in bypass mode takes effect only when an IDLE is in the bypass register This allows the TSU block to be switched on without corrupting data

Each direction of the IEEE 1588 can be bypassed individually by programming the INTERFACE_CTLSPLIT_BYPASS bit Bypass is then controlled by INTRERFACE_CTLINGR_BYPASS and INTERFACE_CTLEGR_BYPASS

Pause frames pass unmodified through the TSU but the latency may cause a violation of the allowed pause flow-control latency limits per IEEE 8023

3616 AnalyzerThe packet analyzer parses incoming packets looking for PTPOAM frames It determines the offset of the correction field within the packet for all PTP framesfor the time stamp in Y1731 OAM frames The analyzer has the following characteristics

bull Can compare against two different filter sets plus one optimized for OAMbull Each filter targets PTP or OAM framesbull Flexible comparator sequence with fixed start (EthernetSNAP) and end (PTPOAM) comparator

Configurable intermediate comparators (EthernetSNAP 2x IPUDPACH and MPLS)The following illustration shows a block diagram of the analyzer

Figure 41 bull Analyzer Block Diagram

SOF detect

DataDataSOF

EthernetSNAPComparator 1

Encap A

IPUDPACHComparator 1

Encap A

MPLSComparator

Encap A

PTPOAMComparator

Encap A

Frame signature builder

Encap Engine A controller

Anal

yzer

Encap B

MPLSComparator

Encap B

PTPOAMComparator

Encap B

Encap Engine B controller

Encap A

MPLSComparator

Encap A

PTPOAMComparator

Encap A

Encap B

MPLSComparator

Encap B

PTPOAMComparator

Encap B

Encap A

MPLSComparator

Encap A

PTPOAMComparator

Encap A

Encap C

MPLSComparator

Encap C

PTPOAMComparator

Encap C

Encap Engine C controller

Align

(OAM optimized)

Offsets amp Next protocol

A-flow

B-flow

A-flow

B-flow

A-flowB-flow

The analyzer process is divided into engines and stages Each engine represents a particular encapsulation stack that must be matched There are up to six stages in each engine Each stage uses a comparator block that looks for a particular protocol The comparison is performed stage-by-stage until the entire frame header has been parsed

Each engine has its own master enable so that it can be shut down for major reconfiguration such as changes in encapsulation order without stopping traffic Other enabled engines are not affected

The SOF detect block searches for the SFD in the preamble and uses that to indicate the SOF position This information is carried along in the pipeline and also passed to the analyzer

The first stage of the analyzer is a data path aligner that aligns the first byte of the packet (without the preamble amp SFD) to byte 0 of the analyzer data path

The encapsulation engine handles numerous types of encapsulation stacks These can be broken down to their individual protocols and a comparator is defined for each type The order in which these are applied is configurable Each comparator outputs a patternflow match bit and an offset to the start of the next protocol The cumulative offset points to the time stamp field

The sequence in which the protocol comparators are applied is determined by configuration registers associated with each comparator and the transfer of parameters between comparators is controlled by the encapsulation engine controller

It receives the pattern match and offset information from one comparator stage and feeds the start-of-protocol position to the next comparator This continues until the entire encapsulation stack has been parsed and always ends with the PTPOAM stage (or until a particular comparator stage cannot find a match in any of its flows) If at any point along the way no valid match is found in a particular stage the analyzer sends the NOP communication to the time stamp block indicating that this frame does not need modification and that it should discard its time stamp

There are two types of engines in the analyzer one optimized for PTP frames and the other optimized for OAM frames The two engine types are mostly identical except that the IP comparators are removed from the OAM engines The following table shows the comparator layout per engine type and the number of flows in each comparator There are two PTP engines and one OAM engine in each analyzer Additional differences in the Ethernet and MPLS blocks are defined in their respective sections For more information see EthernetSNAPLLC Comparator page 69 and MPLS Comparator page 73

Encapsulation matches can be set independently in each direction by setting the ANALYZER_MODESPLIT_ENCAP_FLOW register However strict and non-strict flow cannot be set independently for group A and group B of analyzer engine C

Choice of strict flow or non-strict has to be made on each direction rather than on an engine by engine basis Valid values for INGR_ENCAP_FLOW_ENA and EGR_ENCAP_FLOW_ENA are 3b000 or 3b111

Each comparator stage has an offset register that points to the beginning of the next protocol relative to the start of the current one The offset is in bytes and the first byte of the current protocol counts as byte 0 As an example the offset register for a stage would be programmed to 10 when the header to match is 10 bytes long With the exception of the MPLS stage (offsets are automatically calculated in that stage)

Table 18 bull Flows Per Engine Type

Number of FlowsComparator PTP Engine OAM EngineEthernet 1 8 8

Ethernet 2 8 8

MPLS 8 8

IPACH 1 8 0

IPACH 2 8 0

PTPOAM 6 6

it is the responsibility of the programmer to determine the value to put in these registers This value must be calculated based upon the expected length of the header and is not expected to change from frame-to-frame when matching a given flow

The following table shows the ID codes comparators use in the sequencing registers The PTP packet target encapsulations require only up to five comparators

The following sections describe the comparators The frame format of each comparator type is described first followed by matchmask parameter definition All upper and lower bound ranges are inclusive and all matchmask registers work the same way If the corresponding mask bit is 1 then the match bit is compared to the incoming frame If a mask bit is 0 then the corresponding match bit is ignored (a wildcard)

36161 EthernetSNAPLLC ComparatorThere are two such comparators in each engine The first stage of each engine is always an EthernetSNAPLLC comparator The other comparator can be configured to be at any point in the chain

Ethernet frames can have multiple formats Frames that have an actual length value in the ether-type field (Ethernet type I) can have one of three formats Ethernet with an EtherType (Ethernet type II) Ethernet with LLC or Ethernet with LLC amp SNAP Each of these formats can be compounded by having one or two VLAN tags

361611 Type II EthernetType II Ethernet is the most common and basic type of Ethernet frame The LengthEtherType field contains an EtherType value and either 0 1 or 2 VLAN tags Both VLAN can be of type SC (with EtherType 0x8a880x8100) The payload would be the start of the next protocol

Table 19 bull Ethernet Comparator Next Protocol

Parameter Width DescriptionEncap_Engine_ENA 1 bit For each encapsulation engine and enable bit that turns the engine on or

off The engine enables and disables either during IDLE (all 8 bytes must be IDLE) or at the end of a frame If the enable bit is changed during the middle of a frame the engine will wait until it sees either of those conditions before turning on or off

Encap_Flow_Mode 1 bit There is a separate bit for each engine For each encapsulation engine1 = Strict flow matching a valid frame must use the same flow IDs in all comparators in the engine except the PTP and MPLS comparators0 = A valid frame may match any enabled flow in all comparatorsIf more than one encapsulation produces a match the analyzer sends NOP to the rewriter and sets a sticky bit

Table 20 bull Comparator ID Codes

ID Name Sequence0 Ethernet Comparator 1 Must be the first

1 Ethernet Comparator 2 Intermediate

2 IPUDPACH Comparator 1 Intermediate

4 MPLS Comparator Intermediate

5 PTPOAM Comparator Must be the last

Figure 42 bull Type II Ethernet Basic Frame Format

361612 Ethernet with LLC and SNAPIf an Ethernet frame with LLC contains a SNAP header it always follows a three-octet LLC header The LLC values for DSAP amp SSAP are either 0xAA or 0xAB and the control field contains 0x03 The SNAP header is five octets long and consists of two fields the 3-octet OUI value and the 2-octet EtherType As with the other types of Ethernet frames this format can have 0 1 or 2 VLAN tags The OUI portion of the SNAP header is hard configured to be 0 or 0xf8

The following illustration shows an Ethernet frame with a length in the LengthEtherType field an LLC header and a SNAP header

Figure 43 bull Ethernet Frame with SNAP

The following illustration shows an Ethernet frame with an LLCSNAP header and a VLAN tag in the SNAP header The Ethertype in the SNAP header is the VLAN identifier and tag immediately follows the SNAP header

Figure 44 bull Ethernet Frame with VLAN Tag and SNAP

The following illustration shows the longest form of the Ethernet frame header that needs to be supported two VLAN tags an LLC header and a SNAP header

Figure 45 bull Ethernet Frame with VLAN Tags and SNAP

361613 Provider Backbone Bridging (PBB) SupportThe provider backbone bridging protocol is supported using two Ethernet comparator blocks back-to-back The first portion of the frame has a type II Ethernet frame with either 0 or 1 VLAN tags followed by an I-tag The following illustrations show two examples of the PBB Ethernet frame format

Figure 46 bull PBB Ethernet Frame Format (No B-Tag)

Figure 47 bull PBB Ethernet Frame Format (1 B-Tag)

Destination Address (DA) Source Address (SA) Etype Payload

Source Address (SA)

PayloadVLAN Tag

VLAN Tag 1 VLAN Tag 2 Etype Payload

Destination Address (DA)

5 4 3 2 1 0 5 4 3 2 1 0

3 2 1 0

3 2 1 0 3 2 1 0

1 0

Etype

Destination Address (DA) Source Address (SA) Length5 4 3 2 1 0 5 4 3 2 1 0 1 0

DSAPSSAP CtlAAAB AAAB 0x03 1 0 1 02

Protocol ID0x000000 EtherType

Destination Address (DA) Source Address (SA) Length$ $ $ $ $ $ $ $ $

DSAPSSAP CtlAAABAAAB 0x03

Protocol ID0x000000 VLAN EType

VLAN Tag ID

Source Address (SA)VLAN 1

EtherTypeVLAN 2

Tag Etype PayloadDestination Address (DA)5 4 3 2 1 0 5 4 3 2 1 0 1 0 1 0 1 0 1 0

DSAPSSAP Ctl1 0

VLAN 1 Tag

VLAN 2 EtherType AAAB AAAB 0x03 2 1 0 1 0

Protocol ID

LLC SNAP

Backbone Source Address (B-SA) SIDBackbone Destination Address (B-DA)5 4 3 2 1 0 5 4 3 2 1 0 0 0 5 4 1 03 2

EtherType88E7

1 0 12

Flags5 4 1 03 2

Customer Destination Address (C-DA) Customer Source Address (C-SA) Rest of E-net Header

I-Tag

First Ethernet Comparator Second Ethernet Comparator

Backbone Source Address (B-SA)EtherType

88A8 SID

First Ethernet Comparator

Backbone Destination Address (B-DA)5 4 3 2 1 0 5 4 3 2 1 0 1 0 0 0 5 4 1 01 0

B-VID

I-Tag

3 2

EtherType88E7

B-Tag

1 0 12

Flags5 4 1 03 2

Customer Destination Address (C-DA) Customer Source Address (C-SA)

Second Ethernet Comparator

Rest of E-net Header

361614 Ethernet ComparisonThe Ethernet comparator block has two forms of comparison as follows

bull Next protocol comparison is common for all flows in the comparator It is the single set of registers and is used to verify what the next protocol in the encapsulated stack will be

bull Flow comparison is used to match any of the possible flows within the comparator

361615 Ethernet Next Protocol ComparisonThe next protocol comparison field looks at the last EtherType field in the header (there can be multiple in the header) to verify the next protocol It may also look at VLAN tags and the EtherType field when it is used as a length Each has a pattern matchmask or range and an offset

The following table lists the next protocol parameters for the Ethernet comparator

361616 Ethernet Flow ComparisonThe Ethernet flow is determined by looking at VLAN tags and either the source address (SA) or the destination address (DA) There are a configurable number of these matched sets The following table lists the flow parameters for the Ethernet comparator

Table 21 bull Ethernet Comparator (Next Protocol)

Parameter Width DescriptionEth_Nxt_Comparator 3 bit Pointer to the next comparator

Eth_Frame_Sig_Offset 5 bit Points to the start of the field used to build the frame signature

Eth_VLAN-TPID_CFG 16 bit Globally defines the value of the TPID for an S-tag B-tag or any other tag type other than a C-tag or I-tag

Eth_PBB_ENA 1 bit Configures if the packet carries PBB or not This configuration bit is only present in the first Ethernet comparator block PBB is disabled in Ethernet comparator block 2

Eth_Etype_Match_Enable 1 bit Configures if the Ethertype field match register is used or not Only valid when the packet is a type II Ethernet packet

Eth_Etype_Match 16 bit If the packet is a type II Ethernet packet and Eth_Etype_Match_Enable is a 1 the Ethertype field in the packet is compared against this value

Table 22 bull Ethernet Comparator (Flow)

Parameter Width DescriptionEth_Flow_Enable 1 bitflow 0 = Flow disabled

1 = Flow enabled

Eth_Channel_Mask 1 bitchannelflow

0 = Do not use this flow match group for this channel1 = Use this flow match group for this channel

Eth_VLAN_Tags 2 bit Configures the number of VLAN tags in the frame (0 1 or 2)

Eth_VLAN_Tag1_Type 1 bit Configures the VLAN tag type for VLAN tag 1If PBB is not enabled0 = C-tag value of 0x81001 = S-tag match to the value in CONF_VLAN_TPID (global for all portsdirections)If PBB enabled0 = S-tag (or B-tag) to the value in CONF_VLAN_TPID (global for all portsdirections)There must be 2 VLAN tags 1 S-tag and one I-tag1 = I-tag

Eth_VLAN_Tag2_Type 1 bit Configures the VLAN tag type for VLAN tag 2If PBB is not enabled0 = C-tag value of 0x81001 = S-tag match to the value in CONF_VLAN_TPID (global for all portsdirections)If PBB enabledThe second tag is always an I-tag and this register control bit is not used The second tag in PBB is always an I-tag

Eth_Ethertype_Mode 1 bit 0 = Only type 2 Ethernet frames supported no SNAPLLC expected1 = Type 1 amp 2 Ethernet packets supported Logic looks at the Ethertypelength field to determine the packet type If the field is a length (less than 0x0600) then the packet is a type 1 packet and MUST include a SNAP amp 3-byte LLC header If the field is not a length it is assumed to be an Ethertype and SNAPLLC must not be present

Eth_VLAN_Verify_Ena 1 bit 0 = Parse for presence of VLAN tags but do not check the values For PBB mode the I-tag is still always checked1 = Verify the VLAN tag configuration including number and value of the tags

Eth_VLAN_Tag_Mode 2 bit 0 = No range checking on either VLAN tag1 = Range checking on VLAN tag 12 = Range checking on VLAN tag 2

Eth_Addr_Match 48 bit Matches an address field selected by Eth_Addr_Match_Mode

Eth_Addr_Match_Select 2 bit Selects the address to match0 = Match the destination address1 = Match the source address2 = Match either the source or destination address3 = Reserved do not use

Eth_Addr_Match_Mode 3 bits per flow Selects the address match mode One or multiple bits can be set in this mode register allowing any combination of match types For unicast or multicast modes only the MSB of the address field is checked (0 = unicast 1 = multicast) See section 3231 of 8023 for more details0 = Match the full 48-bit address1 = Match any unicast address2 = Match any multicast address

Eth_VLAN_Tag1_Match 12 bit Match field for the first VLAN tag (if configured to be present)

Eth_VLAN_Tag1_Mask 12 bit Mask for the first VLAN tag If a match set is not used set this register to all 0s

Eth_VLAN_Tag2_Match 12 bit Match field for the update VLAN tag (if configured to be present)

Eth_VLAN_Tag2_Mask 12 bit Mask for the second VLAN tag If a match set is not used set this register to all 0s

Table 22 bull Ethernet Comparator (Flow) (continued)

Parameter Width Description

If the Ethernet block is part of the OAM optimized engine there are two sets of next-protocol configuration registers Both sets are identical except one has an _A suffix and the other has a _B suffix In the per-flow registers an additional register ETH_NXT_PROT_SEL is included to map a particular flow with a set of next protocol register set This function allows the Ethernet block within the OAM-optimized engine to act like two separate engines with a configurable number of flows assignable to each (with a total maximum number of eight flows) It effectively allows two separate protocol encapsulation stacks to be handled within the engine

36162 MPLS ComparatorThe MPLS comparator block counts MPLS labels to find the start of the next protocol The MPLS header can have anywhere from 1 to 4 labels Each label is 32 bit long and has the format shown in the following illustration

Figure 48 bull MPLS Label Format

The S bit is used to indicate the last label in the stack as follows If S = 0 then there is another label If S = 1 then this is the last label in the stack

Also the MPLS stack can optionally be followed by a control word (CW) This is configurable per flow

The following illustration shows a simple Ethernet packet with either one label or three labels and no control word

Figure 49 bull MPLS Label Stack within an Ethernet Frame

The following illustration shows an Ethernet frame with four labels and a control word Keep in mind that this comparator is used to compare the MPLS labels and control words the Ethernet portion is checked in the first stage

Figure 50 bull MPLS Labels and Control Word

There could be VLAN tags between the SA and the Etype fields and potentially a LLC and SNAP header before the MPLS stack but these would be handled in the EthernetLLCSNAP comparator

Eth_VLAN_Tag_Range_Upper 12 bit Upper limit of the range for one of the VLAN fields selected by ETH_VLAN_TAG_MODE register If PBB mode is enabled this register is not used for range checking but rather is the upper 12 bit of the I-tag

Eth_VLAN_Tag_Range_Lower 12 bit Lower limit of the range for one of the VLAN fields selected by ETH_VLAN_TAG_MODE register If PBB mode is enabled this register is not used for range checking but rather is the lower 12 bit of the I-tag SID

Eth_Nxt_Prot_Grp_Sel 1 bit Per flow maps a particular flow to a next-protocol group register set This register only appears in the Ethernet block in the OAM-optimized engine

11 10 9 815 14 13 1219 18 17 16 5 4 3 2 1 07 6 2 1 0 2 1 05 4 37 6Class S Time To LiveLabel

Destination Address (DA) Source Address (SA) Etype Label (S=1)5 4 3 2 1 0 5 4 3 2 1 0 1 0 3 2 1 0

PayloadCW=0

Source Address (SA) Etype Label (S=0)5 4 3 2 1 0 5 4 3 2 1 0 1 0 3 2 1 0Destination Address (DA) PayloadLabel (S=0) Label (S=1)

3 2 1 0 3 2 1 0CW=0

Source Address (SA) Etype Label (S=0)5 4 3 2 1 0 5 4 3 2 1 0 1 0 3 2 1 0Destination Address (DA) Label (S=0) Label (S=1)

3 2 1 0 3 2 1 0PayloadLabel (S=0) Control

3 2 1 0 3 2 1 0CW=1

The only configuration registers that apply to all flows within the comparator are the match_mode register and the nxt_comparator register The match mode register determines how the match filters are used and there is one per stage Each flow has it own complete set of match registers

Table 23 bull MPLS Comparator Next Word

Parameter Width DescriptionMPLS_Nxt_Comparator 3 bit Pointer to the next comparator

Table 24 bull MPLS Comparator Per-Flow

Parameter Width DescriptionMPLS_Flow_Enable 1 bit per flow 0 = Flow disabled

1 = Flow enabled

MPLS_Channel_Mask 1 bit per channel per flow

MPLS_Ctl_Word 1 bit Indicates if there is a 32-bit control word after the last label This should only be set if the control word is not expected to be an ACH header ACH headers are checked in the IP block If the control word is a non-ACH control word only the upper 4 bits of the control are checked and are expected to be 00 = There is no control word after the last label1 = There is expected to be a control word after the last label

MPLS_REF_PNT 1 bit The MPLS comparator implements a searching algorithm to properly parse the MPLS header The search can be performed from either the top of the stack or the end of the stack0 = All searching is performed starting from the top of the stack1 = All searching if performed from the end of the stack

MPLS_STACK_DEPTH 4 bit Each bit represents a possible stack depth as shown in the following list

MPLS_STACK_DEPTH Bit0123

Allowed Stack Depth1234

Table 25 bull MPLS Range_UpperLower Label Map

ParameterMPLS_REF_PNT = 0 top-of-stack referenced

MPLS_REF_PNT=1 end-of-stack referenced

MPLS_Range_UpperLower_0 Top label Third label before the end label

MPLS_Range_UpperLower_1 First label after the top label Second label before the end label

MPLS_Range_UpperLower_2 Second label after the top label First label before the end label

MPLS_Range_UpperLower_3 Third label after the top label End label

The offset to the next protocol is calculated automatically It is based upon the number of labels found and whether a control word is configured to be present It points to the first octet after the last label or after the control word if present

If an exact label match is desired set the upper and lower range values to the same value If a label value is a dont care then set the upper value to the maximum value and the lower value to 0

The MPLS comparator block used in the OAM-optimized engine differs from the one used in the PTP-optimized engine

Just like the Ethernet comparator block there are two sets of next protocol blocks along with a next protocol association configuration field per-flow This allows two different encapsulations to occur in a single engine

36163 IPUDPACH ComparatorThe IPUDPACH comparator is used to verify one of three possible formats IPv4 IPV6 and ACH Additionally IPv4 and IPv6 can also have a UDP header after the IP header There are two of these comparators and they can operate at stages 2 3 or 4 of the analyzer pipeline Note that if there is an IP-in-IP encapsulation a UDP header will only exist with the inner encapsulation

36164 IPv4 Header FormatThe following illustration shows an IPv4 frame header followed immediately by a UDP header IPv4 does not always have the UDP header but the comparator is designed to work with or without it The Header Length field is used to verify the offset to the next protocol It is a count of 32-bit words and does not include the UDP header If the IPv4 frame contains a UDP header the Source and Destination ports are also checked These values are the same for all flows within the comparator Note that IPv4 options extended headers and UDP fragments are not supported

Figure 51 bull IPv4 with UDP

Per flow validation is performed on the Source or Destination Address in the IPv4 header The comparator can be configured to indicate a match in the flow if the source destination or either the source or destination fields match

Table 26 bull Next MPLS Comparator

Parameter Width DescriptionMPLS_Range_Lower 20 bit times 4 labels Lower value of the label range when range checking

is enabled

MPLS_Range_Upper 20 bit times 4 labels Upper value of the label range when range checking is enabled

Table 27 bull Next-Protocol Registers in OAM-Version of MPLS Block

Parameter Width DescriptionMPLS_Nxt_Prot_Grp_Sel 1 bit per flow Maps each flow to next-protocol-register set A or B

Version Hdr Length Total Length

Identification Flags Fragment Offset

Source Address

Destination Address

0

00

31

16128

3 2 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 411 10 9 82 1 0 123 2 1 07 6 5 411 10 9 815 14 13 12

11 10 9 815 14 13 123 2 1 0

OctetBit

Source Port Destination Port

Length Checksum (over-write with 0)24192UDP

Differentiated Services

3 2 1 07 6 5 43 2 1 07 6 5 4 3 2 1 07 6 5 411 10 9 815 14 13 12Header ChecksumTime to Live ProtocolIPv4

36165 IPv6 Header FormatThe following illustration shows an IPv6 frame header followed immediately by a UDP header IPv6 does not always have the UDP header but the comparator is designed to work with or without it The Next Header field is used to verify the offset to the next protocol It is a count of 32-bit words and does not include the UDP header If the IPv6 frame contains a UDP header the Source and Destination ports are also checked These values are the same for all flows within the comparator

If the IPv6 frame is the inner most IP protocol then the checksum field must be valid This is accomplished using a pair of pad bytes after the PTP frame The checksum is computed using ones compliment of the ones compliment sum of the IPv6 header UDP header and payload including the pad bytes If any of the fields in the frame are updated the pad byte field must be updated so that the checksum field does not have to be modified

Note IPv6 extension headers are not supported

36166 ACH Header FormatThe following illustrations show ACH headers They can appear after a MPLS label stack in place of the control word ACH is verified as a protocol only There are no flows within the protocol for ACH The ACH header can optionally have a Protocol ID field The protocol is verified using the Version Channel Type and optional Protocol ID field

Figure 53 bull ACH Header Format

Figure 54 bull ACH Header with Protocol ID Field

36167 IPSecIPSec adds security to the IP frame using an Integrity Check Value (ICV) a variable-length checksum that is encoded with a special key The key value is known by the sender and the receiver but not any of

Version Traffic Class Flow Label

Payload Length Next Header Hop Limit

Source Address

Destination Address

0

00

31

24288

3 2 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 43 2 1 07 6 5 43 2 1 07 6 5 411 10 9 815 14 13 12

11 10 9 815 14 13 1219 18 17 16

OctetBit

Length Checksum40352UDP 3 2 1 07 6 5 411 10 9 815 14 13 12

3 2 1 07 6 5 411 10 9 815 14 13 12

IPv6

0x1 Reserved Channel Type

Protocol ID or Payload Payload

0

00

31

3 2 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 411 10 9 815 14 13 12

11 10 9 815 14 13 12

OctetBit

3 2 1 0

Version

432

3 2 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 411 10 9 815 14 13 122 1 0

Version

3 2 1 07 6 5 411 10 9 815 14 13 12Protocol ID

0 31Octet Bit

00

432

the devices in between A frame must have a correct ICV to be valid The sequence number field is a continuously incrementing value that is used to prevent replay attacks (resending a known good frame)

Little can be done with frames when IPSec is used because the IEEE 1588 block cannot recalculate the ICV and the frame cannot be modified on egress Therefore one-step processing cannot be performed- only two-step processing can be done The only task here is to verify the presence of the protocol header Stored time stamps in the TS FIFO are used to create follow-up messages On ingress the time stamp can be added to the PTP frame by writing it into the reserved bytes or by overwriting the CRC with it and appending a new CRC The CPU must know how to handle these cases correctly

The following illustration shows the format of the IPSec frame It normally appears between the IP header (IPv4 or IPv6) and the UDP header or at the start of the payload

Figure 55 bull IPSec Header Format

There is only one set of matchmask registers associated with IPSec and they are used to verify the presence of the IPSec header The following illustration shows the largest possible IP frame header with IPv6 IPSec and UDP

Figure 56 bull IPv6 with UDP and IPSec

Next Header Reserved

Security Parameters Index (SPI)

Integrity Check Value (ICV)

0

00

31

864

7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 411 10 9 815 14 13 1219 18 17 1623 22 21 2027 26 25 2431 30 29 28

11 10 9 815 14 13 123 2 1 0

OctetBitPayload Length

19 18 17 1623 22 21 2027 26 25 2431 30 29 28 3 2 1 07 6 5 411 10 9 815 14 13 12Sequence Number

variable of octets

Source Address

Destination Address

0

00

31

36288

3 2 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 43 2 1 07 6 5 43 2 1 07 6 5 411 10 9 815 14 13 12

11 10 9 815 14 13 1219 18 17 16

OctetBit

Length Checksum

48384

UDP 3 2 1 07 6 5 411 10 9 815 14 13 12

3 2 1 07 6 5 411 10 9 815 14 13 12

IPv6

Security Parameters Index (SPI)7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4

3 2 1 07 6 5 411 10 9 815 14 13 1219 18 17 1623 22 21 2027 26 25 2431 30 29 28

11 10 9 815 14 13 123 2 1 0

3 2 1 07 6 5 411 10 9 815 14 13 1219 18 17 1623 22 21 2027 26 25 2431 30 29 28Sequence Number

Integrity Check Value (ICV)variable of octets

Next Header ReservedPayload Length

IPSec

36168 Comparator Field SummaryThe following table shows a summary of the fields and widths to verify IPv4 IPv6 and ACH protocols

361681 IPACH Comparator Next ProtocolThe following table shows the registers used to verify the current header protocol and the next protocol They are universal and cover IPv4 IPv6 and ACH They can also be used to verify other future protocols

Table 28 bull Comparator Field Summary

Protocol Next Protocol Fields NPF Bit Widths Flow Fields Flow Bit WidthsIPv4 Header length One 4-bit field Source

Destination Address

One 32-bit field

UDP SourceDestination Port One 32-bit field

IPv6 Next header One 8-bit field Source Destination Address

One 128-bit field

ACH Entire ACH header One 64-bit field

IPSec Next HeaderPayload Length SPI

One 64-bit field

Table 29 bull IPACH Next-Protocol Comparison

Parameter Width DescriptionIP_Mode 2 bit Specifies the mode of the comparator If IPv4 or IPv6 is selected the

version field is automatically checked to be either 4 or 6 respectively If another protocol mode is selected then the version field is not automatically checked In IPv4 the fragment offset field must be 0 and the MF flag bit (LSB of the flag field) must be 00 = IPv41 = IPv62 = Other protocol 32-bit address match 3 = Other protocol 128-bit address match

IP_Prot_Match_1 8 bit Match bit for Protocol field in IPv4 or next header field in IPv6

IP_Prot_Mask_1 8 bit Mask bits for IP_Prot_Match_1 For each bit if it is a 1 the corresponding match bit is valid If it is 0 the corresponding match bit is ignored Disable this matchmask set by setting the mask register to all 0rsquos

IP_Prot_Offset_1 5 bit Indicates the starting position relative to the beginning of the IP frame header to start matching for the matchmask 1 register pair

IP_Prot_Match_2 64 bit Match bits for the IPSec header or any other desired field For ACH this register should be used to match the ACH header

IP_Prot_Offset_2 7 bit Indicates the starting position relative to the beginning of the IP frame header to start matching for the matchmask two-register pair

The IPACH Comparator Flow Verification registers are used to verify the current frame against a particular flow within the engine When this engine is used to verify IPv4 or IPv6 protocol the flow is verified using either the source or destination address in the frame

If the protocol is something other than IPv4 or IPv6 then the flow match can be used to match either a 32 or 128 bit field pointed to by the IP_Flow_Offset register Mask bits can be used to shorten the length of the match but there is no concept of source or destination address in this mode

IP_Nxt_Protocol 8 bit Points to the start of the next protocol relative to the beginning of this header It is the responsibility of the programmer to determine this offset it is not calculated automatically Each flow within an encapsulation engine must have the same encapsulation order and each header must be the same length This field is current protocol header length in bytes

IP_Nxt_Comparator 3 bit Pointer to the next comparator0 = Reserved 1 = Ethernet comparator 22 = IPUDPACH comparator 13 = IPUDPACH comparator 24 = Reserved 5 = PTPOAM comparator 67 = Reserved

IP_Flow_Offset 5 bit Indicates the starting position relative to the beginning of the IP frame header to start matching for the flow matchmask register pair When used with IPv4 or 6 this will point to the first byte of the source address When used with a protocol other that IPv4 or 6 this register points to the beginning of the field that will be used for flow matching

IP_UDP_Checksum_Clear_Ena

1 bit If set the 2-byte UDP checksum should be cleared (written with zeroes) This would only be used for UDP in IPv4

IP_UDP_Checksum_Update_Ena

1 bit If set the last two bytes in the UDP frame must be updated to reflect changes in the PTP or OAM frame This is necessary to preserve the validity of the IPv6 UDP checksumNote that IP_UDP_Checksum_Clear_Ena amp IP_UDP_Checksum_Update_Ena should never be set at the same time

IP_UDP_Checksum_Offset

8 bit This configuration field is only used if the protocol is IPv4 This register points to the location of the UDP checksum relative to the start of this header This info is used later by the PTPY1731 block to inform the rewriter of the location of the checksum in a UDP frame This is normally right after the Log Message Interval field

IP_UDP_Checksum_Width

2 bit Specifies the length of the UDP checksum in bytes (normally 2 bytes)

Table 30 bull IPACH Comparator Flow Verification Registers

Parameter Width DescriptionIP_Flow_Ena 1 bit per flow 0 = Flow disabled

1 = Flow enabled

Table 29 bull IPACH Next-Protocol Comparison (continued)

36169 PTPOAM ComparatorThe PTPOAM comparator is always the last stage in the analyzer for each encapsulation engine It can validate IEEE 1588 PTP frames or OAM frames

361610 PTP Frame HeaderThe following illustration shows the header of a PTP frame

Figure 57 bull PTP Frame Layout

Unlike most of the other stages there is no protocol validation for PTP frames only interpretation of the header to determine what action to take The first eight bytes of the header are used to determine the action to be taken These match fields in the flow comparison registers with a corresponding set of command registers for each flow

361611 Y1731 OAM Frame Header1DM DMM and DMR are the three supported Y1731 frame headers The following illustration shows the header part of a 1DM Y1731 OAM frame

IP_Flow_Match_Mode 2 bit per flow This register is only valid when the comparator block is configured to match on IPv4 or IPv6 It allows the match to be performed on the source address destination address or either address0 = Match on the source address 1 = Match on the destination address 2 = Match on either the source or the destination address

IP_Flow_Match 128 bit Match bits for source amp destination address in IPv4 amp 6 Also used as the flow match for protocols other than IPv4 or 6 When used with IPv4 only the upper 32 bits are used and the remaining bits are not used

IP_Flow_Mask 128 bit Mask bits for IP_Flow_Match For each bit if it is a 1 the corresponding match bit is valid If it is 0 the corresponding match bit is ignored

IP_Channel_Mask 1 bit per channel per flow

Enable for this match set for this channel

IP_Frame_Sig_Offset 5 bit Points to the start of the field that will be used to build the frame signature This register is only present in comparators where frame signature is supported In other words if there is no frame signature FIFO in a particular direction this register will be removed

Table 30 bull IPACH Comparator Flow Verification Registers (continued)

Tspt Spcfc Msg Type Message Length

Reserved

Correction Field

0

00

31

3 2 1 0 3 2 1 03 2 1 0 3 2 1 07 6 5 4

3 2 1 07 6 5 411 10 9 815 14 13 123 2 1 07 6 5 43 2 1 07 6 5 4

11 10 9 815 14 13 123 2 1 0

OctetBit

32256

Rsvd

Flag FieldDomain Number Reserved

Vrsn PTP

Source Port Identity [150] Sequence ID3 2 1 07 6 5 43 2 1 07 6 5 4

3 2 1 07 6 5 4

11 10 9 815 14 13 1211 10 9 815 14 13 12

43 42 41 4047 46 45 44 35 34 33 3239 38 37 36 19 18 17 1623 22 21 2027 26 25 2431 30 29 28

3 2 1 07 6 5 4Control Field Log Message Interval

Source Port Identity [4716]75 74 73 7279 78 77 76 67 66 65 6471 70 69 68 51 50 49 4855 54 53 5259 58 57 5663 62 61 60

Source Port Identity [7948]

Figure 58 bull OAM 1DM Frame Header Format

The following illustration shows a DMM frame header

Figure 59 bull OAM DMM Frame Header Format

The following illustration shows a DMR frame header

Figure 60 bull OAM DMR Frame Header Format

As with PTP there is no protocol validation for Y1731 frames only interpretation of the header to determine what action to take The first four bytes of the header are used to determine the action to be taken

361612 Y1731 OAM PDU1DM DMM and DMR are the three supported G81131 PDUs and DMMDMR are the two supported RFC6374 PDUs The following illustrations show the PDU formats

MEG Version (0) Flags (0)

Reserved for 1DM Receiving Equipment (0)

0

00

31

42 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 43 2 1 0

OctetBit

End TLV (0)20160

TxTimeStampf

Opcode (1DM=45)

3 2 1 07 6 5 4

TLV Offset (16)

(for TxTimeStampf )

1DM Frame Header Format

End TLV (0)

Reserved for DMM Receiving Equipment (0)

0

00

31

42 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 43 2 1 0

OctetBit

36288

TxTimeStampf

Opcode (1DM=47)

3 2 1 07 6 5 4

3 2 1 07 6 5 4TLV Offset (32)

(for RxTimeStampf )

Reserved for DMR (0)(for TxTimeStampb )

Reserved for DMR Receiving Equipment (0)

DMM Frame Header Format

End TLV (0)

MEG Version Flags

RxTimeStampf

0

00

31

42 1 0 3 2 1 07 6 5 4 3 2 1 07 6 5 43 2 1 0

OctetBit

36288

TxTimeStampf

Opcode (DMR=46)

3 2 1 07 6 5 4

TLV Offset

TxTimeStampb

Reserved for DMR Receiving Equipment (0)(for RxTimeStampb )

DMR Frame Header Format

Figure 62 bull G81131draft-bhh DMMDMR1DM OAM PDU Format

As with PTP there is no protocol validation for MPLS OAM only interpretation of the header to determine what action to take The first four bytes of the header are used to determine the action to be taken

361613 PTP Comparator Action Control RegistersThe following registers perform matching on the frame header and define what action is to be taken based upon the match There is one mask register for all flows and the rest of the registers are unique for each flow

Table 31 bull PTP Comparison

Parameter Width DescriptionPTP_Flow_Match 64 bit Matches bits in the PTPY1731 frame starting at the

beginning of the protocol header

PTP_Flow_Mask 64 bit Mask bits for PTP_Flow_Match

PTP_Domain_Range_Lower 8 bit Lower range of the domain field to match

PTP_Domain_Range_Upper 8 bit Upper range of the domain field to match

ETH (1)

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

padding

FCSDM

MD

MR

OAM

PDU

s

141822B

481216B

4B

8B

(variable size)

4B

ETH (1)

DMMDMR

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

End TLV indicator

FCS

DM

MD

MR

OAM

PDU

s

141822B

481216B

4B

8B

1B

4B

ETH (1)

1DM

MPLS labels (2)

ACH

OAM PDU Header

Time stamp 1

End TLV indicator

FCS

1DM

OA

M P

DUs141822B

481216B

4B

8B

4B

1B

PTP_Domain_Range_Enable

1 bit Enable for range checking

PTP_Domain_Offset 5 bit Pointer to the domain field or whatever field is to be used for range checking

PTP_Action_Command 3 bit CommandValue Mnemonic Action0 NOP Do nothing

1 SUB New correction field = Current correction field ndashCaptured local time

2 SUB_P2P New correction field = Current correction field ndashLocal latency + path_delay

3 ADD New correction field = Current correction field + Captured local time

4 SUB_ADD New correction field = Current correction field + (Captured local time + Local latency ndash Time storage field)

5 WRITE_1588 Write captured local time to time storage field

6 WRITE_P2P Active_timestamp_ns = captured local time and path_delay written to time storage field and correction field (deprecated command)

7 WRITE_NS Write local time in nanoseconds to the new field

8 WRITE_NS_P2P

Write local time in nanoseconds + p2p_delay to the new field and correction field

PTP_Save_Local_Time 1 bit When set saves the local time to the time stamp FIFO (only valid for egress ports)

PTP_Correction_Field_Offset 5 bit Points to the location of the correction field Location is relative to the first byte of the PTPOAM header

PTP_Time_Storage_Field_Offset

6 bit Points to a location in a PTP frame where a time value can be stored or read

PTP_Add_Delay_Asymmetry_Enable

1 bit When enabled the value in the delay asymmetry register is added to the correction field of the frame

PTP_Subtract_Delay_Asymmetry_Enable

1 bit When enabled the value in the delay asymmetry register is subtracted from the correction field of the frame

PTP_Zero_Field_Offset 6 bit Points to a location in the PTPOAM frame to be zeroed if this function is enabled

PTP_Zero_Field_Byte_Count 4 bit The number of bytes to be zeroed If this field is 0 then this function is not enabled

Table 31 bull PTP Comparison (continued)

The following table shows controls that are common to all flows

The following table shows the one addition per-flow register

361614 Future Protocol CompatibilityExcept for MPLS the comparators are not hardwired to their intended protocols They can be used as generic field and range comparators because all of the offsets or pointers to the beginning of the fields are configurable The IP comparator is the most generic and would probably be the first choice for validating a new protocol

Additionally if there are not enough comparison resources in a single comparator block to handle a new protocol two comparators back-to-back can used by splitting up the comparison work One portion can be validated in one comparator and then handed off to another The only restriction is that there must be

PTP_Modified_Frame_Byte_Offset

3 bit Indicates the position relative to the start of the PTP frame in bytes where the Modified_Frame_Status bit resides This value is also used to calculate the offset from the beginning of the Ethernet packet to this field for use by the Rewriter

PTP_Modified_Frame_Status_Update

1 bit If set tells the rewriter to update the value of this bit Configuration registers inside the rewriter indicate if the bit will be set to 0 or 1

PTP_Rewrite_Bytes 4 bits Number of bytes in the PTP or OAM frame that must be modified by the Rewriter for the time stamp

PTP_Rewrite_Offset 8 bits Points to where in the frame relative to the SFD that the time stamp should be updated

PTP_New_CF_Loc 8 bits Location where the updated correction field value is written relative to the PTP header start

PTP_Channel_Mask 1 bit per channel per flow

PTP_Flow_Enable 1 bit When set the fields associated with this flow are all valid

Table 32 bull PTP Comparison Common Controls

Parameter Width DescriptionPTP_IP_CHKSUM_Sel 1 bit 0 = Use IP checksum controls from comparator 1

1 = Use IP checksum controls from comparator 2

FSB_Adr_Sel 2 bits Selects the source of the address for use in the frame signature builder

Table 33 bull PTP Comparison Additions for OAM-Optimized Engine

Parameter Width DescriptionPTP_NXT_Prot_Group_Mask 2 bits There are two bits for each flow Each bit indicates if the

flow can be associated with next-protocol group A or B One or both bits may be set If a bit is 1 for a particular next-protocol group then a flow match is valid if the prior comparator stages also produced matches with the same next-protocol group

at least one 64-bit word of separation between the start of the protocol and where the second starts to operate

361615 ReconfigurationThere are three ways to perform reconfiguration

1 Disable an entire encapsulation engineOnce an engine has been disabled any of the configuration registers associated with it may be modified in any order If other encapsulation engines are still active they will still operate normally

2 Disable a flow in an active engineEach stage in the engine has an enable bit for each flow If a flow is disabled in a stage its registers may be modified Once reconfiguration for a flow in a stage is complete it can be enabled

3 Disable a comparatorEach comparator within the active encapsulation engine can be disabled If an Ethernet header according to the configuration Type I or Type II with SNAPLLC is not found then subsequent flows will not be matched The ETH1 comparator can also be disabled so that all frames flowing through the IEEE 1588 block are time stamped

The disabling of engines and flows is always done in a clean manner so that partial matches do not occur Flows and engines are always enabled or disabled during inter-packet gaps or at the end of a packet This guarantees that when a new packet is received that it will be analyzed cleanly

If strict flow matching is enabled and a flow is disabled in one of the stages then the entire flow is automatically disabled

If any register in a stage that applies to all flows needs to be modified then the entire encapsulation engine must be disabled

361616 Frame Signature BuilderAlong with time stamp and CRC updates the analyzer outputs a frame signature that can be stored in the time stamp FIFO to help match frames with other info in the FIFO This information is used by the CPU so that it can match time stamps in the time stamp FIFO with actual frames The frame signature is up to 16 bytes long and contains information from the Ethernet header (SA or DA) IP header (SA or DA) and from the PTP or OAM frame The frame signature is only used in the egress direction

The PTP block contains a set of mapping registers to configure which bytes are mapped into the frame signature The following tables show the mapping for each byte

Table 34 bull Frame Signature Byte Mapping

Select Source Byte0-23 PTP header byte number = (31-select)

24 PTP header byte number 6

27 Reserved

28-35 Selected address byte (select-28)

Table 35 bull Frame Signature Address Source

Parameter Width DescriptionFSB_Map_Reg_0-15 6 bits For each byte of the frame signature use Table 34 page 85 to

select which available byte is used Frame signature byte 0 is the LSB If not all 16 bytes are needed the frame signature should be packed towards the LSB and the upper unused byte configuration values do not need to be programmed

Configuration registers in each comparator block supply an address to select if it is the source address or the destination address

A frame signature can be extracted from frames matching in all the three engines The frame signature address selection is limited to Ethernet Block1 because only a limited number of encapsulations are supported in the third engine Engine C

Engine C has two parts part A and part B Part A supports ETH1 ETH2 MPLS protocols while part B supports only ETH1 protocol Selection of Ethernet block 1 or 2 is dependent on whether part A flow matches or part B flow matches

If a frame matches part A flow configuration then the frame signature as configured in ETH1_NXT_PROTOCOL_A and ETH2_NXT_PROTOCOL_A using FSB_ADR_SEL will be considered in computing the frame signature

If a frame matches part B flow configuration then the frame signature as configured in ETH1_NXT_PROTOCOL_A and FSB_ADR_SEL will be considered in computing the frame signature In this configuration if FSB_ADR_SEL is set to 1 to select ETH2 then all zeros are padded as frame signature because ETH2 is not supported by part B

361617 Configuration SharingThe analyzer configuration services both channels Each flow within each comparator has a channel-mask register that indicates which channels the flow is valid for Each flow can be valid for channel A channel B or both channels

A total of eight flows can be allocated the two channels if the analyzer configuration cannot be shared They can each have four distinct flows (or three for the one and five for the other etc)

361618 OAM-Optimized EngineThe OAM optimized engine Engine C supports a fewer set of encapsulations such as ETH1 ETH2 MPLS and ACH Engine C is was enhanced with an ACH comparator to support the MPLS-TP OAM protocol The MPLS-TP OAM protocol for Engine C is configured in the following registers

bull EGR2_ACH_PROT_MATCH_UPPERLOWER_Abull EGR2_ACH_PROT_MASK_UPPERLOWER_Abull EGR2_ACH_PROT_OFFSET_AThe ACH comparator will start the comparison operation right after the MPLS comparator

In addition to the descriptions of the Ethernet and MPLS blocks in the OAM optimized engine there is the notion of protocol-Aprotocol-B When a match occurs in the Ethernet 1 block the status of the protocol set that produced the match is indicated There are two bits one for protocol A and another for protocol B If both sets produce a match then both bits are set

These bits are then carried to the next comparison block and only allow flow matches for the protocol sets that produced matches in the prior block This block also produces a set of protocol match bits that are also carried forward

This feature is provided to prevent a match with protocol set A in the first block and protocol set B in the second block

FSB_Adr_Sel 2 bits Selects the source of the address for use in the frame signature builder according to the following list

Select Value0123

Address SourceEthernet block 1Ethernet block 2IP block 1IP block 2

Table 35 bull Frame Signature Address Source (continued)

3617 Time Stamp ProcessorThe primary function of the time stamp processor block is to generate a new Timestamp_field or new Correction_field (Transparent clocks) for the rewriter block The time stamp block generates an output that is either a snapshot of the corrected Local Time (struct time stamp) or a signed (twos complement) 64 bit Correction_field

In the ingress direction the time stamp block calculates a new time stamp for the rewriter that indicates the earlier time when the corresponding PTP event frame entered the chip (crossed the reference plane referred to in the IEEE 1588 standard)

In the egress direction the time stamp block calculates a new time stamp for the rewriter in time for the PCS block to transmit the new time stamp field in the frame In this case the time stamp field indicates when the corresponding PTP event frame will exit the chip

Transparent clocks correct PTP event messages for the time resided in the transparent clock Peer-to-Peer transparent clocks additionally correct for the propagation time on the inbound link (Path_delay) The Path_delay [ns] input to the time stamp block is software programmed based upon IEEE 1588 path delay measurements

In general the IEEE 1588 standard allows for a transparent clock to update the Correction_Field for both PTP event messages as well as the associated follow up message (for two-step operation) However the TSP only updates PTP event messages Also the 1588 standard allows that end-to-end transparent clocks correct and forward all PTP-timing messages while Peer-to-Peer transparent clocks only correct and forward Sync and Follow_Up messages Again the TSP only updates PTP event messages (not Follow_Up messages)

Internally the time stamp block generates an Active_timestamp from the capturedtime stamped Local time (Raw_timestamp) The Active_time stamp is the Raw_timestamp corrected for the both fixed (programmed) local chip and variable chip latencies relative to where the Start_of_Frame_Indicator captures the local time The time stamp block operates on the Active_timestamp based on the Command code

The Active_timestamp is calculated differently in the Ingress and Egress directions and the equations are given below

In the ingress direction

Active_timestamp = Raw_timestamp - Local_latency - Variable_latencyIn the egress direction

Active_timestamp = Raw_timestamp + Local_latency + Variable_latencyIn addition the following values are also calculated for use by the commands

Active_timestamp_ns = Active_timestamp converted to nanosecondsActive_timestamp_p2p_ns = active_timestamp_ns + path delayThe Local_latency is a programmed fixed value while the Variable_latency is predicted from the PCS logic based upon the current state of the ingress or egress data pipeline

For the option of Peer-to-Peer transparent clocks the ingress Active_timestamp calculation includes an additional Path_delay component The path delay is always added for a transparent clock per the standard The path delay is always added to the correction field

The signed 32-bit twos complement Delay Asymmetry register (bits 31ndash0) can be programmed by the user Bit 31 is the sign bit Bits 15ndash0 are scaled nanoseconds just like for the CorrectionField format The DelayAsymmetry register (whether it be positive or negative) will be sign extended and added to the 64-bit correction field (signed add) if the Add_Delay_Asymmetry bit is set The DelayAsymmetry register (whether it be positive or negative) will be sign extended and subtracted from the 64-bit correction field (signed Subtract) if the Subtract_Delay_Asymmetry bit is set

The time stamp block keeps a shadow copy of the programmed latency values (Local_latency Path_delay and Delay_Asymmetry) to protect against CPU updates

3618 Time Stamp FIFOThe time stamp FIFO stores time stamps along with frame signature information This information can be read out by a CPU or pushed out on a dedicated Serial Time Stamp Output Interface and used in 2-step processing mode to create follow-up messages The time stamp FIFO is only present in the egress data path

The time stamp FIFO takes a frame signature from the analyzer and the updated correction field and the full data set for that time stamp is saved to the FIFO This creates an interrupt to the CPU If the FIFO ever overflows this is indicated with an interrupt

The stored frame signature can be of varying sizes controlled by the EGR_TSFIFO_CSREGR_TS_SIGNAT_BYTES register Only the indicated number of signature bytes is saved with each time stamp The saved values are packed so that reducing the number of signature bytes allows more time stamps to be saved

The packing of the time stamp data is done by logic before the write occurs to the FIFO When no compression is used each time stamp may contain 208 bits of information (consisting of 128 bits of frame signature and 80 bits of time stamp data) Therefore a full-sized time stamp is 26 bytes long Compressing the frame signature can reduce this to as little as 10 bytes (or 4 bytes if EGR_TSFIFO_CSREGR_TS_4BYTES = 1) if no signature information is saved (EGR_TSFIFO_CSREGR_TS_SIGNAT_BYTES = 0) The value to store is built up in an internal register When the register contains 26 valid bytes that data is written to the time stamp FIFO Data in the FIFO is packed end-to-end It is up to the reader of the data to unpack the data

The time stamps in the FIFO are visible and accessible for the CPU as a set of 32-bit registers Multiple register reads are required to read a full time stamp if all bits are used Bit 31 in register EGR_TSFIFO_0 contains the current FIFO empty flag which can be used by the CPU to determine if the current time stamps are available for reading If the bit is set the FIFO is empty and no time stamps are available The value that was read can be discarded because it does not contain any valid time stamp data If the bit is 0 (deasserted) the value contains 16 valid data bits of a time stamp The remaining bits should be read from the other registers in the other locations and properly unpacked to recreate the time stamp Care should be taken to read the time stamps one at a time as each read of the last (7th) address will trigger a pop of the FIFO

Time stamps are packed into seven registers named EGR_TSFIFO_0 to EGR_TSFIFO_6 If the time stamp FIFO registers are read to the point that the FIFO goes empty and there are remaining valid bytes in the internal packing register then the packing register is written to the FIFO In this case the registers may not be fully packed with time stamps Flag bits are used to indicate where the valid data ends within the set of seven registers The flag bits are in register EGR_TSFIFO_0EGR_TS_FLAGS (together with the empty flag) and are encoded as follows

000 = Only a partial time stamp is valid in the seven register set

001 = One time stamp begins in the current seven register set

010 = Two time stamps begin in the current seven register set

011 = Three time stamps begin in the current seven register set (4-byte mode)

100 = Four time stamps begin in the current seven register set (4-byte mode)

101 = Five time stamps begin in the current seven register set (4-byte mode)

110 = Six time stamps begin in the current seven register set (4-byte mode)

111 = The current seven register set is fully packed with valid time stamp data

The FIFO empty bit is visible in the EGR_TSFIFO_0EGR_TS_EMPTY register so the CPU can poll this bit to know when time stamps are available There is also a maskable interrupt which will assert whenever the time stamp FIFO level reaches the threshold given in EGR_TSFIFO_CSREGR_TS_THRESH register The FIFO level is also visible in the EGR_TSFIFO_CSREGR_TS_LEVEL register If the time stamp FIFO overflows writes to the FIFO are inhibited The data in the FIFO is still available for reading but new time stamps are dropped

Note Time stamp FIFO exists only in the Egress direction There is no time stamp FIFO in the Ingress direction

3619 Serial Time Stamp Output InterfaceFor each 1588 Processor 0 and 1 time stamp information stored in the Egress direction can be read through either the register interface or through the Serial Time Stamp interface These two ways to read registers are mutually exclusive While enablingdisabling the serial interface is done on a Processor level only one serial interface exists This means the serial interface can be enabled for Processor 0 while the time stamp FIFO can be read through registers for Processor 1 If the serial interface is enabled for both Processor 0 and 1 then the serial interface will arbitrate between two Egress time stamp FIFOs in Processor 0 and 1 and push the data out

The time stamp FIFO serial interface block writes or pushes time stampframe signature pairs that have been enqueued and packed into time stamp FIFOs to the external chip interface consisting of three output pins 1588_SPI_DO 1588_SPI_CLK and 1588_SPI_CS There is one interface for all channels

When the serial interface (SPI) is enabled the time stampframe signature pairs are dequeued from time stamp FIFO(s) and unpacked Unpacked time stampframe signature pairs are then serialized and sent one at a time to the external interface Unpacking shifts the time stampframe signature into alignment considering the configured size of the time stamps and frame signatures (a single SI write may require multiple reads from a time stamp FIFO) The time stamp FIFO serial interface is an alternative to the MDIO register interface described in the time stamp FIFO section When the serial time stamp interface is enabled in register TS_FIFO_SI_CFGTS_FIFO_SI_ENA data read from the time stamp FIFO registers described in Time Stamp FIFO page 88 are invalid

Time stampFrame signature pairs from two egress time stamp FIFOs are serialized one at a time and transmitted to the interface pins The TS_FIFO_SI arbitrates in a round-robin fashion between the ports that have non-empty time stamp FIFOs The port associated with each transmitted time stampframe signature pair is indicated in a serial address that precedes the data phase of the serial transmission Because the time stamp FIFOs are instantiated in the per port clock domains a small single entry asynchronous SI FIFO (per port) ensures that the time stampframe signature pairs are synchronized staged and ready for serial transmission When an SI FIFO is empty the SI FIFO control fetches andor unpacks a single time stampframe signature performing any time stamp FIFO dequeues necessary The SI FIFO goes empty following the completion of the last data bit of the serial transmission Enabled ports (TS_FIFO_SI_CFGTS_FIFO_SI_ENA) participate in the round-robin selection

Register TS_FIFO_SI_TX_CNT accumulates the number of time stampframe signature pairs transmitted from the serial time stamp interface for each channel Register EGR_TS_FIFO_DROP_CNT accumulates the number of time stampframe signature pairs that have been dropped per channel due to a time stamp FIFO overflow

The SPI compatible interface asserts a chip select (SPI_CS) for each write followed by a write command data bit equal to 1 followed by a dont care bit (0) followed by an address phase followed by a data phase followed by a deselect where SPI_CS is negated Each write command corresponds to a single time stampframe signature pair The length of the data phase depends upon the sum of the configured lengths of the time stamp and signature respectively The address phase is fixed at five bits The SPI_CLK is toggled to transfer each SPI_DO bit (as well as the command and address bits) The Time Stamp and Frame Identifier Data from the following illustration are sent MSB first down to LSB (bit 0) in the same format as stored in the seven registers of TS FIFO CSRs For more information see Time Stamp FIFO page 88 and Figure 63 page 90

The frequency of the generated output 1588_SPI_CLK can be flexibly programmed from 10 MHz up to 625 MHz using TS_FIFO_SI_CFG to set the number of CSR clocks that the 1588_SPI_CLK is both high and low For example to generate a 1588_SPI_CLK that is a divide-by-6 of the CSR clock the CSR register would be set such that both SI_CLK_LO_CYCS and SI_CLK_HI_CYCS equal 3 Also the number of CSR clocks after SPI_CS asserts before the first 1588_SPI_CLK is programmable (SI_EN_ON_CYCS) as is the number of clocks before SI_EN negates after the last 1588_SPI_CLK (SI_EN_OFF_CYCS) The number of clocks during which SI_EN is negated between writes is also programmable (SI_EN_DES_CYCS) The 1588_SPI_CLK may also be configured to be inverted (SI_CLK_POL)

Without considering de-selection between writes if the PTP 16-byte SequenceID (frame signature) is used as frame identifier each 10 byte time stamp write take 2 + 55 + 10 times 8 + 16 times 8 = 265 clocks (at

40 MHz) ~6625 ns This corresponds to a time stamp bandwidth of gt 015 M time stampsecondport The following illustration shows the serial time stampframe signature output

Figure 63 bull Serial Time StampFrame Signature Output

3620 RewriterWhen the rewriter block gets a valid indication it overwrites the input data starting at the offset specified in Rewrite_offset and replaces N bytes of the input data with updated N bytes Frames are modified by the rewriter as indicated by the analyzer-only PTPOAM frames are modified by the rewriter

The output of the rewriter block is the frame data stream that includes both unmodified frames and modified PTP frames The block also outputs a count of the number of modified PTP frames in INGR_RW_MODFRM_CNTEGR_RW_MODFRM_CNT depending upon the direction This counter accumulates the number of PTP frames to which a write was performed and includes errored frames

36201 Rewriter Ethernet FCS CalculationThe rewriter block has to recalculate the Ethernet CRC for the PTP message to modify the contents by writing a new time stamp or clear bytes Two versions of the Ethernet CRC are calculated in accordance with IEEE 8023 Clause 329 one on the unmodified input data stream and one on the modified output data stream The input frame FCS is checked against the input calculated FCS and if the values match the frame is good If they do not then the frame is considered a bad or errored frame The new calculated output FCS is used to update the FCS value in the output data frame If the frame was good then the FCS is used directly If the frame was bad the calculated output FCS is inverted before writing to the frame Each version of the FCS is calculated in parallel by a separate FCS engine

A count of the number of PTPOAM frames that are in error is kept in the INGR_RW_FCS_ERR_CNT or EGR_RW_FCS_ERR_CNT register depending upon the direction

36202 Rewriter UDP Checksum CalculationFor IPv6UDP the rewriter also calculates the value to write into the dummy blocks to correct the UDP checksum The checksum correction is calculated by taking the original frames checksum the value in the dummy bytes and the new data to be written and using them to modify the existing value in the dummy byte location The new dummy byte value is then written to the frame to ensure a valid checksum The location of the dummy bytes is given by the analyzer The UDP checksum correction is only performed when enabled using the following register bits

bull INGR_IP1_UDP_CHKSUM_UPDATE_ENAbull INGR_IP2_UDP_CHKSUM_UPDATE_ENAbull EGR_IP1_UDP_CHKSUM_UPDATE_ENAbull EGR_IP2_UDP_CHKSUM_UPDATE_ENABased upon the analyzer command and the rewriter configuration the rewriter writes the time stamp in one of the following ways

bull Using PTP_REWRITE_BYTES to choose four bytes write to PTP_REWRITE_OFFSET This method is similar to other PTP frame modifications and the time stamp is typically written to the reserved field in the PTP header

bull Using PTP_REWRITE_BYTES and RW_REDUCE_PREAMBLE to select the mode of operation when writing Rx time stamps into the frame In these modes it cannot do both a time stamp writeappend and a PTP operation in the same frame If PTP_REWRITE_BYTES = 0xE and RW_REDUCE_PREAMBLE = 1 it does it by overwriting the existing FCS with the time stamp in the lowest four bytes of the calculated time stamp and generating a new FCS and appending it

SPI_CS

SPI_Clk

SPI_DO 4 3 2 1 9 8 7 6 5 4 3 2 1 0

Time stamp (4 or 10 bytes)

0

Frame Identifier Data (0 to 16 bytes)

2 34567891 2 1 00

Port

Because the rewriter cannot modify the IFG or change the size of the frame if the original FCS is overwritten with time stamp data a new FCS needs to be appended and the frame shortened by reducing the preamble The preamble length includes the S character and all preamble characters up to but not including the SFD In this mode it is assumed that all incoming preambles are of sufficient (5 to 7-byte) length to delete four bytes and the preamble of every frame (not only PTP frames) will be reduced by four bytes by deleting four bytes of the preamble Then the new FCS is written at the end of the matched frame For unmatched frames or if the PTP_REWRITE_BYTES is anything but 0xE the IFG is increased by adding four IDLE (I) characters after the T which ends the packet

To time stamp a frame in one of the modes the actual length of the preamble is then checked and if the preamble is too short to allow a deletion of four bytes (if the preamble is not five bytes or more) then no operations are performed on the preamble the FCS is not overwritten and no time stamp is appended For all such frames a counter is maintained and every time an unsuccessful operation is encountered the counter is incremented This counter is read through register INGR_RW_PREAMBLE_ERR_CNTEGR_RW_PREAMBLE_ERR_CNT The following illustration shows the deleted preamble bytes

Figure 64 bull Preamble Reduction in Rewriter

If PTP_REWRITE_BYTES = 0xF and RW_REDUCE_PREAMBLE = 0 the rewriter replaces the FCS of the frame with the four lowest bytes of the calculated time stamp and does not write the FCS to the frame In this mode all the frames have corrupted FCSs and the MAC needs to be configured to handle this case In the case of a CRC error in the original frame the rewriter writes all ones (0xFFFFFFFF) to the FCS instead of the time stamp This indicates an invalid CRC to the MAC because this is reserved to indicate an invalid time stamp In the rare case that the actual time stamp has the value 0xFFFFFFFF and the CRC is valid the rewriter increments the time stamp to 0x0 and writes that value instead This causes an error of 1 ns but is required to reserve the time stamp value of 0xFFFFFFFF for frames with an invalid CRC

A flag bit may also be set in the PTP message header to indicate that the TSU has modified the frame (when set) or to clear the bit (on egress) The analyzer sends the byte offset of the flag byte to the rewriter in PTP_MOD_FRAME_BYTE_OFFSET and indicates whether the bit should be modified or not using PTP_MOD_FRAME_STATUS_UPDATE The bit offset within the byte is programmed in the configuration register RW_FLAG_BIT When the PTP frame is being modified the selected bit is set to the value in the RW_FLAG_VAL This only occurs when the frame is being modified by the rewriter when the PTP frame matches and the command is not NOP

3621 Local Time CounterThe local time counter keeps the local time for the device and the time is monitored and synchronized to an external reference by the CPU The source clock for the counter is selected externally to be a 250 MHz 200 MHz 125 MHz or some other frequency The clock may be a line clock or the dedicated CLK1588PN pins The clock source is selected in register LTC_CTRLLTC_CLK_SEL

To support other frequencies a flexible counter system is used that can convert almost any frequency in the 125ndash250 MHz range into a usable source clock Supported frequencies of local time counter are 125 MHz 15625 MHz 200 MHz and 250 MHz The frequency is programmed in terms of the clock period Set the LTC_SEQUENCELTC_SEQUENCE_A register to the clock period to the nearest whole number of nanoseconds to be added to the local time counter on each clock cycle Set LTC_SEQLTC_SEQ_E to the amount of error between the actual clock period and the LTC_SEQUENCELTC_SEQUENCE_A setting in femtoseconds Register LTC_SEQLTC_SEQ_ADD_SUB indicates the direction of the error

S

Pre1

Pre2

Pre3

Pre4

Pre5

Pre6

SFD0xD5

S

Pre5

Pre6

SFD0xD5

An internal counter keeps track of the accumulated error When the accumulated error exceeds 1 nanosecond an extra nanosecond is either added or subtracted from the local time counter Use the following as an example to program a 59 ns period

LTC_SEQUENCELTC_SEQUENCE_A = 6 (6 ns)LTC_SEQLTC_SEQ_E = 100000 (01 ns)LTC_SEQLTC_SEQ_ADD_SUB = 0 (subtract an extra nanosecond ie add 5 ns)To support automatic PPM adjustments an internal counter runs on the same clock as the local time counter and increments using the same sequence to count nanoseconds The maximum (rollover) value of the internal counter in nanoseconds is given in register LTC_AUTO_ADJUSTLTC_AUTO_ADJUST_NS At rollover the next increment of the local time counter is increased by one additional or one less nanosecond as determined by the LTC_AUTO_ADJUSTLTC_AUTO_ADD_SUB_1NS register When LTC_AUTO_ADJUSTLTC_AUTO_ADD_SUB_1NS is set to 0x1 an additional nanosecond is added to the local time counter When it is set to 0x2 one less nanosecond is added to the local timer counter No PPM adjustments are made when the register is set to 0x0 or 0x3

PPM adjustments to the local time counter can be made on an as-needed basis by writing to the one-shot LTC_CTRLLTC_ADD_SUB_1NS_REQ register One nanosecond is added or subtracted from the local time counter each time LTC_CTRLLTC_ADD_SUB_1NS_REQ is asserted The LTC_CTRLLTC_ADD_SUB_1NS register setting controls whether the local time counter adjustment is an addition or a subtraction

The current time is loaded into the local time counter with the following procedure

1 Configure the 1588_LOAD_SAVE pin2 Write the time to be loaded into the local time counter in registers LTC_LOAD_SEC_H

LTC_LOAD_SEC_L and LTC_LOAD_NS3 Program LTC_CTRLLTC_LOAD_ENA to a 14 Drive the 1588_LOAD_SAVE pin from low to highThe time in registers LTC_LOAD_SEC_H LTC_LOAD_SEC_L and LTC_LOAD_NS is loaded into the local time counter when the rising edge of the 1588 LOAD_SAVE strobe is detected The LOAD_SAVE strobe is synchronized to the local time counter clock domain

When the 1588_DIFF_INPUT_CLK_PN pins are the clock source for the local time counter and the LOAD_SAVE strobe is synchronous to 1588_DIFF_INPUT_CLK_PN the LTC_LOAD registers are loaded into the local time counter as shown in the following illustration

Figure 65 bull Local Time Counter LoadSave Timing

When the LOAD_SAVE strobe is not synchronous to the 1588_DIFF_INPUT_CLK_PN pins or an internal clock drives the local time counter there is some uncertainty as to when the local time counter is loaded when higher accuracy circuit is turned off This reduces the accuracy of the time stamping function by the period of the local time counter clock When higher accuracy circuit is ON any difference between the 1588_DIFF_INPUT_CLK_P and the rising edge of 1588_LOAD_SAVE is compensated within an error of 1 ns This applies to both load and save operations

Note There is a local time counter in each channel The counter is initialized in both channels if the LTC_CTRLLTC_LOAD_ENA register in each channel is asserted when the LOAD_SAVE strobe occurs

LOAD_SAVE

CLK1588P

System generates LOAD_SAVE here

Device captures LOAD_SAVE here

Time loaded into Local Time Counter here

When LTC_CTRLLTC_SAVE_ENA register is asserted when the 1588 LOAD_SAVE input transitions from low to high the state of the local time counter is stored in the LTC_SAVED_SEC_H LTC_SAVED_SEC_L and LTC_SAVED_NS registers

The current local time can be stored in registers with the following procedure

1 Configure the 1588_LOAD_SAVE pin2 Program LTC_CTRLLTC_SAVE_ENA to a 13 Set SER_TOD_INTFLOAD_SAVE_AUTO_CLR to 1 if the operation is one-time save operation

This will clear LTC_CTRLLTC_SAVE_ENA after the operation4 Drive the 1588_LOAD_SAVE pin from low to high5 Read the value from LTC_SAVED_SEC_H LTC_SAVED_SEC_L and LTC_SAVED_NS registersAs with loading the local time counter there is one clock cycle of uncertainty as to when the time is saved if the LOAD_SAVE strobe is not synchronous to the clock driving the counter

3622 Serial Time of Day In addition to loading or saving as described in the preceding sections it is possible to load or save LTC time in a serial fashion For serial load 1588_LOAD_SAVE has to send Time of Day (ToD) information in a specific format For serial save when the appropriate register bits is set then PPS will drive out the ToD information The following illustration shows the format for serial load and save

Figure 66 bull Standard PPS and 1PPS with TOD Timing Relationship

36221 Pulse per Second SegmentIn the preceding illustration segment A is the pulse per second segment The PPS signal is transmitted with high voltage The rising edge of the PPS signal is aligned with the rising edge of the standard PPS signal This segment lasts 1 micros To obtain high accuracy the response delay of the rising edge of the PPS signal should be considered

36222 Waiting SegmentIn the preceding illustration segment B is the Waiting segment Due to the speed of operation this segment is needed to make it easier for the receiver to obtain the following Time-of-Day information in current PPS cycle The signal is in low voltage during this segment which lasts 20 micros

36223 Time-of-Day SegmentIn the preceding illustration segment C is the Time-of-Day segment The ToD information being carried in this segment indicates the time instant of the rising edge of the PPS signal transmitted in segment A of the current PPS cycle The time instant is measured using the original network clock In this segment the ToD information is continuously transported and is represented in 16 octets It consists of the following fields

bull Second field 6 octets It represents the time instant of the rising edge of the PPS signal in second The value is defined as in IEEE 1588-2008

bull Date field 6 octets It represents the time instant of the rising edge of the PPS signal in year month day hour minute and second Each part is represented by one octet (the format of this field is 0xYYMMDDHHMMSS) In particular only the lowest 2 decimal digits of the year are represented The receiver can easily obtain the time instant of the rising edge of the PPS signal in this transparent format without additional circuitry to translate the value of the second field It also has the significant

1PPS Cycle (1 s)

High Voltage

Low Voltage

D9998190 micros

C160 micros

B20 micros

A10 micros

Standard PPS Signal

1PPS with ToD Signal

benefit of changing the value of this field when leap year or leap second occurs (The Date field is ignored at the serial ToD input and is not generated at the serial ToD output)

bull Reserved field 4 octets Reserved for future useThe ToD information is represented in units of octet with each octet being transmitted with the low-order bit first The following illustration shows an octet is transmitted between a start bit with high voltage and a stop bit with low voltage The other octets are transmitted in the same manner As a result (1+8+1) times 1 micros = 10 micros are needed to transport one octet This segment lasts 16 times 10 micros = 160 micros to convey the ToD information

Figure 67 bull ToD Octet Waveform

The entire Time-of-Day segment should be detected If the second 6 octets representing the Date field are not used by the upper layer the Date field should still be detected and its value can be ignored

36224 Idle SegmentSegment D is the Idle segment in Figure 66 page 93 It follows segment C with high voltage until the end of the PPS cycle The duration of the Idle segment is given by the following calculation

1 s ndash 05 micros ndash 20 micros ndash 160 micros = 9998195 micros

Use the following steps to enable Serial load

1 Set SER_TOD_INTFSER_TOD_INPUT_EN to 12 Set LTC_CTRLLOAD_EN to 13 Start the transmission of 1588_LOAD_SAVE conforming to the format4 To check the data transmission enable serial save or save LTC time to check the registers5 To enable serial save set SER_TOD_INTFSER_TOD_OUTPUT_EN to 1The following table lists the different options to load or save LTC time

Table 36 bull LTC Time LoadSave Options

LTC_CTRLLOAD_EN

SER_TOD_INTFSER_TOD_INPUT_EN

LTC_CTRSAVE_EN Expected Operation

0 0 1 Parallel Save

0 1 1 Save

0 0 0 No operation

0 1 0 No operation

1 0 0 Parallel Load

1 1 0 Serial Load

Transmitting 1 ToD Octet (10 micros)

High Voltage

Low Voltage

ToD Octet (1 Octet)

LSB MSB

0 0 0 01 1 1 1

Start Bit Stop Bit

When SER_TOD_INTFSERIAL_ToD_OUTPUT_EN is set the PPS output is driven with a serial ToD output based on the LTC timer value

3623 Programmable Offset for LTC Load RegisterWhen a new LTC value is loaded into the system a fixed offset may need to be added to the loaded value Program SER_TOD_INTFLOAD_PULSE_DLY and this value will be added to LTC counter whenever a new load occurs either through software load_save pin or through serial ToD

3624 Adjustment of LTC CounterLTC counter value can be adjusted by about a second without reloading a new LTC value LTC value can be programmed to tune the current value by adding or subtracting a specific value The offset adjustment can be positive or negative very similar to 1 ns adjustment being positive or negative An adjustment every 232 ns can be performed using LTC_OFFSET_ADJ Additionally an adjustment every 220 ns can be performed using LTC_AUTO_M_x

The purpose of this register is to addsubtract a programmable offset register of 30-bit width in ns to the register block in order to cover the entire nanosecond portion of the 80-bit LTC This offset control is independent of the LTC load control The LTC timer is adjusted - added or subtracted as per the bit LTC_OFFSET_ADJLTC_ADD_SUB_OFFSET by the value LTC_OFFSET_ADJLTC_OFFSET_VAL when a load offset command is issued by the software (assertion of LTC_OFFSET_ADJLTC_OFFSET_ADJ) The hardware sets the status bit LTC_OFFSET_ADJ_STATLTC_OFFSET_DONE after completing the operation However in case the hardware cannot complete the operation because of the LTC value itself getting updated synchronously due to parallel or serial LTC load at the same time it sets the bit LTC_OFFSET_ADJ_STATLTC_OFFSET_LOAD_ERR The software on seeing either of these status bits set (LTC_OFFSET_ADJ_STATLTC_OFFSET_DONE or LTC_OFFSET_ADJ_STATLTC_OFFSET_LOAD_ERR) de-asserts the control bit (LTC_OFFSET_ADJLTC_OFFSET_ADJ) and might potentially retry the operation

The maximum value in nanoseconds for the offset LTC_OFFSET_ADJLTC_OFFSET_VAL can be up to 109 - 1 Thus for addition operation the maximum carry to the seconds counter is 2 because of the clock period addition to this maximum value present in the offset and LTC nanoseconds counter For subtraction operation if the resultant subtraction is negative or underflows the LTC timer would be set to wrong value Therefore such operations should never be allowed

LTC_OFFSET_ADJ register (with LTC_OFFSET_VAL[290] and LTC_ADD_SUB_OFFSET) should be updated before asserting LTC_OFFSET_ADJ bit in LTC_OFFSET_ADJ register

LTC_OFFSET_ADJ_STATLTC_OFFSET_DONE and LTC_OFFSET_ADJ_STATLTC_OFFSET_LOAD_ERR bits are set by the hardware and cleared by the software by writing a zero

Should a conflict occur between LTC update due to parallelserial load and LTC update due to offset adjustment the load LTC takes precedence and the error condition is noted so that the polling software does not hang on the offset status bit assertion

LTC counter could be adjusted for any known drift that occurs on every second This feature will add or subtract one nanosecond every time LTC crosses over LTC_AUTO_ADJ_M_NS

Example 1 If LTC_AUTO_ADJ_M_NS is 100 ns and LTC is started from reset with a value of 0 ns then LTC counter will be addedsubtracted 1 ns every time counter rolls over 100 ns

Example 2 If LTC_AUTO_ADJ_M_NS is 100 ns and LTC is started from reset with a value of 0 ns then LTC counter will be addedsubtracted 1 ns every time counter rolls over When counter is at 10 ns and

1 0 1 Parallel Load and Save

1 1 1 Serial Load and Save

Table 36 bull LTC Time LoadSave Options (continued)

LTC_CTRLLOAD_EN

LTC counter is loaded with 2 sec 80 ns Now 1 ns is adjusted when counter increments from 10 ns and rolls over 100 ns It does not addsubtract when LTC timer rolls over 100 ns

Example 3 LTC_AUTO_ADJ_M_NS value is loaded with 400 ns and after some time LTC_AUTO_ADJ_M_NS value is loaded with 500 ns The AUTO_ADJ_M_COUNTER value when the new value is loaded is 333 ns Then the next adjustment happens after 177 ns after load because the AUTO_ADJ_M_COUNTER continues to count until it reaches the newly loaded value 500 ns

Example 4 LTC_AUTO_ADJ_M_NS value is loaded with 400 ns and after some time LTC_AUTO_ADJ_M_NS value is loaded with 100 ns The AUTO_ADJ_M_COUNTER value when the new value is loaded is 333 ns Then adjustment happens immediately because 333 gt 100 and the AUTO_ADJ_M_COUNTER is reset to zero after the adjustment

If LTC counter is loaded with a new value set LTC_AUTO_ADJ_M_UPDATE bit to 1 and reload the LTC_AUTO_ADJ_M_NS value

3625 Pulse per Second Output The local time counter generates a one pulse-per-second (1PPS) output signal with a programmable pulse width routed to GPIO pins The pulse width of the 1PPS signal is determined by the LTC_1PPS_WIDTH_ADJ register

When the LTC counter exceeds the value in PPS_GEN_CNT (both are in nanoseconds) the PPS signal is asserted In default operation where PPS_GEN_CNT = 0 the LTC timer generates a PPS signal every time LTC crosses the 1 sec boundary By writing a large value (such as 109-60 ns) the 1PPS pulse reaches its destination 60 ns away simultaneously with the LTC second wrap thus providing time-of-day synchronism between two systems

The 1PPS output has an alternate mode of operation that increases the frequency of the pulses This mode may be used for applications such as locking an external DPLL to the IEEE 1588 frequency In the alternate mode the 1PPS signal is driven directly from a single bit of the nanosecond field counter of the local time counter The pulse width cannot be controlled in this alternate operation mode The alternate mode is enabled with register LTC_CTRLLTC_ALT_MODE_PPS_BIT

The output frequencies that result are 1 divided by powers of 2 nanoseconds (bit 4 = 132 ns bit 5 = 164 ns bit 6 = 1128 ns hellip) The output pulses may jitter by the amount of the programmed nanoseconds of the adder to the local nanoseconds counter and any automatic or one-shot adjustments

The following table shows the possible output pulse frequencies (including the range of 4 kHz to 10 MHz) usable for external applications

Table 37 bull Output Pulse Frequencies

Nanosecond Counter Bit Output Pulse Frequency4 3125 MHz

5 15625 MHz

6 78125 MHz

7 390625 MHz

8 1953125 MHz

9 9765625 kHz

10 48828125 kHz

11 244140625 kHz

12 1220703125 kHz

13 6103515625 kHz

14 3051757813 kHz

15 1525878906 kHz

In addition to the preceding frequencies a specific frequency can be chosen by enabling the synthesizer on the PPS pin using the following steps

1 Set LTC_FREQ_SYNTHLTC_FREQ_SYNTH_EN to 12 A toggle signal with the frequency specified will be pushed out onto PPS The number of

nanoseconds the signal stays high can be specified by LTC_FREQ_SYNTHFREQ_HI_DUTY_CYC_NS The number of nanoseconds the signal stays low can be specified by LTC_FREQ_SYNTHFREQ_LO_DUTY_CYC_NS

3 The above nanoseconds should be exactly divisible by clock frequency otherwise the signal may have a jitter as high as the high durationclock period or low durationclock period

4 To disable the this feature and revert back to PPS functionality reset LTC_FREQ_SYNTHLTC_FREQ_SYNTH_EN to 0

For example to output a 10 MHz signal set the FREQ_HI_DUTY_CYC_NS to 50 ns and FREQ_LO_DUTY_CYC_NS to 50 ns On a 250 MHz LTC clock this will make high time and low time of signal shift between 48 ns and 52 ns

3626 ResolutionThe IEEE 1588 processor achieves time stamp resolution in any mode of operation of 1 ns utilizing special high-resolution circuitry The accuracy of a device using high-resolution circuitry is improved more than 100 over the first generation IEEE 1588 engine High accuracy for these devices will be supported regardless of the local time counter clock frequency supplied to the reference clock input The timestamp accuracy is a system-level property and may depend upon oscillator selection port type and speed system configuration and calibration decisions Supported frequencies of the local time counter are 125 MHz 15625 MHz 200 MHz and 250 MHz

There are a total of five high resolution blocks per port to improve resolution for the following events

bull One pulse-per-second (1PPS) output signalbull 1588_PPS_RI input signalbull Start-of-frame in the egress directionbull Start-of-frame in the ingress directionbull 1588_LOAD_SAVE input (strobe) signal directionEach of these blocks can individually be enabled using ACC_CFG_STATUS Contact Microsemi with any questions regarding PTP accuracy calculations

3627 LoopbacksLoopback options provide a means to measure the delay at different points to evaluate delays between on chip wire delays and external delays down to a nanosecond

36271 Loopback from PPS to PPS_RI PinIn this loopback an external device will connect the PPS coming out of the IEEE 1588 to PPS_RI of the IEEE 1588 device The external device could even process the PPS signal and then loopback at a far-end

36272 Loopback from LOAD_SAVE to PPSWhen LOAD_SAVE_PPS_LPBK_EN is set input load_save pin is connected to output PPS coming out of the IEEE 1588 In this mode input load_save pin is taken as close to the pin as possible without going through any synchronization logic on the load_save pin

16 7629394531 kHz

17 3814697266 kHz

Table 37 bull Output Pulse Frequencies (continued)

Nanosecond Counter Bit Output Pulse Frequency

36273 Loopback of LOAD_SAVE PinWhen LOAD_SAVE_LPBK_EN is set one clock cycle before the PPS is asserted an output enable for load_save pin is generated and PPS signal is pushed out on the load_save pin acting as an output pin After two cycles output enable is brought down and load_save will behave as an input pin

36274 Loopback from PPS to LOAD_SAVE PinWhen PPS_LOAD_SAVE_LPBK_EN bit enabled output pps signal is taken as close to the IO as possible and looped back onto load_save input pin This is to account for any delays from PPS generation block to the PPS output pin

3628 Accessing 1588 IP RegistersThe following sections describe how the IEEE 1588 IP registers are accessed in the VSC8490-17 device

Note Contact Microsemi for an initialization script that supports the quick initialization of IEEE 1588 registers

37 MACsec Block OperationThe VSC8490-17 device includes a high-performance streaming MACsec frame processing engine that provides hardware acceleration for the complete MACsec frame transform along with frame classification and statistics counter updates The following list includes some of the major features of the MACsec engine

bull Fully IEEE 8021AE-2006 IEEE 8021AEbn and IEEE 8021AEbw-2013 compliantbull 64 secure associations (SA) per direction and 64 ingress consistency check rulesbull MACsec cipher suite GCM-AES-128 supportbull MACsec cipher suite GCM-AES-256 supportbull MACsec cipher suite GCM-AES-XPN-128256 supportbull VLAN and Q-in-Q tag detectionbull MACsec tag detection and sub-classification (Untagged Tagged BadTag KaY)bull Programmable ldquocontrolrdquo packet classificationbull 8-entry programmable non-match flow operation selection (drop bypass) depending on MACsec

tag sub-classification and control packet classificationbull Programmable confidentiality offset (0 B ndash 127 B)bull SecTAG insertion and removalbull Integrity Check Value (ICV) checkingremoval and calculationinsertionbull Packet number generation and checkingbull IEEE 8021AE MACsec statistics counter supportbull Ingress path consistency checking (ICC)ndash6416 entry programmable matching table with separate

droptransfer decisionsbull MTU checking and oversize dropping dependent on VLAN User priority for VLAN frames and at

global level for non-VLAN framesbull Advanced MACsec transformationsndashVLAN tag bypass and EoMPLS header bypassbull Hardware offload for the nextPN and lowestPN update from the host(KaY)bull Support for AES-ECB AES-CTR and AES-GCMGMAC transformation for FIPS certification of the

crypto corebull Patent-pending architecture to enable use with IEEE 1588v2 with minimal and predictable delays

371 MACsec ArchitectureThe MACsec block operates as a frame processing pipeline whose main function is the implementation of the MACsec transform on Ethernet frames The following illustration shows the MACsec data flow in one direction

Figure 68 bull MACsec Architecture

The following sections describe the blocks in the MACsec data flow

3711 PKT64to128The Packet 64to128 block is the Rx interface of the MACsec IP with the other blocks It converts the 64-bit packet interface to the 128-bit packet interface with which the MACsec IP works It also presents the port information associated with the current frame In the egress configuration the PKT64to128 block has a FIFO to temporarily handle back-pressure from the MACsec IP due to frame expansion Based on packet expansion within the MACsec IP the PKT64to128 block provides flow control feedback to the flow control buffer which manages all data build up that occurs as a result of MACsec frame expansion

3712 Input AdapterThe Input Adapter manages the Input Packet interface to ensure interface protocol compliance

3713 Input Classification EngineThe Input Classification engine inspects the received frame data and performs the following functions

bull Control Frame Classification- A total of 29 programmable rules to classify the frame as a control frame

bull VLAN Tag Detection- Programmable functionality to detect VLAN tags and extract information before further classification

bull MACsec Tag Detection- Programmable functionality to detect MACsec tags and check if they are valid (also detects special KaY packet tags)

bull Default Frame Handling- Classifies packets into eight classes based on the outputs of the control frame classification and MACsec tag detection modules with control registers to define what to do with a packet (drop or bypass) for each class

FIFO Interf

Pre-proc

AES-GCMCore with nAES cores

Post-Proc

FIFOInterf

Token

Context

Crypto Engine

ClassificationEngine

HdrBypassproc

InputAdapter

Pkt64to128

conv

OutputAdapter

Post-ProcessEngine

StatisticsUpdateEngine

ConsistencyChekcingEngine

HdrBypassproc

Latency Monitoring and Control

Bypass

SystemControl

Interrupt Control

TransformRecords

RAM

Statistics RAM

Host Control Bus

CSRHandler

CSRTarget

Input Token

Input Packet Buffer

Bypass

Output Token

Output Packet Buffer Pkt

128to64conv

tx_adrTx

Stat events

Rx

rx_adr

reset_n

clk

clk_en

InterruptOutputs

RX

Tx

MACSec IP

MUX

bull Flow Lookup Frame Classification and Frame Handling- Classifies frames based on frame header field contents and outputs of the control frame classification VLAN tag detection and MACsec tag detection modules Flow control registers define what to do with a frame (drop bypass or MACsec process) when matching entries A programmable per-rule priority level resolves any overlap between these rules

bull Flow LookupDefault Classification Multiplexer- Gives priority to the decision from the flow lookup frame classification The default frame handling is used for a frame only if none of the flow lookup entries match

3714 Latency Monitoring and ControlThe Latency Monitoring and Control module monitors the latency that the first word of each frame incurs going through the pipeline and optionally stalls the output side until this latency matches a programmable value This ensures each frame incurs the same latency through the pipeline irrespective of any processing time differences

3715 MACsec Crypto EngineThe MACsec Crypto engine performs the standard MACsec encapsulationdecapsulation processing This engine is able to perform a MACsec transform on a frame using GCM-AES-128 according to the IEEE 8021AE-2006 MACsec specification and its amendment IEEE 8021AEbn-2011 which adds the GCM-AES-256 cipher suite The crypto engine also transforms a frame using GCM-AES-XPN-128256 according to IEEE 8021aebw-2013 This includes modifications to the Ethernet frame header insertionremoval of the MACsec header (SecTAG) encryptiondecryption authentication and authentication result insertionverification It does not perform MACsec header parsing but relies on external logic to provide a processing token that tells it how to process the incoming frame

In addition to the MACsec specifications 0-byte 30-byte and 50-byte confidentiality offset the MACsec crypto engine supports byte-grained confidentiality offsets from 1 to 127 bytes The MACsec crypto engine supports one or two VLAN tag bypass operation wherein VLAN tags that bypass MACsec processing are fully excluded from the encryption and authentication such that the receiver side must be able to remove the bypassed VLAN tags without breaking the MACsec packet It also supports MPLS header bypass wherein the MPLS link header is excluded from encryption and authentication and the client Ethernet frame is subjected to MACsec transformations

3716 Consistency Checking EngineThe Consistency Checking engine checks the contents of a frame at the output of the MACsec Crypto engine (after any MACsec decryption) against a set of 1664 programmable rules (depending on the configuration) for consistency A programmable per-rule priority level resolves any overlap between these rules This engine is not present in the egress configuration

3717 Output Post-Processing EngineThe Output Post-Processing engine checks the classification and MACsec Crypto engine processing results against a fixed set of MACsec compliance rules resulting in a drop decision if the rules are violated Additionally it performs programmable MTU checking on the MACsec Crypto engine output frame with individual global and per-VLAN-user-priority MTU settings

The engine combines these internal decisions with decisions made by the Classification and Consistency Checking engines into a final passdrop decision to the output adapter Based on all the information from the MACsec Crypto engine and the consistency checking engine available to it the Output Post-Processing engine also decides which statistics counters to increment

3718 Statistics Update EngineThe Statistics Update engine updates the statistics counter in the statistics RAM as instructed by the Output Post-process engine This allows updating to be scheduled with external statistics access and to occur in parallel with the post-processing of the next frame This engine also can be configured to skip certain statistics counters

3719 Output AdapterThe Output Adapter block manages the output packet interface and ensures interface protocol compliance by isolating the MACsec IP from this interface

37110 PKT128to64The Packet 128to64 block is the interface of the MACsec IP with the other blocks It converts the 128-bit packet interface of MACsec IP to the 64-bit packet interface used to communicate with other blocks It also prepares the security fail debug code to be put into FCS field for packets failing security check

372 MACsec Target ApplicationsThe MACsec engine targets the following applications

bull Secure enterprise infrastructure and WAN portsbull Secure end-to-end Carrier Ethernet connectionsbull Secure Carrier Ethernet Mobile Backhaul including high precision IEEE 1588v2 timing

3721 MACsec Secured Enterprise Infrastructure and WAN PortThe following illustration shows an enterprise branch office or campus where a Local Area Network (LAN) connected to a Wide Area Network (WAN) operated by a service provider is protected using MACsec

Figure 69 bull Secure Enterprise Infrastructure and WAN

Each host has a dedicated physical link to an Enterprise Ethernet switch and the switches are connected to an enterprise branch router that also provides WAN access In smaller configurations hosts can also connect directly to the branch router All internal branch office Ethernet ports are secured using MACsec

The branch router connects across an access link to a service providerrsquos service edge router and this access link is secured using MACsec MACsec may also be used to secure the service providers network

The 8021X security protocols can be used for authentication and to automate the distribution and management of MACsec encryption keys The VSC8490-17 device supports 128-bit and 256-bit encryption

3722 MACsec Secured Carrier Ethernet ConnectionThe following illustration shows a Carrier Ethernet network providing end-to-end MACsec secured WAN connectivity for an enterprise

EnterpriseSwitches

EnterpriseBranch Router

Access Link

Service Edge Router

Enterprise Branch Office or CampusService Provicer

Point of Presence (POP)

Provider Network or Internet

MACsec-SecuredWAN access port

MACsec-Secured LAN infrastructureMACsec-Secured

Service Provider infrastructure

Hosts

Figure 70 bull Secure Carrier Ethernet Connection

With traditional MACsec VLAN tags or MPLS labels are fully encrypted and hidden from the Carrier Ethernet network thereby limiting the enterprise to only the simplest point-to-point private line connectivity services

The VSC8490-17 device supports leaving the VLAN tags or MPLS labels unencrypted for use by the Carrier Ethernet network while fully securing the enterprises Ethernet data inside these encapsulations This approach uses standard non-proprietary encapsulation formats with 128-bit and 256-bit encryption

By enabling these features the enterprise is able to take advantage of the latest Layer-2 (L2) VPN services available from a Carrier Ethernet network These L2 VPN services can be point-to-point or multipoint and can use standardized Metro Ethernet Forum (MEF) Carrier Ethernet and Internet Engineering Task Force (IETF) MPLS service offerings including multiple Virtual Private Lines per WAN port

3723 MACsec Secured Mobile Backhaul with IEEE 1588The following illustration shows a a typical mobile backhaul application where multiple network operators collaborate to deliver mobile service In this application a mobile service provider uses MACsec to secure the backhaul connections end-to-end through the network

Figure 71 bull Secure Mobile Backhaul with IEEE 1588

The mobile service provider may choose to leave VLAN tags or MPLS labels unencrypted so that the access operator can map the virtual private line services

In addition to backhauling data IEEE 1588 packet-based timing technology delivers high-precision frequency and phase synchronization to the base stations IEEE 1588 packets may be encrypted along with backhaul data and tunneled through the access operator network or delivered as an unencrypted synchronization service directly from the access operator network To meet 4GLTE specifications nanosecond-accurate time stamping of IEEE 1588 packets is required However such tight tolerances

Branch Offices

Carrier EthernetNetwork

Corporate Headquarters

MACsec-secured dataover MEF EVC or MPLS

Mobile ServiceProvider NID

Access OperatorNetwork

IEEE-1588Transparent Clockor Boundary Clock

IEEE-1588Slave

Mobile Service Provider

Mobile ServiceProvider Base Station

Timing

MACsec-secured datathrough Access Operators network

cannot be achieved using traditional MACsec even if the IEEE 1588 packets themselves are unencrypted

The Microsemi IEEE 1588 time stamping engine in the VSC8490-17 device works in conjunction with the MACsec engine to deliver 4GLTE timing quality over Carrier Ethernet connections while using MACsec for end-to-end security across the access operator network

373 Formats Transforms and ClassificationThis section shows the frame formats before and after MACsec transformation with an overview of the classifiable fields that can be used for SA classification for different MACsec applications Classification fields are selectable per SA In depicting which fields may be used for pre-decrypt classification it is assumed that the confidentiality offset field is not used (all fields after SecTAG are encrypted)

3731 Standard MACsec FormatsThe following table summarizes the MACsec frame combinations in the standard MACsec mode

The following illustrations show each frame format before and after standard MACsec transformation

Figure 72 bull Untagged Ethernet

Figure 73 bull Standard MACsec Transform of Untagged Ethernet

Figure 74 bull Single-Tagged Ethernet

Figure 75 bull Standard MACsec Transform of Single-Tagged Ethernet

Table 38 bull Standard MACsec Frame Combinations

Unencrypted Format Pre-Encryption (Tx) Classification FieldsPre-Decryption (Rx) Classification Fields

Untagged Ethernet DA SA Etype DA SA SecTAG

Single-tagged Ethernet DA SA TPID VID Etype DA SA SecTAG

Dual-tagged Ethernet DA SA TPID1 VID1 TPID2 VID2 Etype DA SA SecTAG

Payload FCSDA SA Etype

Classifiable Pre-Encryption

payload FCSDA SA SecTAG ICV

Protected by ICV

Classifiable pre-decryption

Etype

Payload FCSDA SA EtypeVLAN Tag

payload FCSDA SA ICV

Protected by ICV

EtypeVLAN TagSecTAG

Figure 76 bull Dual-Tagged Ethernet

Figure 77 bull Standard MACsec Transform of Dual-Tagged Ethernet

3732 Advanced MACsec FormatsThe following table summarizes the MACsec frame combinations in the advanced MACsec mode

The following illustrations show each frame format before and after advanced MACsec transformation

Figure 79 bull MACsec Transform to Single Tag Bypass

Table 39 bull Advanced MACsec Frame Combinations

Unencrypted Format

Encrypted Format

Pre-Encryption (Tx) Classification Fields

Pre-Decryption (Rx) Classification Fields

Single-tagged Ethernet

MACsec plus single tag bypass

DA SA TPID VID Etype DA SA TPID VID SecTAG

Dual-tagged Ethernet

DA SA TPID1 VID1 TPID2 VID2 Etype

DA SA TPID1 VID1 SecTAG

MACsec plus dual tag bypass

DA SA TPID1 VID1 TPID2 VID2 SecTAG

EoMPLS with one Label

MACsec plus EoMPLS header bypass

C-DA C-SA MPLS Etype 32-bit Label

C-DA C-SA MPLS Etype 32-bit label SecTAG

EoMPLS with two Labels

C-DA C-SA MPLS Etype 32-bit Label1 32-bit Label2

C-DA C-SA MPLS Etype 32-bit label1 32-bit label2 SecTAG

Payload FCSDA SA VLAN Tag1 VLAN Tag2

Etype

Protected by ICV

VLAN Tag1SecTAG

EtypeVLAN Tag2

P ayload FCSDA SA IC V

P rotected by ICV

E typeV LA N Tag S ecTA G

C lassifiab le P re-D ecryption

P rotected by ICV

Etype

Figure 81 bull MACsec Transform to Single and Dual Tag Bypass

Figure 82 bull EoMPLS with One Label

Figure 83 bull Standard and Advanced MACsec Transform

Figure 84 bull EoMPLS with Two Labels

374 MACsec Integration in PHYThe MACsec block is designed to be integrated with a host MAC and a line MAC to form a plug-in MACsec solution between an existing Ethernet MAC (system-side) and an existing Ethernet PHY (line-side) MACsec adds bandwidth in egress This increase in bandwidth is handled adding IEEE 8023 pause flow control toward the system The FC buffer block provides packet buffering and controls the

Payload FCSDA SA ICVSecTAGVLAN Tag1

Protected by ICV

Payload FCSDA SA ICVVLAN Tag2VLAN Tag1

Protected by ICV

Etype

Classifiable Pre-Decryption

VLAN Tag2

SecTAG

Classifiable Pre-Decryption (may need CO)

MACsec plus Single Tag Bypass

MACsec plus Dual Tag Bypass

Protected by ICV

FCSDA SA MPLSEtype

OptionalCW ACH

MPLSLabel [S=1]

Client_DA Client_ SA Client PayloadEtype

FCSICVClient PayloadEtype

FCSDA SA ICV

Protected by ICV

SecTAG

Classifiable Pre-DecryptionStandard MACsec format

MPLSEtype

OptionalCWACH

MPLSLabel [S=1]

DA SA

MACsec plus EoMPLS Header Bypass

Protected by ICV

MPLSEtype

OptionalCWACH

MPLSLabel [S=1]

Client_DA Client_SA SecTAG

Client_DA Client_SA Client PayloadEtype

FCSDA SA MPLSEtype

OptionalCW ACH

MPLSLabel1 [S=0]

Client_DA Client_SA Client PayloadMPLSLabel2 [S=1]

Etype

DA SA

Protected by ICV

SecTAG

MPLSEtype

OptionalCWACH

MPLSLabel1 [S=0]

MPLSLabel2 [S=1]

DA SA

Classifiable Pre -DecryptionMACsec plus EoMPLS Header Bypass

MPLSEtype

OptionalCWACH

MPLSLabel2 [S=1]

MPLSLabel1 [S=0]

FCSICVClient_DA Client_SA Client PayloadEtype

Protected by ICV

Classifiable Pre -Decryption

IEEE 8023 pause flow control generation to handle MACsec frame expansion The IEEE 1588 block is on the host-side of MACsec and the IEEE 1588 PTP frames are also subjected to MACsec transformations

The following illustration shows the integration of MACsec in the PHY

Figure 86 bull MACsec in PHY

375 MACsec Pipeline OperationMACsec ingress and egress pipeline operations are identical except for a few situations mentioned in the following sections The MACsec block always operates in cut-through mode The length of the frame is calculated on the fly and does not need to be known before the start of processing This means that MACsec egress processing encrypts (protects) all bytes of the frame fed into the MACsec core If the frame contains Ethernet padding this padding is encryptedprotected by MACsec and the ICV is appended after it For ingress processing the MACsec block accepts frames with Ethernet padding and it strips Ethernet padding from short MACsec frames

Ethernet frames are submitted to the MACsec egressingress block with their Ethernet header (destination address source address Ethertype) but without the leading preamble and start-of-frame bytes and trailing 4-byte CRC (FCS) It is the responsibility of the hostline MAC to strip and check the CRC of each incoming frame

In the case of large frames the first output data word of a frame may leave the MACsec pipeline before the last input data word of a frame enters and errors such as ICV check verification or MTU checking may only be detected after the last byte of frame data has been processed As a consequence dropping a frame is accomplished by setting the frame abort signal and not by preventing the frame from appearing on the output In other words the systemline MAC transmits a frame with bad CRC The engine can be programmed to drop frames completely (internal drop) but only if the decision to drop has been made by the flow lookup stage The pipeline outputs the (processed) frames in the same order they are input unless the frame is dropped internally The MACsec block can also be bypassed completely to improve latency

The SL field in MACsec indicates the end of the MACsec frame which is needed to locate the ICV in case Ethernet padding follows the ICV For such frames the MACsec block uses the information from the SecTAG of the frame to calculate the actual MACsec frame length and uses this length during ingress processing All data that follows the ICV is removed from the data stream by the MACsec block This action is the de-padding action using the MACsec protocol header The ICV is assumed to be at the location as indicated by the SecTAG otherwise the frame does not pass the MACsec integrity check

If the SL field in the MACsec frame indicates a longer frame than the packet actually received by the MACsec block (if the frame does not pass MACsec PDU check) the MACsec block flags this situation as an integrity check failure or packet length error depending on the difference in length

Host MAC Rx(Egress)

1588(Egress)

MACSec(Egress)

Line MAC Tx(Egress)

Host MAC Tx(Ingress)

1588(Ingress)

MACSec(Ingress)

Line MAC Rx(Ingress)

PHY with MACSec

FC Buffer

(Ingress)

FC Buffer

(Egress)

xMII

MACSec SubSystem

xMIIPCS + PMA

PCS + PMA

LINE

SYSTEM

PHY XS

xMII

Note The de-padding action is applicable only for MACsec frames that are going to be decryptedvalidated by the MACsec flow and will not change the regular MACsec processing latency No de-padding action is performed on bypassdrop frames

After ingress MACsec processing it is possible for the frame to become smaller than 64 bytes Such frames are then padded by the host MAC (if enabled) and the packet processing switchsystem receives 64 byte frames after Ethernet padding

In the egress direction the MACsec core calculates and updates the SL field in the MACsec header and authenticates and encrypts (optionally) the frame if a frames size (including the MACsec header and ICV) is less than 64-bytes

Note This short length field indicates frame data from after the first byte of the MACsec header to byte immediately before ICV

For this feature to work host MAC receiver should be configured to allow undersized frames and line MAC transmitter should be configured to pad frames

Host and line MACs do not accept less than 64 byte frames (without Ethernet padding) from systemline interfaces and do not remove the Ethernet padding from the frames

Each frame at input is accompanied by the following signals

bull Port Number- Two-bit signal that indicates the source port (common reserved controlled or uncontrolled) of the packet as defined in the IEEE 8021AE standard

bull Bad CRCPacket Error- Bits that indicate that the packet has a bad CRCpacket error Frames with a bad CRC or other packet errors are forwarded to the output with the same errors unless their classification leads to a decision to drop them Because error signals appear at the end of a frame and processing must start before the end of a frame is received classification and processing is performed but statistics are not updated

The source port for MAC datacontrol frames is configurable Typically egress MAC data frames are put on the controlled port and MAC control frames are put on the uncontrolled port All ingress frames are put on the common port This configuration is controlled using MAC_DATA_FRAMES_SRC_PORT and MAC_CTRL_FRAMES_SRC_PORT in the MACSEC_CTL_CFG register Control packet classification determines the frames that are assumed to have come from controlleduncontrolled ports in egress and the frames that should go to controlleduncontrolled ports in ingress

LPI and fault signals that appear on the Ethernet interface can be detected by the MAC and converted into internal status frames (single-byte frames containing the state of the signals) The MACsec block can recognize these status frames on the input and propagate them to its output

Status frames travel through the pipeline along with normal Ethernet frames so they appear at the output after the preceding Ethernet frame and before any frames that appear after the status change However status frames do not take part in any operations of the pipeline They are invisible to static classification flow lookup MACsec processing and consistency checking

The following illustrations show the egress and ingress MACsec data flows

Figure 87 bull MACsec Egress Data Flow

Figure 88 bull MACsec Ingress Data Flow

The following sections describe the pipeline stages Of these pipeline stages the MACsec transform stage is the only one that can modify the frame data or drop a frame completely (no frame will appear at the output of the pipeline in that case) Other stages can only perform the following actions for frame data

bull Inspect the frame data such as performing a classification based on fields in a header bull Drop the frame (which is already streaming out) by setting the frame abort signal along with the last

word of dataStatic Classification

This is the first stage of packet classification Control packet classification MACsec tag parsing and VLAN tag parsing are carried out in parallel

Flow Lookup

Each table of 16 SA flows can match on a number of criteria An action and a MACsec context is associated with each flow If the packet does not match any of these 16 flows one of eight default actions is selected depending on the results of MACsec tag parsing and control packet classification

MACsec Transform

This stage carries out the actual MACsec encryption and authentication It uses the MACsec context associated with the flow that was matched in the previous stage A MACsec context is a data structure containing all information (such as key and sequence numbers) needed to carry out a MACsec transform This stage can also bypass or drop certain packets

The MACsec transform stage can be bypassed by setting MACSEC_BYPASS_ENA = 1 in the MACSEC_ENA_CFG register Setting the MACSEC_BYPASS_ENA = 0 and MACSEC_ENA = 1 results

29 waycontrol frame classification

EoMPLS header bypass proc

VLAN tag detection

MACSec tag detection

8 entry default packethandling registers

6416 entry flow

lookuppacket

classification

6416 entry flow

packethandlingregisters

Programmable latency control

MACSec crypto -core with Vlan Tag bypass

and MPLS header bypass

6416 entry transformparameters amp state

MTU Checking andblocking module

Statistics module

Static bypass

0

1S

control

VLANQinQ

MPLSflow hit

dropbypassprocess

128128

Egress MACSec Core

LINE

SYSTEM

dropbypassprocess

dropbypass

VLAN tag detection

6416 entry flow

lookuppacket

classification

6416 entry flow

MACSec crypto -core with vlan tag bypass and MPLS

header bypass6416 entry transform

parameters amp state

6416 entry programmable consistency

checking(only on

ingress side )

MTU Checking and

blocking module

Statistics module

Static bypass

0

1S

control

VLAN Q inQ

MPLSflow hit

Drop BypassProcess

128128

MACSec Ingress

LINE

SYSTEM

Drop BypassProcess

DropBypass

in traffic passing through the MACsec transform block Setting the MACSEC_BYPASS_ENA and MACSEC_ENA bits to 0 results in all traffic being dropped at the input interface of MACsec

Ingress Consistency Checking

This stage is not present in the egress-only version of the MACsec block It extracts information from the decrypted packet and checks it against a table of 6416 rules Rules can either reject or pass certain packets Separate default actions can be configured for control and non-control packets (in case no match is found in the table)

Output Postprocessor

This stage checks the results of the MACsec transform operation It also checks that the length of a packet does not exceed the MTU (incrementing a counter if the MTU is exceeded and optionally tagging the packet for deletion) Each of the eight VLAN user priorities and non-VLAN packets can have a different MTU This stage implements the MACsec-compliant post-processing decision tree and updates all MACsec statistics

3751 Static ClassificationControl packet classification MACsec header parsing and VLAN tag parsing are the three static classification operations performed in parallel to produce the following results

bull Control- Single bit that is set if the packet is classified as a control packetbull MACsec Tag Status- One of four values untagged tagged bad tag and KaY where tagged means

the packet has a valid non-KaY MACsec SecTAGbull VLAN Related Status Signals- VLAN valid VLAN ID Inner VLAN ID VLAN User Priority Inner

VLAN User Priority QTAG valid STAG valid and QinQ valid bull Parsed Ethertype- First non-VLAN Ethertype found in the frame The following sections describe the static classification operations

37511 Control Packet ClassificationControl packet classification is used to identify frames from uncontrolled ports and exclude them from MACsec processing Frames such as the MAC control frames and MKAEAPOL frames are forwarded without MACsec processing because they use uncontrolled ports for transmission MKAEAPOL frames are used for Key exchange and have Ethertype 0x888E

The control packet classification logic classifies a packet as a control packet based on its destination address andor its Ethertype It yields a single-bit output (control) classifying the packet either as a control packet or not

The control packet classification logic can match a packet based on 29 individually-enabled criterion If the packet matches one or more of the enabled criterion the packet is classified as a control packet and the control output is set to 1 If no enabled criterion is matched the packet is not classified as a control packet The CTL_PACKET_CLASS_PARAMS and CTL_PACKET_CLASS_PARAMS2 registers configure control packet classification The match criterion are as follows

bull The fixed Ethernet destination address 01_00_0C_CC_CC_CC The corresponding register CP_MAC_DA_48 has this address as a reset value but this value can be changed if needed

bull The fixed Ethernet destination address range 01_80_C2_00_00_0 (the first 44 bits must match the trailing 4 bits are dont care) The corresponding register CP_MAC_DA_44 has this address range as a reset value but this value can be changed if needed It is always a range with 44 matching bits and 4 dont care bits

bull One free to program Ethernet destination address range specified by the CP_MAC_DA_START and CP_MAC_DA_END registers Ethernet addresses are treated as unsigned 48-bit integers as shown in the following examples

If CP_MAC_DA_START = 00_80_C2_00_00_00 and CP_MAC_DA_END = 00_80_C2_00_00_0F the matched range is identical to the range normally matched by MAC_DA_44 If CP_MAC_DA_START = 00_00_00_00_00_00 and CP_MAC_DA_END = FF_FF_FF_FF_FF_FF all destination addresses are matched (every packet is classified as a control packet)If CP_MAC_DA_START = CP_MAC_DA_END then only a single address will be matched

bull Eight individual Ethernet destination addresses CP_MAC_DA_MATCH_0 through CP_MAC_DA_MATCH_7

bull Sixteen individual Ethertypes CP_MAC_ET_MATCH_0 through CP_MAC_ET_MATCH_7 where each Ethertype compare value field shares a register with two destination address compare value bytes and CP_MAC_ET_MATCH_10 through MAC_ET_MATCH_17 registers

bull Two combinations of destination address and Ethertype CP_MAC_DA_ET_MATCH_8 and CP_MAC_DA_ET_MATCH_9 A packet matches only if both the destination address and the Ethertype match

bull Even though the registers for destination addresses and Ethertypes 8 and 9 have the same format as those for destination addresses and Ethertypes 0 to 7 and 10 to 17 they have different semantics Destination address 8 can only be enabled in combination with Ethertype 8 and only packets with both a matching destination address and a matching Ethertype will match this criterion The same applies to destination address and Ethertype 9 On the other hand destination addresses 0 to 7 can be enabled independent of Ethertypes 0 to 7 When both destination address 0 and Ethertype 0 are enabled packets that have either a matching destination address or a matching Ethertype (or both) will be classified as control packets

bull After reset control packet matching criteria are disabled The registers for a matching criterion must be programmed to enable it

bull Either the first Ethertype after the DASA fields or the parsed Ethertype determined by the VLAN parsing algorithm is the Ethertype value (number 0 to 17 including the combined numbers 8 9) from the packet that can be used to compare This selection is done using the CP_MATCH_MODE register

bull Rules are enabled using the CP_MATCH_ENABLE register

37512 MACsec Tag ParsingThe MACsec tag parsing logic inspects MACsec tags MACsec tags must follow the source address without any intervening VLAN tags- they may follow VLAN tags only in VLAN tag bypass mode MACsec tag parsing classifies each packet into one of four categories

bull Untagged- No MACsec tag (Ethertype differs from 0x88E5) bull Bad Tag- Invalid MACsec tag as determined by the tag detection logicbull KaY Tag- These packets are generated andor handled by software and no MACsec processing is

performed on them by the hardware except for straight bypassbull Tagged- Valid MACsec tag that is not KaY The following table shows the IEEE 8021AE checks that determine the status of the MACsec tag parsing

MACsec tag parsing checks are controlled by configuring the SAM_NM_PARSING register

37513 VLAN Tag ParsingThe VLAN tag parsing logic recognizes VLAN tags that immediately follow the source address Both 8021Q and 8021s tags can be recognized Packets with two VLAN tags can also be recognized

Table 40 bull MACsec Tag Parsing Checks

MACsec Tag (SecTAG) Check ResultEthertype is not MACSec type Untagged

V bit = 1 Bad tag

C bit = 0 and E bit = 1 KaY

C bit =1 and E bit = 0 Bad tag

SC bit = 1 and ES bit = 1 Bad tag

SC bit = 1 and SCB bit = 1 Bad tag

SL ge 48 Bad tag

PN = 0 Bad tag

All other Tagged

The VLAN tag parsing logic generates the following signals that can be used by flow lookup and other processing stages

bull VLAN Valid- Single bit that is set when a VLAN tag (of any type) is successfully parsedbull Stag Valid- Single bit that is set if the first valid VLAN tag is an 8021S tagbull Qtag Valid- Single bit that is set if the first valid VLAN tag is an 8021Q tagbull Q-in-Q Found- Single bit that is set if two valid VLAN tags were foundbull VLAN User Priority- Three-bit field derived from the first VLAN tag For non-VLAN tag packets the

default user priority is returned User priority processing can be disabled to also return the default user priority

bull VLAN ID- Twelve-bit field taken from the first VLAN tag Undefined for non- VLAN packetsbull Inner VLAN User Priority- Three-bit field derived from the second (inner) VLAN tag This value is

always passed through the re-mapping table (the SAM_CP_TAG2 register) and the result value is used in classification Undefined for non-VLAN packets or VLAN packets without a second VLAN tag

bull Inner VLAN ID- Twelve-bit field that is taken from the second (inner) VLAN tag Undefined for non-VLAN packets or VLAN packets without a second VLAN tag

bull Ethertype- Ethertype extracted from the packet after zero one or two VLAN tags VLAN parsing is controlled by configuring the SAM_CP_TAG SAM_PP_TAGS SAM_PP_TAGS2 and SAM_CP_TAG2 registers

The parsed VLAN fields (including UP) are used in SA flow classification lookup The MACsec block also maintains VLAN statistics on a per user priority basis This includes dropped and oversize packets on a user priority basis

3752 Flow LookupSA Flow ClassificationThe flow lookup logic associates each packet with one of the two following flows

bull A table of SA matching flows each of which can match a packet based on a set of match criterion If a packet matches multiple (enabled) SA flows the SA flow with the highest user-defined priority value is selected The flow specifies which action must be performed (drop the packet pass it unchanged or perform a MACsec transform) Each SA flow for which a MACSec operation is specified corresponds to exactly one MACsec context (and hence to a single MACsec SA either ingress or egress) In other words all packets that are to be processed using a single MACsec SA have to be matched by a single SA flow

bull A table of eight non-matching flows If no enabled SA flow matches a packet a non-matching flow is selected based on the MACsec tag parsing result and the control bit (from the control packet classification) For these non-matching flows the only possible actions are bypass and drop (MACsec operations cannot be selected here)

The output of the flow lookup is as follows

bull SA Hit- Single bit signal that is set if the packet matched an enabled SA flowbull SA Index- Index of the SA flow being matched If no SA flow was matched this field is composed

from the control packet classification and MACsec tag parsing results which identifies the non-matching flow used

37521 SA Match CriteriaEach SA flow has a set of registers that specify the match criteria using one of two following categories

bull The four MACsec tag match bits (untagged tagged bad_tag and kay_tag in the SAM_MISC_MATCH registers) If the corresponding bit is set in the SAM_MISC_MATCH register packets from that category (as classified by the MACsec classification logic) can be matched if the other criteria are also satisfied If the corresponding bit is clear packets from that category can not be matched

bull The mask-able match criteria Each of these criteria can be masked by a mask bit in the SAM_MASK registers If the corresponding mask bit is clear the matching criterion is not tested and packets may be matched regardless of actual value in the packet If the corresponding mask bit is set the matching criterion is tested if the packet has a different value from that specified in the flow the packet will not be matched

The following table shows the match criteria and maskable bits

If all four MACsec tag match bits are set and none of the mask bits are set the flow matches all possible packets If none of the MACsec tag match bits are set the flow does not match any packets

If an exact match of the MAC source address is desired all six mac_sa_mask bits must be set If an exact match of the MAC destination address is desired all six ma_da_mask bits must be set

The SCI and TCIAN fields are used in only in the ingress SA flow classification The TCIAN field match can be masked per bit If an exact match of the TCIAN field is desired all eight tci_an_mask bits must be set If a match on the SCI field is desired make sure that the SCI field is expected in the packet and match on the SC bit in the TCI field (SC bit must be set) For packets without an SCI field the TCI field in combination with the MAC source address determines the match criterion (as defined in the IEEE 8021AE standard)

The VLAN ID output can be undefined for non-VLAN packets When matching packets on VLAN ID also match on vlan_valid = 1

A packet is matched on the parsed Ethertype from the VLAN classification logic This differs from the Ethertype used by the control packet classification logic

Each flow can be enabled or disabled individually Only enabled flows are selected when they match a frame When multiple enabled flows match a frame the one with the highest match_priority field (a number from 0 to 15) will be selected among equal priority flows the one with the lowest index will be selected

The match_priority field is always 4-bit wide (16 priority levels) regardless of the number of SAs supported in the given configuration The SA_MATCH_PARAMS registers control the SA match criteria

Table 41 bull Match Criteria and Maskable Bits

EgressIngress SA Match Classifiers Data Bits Mask BitsMAC SA and MAC DA (mask bit per byte) 96 12

MAC Ethertype (parsed Ethertype) 16 1

VLAN class parsing result (vlan_valid qtag_valid stag_valid qinq_found)

4 4

VLAN UP (parsed User Priority) 3 1

VLAN ID 12 1

Inner VLAN UP (inner User Priority when Q-in-Q is detected)

3 1

Inner VLAN ID (inner VLAN ID when Q-in-Q is detected) 12 1

Source port (controlleduncontrolledcommonreserved) 2 1

Control packet 1 1

MACsec tag classifier output (untaggedtaggedbad tagKaY)

0 4

MACsec SCI (compared only for MACsec tagged frames available only in ingress)

64 1

MACsec TCIAN (compared only for MACsec tagged frames available only in ingress individually masked)

8 8

Field_2B_16B (used in MPLS header bypass mode) 64 64

SA match priority 4 0

Entry enable 1 0

37522 Enabling and Disabling FlowsSA_MATCH_CTL_PARAMS registers control the enabling and disabling of matching table entries in the main SA matching module It is also possible to set clear and toggle enable bits with a single write action

Note To write the match registers of an SA flow or the MACsec context the flow must be disabled first to ensure that all flow parameters are loaded into the engine when the flow is enabled again

If the block supports more than 32 SAs setting clearing and toggling of enable bits for SA entries beyond 32 requires two write operations The upper flags are stored with the first write operation to SAM_TOGGLE2 SAM_SET2 or SAM_CLEAR2 respectively The action for all SA entries is applied and the upper flags are cleared to zero with the second write operation to SAM_TOGGLE1 SAM_SET1 or SAM_CLEAR1 respectively

Each SA flow can be enabled or disabled individually If an SA flow is disabled it will not match any packets

When a previously enabled SA flow is disabled (by writing to the SAM_ENTRY_CLEAR12 or SAM_ENTRY_TOGGLE12 registers) the hardware loads the unsafe field in SAM_IN_FLIGHT register with the number of packets currently processed in the pipeline and the software must wait for the unsafe field to reach zero before it writes to the MACsec context or any of the registers belonging to that SA flow This is necessary to make sure that all packets that might make use of the disabled flow or the associated MACsec context have left the engine

37523 Flow ActionsEach SA flow has a SAM_FLOW_CTRL_IGREGR register that specifies the action that must be taken when a frame is matched by that SA flow The action is determined by one of the following four flow types

bull Bypass- The frame is passed unchanged bull Drop- The frame is dropped The drop_action field specifies the action

The packet can be forwarded with a corrupt CRC indicationThe packet can be forwarded with a bad packet (packet error) indication

Note In both cases the frame abort signal is set towards the MAC and the drop behavior is the same

bull The packet can be dropped internally The dropped packet does not appear on the output of the MACsec because the drop_internal decision is taken before the end of the packet is seen This operation can drop packets received with CRC andor packet errors

37524 MACsec Ingress and Egress ProcessingMACsec ingress and egress processing includes performing the MACsec transform (addingremoving SecTag encryptiondecryption and generatingverifying ICV) post-processing steps and updating statistics counters A properly configured MACsec block implements all per-packet steps of a compliant MACsec implementation

The flow action also specifies the destination port of the packet (as defined in the IEEE 8021AE standard) in a two-bit field that appears at the output of the data pipeline to PKT128to64 and will be used for statistics

The following table shows the egress SA flow action related to a matching entry as defined in the SAM_FLOW_CTRL_EGR register

Table 42 bull Egress SA Flow Actions

SA Flow Action Description Data BitsFlow type BypassDropEgress process 2

The following table shows the ingress SA flow action related to a matching entry as defined in the SAM_FLOW_CTRL_IGR register

MACsec contexts which store the sequence number keys SCI and other information are used for further transformation of frames for MACsec egressingress flow type processes

37525 Non-Matching FlowsThe SAM_NM_FLOW_NCPSAM_NM_FLOW_CP registers define how packets that did not match any of the SA match entries are handled This is subdivided into eight packet type categories split by whether or not the packet was classified as a control packet and the output of the MACsec tag classification logic (untaggedtaggedbad tagKaY)

Dest_port Destination port00b Common port01b Reserved port10b Controlled Port11b Uncontrolled port

2

Drop_action Defines the way drop operation is performed 2

protect_frame 1b Enable frame protection0b Bypass frame through crypto-core

1

sa_in_use MACsec SA is in use for the looked up SA 1

include_sci Enables use of implicitexplicit SCI 1

use_es Enable ES bit 1

use_scb Enable SCB bit 1

Tag_bypass_size The number of allowed tags to bypass MACsec (012) 2

Confidentiality offset The number of bytes that must be authenticated but not encrypted after SecTAG

7

Confidentiality protect Enables confidentiality protection 1

Table 43 bull Ingress SA Flow Actions

SA Match Action Description Data BitsFlow Type BypassDropIngress process 2

2

Drop_non_reserved Perform drop_action if packet is not from the reserved port 1

Replay_protect EnableDisable frame replay protection 1

validate_frames Frame validation level for MACsec ingress processing (disablecheckstrict)

2

Confidentiality offset The number of bytes that must be authenticated but not decrypted after SecTAG

7

Table 42 bull Egress SA Flow Actions (continued)

SA Flow Action Description Data Bits

The actions specified for each flow are a subset of those specified for SA flows (only pass and drop are possible) Each of these flows can specify that a packet must be dropped or bypassed It also specifies the destination port The way a packet must be dropped can also be specified

3753 VLAN Tag and EoMPLS Header Bypass ModesVLAN tag bypass and EoMPLS header bypass are advanced MACsec processing modes with the following classification extensions to the standard configuration

bull Handling of VLAN Tag bypass format (tag bypass)bull Handling of EoMPLS header bypass format (header bypass)bull Processing of packets with SecTAG appearing after one or two VLAN tags where VLAN tags are not

included in the cryptographic operations (Microsemi tag bypass format)bull Processing of packets with SecTAG (and C-SA amp C-DA) appearing after an Ethernet Header (SA

DA ET) with from 2 to 16 bytes of data where the header and data is not included in the cryptographic operations (Microsemi header bypass format)

bull Control packet detection for packets in these proprietary formatsbull Programmable match fields used in SA lookup for packets in these proprietary formats

37531 Tag Bypass Frame FormatTag bypass is an extension to the standard MACsec frame that allows one or two VLAN tags in front of the SecTAG These VLAN tags are fully excluded from MACsec protection and bypassed instead The following illustration shows the format of the frame

Figure 89 bull VLAN Tag Bypass Format

The following logic is used to process the tag bypass format

bull For egress processing the number of bypassed VLAN tags for encryption is looked-up in the MACsec flow action (SAM_FLOW_CTRL_EGRTAG_BYPASS_SIZE) If this value is zero the standard MACsec protection is applied

bull For ingress processing the number of bypassed VLAN tags is determined by the VLAN parser and position of the SecTAG The VLAN parser does not look beyond the SecTAG

bull KaY packets (to be bypassed) are detected on both egress and ingress configurations (the VLAN parser defines SecTAG position)

bull VLAN tags that bypass MACsec processing are fully excluded from the encryption and authentication such that the receiver side must be able to remove the bypassed VLAN tags without breaking the MACsec packet

37532 EoMPLS Header Bypass Frame FormatEoMPLS Header Bypass is an extension to the frame handling of the standard MACsec frame format that allows an additional proprietary header in front of the MAC frame The following illustration shows the format of the frame

DA SA 1 or 2 VLAN Tags Rest of Payload FCS

Original Frame (pre-encrypt post-decrypt)

Secure frame TAG Bypass format

SecTAG ICV

Protected by ICV

Bypasses MACsecInserted Inserted Updated

Encryptedopt confident offset

Figure 90 bull EoMPLS Header Bypass Format

The following restrictions are applied to the EoMPLS header bypass format

bull The mode is statically controlled by programming the size of the bypassed header Size of zero indicates absence of the bypassed header

bull No other secure format is possible on the port when header bypass is enabledbull 2Bndash16B field is always one size on a port configurable to be 2 4 616 Bytes A static configuration

register specifies size of the field For EoMPLS this is generally configured as multiple of 4BThe following logic is used to process the EoMPLS header bypass format

bull Control Packet Detection- Based on Etype2 matching a configured (static) valueIf Etype2 matches detect and process control packets using MAC_DA MAC_SA and parsed Etype (after MAC_SA) to detect EAPOLMKA transported in MPLS tunnelsOther Etype2 values detect and process control packets using MAC_DA2 MAC_SA2 and Etype2 to detect any other MAC control frames

bull SecTAG Position- Determined by size of 2Bndash16B field and located right after itbull Egress SA Match- Uses Etype2 up to first 64 bits of the 2Bndash16B field MAC_DA and MAC_SA

The 2Bndash16B match field in the SA is bit-maskable bull Ingress SA Match- Uses Etype2 up to first 64 bits of the 2Bndash16B field MAC_DA MAC_SA and

SecTAG fields The 2Bndash16B match field in the SA is bit-maskable

3754 MACsec TransformThe MACsec transform carries out the actual frame transformation For egress MACsec operations it inserts the SecTAG optionally encrypts the payload data and appends the ICV For ingress MACsec operations it removes the SecTAG optionally decrypts the payload data and removes and validates the ICV The MACsec transform stage can detect error conditions (such as sequence number and authentication errors) that cause the frame to be dropped by applying a flow define drop_action

The MACsec transform does not detect errors in the SecTag that the MACsec classification logic can catch Only packets that are classified as tagged (valid non-KaY tag) may be submitted to ingress MACsec processing

The MACsec transform stage uses the MACsec crypto engine for the actual MACsec transform which operates in the following two major modes

bull In MACsec mode the crypto engine is active and MACsec transforms can be performedbull In static bypass mode the crypto engine is effectively bypassed which leads to a lower system

latency In this mode no MACsec transforms are possible The classification consistency checking and MTU check logic are still functional and the MACsec block may still filter (pass or drop) frames

The MISC_CONTROL register enables static bypass controls the latency equalization function allows MACsec-compliant handling of MACsec frames for which no MACsec SA is available and controls the maximum size of transform record

If a MACsec SecY receives a MACsec frame on the common port for which it has no SA and the frame payload is unchanged (authenticate-only operation C = 0 E = 0) it can still forward the frame to the

DA2 Etype2 Rest of Payload

SA2 2B ndash 16B DA SA FCS

Secure frame Header Bypass format

Bypasses MACsecInserted Inserted UpdatedEncrypted

opt confident offset

DA2 Etype2 Rest of PayloadSA2 2B ndash 16B DA SA FCSICVSecTAG

Protected By ICV

controlled port without checking the authentication simply by stripping the SecTAG and ICV This will occur if all the following conditions are met

bull The frame is classified as tagged bull The frame is not matched by any installed MACsec SAs The frame may either match no SA flow at

all or a non-MACsec SA flowbull The flow type of SAM_NM_FLOW_CPSAM_NM_FLOW_NCP (whichever is applicable to that

packet) for tagged frames is set to bypassbull The TCI field has C = 0 E = 0bull The nm_macsec_en bit is setbull The validate_frames setting is either disabled or check but not strict

37541 MACsec Context and Transform RecordThe MACsec block contains an array of MACsec transform records that correspond to the number of supported SAs Each transform record is 20 times 32-bit words (80 bytes) in size in the ingress direction and 24 times 32-bit words (96 bytes) in size in the egress direction and corresponds to the SA flow with the same index The MACsec transform operation is fully specified by a combination of the contents of the SAM_FLOW_CTRL_IGREGR register and the contents of the transform record It corresponds to the operation of a single MACsec SA

Transform record refers to the data structure as stored in the array MACsec context refers to the information contained in a transform record Transform record data are stored in the XFORM_RECORD_REGS registers The following tables show the format for each transform record

Table 44 bull Transform Record Format (Non-XPN)

128 Bit AES Keys 256 Bit AES key128 Bit block Egress Ingress Egress Ingress0 CTRL Word CTRL Word CTRL Word CTRL Word

Context ID Context ID Context ID Context ID

Key0 Key0 Key0 Key0

Key1 Key1 Key1 Key1

1 Key2 Key2 Key2 Key2

Key3 Key3 Key3 Key3

HashKey0 HashKey0 Key4 Key4

2 HashKey2 HashKey2 Key6 Key6

Seq Seq HashKey0 HashKey0

IV0 Mask11

1 For MACsec MASK is an unsigned integer controlling a valid range of packet numbers

HashKey1 HashKey1

3 IV1 IV0 HashKey2 HashKey2

(Zero) IV1 HashKey3 HashKey3

(Zero) (Zero) Seq Seq

(Zero) (Zero) IV0 Mask1

4 IV1 IV0

(Zero) IV1

(Zero) (Zero)

All fields of the transform record must be populated by the host software before the corresponding SA flow can be enabled The ctx_size bit in the CONTEXT_CTRL register controls the size of the context that must be fetched For bypass and drop flows the transform record is not used The hardware only updates the sequence number field it does not modify the other fields during MACsec egress and ingress processing

The context control word is the first 32-bit word in each transform record It specifies the type of operation Only those settings that are relevant for MACsec operations need to be defined The following table shows the fields in context control word

Table 45 bull Transform Record Format (XPN)

Key0 Key0 Key0 Key0

Key1 Key1 Key1 Key1

Key3 Key3 Key3 Key3

Seq Low Seq Low HashKey0 HashKey0

Sec High Sec High HashKey1 HashKey1

3 DUMMY Sec Mask HashKey2 HashKey2

IS0 (Salt) IV0 (Salt) HashKey3 HashKey3

IS1 (Salt) IV1 (Salt) Seq Low Seq Low

IS2 (Salt) IV2 (Salt) Sec High Sec High

4 IV0 (SCI) DUMMY Sec Mask

IV1 (SCI) IS0 (Salt) IV0 (Salt)

IS1 (Salt) IV1 (Salt)

5 IV0 (SCI)

IV1 (SCI)

Table 46 bull Context Control Word Fields

Bits Name Description30 ToP Type of packet

0110b Egress 1111b IngressAll other values are invalid

4 Reserved Write with zero and ignore on read

5 IV0 First word of IV present in context (SCI for MACsec)Must be set to 1b

The following list shows the other fields of the transform record

bull Context IDUnique identifier for each context It is sufficient to give all transform records a different context ID possibly by assigning them a number from 0 to maximum index

bull Key 0 hellip Key 7AES encryption key for the MACsec SA Each word of the key is a 32-bit integer representing four bytes of the key in little-endian order The number of words depends on AES key length

bull H_Key 0 H_Key 1 H_Key 2 and H_Key 3128-bit key for the authentication operation It is represented in the same byte order as Key 0Key 7 It is derived from Key 0Key 7 as follows H_key = E (Key 128h0) This means performing a 128256 bit AES-ECB block encryption operation with Key 0Key 7 as the key and a block of 128 zero bits as the plaintext input The cipher-text result of the AES block encryption is the 128-bit H_Key

bull Sequence NumberFor egress MACsec this is one less than the sequence number (PN) that is to be inserted into the MACsec frame For a new SA this must be initialized to 0 After each egress packet this field is

6 IV1 Second word of IV present in context (SCI for MACsec)Must be set to 1b

7 IV2 Third word of IV present in context (use sequence number instead) Must be set to 0b

13 Updated Seq Update sequence numberMust be set to 1b for MACsec

14 IV Format If set use sequence number as part of IVMust be set to 1b for MACsec

15 Encrypt Auth If set encrypt ICVMust be set to 1b for MACsec

16 Key Load crypto key from contextMust be set to 1b for MACsec

1917 Crypto Algorithm Algorithm for data encryption 101b AES CTR 128 111b AES CTR 256

2221 Digest Type Type of digest keyOnly single digest key is supported setting 10b

2523 Auth Algorithm Algorithm for authenticationOnly AES-GHASH is supported setting 100b

2726 AN The two-bit Association Number inserted in the SecTag for egress operationsMust be kept 00b for ingress

2928 Seq type Type of sequence number only supported setting is 01bUse 32-bit sequence number on ingress use the mask as a replay window size

30 Seq mask Sequence mask is present in context0b Egress1b Ingress

31 Context ID Context ID present must be set to 1b

Table 46 bull Context Control Word Fields (continued)

Bits Name Description

incremented by 1 If it rolls over from 0xFFFFFFFF to 0 a sequence number error occurs and the context is not updated which means that the same error will occur again for any subsequent egress packets with that context - the external system will forward these packets to the line with CRCpacket error For ingress MACsec the sequence number must be initialized to 1

bull Mask (replay window size)Window size for ingress sequence number checking By default it is 0 (strict ordering enforced) It can be set to any integer value up to 232ndash1 in which case any nonzero sequence number is accepted

bull SCI 0 and SCI 1SCI that belongs to the specific MACsec SA An SCI that depends on the source MAC address and the ES and SCB bits is defined even in modes that do not explicitly transmit or receive the SCI with each packet This is a 64-bit block represented by two 32-bit integers in little-endian order It is the same byte order in which SAM_SCI_MATCH_HISAM_SCI_MATCH_LO represent an SCI

When the sequence number of an egress SA is about to roll over it must be replaced by a new SA with different keys It is not allowed to reset the sequence number of an egress SA to a lower value because doing so generally leads to sequence number checking failures at the receiving end of the connection

For inbound frames the PN is compared against the sequence number (PN) from the context resulting in one of the following three cases

bull If the received number is above or equal to the number in the context received_PN next_PNIn this case the context sequence number (PN) is updated (if the update_seq bit is set to 1b) The updated value is the received number plus one

bull If the received number is below the number from the context but within the replayWindowreceived_PN lt next_PN and received_PN ge (next_PN - replayWindow)In this case no context update is required

bull If the received number is below the number from the context and outside the replayWindowreceived_PN lt (next_PN - replayWindow) In this case the sequence number check fails and error bit e10 is set in the result token No context update is done

37542 MACsec Crypto Engine Interrupt ControlStatus RegisterThe INTR_CTRL_STATUS register provides control and status for interrupts within the MACsec crypto engine only The interrupt output pin controlled here is one of the inputs on the top-level Advanced Interrupt Controller (controlled using the AIC registers)

The following main interrupts are given by the Crypto engine

bull Bit 4 Outbound Sequence Number Threshold This interrupt is triggered if a sequence number exceeds the programmed sequence number threshold (specified in SEQ_NUM_THRESH) due to an outbound sequence number increment

bull Bit 5 Outbound Sequence Number Roll-overThis interrupt is triggered if a sequence number rolls over (increment from maximum to zero) due to an outbound sequence number increment

3755 Ingress Consistency CheckingConsistency checking is used to verify that MACsec ingress packets satisfy certain properties after decryption Packets are passed or dropped based on a set of rules The number of rules is a fixed hardware parameter As opposed to the static classification and flow lookup stages consistency checking logic inspects the packet data after the MACsec transform

Consistency checking logic contains a complete VLAN tag parser performing the same operations as the VLAN tag parser located in the input packet classification logic The configuration of the parser is controlled by a separate set of registers (IG_CP_TAG IG_PP_TAGS IG_PP_TAGS2 and IG_CP_TAG2) similar to the input packet VLAN tag parser It extracts the payload Ethertype from the second or third Ethertype location in the packet if that packet contains one and two VLAN tags respectively The VLAN tag parser also extracts (and post-processes) the following fields

bull User Priority field from the first VLAN tag it encounters to be used by the MTU checking logic and statistics counters update logic

bull VLAN ID and VLAN Up from the second VLAN tag in case of Q-in-Q Each consistency check rule can match on a set of mask-able match criteria If the corresponding mask bit is cleared the match criterion is not checked and packets can satisfy the rule regardless of the value in the packet If the corresponding mask bit is set a packet only satisfies the rule if the value in the packet matches the value in the rule The following list shows the mask-able match criteria

bull sai_hit (1b or 0b)- The packet was matched by one of the SA flows during flow lookup bull sai_nr (range 0 to SAmax-1)- The packet was matched by the specific SA flow (or is not matched

by any SA flow and has a specific combination of control packet and MACsec tag classification) To match packets that were matched by a specific SA flow also match on sai_hit = 1

bull vlan_valid (1b or 0b)- The packet contains a valid VLAN tag bull vlan_id (12 bits value)- The packet has the specified VLAN ID A match on this criterion is only

meaningful if also matched on vlan_valid = 1 bull vlan_id_inner (12 bits value)- The packet has the specified VLAN ID at second VLAN tag A match

on this criterion is only meaningful if also matched on vlan_valid = 1 and Q-in-Q is detected bull vlan_up_inner (3 bits value)- The packet has the specified VLAN Up at second VLAN tag A match

on this criterion is only meaningful if also matched on vlan_valid = 1 and Q-in-Q is detected bull etype_valid (1b or 0b)- The Ethertype is greater than cp_etype_max_len bull payload_e_type (16 bits value)- The packet has a specific Ethertype if a VLAN packet is detected

this value is the Ethertype following the VLAN tag bull ctrl_packet (1b or 0b)- The packet is a control packet If all mask bits are cleared the rule will match every possible packet

Each of the consistency check rules can be enabled or disabled individually If a rule is disabled it will not be selected for match checking If more than one enabled rule is matched the one with the highest priority (3 bit number from 0 to 7) is picked The lowest numbered rule is picked from equal priority rules

The rule that is eventually selected specifies either a pass or a drop action

If no rules match the default action is taken (pass or drop) It is possible to define different default actions for control and non-control packets After reset the default action for both of them is drop

ICC rule configuration is controlled by the IG_CC_PARAMS and IG_CC_PARAMS2 registers

3756 Output Post-ProcessorThe final stage of the pipeline is the output post-processor It implements the post-processing decision tree that includes MACsec-compliant post-processing as well as processing and MTU checking for non-MACsec frames It can drop the frame due to error conditions detected by the MACsec transform stage (such as sequence number rollover and authentication failure) it checks for the correct combinations of port numbers it checks the frame length against the MTU and it updates all statistics counters For ingress packets the post-processor uses results of the consistency checking modules VLAN tag detection logic instead of the VLAN parser in front of the MACsec crypto-engine

The post-process statistics updating is done in accordance with the IEEE 8021AE standard for secure frame generation and secure frame verification management control and frame counters

37561 MTU CheckingRegisters provide MTU limit values for VLAN tagged frames (per User Priority as provided by the consistency checking module) and one global MTU limit value for non-VLAN frames (detected by the consistency checking module) The limits programmed are also used for statistics counters that rely on an MTU value

Ingress Frame MTU Checking

bull The frame length is the size of the input frame (including header and excluding Ethernet preamble start-of-frame byte and CRC)

bull The VLAN User Priority is extracted from the VLAN tag as parsed (and post-processed) by the VLAN tag parser implemented in the consistency checking logic

Egress Frame MTU Checking

bull The frame length is the size of the output frame (including header and excluding Ethernet preamble start-of-frame byte and CRC)

bull The VLAN user priority is the one provided by the VLAN parsing logic in the static classification logicMTU checking is configured using the VLAN_MTU_CHECK and NON_VLAN_MTU_CHECK registers

37562 StatisticsThe following two types of statistics counters are used

bull Per-frame counters are 40 bits wide They overflow after about 1012 frames A MACsec block processing 10 Gbps traffic can process in the order of 107 frames per second so that the 40-bit counters only saturate after 105 seconds (one day)

bull Per-octet counters are 80 bits wide They overflow after about 1024 octets Even for a system that processes in excess of 109 bytes per second this means that they will never overflow during the expected lifetime of the system

The statistics counters can be configured to be auto-cleared on read They can also be configured to saturate at maximum value instead of rolling over

There are three classes of statistics counters as follows

bull Global Statistics- The MACsec block maintains global statistics counters to implement MACsec Some global statistics are maintained per-SA so they must be obtained by accumulating (summing) the per-SA statistics of the relevant SAs

bull Per-SA Statistics- The MACsec block maintains all per-SA statistics for ingress and egress MACsec operations Software maintains statistics for all four SAs that might belong to an SC It keeps the per-SA statistics even for SAs that it has deleted from the SA flow table When an SA flow is deleted its final SA statistics must be collected and added into the per-SA and per-SC statistics

bull Per-SC Statistics- The MACsec block does not maintain any per-SC statistics However the per-SC statistics are the sum of per-SA statistics of the SAs belonging to that SC Whenever the software reads per-SA statistics from the hardware it must not only add them to the per-SA statistics administration but to the per-SC statistics administration as well

The following tables show the per SA (per SC) global (SecY) and per user priority egress statistics generated Eight sets of user priority counters are implemented If a frame is detected as VLAN it also increments user priority counters in addition to per-SAglobal (SecY) counters

Table 47 bull Egress SA Counters

Egress SA STAT Counters SizesaOutOctetsEncryptedsaOutOctetsProtected 80

saOutPktsEncryptedsaOutPktsProtectedsaOutPktsHitDropReserved 40

saOutPktsTooLong (MTU check) 40

saifOutBroadcast 40

saifOutMulticast 40

saifOutUnicast 40

Table 48 bull Egress Global Counters

Egress Global Counters SizeglobalTransformErrorPkts 80

globalOutPktsCtrl 80

globalOutPktsUnknownSA 40

globalOutOverSizePkts (MTU check) 40

globalifOutBroadcast 40

globalifOutMulticast 40

The following tables show the per SA (per SC) global (SecY) and per user priority ingress statistics generated Eight sets of user priority counters are implemented If a frame is detected as VLAN it also increments user priority counters in addition toper-SAglobal (SecY) counters

globalifOutUnicast 40

globalifOutOctets 40

Table 49 bull Egress Per-User Global Counters

Egress Global Counters SizeVlanOutOctetsUP 80

VlanOutPktsUP 40

VlanOutDroppedPktsUP 40

VlanOutOverSizePktsUP 40

Table 50 bull Ingress SA Counters

Ingress SA STAT Counters SizesaInOctetsDecryptedsaInOctetsValidated 80

saInPktsUncheckedsaInPktsHitDropReserved 40

saInPktsDelayed 40

saInPktsLate 40

saInPktsOk 40

saInPktsInvalid 40

saInPktsNotValid 40

saInPktsAuthFail1

1 Implemented indirectly saInPktsAuthFail is reported in software by adding saInPktsInvalid and saInPktsNotValid saInPktsSAMiss is reported in software by adding saInPktsNotUsingSA and saInPktsUnusedSA

40

saInPktsNotUsingSA 40

saInPktsUnusedSA 40

saInPktsSAMiss1 40

saInPktsUntaggedHit 40

saifInBroadcast 40

saifInMulticast 40

saifInUnicast 40

Table 51 bull Ingress Global Counters

Ingress Global Counters SizeglobalTransformErrorPkts 80

globalInPktsCtrl 80

globalInPktsNoTag 40

Table 48 bull Egress Global Counters (continued)

Egress Global Counters Size

3757 Correlation with IEEE 8021AE MACsec StatisticsThe following table shows how the MACsec block statistics are derived from the MACsec standard

globalInPktsUntagged 40

globalInPktsTagged 40

globalInPktsBadTag 40

globalInPktsUntaggedMiss 40

globalInPktsNoSCI 40

globalInPktsUnknownSCI 40

globalInPktsSCIMiss

globalInConsistCheckControlledNotPass 40

globalInConsistCheckUncontrolledNotPass 40

globalInConsistCheckControlledPass 40

globalInConsistCheckUncontrolledPass 40

globalInOverSizePkts 40

globalifInBroadcast 40

globalifInMulticast 40

globalifInUnicast 40

globalifInOctets 40

Table 52 bull Ingress Per-User Global Counters

VlanOutPktsUP 40

Table 53 bull IEEE 8021AE Correlation

MACsec name (IEEE 8021AE) Direction Type Microsemi MACsec registerFrame verification statistics (MACsec specification 1079)

InPktsUntagged Ingress Global globalInPktsUntagged

InPktsNoTag Ingress Global globalInPktsNoTag

InPktsBadTag Ingress Global globalInPktsBadTag

InPktsUnknownSCI Ingress Global globalInPktsUnknownSCI

InPktsNoSCI Ingress Global globalInPktsNoSCI

InPktsOverrun Ingress Global Not implemented condition does not occur report as zero

InPktsUnchecked Ingress Per-SC saInPktsUnchecked

InPktsDelayed Ingress Per-SC saInPktsDelayed

Table 51 bull Ingress Global Counters (continued)

Ingress Global Counters Size

3758 InterruptsThe MACsec block can raise five interrupts from ingress and four from the egress block The available interrupts are as follows

37581 MACsec Crypto-Core Interrupt Indicates several errors detected by the MACsec crypto engine block The software must read the INTR_CTRL_STATUS register of the MACsec crypto core to see which condition caused the interrupt The software must then write the same bits to INT_CTRL_STATUS to clear the interrupt condition as applicable

bull Input error (bit 0) may occur if the MACsec crypto core attempts to process certain malformed short MACsec packets where the packet is shorter than indicated by the SL field

bull Output error and fatal error (bits 1 and 14) indicate a hardware error bull Processing error (bit 2) may indicate a hardware error but more likely the flow type in

SAM_FLOW_CTRL is inconsistent with the context control word in the transform record (MACsec ingress versus MACsec egress)

InPktsLate Ingress Per-SC saInPktsLate

InPktsOK Ingress Per-SC per-SA saInPktsOK

InPktsInvalid Ingress Per-SC per-SA saInPktsInvalid

InPktsNotValid Ingress Per-SC per-SA saInPktsNotValid

InPktsNotUsingSA Ingress Per-SC per-SA saInPktsNotUsingSA

InPktsUnusedSA Ingress Per-SC per-SA saInPktsUnusedSA

Frame validation statistics (MACsec specification 10710)

InOctetsValidated Ingress Global Accumulate over each ingress SA with authentication only saInOctetsDecryptedValidated

InOctetsDecrypted Ingress Global Accumulate over each ingress SA with encryption saInOctetsDecryptedValidated

Frame generation statistics (MACsec specification 10718)

OutPktsUntagged Egress Global globalOutPktsUntagged

OutPktsTooLong Egress Global Accumulate over each egress SA saOutPktsTooLong

OutPktsProtected Egress Per-SC per-SA saOutPktsEcnryptedProtected if the SA is authenticate only

OutPktsEncrypted Egress Per-SC per-SA saOutPktsEncryptedProtected if the SA uses encryption

Frame protection statistics (MACsec spec 10719)

OutOctetsProtected Egress Global Accumulate over each egress SA with authentication only saOutOctetsEncryptedProtected

OutOctetsEncrypted Egress Global Accumulate over each egress SA with encryption saOutOctetsEncryptedProtected

Table 53 bull IEEE 8021AE Correlation (continued)

MACsec name (IEEE 8021AE) Direction Type Microsemi MACsec register

bull Context error (bit 3) indicates an error in the transform record probably the context control word especially the settings for encryption and authentication algorithms

bull Sequence number threshold (bit 4) indicates that an egress flow has exceeded its sequence number threshold The MACsec SA must be re-keyed to prevent a sequence number rollover Exceeding the sequence number threshold will not affect packet processing it is meant to be used as a warning for imminent sequence number rollover

bull Sequence number rollover (bit [5]) indicates that an egress flow has encountered a sequence number rollover The software must look in the transform record table to see which active egress SA has a sequence number value of 0xFFFFFFFF in case of 32-bit Packet number or 0xFFFFFFFF_FFFFFFFF in case of 64-bit packet number This egress SA flow must immediately be disabled and it must be re-keyed

Use the following steps to make effective use of the sequence number threshold interrupt

1 Set the SEQ_NUM_THRESHOLD register to an appropriate value A suitable value might be 0xF0000000 for a 32-bit packet number

2 Make sure the sequence number threshold interrupt is enabled Use the following steps if the sequence number threshold interrupt occurs

1 Temporarily disable the sequence number threshold interrupt then clear that interrupt bit 2 Check all transform records of active egress SAs for a sequence number that is either over the

threshold or close to it (any egress SA with a sequence number above 0xE0000000) 3 Start a re-keying procedure for all those SAs 4 After re-keying has been completed (and new SAs are installed on both sides of the connection) re-

enable the sequence number threshold interrupt

37582 Classification Drop Interrupt Raised when a packet is dropped by the flow lookup logic where either the SA flow or the non-matching flow specifies a drop action

37583 Consistency Check Drop Interrupt (ingress only) Raised when a packet is dropped by the ingress consistency checking logic

37584 Post-Processing Drop Interrupt Raised when a packet is dropped by the post-processing stage for any other reason than MTU check failure Ingress packets with an ICV check failure or sequence number check failure raise this interrupt

37585 MTU Check Drop Interrupt Raised when a packet is dropped due to MTU check failure

Note Frequent packet dropping may indicate an attack attempt a configuration error or a software malfunction

3759 Updating the MACsec SA for IngressFor synchronization purposes the MACsec standard requires the lowestPN and the nextPN in an active SA to be updated to a greater value provided by the KaY (unless it is not already reached) This is achieved in the MACsec core by updating the sequence number in an active context to a greater value if the sequence number in the context did not reach this value The lowest acceptable PN is implicitly updated assuming that the replay window size is not changed The host must program next_pn_lower (and next_pn_upper for XPN flow) to the desired sequence number must specify the flow for which the update should occur in next_pn_context_id register and should enable the update in enable_update register MACsec core will clear this enable_update register once the transform record field is updated If the sequence number is already equal or above the configured value then no internal update is performed

376 Debug Fault Code in FCSIncrementing a counter for a packet may be a security failure in some cases The SA_SECFAIL_MASKGLOBAL_SECFAIL_MASK register can be used to configure which counter increments are regarded as security fail events Debug functionality enables packets failing security check to be transmitted with corrupted FCS which consists of a debug fault code to debug the security

failing packet The FCS of a frame failing security check is corrupted on the output The corrupted FCS field contains a fault code for debugging using a frame analyzer The fault code uses 31 bits with the last FCS bit reserved to make sure the FCS check fails

The following table shows the FCS fault code for the 32 bits

The following tables show the format of the ingress global and SA stat event vectors

Table 54 bull FCS Fault Codes

Bit Description31 Reserved to make sure that FCS check fails

30 SA hit

2924 SA pointerIf the SA-hit bit[30] is 0 then bits[2927] are reserved bit[26] indicates if the frame is classified as control frame and bits[2524] indicate the MACsec tag classification of the frame00b = untagged 01b = tagged 10b = bad tag 11b = KaY tag

2310 Global stat event vector

90 SA stat event vector

Table 55 bull Ingress Global Stat Event Vector Format

Event Bit Position Ingress Global Counter0 globalTransformErrorPkts

1 globalInPktsCtrl

2 globalInPktsNoTag

3 globalInPktsUntagged

4 globalInPktsTagged

5 globalInPktsBadTag

6 globalInPktsUntaggedMiss

7 globalInPktsNoSCI

8 globalInPktsUnknownSCI

9 globalInConsistCheckControlledNotPass

10 globalInConsistCheckUncontrolledNotPass

11 globalInConsistCheckControlledPass

12 globalInConsistCheckUncontrolledPass

13 globalInOverSizePkts

14 globalifInUcastPkts

15 globalifInMulticastPkts

16 globalifInBroadcastPkts

17 globalifInOctets

Table 56 bull Ingress SA Stat Event Vector Format

Event Bit Position Ingress SA Stat Counter0 saInOctetsDecryptedInOctetsValidated

The following tables show the format of the egress global and SA stat event vectors

1 saInPktsUncheckedInPktsHitDropReserved

2 saInPktsDelayed

3 saInPktsLate

4 saInPktsOk

5 saInPktsInvalid

6 saInPktsNotValid

7 saInPktsNotUsingSA

8 saInPktsUnusedSA

9 saInPktsUntaggedHit

10 saifInUcastPkts

11 saifInMulticastPkts

12 saifInBroadcastPkts

Table 57 bull Egress Global Stat Event Vector Format

Event Bit Position Egress Global Counter0 globalTransformErrorPkts

1 globalOutPktsCtrl

2 globalOutPktsUnknownSA

3 globalOutPktsUntagged

4 globalOutOverSizePkts (MTU check)

5 globalifOutUcastPkts

6 globalifOutMulticastPkts

7 globalifOutBroadcastPkts

8 globalifOutOctets

139 Reserved zeroes

Table 58 bull Egress SA Stat Event Vector Format

Event Bit Position Egress SA Stat Counter0 saOutOctetsEncryptedOutOctetsProtected

1 saOutPktsEncryptedOutPktsProtectedOutPktsHitDropReserved

2 saOutPktsTooLong (MTU check)

3 saifOutUcastPkts

4 saifOutMulticastPkts

5 saifOutBroadcastPkts

106 Reserved zeroes

Table 56 bull Ingress SA Stat Event Vector Format (continued)

Event Bit Position Ingress SA Stat Counter

377 Capture FIFOA 512-byte capture FIFO can be used to capture up to first 504 bytes for packets failing any security check The security fail event can be used as a trigger The FIFO can also be enabled to capture the first packet of any given SA using the CAPT_DEBUG_TRIGGER_SA12 control Multiple packets can also be captured and the maximum size of the packet to be captured is configured using CAPT_DEBUG_CTRLMAX_PKT_SIZE This FIFO can be programmed to capture frames from either egress or ingress direction (CAPT_DEBUG_CTRLSIDE) Frames are captured after MACsec transformation Software can view the FIFO as 32-bit wide and 128 deep Each 32-bit location is accessible to CSR using CAPT_DEBUG_DATA (0 to 127) Each packet is captured in the FIFO with a 64-bit administration header The following illustration shows the layout of multiple packets in the capture FIFO

Figure 91 bull Capture FIFO Layout

Each stored packet is preceded by a 64-bit administration header that contains the following information

3771 ADM_HDR0 22 bits reserved 1 bit truncated 9 bit pkt_size

3772 Truncated (1 bit) Indicates the packet is truncated and only a part of the packet is captured The captured packet could be truncated because the packet could be bigger than the MAX_PKT_SIZE programmed by software to capture

3773 Pkt_size (9 bits) Indicates the size of the captured packet in bytes

3774 ADM_HDR1 32-bit security fail debug code see section 441

The status of the capture FIFO can be accessed using the CAPT_DEBUG_STATUS register (PKT_COUNT FULL WR_PTR)

Use the following steps to capture frames

PKT1

ADM_HDR0

ADM_HDR1

PKT2

ADM_HDR0

ADM_HDR1

32-bit

128-deep

1 Decide the SIDE and MAX_PKT_SIZE and program in CAPT_DEBUG_CTRL2 Enable the SA to capture the first packet For enabling first packet capture on any SA program

CAPT_DEBUG_TRIGGER_SA1SA2 = 0xFFFFFFFF To enable first packet capture on SA index [0] program CAPT_DEBUG_TRIGGER_SA1 = 0x1

3 Enable the capture by programming CAPT_DEBUG_TRIGGERENABLE = 14 Send frames5 Keep polling CAPT_DEBUG_STATUS to see if any frames have been captured (PKT_COUNT

FULL WR_PTR)6 If PKT_COUNT gt 0 then frames have been captured read CAPT_DEBUG_TRIGGER_SA1SA2 to

confirm if the packet for that SA has been captured Bits will fall back to 0b automatically when a packet is captured for the SA

7 Stop the capture by programming CAPT_DEBUG_TRIGGERENABLE = 0 to enable software to access the FIFO

8 Read CAPT_DEBUG_DATA (0 to 127) to read the packet from the capture FIFO

378 Flow Control BufferThe following list provides an overview of the flow control buffer functionality in the VSC8490-17 device

bull Frame buffering in egress to handle frame expansion by MACsec and flow control back-pressure to hostswitch ASIC

bull Frame buffering in ingress to handle pause frame insertion (from host MAC) and rate adaptationbull Cut-through mode of operationbull Configurable pause reaction (including pause timer handling) for line received pause framesbull Pause generation triggers to host MAC based on configurable XOFFXON thresholdsbull Control queue and data queue with strict priority scheduling in egress with highest priority given to

control queuebull Transmit MAC control frames irrespective of pause statebull Rate adaptation between line and host clocks for PPM compensationbull Rate difference between line and host clocks based on LANWAN modesbull Flow control (back-pressure) feedback from MACsec block by compensating gap between framesbull Pass link faultLFRFLPI in both directions using special control word in-band with framesbull EEE controller state machine for activating LPI and wake-upbull 4X MTU buffering in egressbull Ingress buffer for pause frame insertion by host MACbull ECC support in RAMsbull Frame drops recorded for statisticsbull Sticky bits and interrupt

3781 Flow Control HandlingThis section describes the basic flow control mode of operation Buffering provided handles frame expansion and its own latency Buffering required for long interconnects that depend upon cablefiber length need to be provided separately The following illustration shows the sequence of events when a pause frame is received from line

Figure 92 bull Line Back-Pressure by Remote Link Partner

The following steps describe the sequence of events depicted in the illustration

1 Pause frame (XOFF) is received by PHY at line MAC Rx This frame is internally consumed by MAC The MAC Rx signals the Tx FC buffer with pause received indication and pause quanta

2 The Tx FC buffer goes to pause state at the next frame boundary Pause timer will be maintained by Tx FC buffer and is started only after it goes to pause state which may be immediate in some cases The Tx FC buffer drain rate is 0 and fill rate can be max port speed The Tx FC buffer signals XOFF to host MAC Tx to schedule a pause transmission upstream This signaling is shown via the optional OR gate Without back-pressured from the remote link partner the Tx FC buffer uses XOFFXON thresholds to signal XOFFXON to host MAC Tx to manage frame expansion due to MACsec

3 The host MAC Tx can schedule a pause frame for transmission at the next frame boundary The Tx FC buffer needs to be able to hold at least one jumbo frame until XOFF pause is scheduled so that it can continue to receive data downstream The XOFF frame is then received by hostswitch

4 The host device can only stop transmission at next frame boundary because it may have started transmitting a second jumbo frame

The following configuration signals control the basic flow control mode

37811 PAUSE_REACT_ENA Enables pause reaction and pause timer maintenance in egress flow control buffer Set to 1

37812 PAUSE_GEN_ENA Enables XON and XOFF pause frame signaling to host MAC based on XON and XOFF thresholds Set to 1

37813 INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN Enables the optional OR and AND gate Set to 1 If not enabled the pause gen signaling to host MAC is purely based on XOFFXON thresholds

The following illustration shows the sequence of events when a pause frame is received from host

Host MAC Rx(Egress)

1588(Egress)

MACSec(Egress)

Line MAC Tx(Egress)

FC Buffer(Egress)

1588(Ingress)

MACSec(Ingress)

FC Buffer(Ingress)

H L

xMII

Host SwitchMAC

2

1

3

4

PHY with MACSec

Tx-XOFF Tx-XON

AND

OR

xMII

Figure 93 bull Host Back-Pressure by Remote Link Partner

1 Host experiences congestion in ingress and sends pause (XOFF) to line2 Host MAC Rx receives pause frame It is not enabled to react on received pause frames so it

passes the pause frame to Tx FC buffer3 Tx FC buffer maintains two logical queues one for data and one for MAC control frames If a data

frame is already scheduled and in progress it passes on MAC control frames at the next boundary to quickly relay MAC control frames to line despite the presence of other data frames in the data queue

4 Tx FC buffer transmits any or all control frames in the control queue5 Pause frame passes through the MACsec block The MACsec egress block detects frame as a

control frame and does not encrypt it Frame eventually passes through the line MAC Tx block and the rest of the PHY blocks

TX_CTRL_QUEUE_ENA determines if the control queue is enabled in the egress flow control buffer This should be set to 1 in basic flow control mode The physical memory of egress FC buffer can be partitioned between data and control queues using TX_CTRL_QUEUE_STARTEND and TX_DATA_QUEUE_STARTEND configuration fields

3782 Advanced Flow Control HandlingThe following illustration shows the sequence of events when the PHY is configured to the advanced flow control mode of operation PAUSE_GEN_ENA needs to be set to 1 and other configuration bits of FC buffer (such as PAUSE_REAhT_ENA INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN and TX_CTRL_QUEUE_ENA) need to be set to 0 All other configurations for this mode are part of line MAC and host MAC

Host MAC Rx(Egress)

1588(Egress)

MACSec(Egress)

Line MAC Tx(Egress)

FC Buffer(Egress)

1588(Ingress)

MACSec(Ingress)

FC Buffer(Ingress)

Host SwitchMAC

5

1

PHY with MACSec

CRTL Queue

2

3

4xMII

xMII

Figure 94 bull Advanced Flow Control Handling

37821 PHY Back-Pressured by Remote Link Partner1 Pause frame (XOFF) is received by PHY at line MAC Rx This frame is internally consumed by MAC

Line MAC Rx signals line MAC Tx with pause received indication and pause quanta 2 Line MAC Tx goes to pause state at the next frame boundary Line MAC Tx stalls to pause the

pipeline Pause timer maintained by line MAC Tx is started only after it goes to pause state The Tx FC buffer signals XOFFXON to host MAC Tx based on XOFFXON threshold

37822 Host Back-Pressuring Remote Link Partner3 System pause is consumed by host MAC Rx Pause timer maintained in host MAC Rx (instead of

Tx) for egress direction to generate XOFFXON pause gen signal for line MAC Tx4 Line MAC Tx stalls to send pause frame (either XOFF or XON) This path will work irrespective of

whether line MAC is in pause state

3783 Frame Drop StatisticsThe following 32-bit counters provide frame drop statistics These counters roll over to 0 when the maximum value is reached

37831 TX_CTRL_QUEUE_OVERFLOW_DROP_CNT Number of control frame drops due to overflow in the control queue of the egress flow control buffer

37832 TX_CTRL_QUEUE_UNDERFLOW_DROP_CNT Number of control frame drops due to underflow in the control queue of the egress flow control buffer

37833 TX_CTRL_UNCORRECTED_FRM_DROP_CNT Number of control frames aborted due to ECC check fail during reading from RAM in egress flow control buffer

37834 TX_DATA_QUEUE_OVERFLOW_DROP_CNT Number of data frame drops due to overflow in the data queue of the egress flow control buffer

37835 TX_DATA_QUEUE_UNDERFLOW_DROP_CNT Number of data frame drops due to underflow in the data queue of the egress flow control buffer

37836 TX_DATA_UNCORRECTED_FRM_DROP_CNT Number of data frames aborted due to ECC check fail during reading from RAM in egress flow control buffer

Host MAC Rx(Egress)

1588(Egress)

MACSec(Egress)

Line MAC Tx(Egress)

FC Buffer(Egress)

1588(Ingress)

MACSec(Ingress)

FC Buffer(Ingress)

H L

xMII

Host SwitchMAC

2

1

3

4

PHY with MACSec

Tx-XOFF

Pause

xMII

Tx-XOFF Tx-XON

Tx-XOFF XON

37837 RX_OVERFLOW_DROP_CNT Number of frame drops due to overflow in the ingress flow control buffer

37838 RX_UNDERFLOW_DROP_CNT Number of frame drops due to underflow in the ingress flow control buffer

37839 RX_UNCORRECTED_FRM_DROP_CNT Number of frames aborted due to ECC check fail during reading from RAM in ingress flow control buffer

379 Media Access ControlThis section describes the media access control sub layer (MAC) block There are two instances of MAC block in each channel One instance which interfaces with MACsec and PCSPMA is called Line MAC and the other instance that interfaces with FC Buffer and PHY XS is called Host MAC

The MAC is defined in IEEE 8023 clauses 3 and 4 The purpose of the MAC is to control the MACsec block access to the physical layer In other words it takes frames from the MACsec and converts those to a continuous byte stream on the xMII interface In doing so it is responsible for frame CRC generation and checking preamble insertion and extraction and pause frame generation and detection The MAC block also contains the counters for an SNMP management information base (MIB) statistics module

The MAC block supports frame sizes up to 10240 bytes in both receive and transmit directions The maximum frame size is controlled by the host The maximum frame size can also be set to the standard 1518 bytes or 1522 bytes if desired Maximum frame length restrictions are not enforced in the transmit direction The following illustration shows the block diagram of MAC

Figure 95 bull MAC Block Diagram

3791 MAC TransmitThe transmit section of the MAC contains three blocks packet interface wrapper pause frame generator and MAC Tx kernel All three blocks operate off the same clock TX_MAC_CLK

RX-MAC

TX- MAC

KERNEL

Pause Frame

Detector

Pause Frame

Generator

Configuration Status Counters (CSR)Interface

xMII Tx I F

mac_pause_frm

xMII Rx I F

Pause State

Packet Rx I F

Packet Tx IF

Rx Clock Domain

Tx Clock Domain

MAC

Pause frame Indication

MAC ready IndicationPause gen Signalling

Host I F to Packet IFConverter

CW Generator

WRAPPER

Packet IF toHost IF

Converter

CW DetectForceLFRFLPI

LF RF StatusLPI Detect

Early Pause Detector

Early Pause Detect

The MAC Tx kernel block handles the reconciliation sublayer functions as per IEEE 8023

bull Calculates the CRC for pause frames generated by the pause frame generator bull Converts MAC frames to the xMII format and adds control characters for framing as required by

IEEE 8023 bull Generates the interframe gap (IFG) on the xMII using the deficit idle count algorithm to achieve an

average IPG of 12 bytes bull Shapes all the traffic to go out with an average IPG of 12 bytes after MACsec frame expansionbull Analyzes each packet and increments statistical counters used for RMON supportThe Pause Frame Generator (PFG) block performs the following two major functions

bull Requests packets from the upstream blocks when packets are present and the Tx direction is not in the pause state (because a pause frame has been received in the Rx direction) They are forwarded to the MAC Tx kernel block for further processing

bull Generates flow control packets Pause frames are generated based upon seeing the MAC_PAUSE_FRM_GEN signal For the Host MAC this signal is generated by the FC buffer based upon programmable XOFFXON threshold values in the FC buffer In advance flow control mode of operation the line MAC can also generate pause frames based on MAC_PAUSE_FRM_GEN signal from Host MAC to relay pause frames that are deleted in Host MAC in this mode

When the pause frame generator sees the MAC_PAUSE_FRM_GEN signal asserted it generates pause frames using settings in configuration registers Part of the pause frame is the pause value which specifies how long the link partner (the network entity that the pause frame is destined for) stops sending traffic The pause value specifies the requested delay in bit times and uses the equation 512 times PAUSE_VALUE

After the PFG starts generating pause frames it continues to generate pause frames at specified intervals until the de-assertion of the MAC_PAUSE_FRM_GEN signal When this signal is deasserted the PFG does one of two things depending upon the configuration in MAC_TX_PAUSE_MODE In normal mode the PFG stops sending pause frames This causes the link partner to start sending frames again after its pause frame timer has expired In XON mode the PFG generates a single pause frame with a pause value of 0 and sends it to the link partner This causes the link partner to start sending frames again right away

The PFG contains a configurable pause frame interval register MAC_TX_PAUSE_INTERVAL This register controls the time between generated pause frames when the FC buffer continues to request that pause frames be generated

The packet interface wrapper handles the following functions

bull Provides the packet interfacing support to MACsec and FC buffer blocks On this packet interface frames are transported without preamble and FCS

bull Supports LFRFLPI generation on xMII interface through special control word received on packet interface This special control word is received on packet interface if relaying of LFRFLPI is desired in MACsec subsystem

bull Padding of frames whose length is less than 64 bytes This is required for padding of MACsec short length frames whose length is less than 64 bytes This padding is enabled by configuring ENABLE_TX_PADDING in host MAC

bull Standard preamble insertionbull FCS insertion

3792 MAC ReceiveThe receive section of the MAC contains three blocks MAC Rx kernel pause frame detector and packet interface wrapper All three blocks operate off the same clock RX_MAC_CLK

The MAC Rx kernel receives the byte stream from the xMII interface and handles the reconciliation sub layer processing to convert them to frames sent over the host interface It checks the CRC of each frame for validity and abort marks any frame with an invalid CRC A variety of length checks are performed including looking for short frames (less than 64 bytes) oversized and jabber frames (longer than the configured maximum) VLAN tagging is supported up to three VLAN tags Length checks are adjusted accordingly when VLAN tags are encountered The Rx kernel supports counters in support of RMON statistics

The pause frame detector (PFD) detects and reacts to valid pause frames received by the MAC from the xMII interface The PFD reacts to PAUSE frames with a DMAC equal to either the multicast address (01-80-c2-00-00-01) or the address of the MAC (MAC_ADDRESS_LSBMSB register value) in accordance with IEEE 8023-2008 Annex 31B Pause frames that are too short or have invalid CRC are abort marked and ignored by the PFD Pause frames carry a pause value that indicates the desired pause time in units of pause quanta where 1 pause-quantum equals 512 bit times Because the data path in the MAC is 8 bytes (or 64 bits) wide the extracted pause value is multiplied by 8 and stored in the pause counter A signal from the PFG indicates if a packet is currently being transmitted

After the current packet has completed or if there is no packet the PFD tells the PFG to stop requesting packets (XOFF) and the pause counter is decremented by one for each MAC Rx clock cycle When the counter reaches 0 the PFG is instructed that it may resume requesting packets from the upstream blocks Pause frames must have a destination address equal to either the multicast address (01-80-c2-00-00-01) or the address of the MAC (MAC_ADDRESS_LSBMSB register value) If there is no match then the pause frame is ignored If a pause frame is received while the Tx direction is already being paused (because a valid pause frame was already received and the pause counter had not yet counted down to 0) the pause counter is simply updated with the new value If the received pause value is 0 then the state machine transitions immediately to END_PAUSE and frames are again requested from the upstream blocks

bull Supports LFRFLPI indication on packet interface through special control word This special control word is relayed to other MAC if relaying of LFRFLPI is desired

bull Preamble strip on packet interfacebull FCS check and strip

3793 RMON Statistical CountersThe following counters count the number of bytes or frames received or transmitted The counters count continuously and are only cleared if the device is reset or the counter is written with 0 through the CPU interface These counters roll-over to 0 when the maximum value is reached Unless specified otherwise each counter is 32 bits

bull RX_IN_BYTES_CNT (40 bits) counts the total bytes received including preamblebull RX_OK_BYTES_CNT (40 bits) counts the number of bytes received in valid framesbull RX_BAD_BYTES_CNT counts the number of bytes received in invalid framesbull TX_OUT_BYTES_CNT (40 bits) counts the total number of bytes transmitted including preamblebull TX_OK_BYTES_CNT (40 bits) counts the number of bytes in successfully transmitted framesThe following counters are based on the type of frame received or transmitted

bull RX_PAUSE_CNT counts the number of pause frames receivedbull RX_UNSUP_OPCODE_CNT counts the number of control frames received with unsupported

opcodesbull RX_UC_CNT counts the number of unicast frames receivedbull RX_MC_CNT counts the number of multicast frames receivedbull RX_BC_CNT counts the number of broadcast frames receivedbull TX_PAUSE_CNT counts the number of pause frames transmittedbull TX_UC_CNT counts the number of unicast frames transmittedbull TX_MC_CNT counts the number of multicast frames transmittedbull TX_BC_CNT counts the number of broadcast frames transmittedThe following error counters are provided

bull RX_SYMBOL_ERR_CNT counts the number of symbol errors receivedbull RX_CRC_ERR_CNT counts the number of frames received with CRC errorsbull RX_UNDERSIZE_CNT counts the number of undersized frames received with valid CRCbull RX_FRAGMENTS_CNT counts the number of undersized frames received with invalid CRCbull RX_IN_RANGE_LENGTH_ERR_CNT counts the number of frames where the length field does not

match the frame length

bull RX_OUT_OF_RANGE_LENGTH_ERR_CNT counts the number of frames with an illegal length field

bull RX_OVERSIZE_CNT counts the number of oversize frames with valid CRCbull RX_JABBERS_CNT counts the number of oversize frames with an invalid CRCbull RX_XGMII_PROT_ERR_CNT counts the number of XGMII protocol errors detectedThe following size histogram counters are provided for both transmit and receive directions

bull Frames with 64-byte payloadsbull Frames with 65-byte to 127-byte payloadsbull Frames with 128-byte to 255-byte payloadsbull Frames with 256-byte to 511-byte payloadsbull Frames with 512-byte to 1023-byte payloadsbull Frames with 1024-byte to 1518-byte payloadsbull Frames with 1519-byte to maximum size payloadsFrame size counters also count invalid frames as long as they are not short frames fragments long frames or jabber frames Long frames are defined as those greater than MAX_LEN bytes

38 Flow Control BuffersFlow control buffers are used in the data paths when the MACs are enabled Ethernet frames are stored in the buffers When a buffer is close to being full the MAC will issue a pause frame to the device sending data to the VSC8490-17 device This is done to prevent the data paths flow control buffer from overflowing

The flow control feedback is particularly common for the host interface when in 10G WAN mode due to the transmitted line WAN data rate being less than the received host LAN data rate The feedback is also necessary to address ethernet frame size expansion in the egress path when MACsec frame encryption is enabled For more information see Flow Control Buffer page 130

39 Rate Compensating BuffersRate compensating buffers are used in the data paths when the MACs are disabled The rate compensating buffers add and drop idle characters between ethernet packets when necessary to address clock rate differences between the line-side and host-side interfaces Rate offsets from ideal frequencies measured in ppm (not MHz) can be tolerated

The maximum data throughput on the line interface is less in 10G WAN mode than 10G LAN mode The lines data rate is reduced to 9953 Gbps from 103125 Gbps Part of that bandwidth includes SONETSDH frame overhead data

Note Care must be taken by the device sending data to the host interface in the egress data path to ensure the rate compensating buffer does not overflow

310 LoopbackThe VSC8490-17 device has several options available for routing traffic between the host-side and the line-side The following table shows the name and location of the loopback modes These modes may be extremely useful for both test and debug purposes

Table 59 bull Host-Side Loopbacks

Name Location Line-Side Tx NotesH2 XAUI-PHY interface (1G and 10G) Mirror XAUI data

H3 PCS after the gearbox (10G) 0xFF00 repeating IEEE PCS system loopback

H4 WIS-PMA interface (10G) 0xFF00 repeating IEEE WIS system loopback

The following illustration shows the host and line-side loopbacks

Figure 96 bull Host-Side and Line-Side Loopbacks

311 Cross-Connect (Non-Hitless Operation)The VSC8490-17 device features a cross-connect between the two adjacent ports to support protection-switching applications and failover capabilities It supports cross-connect and line broadcast (bridge and select) to host-side between the two adjacent ports

In the cross-connect configuration each ports line-side which is normally connected to its own port host-side is connected to the other ports host-side In a broadcast configuration a line-side of one port is connected to both ports host-sides

XAUI interfaces in the VSC8490-17 device support the following failover capabilities

bull Network traffic on Chan0 is switchable between XAUI channel 0 or 1bull Network traffic on Chan1 is switchable between XAUI channel 1 or 0The VSC8490-17 device supports failover and SFI to XAUI broadcasting

The XAUI data at channel_0 can be routed to either SFI of channel_0 or SFI of channel_1 but not both at the same time Similarly the XAUI data at channel_1 can be routed to ether SFI of channel_1 or SFI of channel_0 but not both at the same time However the SFI data of either channel_0 or channel_1 can be routed to XAUI of channel_0 or XAUI of channel_1 or broadcast to XAUI of both channel_0 and channel_1

For example in normal operation the XAUI of channel_0 is routed to SFI of channel_0 When a problem occurs on the link connecting to SFI of channel_0 re-route the XAUI of channel_0 to SFI of channel_1 Or if there is a problem at the MAC interfacing to the XAUI of channel_0 re-route the SFI data of channel_0 to XAUI of channel_1 Broadcasting from SFI to both XAUI ports enables the passing of traffic between XAUI of channel_0 and SFI of channel_0 and to use XAUI of channel_1 to snoop the incoming data from SFI of channel_0 if so desired

Table 60 bull Line-Side Loopbacks

Name Location Host-Side Tx NotesL1 XAUI loopback (10G) Mirror SFP+ data IEEE PHY-XS network loopback ()

L2 XGMII interface (10G) Mirror SFP+ data

L3 PMA interface (1G and 10G) Mirror SFP+ data

XAUI Tx XGXS

Host 10G MAC

1588 MACsecLine 10G MAC

PCS WIS PMA

XAUI Tx XGXS

Host 10G MAC

PCS WIS PMA

XRX[30]

XTX[30]

TXDOUT

TXDIN

L1 H2 L3H4L2 H3

The following table lists the available settings for failoverbroadcasting modes

The following illustration shows the cross-connect configurations

Table 61 bull Failover and Broadcasting Modes

Setting Mode1Ex0003 =0x00 XAUI channel_0 tofrom SFI channel_0 interface

XAUI channel_1 from SFI channel_0 interfaceSFI channel_1 from XAUI channel_1

1Ex0003 = 0x01 XAUI channel_0 from SFI channel_0 interfaceXAUI channel_1 tofrom SFI channel_0 interfaceSFI channel_1 from XAUI channel_0

1Ex0003 =0x20 XAUI channel_0 tofrom SFI channel_0 interfaceXAUI channel_1 tofrom SFI channel_1

1Ex0003 =0x21 XAUI channel_0 from SFI channel_0XAUI channel_1 from SFI channel_1SFI channel_0 from XAUI channel_1SFI channel_1 from XAUI channel_0

1Ex0003 =0x11 XAUI channel_0 tofrom SFI channel_1XAUI channel_1 tofrom SFI channel_0

1Ex0003 =0x30 XAUI channel_0 from SFI channel_1XAUI channel_1 tofrom SFI channel_1SFI channel_0 from XAUI channel_0

1Ex0003 =0x31 XAUI channel_0 tofrom SFI channel_1XAUI channel_1 from SFI channel_1SFI channel_0 from XAUI channel_1

Figure 97 bull Cross-Connect Configuration

312 Host-Side InterfaceThe XAUI RXAUI and 1 GbE host interfaces in the VSC8490-17 device support the following rates

bull XAUI 4 times 3125 Gbpsbull RXAUI 2 times 625 Gbpsbull 1 GbE 1 times 125 GbpsIn RXAUI mode the two RXAUI lanes are XAUI lane 0 and lane 2 XAUI lane 0 is the RXAUI lane 0 and XAUI lane 2 is RXAUI lane 1 The LSB are sent on lane 0 while MSB are sent on late 1 In 1 GbE mode the 1 GbE lanes may be either XAUI lane 0 or lane 3 The following illustration shows the host-side IO interface

The XAUI lane order could be swapped through register 4xF002 where bit 2 is to map lane 0 on 3 lane 1 on 2 lane 2 on 1 and lane 3 on 0 of the XAUI output Bit 0 of same register is to map lane 0 on 3 lane 1 on 2 lane 2 on 1 and lane 3 on 0 of the XAUI input Furthermore bit 2 of 4xF002 could be used to invert the polarity of the differential pairs of all four XAUI outputs and bit 1 of 4xF002 could be used to invert the polarity of the differential pairs of all four XAUI inputs There is an API function call to assist with setting the lane swap and polarity inversion

Note Use AC-coupling for the receive and transmit sides of the host-side interface For optional DC-coupling contact your Microsemi representative

XRX0[30]

XTX0[30]

XRX1[30]

XTX1[30]

TXDOUT0

RXDIN0

TXDOUT1

RXDIN1

NORMAL TRAFFIC Data_Switches_Clock_Control = 0x20 (default)

CROSS-CONNECT Data_Switches_Clock_Control = 0x11

BROADCAST FROM XFI0 Data_Switches_Clock_Control = 0x00 or 0x01

XAUI RX

Channel 0

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI RX

Channel 1

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI0_DOUT_SRC = 0

XAUI RX

Channel 0

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI RX

Channel 1

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI RX

Channel 0

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI RX

Channel 1

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XRX0[30]

XTX0[30]

XRX1[30]

XTX1[30]

TXDOUT0

RXDIN0

TXDOUT1

RXDIN1

XRX0[30]

XTX0[30]

XRX1[30]

XTX1[30]

TXDOUT0

RXDIN0

TXDOUT1

RXDIN1

XRX0[30]

XTX0[30]

XRX1[30]

XTX1[30]

TXDOUT0

RXDIN0

TXDOUT1

RXDIN1

XAUI RX

Channel 0

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

XAUI RX

Channel 1

4 CORE TX 10

PMATX

XAUITX CORE RX

PMA RX4 10

PMA_DOUT_SRC = 0

XAUI1_DOUT_SRC = 0

XAUI0_DOUT_SRC = 0

XAUI1_DOUT_SRC = 0

PMA_DOUT_SRC = 0 or 1

XAUI0_DOUT_SRC = 1

XAUI1_DOUT_SRC = 0

PMA_DOUT_SRC = 1 XAUI0_DOUT_SRC = 1

XAUI1_DOUT_SRC = 1

Figure 98 bull Host-Side IO Interface

3121 RXAUI InteroperabilityThe RXAUI implementation is fully interoperable with the Dune network mode 1 and mode 2 RXAUI specification as summarized in the following table

A host-side SerDes macro (SD6G) is used by each XAUI lane The SerDes macros are automatically configured to sendreceive the proper data rate when the host interface changes between the XAUIRXAUI1 GbE modes The appropriate lanes are also powered down when not in use For example XAUI lanes 1 and 3 are powered down when the RXAUI interface is in use

313 ClockingThe following sections describe the clocking functionality of the VSC8490-17 device

3131 PLLThe VSC8490-17 device includes two PLLs one on the line-side and another on the host-side The line-side PLL uses either XREFCK or WREFCK as its reference clock The host-side PLL uses XREFCK The following table shows the supported reference clock frequencies

Table 62 bull RXAUI Interoperability

Mode1 Mode2De-interleaving uses XAUI ||A|| column (align column)

Transmitter No internal logic modification Two 10b characters are presented to one physical lane at a time

Transmitter Replaces some |K| code groups with other code groups to allow receiver to perform de-interleaving (comma replacement)

Receiver Separates two characters in double rate lane into two physical standard rate lanes Lane byte ordering block ensures first |A| character mapped to first logical lane and |A| column aligned for the deskew block

Obeys 625 Gbps disparity rules Obeys 625 Gbps disparity rules

Table 63 bull Supported Reference Clock Frequencies

Clock Applications FrequenciesXREFCK Mainly LAN mode 125 MHz and 15625 MHz

WREFCK LAN or WAN mode Synchronous Ethernet 15552 MHz and 16113 MHz

XRX_0

XRX_1

XRX_2

XRX_3

XTX_0

XTX_1

XTX_2

XTX_3

XAUI

4x 3

125

Gbp

s

RXAUI

XRX_0

NC

XRX_1

NC

XTX_0

NC

XTX_1

NC2x

62

5 G

bps

1 GbE

OR

NC

1G_RX

NC

1G_TX

1x 1

25

Gbp

s

1G_RX

NC

1G_TX

NC

1x 1

25

Gbp

s

3132 Reference ClockThe VSC8490-17 device uses three differential input CML level reference clocks XREFCK WREFCK and SREFCK The XREFCK is required all the time and may be either 15625 MHz or 125 MHz

The VSC8490-17 device features an internal frequency synthesizer that enables operation in 10G LAN10G WAN1G LAN modes using a single reference clock input (XREFCK) The host-side PLL is always driven by XREFCK It is recommended to have the line-side PLL be driven by XREFCK

For backward compatibility with previous generation PHY chips WREFCK may be used to drive the line-side PLL For Synchronous Ethernet applications with non-hitless XREFCK SREFCK could be used to drive the line-side PLL

The XREFCK frequency has to be decided before power up and is selected using the MODE1 and MODE0 pins The following table shows the MODE pin settings for the various XREFCK frequencies

The following table shows the supported clock rates and modes

SREFCK Synchronous Ethernet 125 MHz 15552 MHz and 15625 MHz

Table 64 bull XREFCK Frequency Selection

MODE1 Pin MODE0 Pin XREFCK Frequency0 0 15625 MHz (default)

0 1 Reserved

1 0 125 MHz

1 1 Reserved

Table 65 bull Supported Clock Rates and Modes

Mode XREFCK WREFCK SREFCK Tx CMU REF Rx CMU REF103125G LAN single ref 15625 MHz XREFCK XREFCK

995328G WAN single ref 15625 MHz XREFCK XREFCK

125G LAN single ref 15625 MHz XREFCK XREFCK

103125G Sync-E LAN single ref 15625 MHz (Hitless)

XREFCK XREFCK

103125G Sync-E LAN dual ref 15625 MHz 16113 MHz SREFCK XREFCK

15625 MHz 15625 MHz SREFCK XREFCK

995328G Sync-E WAN single ref 15625 MHz (Hitless)

XREFCK XREFCK

995328G Sync-E WAN dual ref 15625 MHz 15552 MHz SREFCK XREFCK

995328G Sync-E WAN dual ref 15625 MHz 15552 MHz WREFCK WREFCK

XREFCK XREFCK

Table 63 bull Supported Reference Clock Frequencies (continued)

Clock Applications Frequencies

3133 Synchronous Ethernet SupportThe VSC8490-17 device supports several synchronous Ethernet configurations for 1G and 10G modes of operation In synchronous Ethernet applications only one master at a time may be selected from one of the internal line-side Rx or the SREFCK

bull Single device internal master in this configuration the line-side Rx captures the serial data input and generates a lane-synchronization signal that contains information about the incoming data rates The signal is then distributed to all ports of the line-side Tx to form a source-synchronous operation

bull Single clock LAN external master in this configuration the XREFCK is gradually changed to the externally generated synchronous Ethernet clock using an external clock distribution chip The change has to be hitless to avoid data corruption The XREFCK source may come from one of the port recovered clocks through the RXCKOUT pin

bull Dual clock LAN external master in this configuration the XREFCK remains connected to the stable 15625 MHz system clock or crystal All the line-side transmits are then synchronized to SREFCK The F to delta F block accepts the SREFCK clock from external synchronous Ethernet master and generates the lane Sync signal to effectively synchronize all the line-side Tx to this external clock SREFCK must be 15625 MHz

bull Dual clock WAN external master in this configuration the XREFCK remains connected to the stable 15625 MHz system clock or crystal The XREFCK is configured to drive the host-side PLL while the WREFCK is configured to drive the line-side PLL The synchronous Ethernet clock is then routed through the SREFCK clock to synchronize all the line-side transmits SREFCK must be 15552 MHz

314 Operating ModesThe VSC8490-17 device has three main operation modes LAN WAN and 1 GbE Each mode may have the 1588 and MACsec blocks on or off

3141 10G LAN with 1588 and MACsecIn 10G LAN mode with 1588 and MACsec the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is LAN SFP+ (103125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 MACs are part of the data path when MACsec is enabled

Figure 99 bull 10G LAN with 1588 and MACsec

Table 65 bull Supported Clock Rates and Modes (continued)

Mode XREFCK WREFCK SREFCK Tx CMU REF Rx CMU REF

SerDes

XGXSSerDes

SerDes

XAUI 4x 3125 GbpsRXAUI 2x 625 Gbps (Ln0 and Ln2)

HOSTXAUIRXAUI

XRX[30]

XTX[30]

TXOUT

RXIN

LAN 103125 Gbps

LINESFP+KR

1588 MACsec 10G PCS SerDes

SerDes

Host MAC

Flow Control Buffer

Line MAC

XGXS 1588 MACsec 10G PCS SerDesHost

MAC

Flow Control Buffer

Line MAC

3142 10G LAN with 1588In 10G LAN mode with 1588 the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is LAN SFP+ (103125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 Because the MACsec block is off the rate compensation is done in the FIFO

Figure 100 bull 10G LAN with 1588

3143 10G LANIn 10G LAN mode the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is LAN SFP+ (103125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies Table 65 page 142 Because the MACsec block is off the rate compensation is done in the FIFO

Figure 101 bull 10G LAN

3144 10G WAN with 1588 and MACsecIn 10G WAN mode with 1588 and MACsec the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is SONETSDH STS-192c (995328 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 Optionally WREFCK may be used as the 15552 MHz reference clock for the line interface A 622 MHz WREFCK reference frequency is not supported MACs are part of the data path when MACsec is enabled

SerDes

XGXSSerDes

SerDes

HOSTXAUIRXAUI

XRX[30]

XTX[30]

TXOUT

TXIN

LAN 103125 Gbps

LINESFP+KR

10G PCS SerDes

SerDes

FIFO 1588

XGXS 10G PCS SerDesFIFO 1588

SerDes

XGXSSerDes

SerDes

HOSTXAUI RXAUI

XRX[30]

XTX[30]

TXOUT

TXIN

LAN 103125 Gbps

LINESFP+KR

10G PCS SerDes

SerDes

FIFO

XGXS 10G PCS SerDesFIFO

Figure 102 bull 10G WAN with 1588 and MACsec

3145 10G WAN with 1588In 10G WAN mode with 1588 the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is SONETSDH STS-192c (995328 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 Optionally WREFCK may be used as the 15552 MHz reference clock for the line interface A 622 MHz WREFCK reference frequency is not supported Because the MACsec block is off the rate compensation is done in the FIFO

Figure 103 bull 10G WAN with 1588

3146 10G WANIn 10G WAN mode the host interface is XAUI (4 times 3125 Gbps) or RXAUI (2 times 6250 Gbps) and the line interface is SONETSDH STS-192c (995328 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 Optionally WREFCK may be used as the 15552 MHz reference clock for the line interface A 622 MHz WREFCK reference frequency is not supported Because the MACsec block is off the rate compensation is done in the FIFO

SerDes

XGXSSerDes

SerDes

HOSTXAUIRXAUI

XRX[30]

XTX[30]

1588 MACsec 10G PCS

SerDes

Host MAC

Flow Control Buffer

Line MAC

XGXS 1588 MACsec 10G PCS

Host MAC

Flow Control Buffer

Line MAC

TXOUT

WAN 995328 Gbps

LINESONETSDH STS-192c

SerDesWIS

RXINSerDesWIS

SerDes

XGXSSerDes

SerDes

HOSTXAUIRXAUI

XRX[30]

XTX[30]

TXOUT

RXIN

10G PCS SerDes

SerDes

FIFO 1588

WIS

WAN 995328 Gbps

Figure 104 bull 10G WAN

3147 1 GbE with 1588 and MACsecIn 1 GbE mode with 1588 and MACsec one XAUI lane on the host interface services the 1 GbE signal (125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 MACs are part of the data path when MACsec is enabled

Figure 105 bull 1 GbE with 1588 and MACsec

3148 1 GbE with 1588 and MACsIn 1 GbE mode with 1588 and MACs one XAUI lane on the host interface services the 1 GbE signal (125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 MACs should be enabled to meet the pause turn around time spec as defined in the IEEE specifications

Figure 106 bull 1 GbE with 1588 and MACs

SerDes

XGXSSerDes

SerDes

HOSTXAUIRXAUI

XRX[30]

XTX[30]

TXOUT

RXIN

10G PCS SerDes

SerDes

FIFO

WIS

WAN 995328 Gbps

1GSGMII 125 Gbps

HOST1 GbE

XRX[3] or

XRX[0]TXOUT

RXIN

LINESFP

SerDes

1GSGMII 125 Gbps

SerDes

XTX[3] or

XTX[0]

1G PCS 1588 MACsec 1G PCS SerDesHost MAC

Flow Control Buffer

Line MAC

Flow Control Buffer

Line MAC

1GSGMII 125 Gbps

HOST1 GbE

XRX[3] or

XRX[0]TXOUT

TXIN

LINESFP

SerDes

1GSGMII 125 Gbps

SerDes

XTX[3] or

XTX[0]

1G PCS 1G PCS SerDesHost MAC

Flow Control Buffer

Line MAC

Flow Control Buffer

Line MAC

1588

3149 1 GbEIn 1 GbE mode one XAUI lane on the host interface services the 1 GbE signal (125 Gbps) A single reference clock input pin XREFCK is used by both the line-and host-side interfaces to transmit appropriate rates For more information about supported reference clock frequencies see Table 65 page 142 MACs should be enabled to meet the pause turn around time spec as defined in the IEEE specifications

Figure 107 bull 1 GbE

315 Management InterfacesThis section contains information about the low-speed serial interfaces of the VSC8490-17 device The primary control and monitor interfaces in the design are as follows

bull MDIObull SPI slavebull Two-wire serial (slave)bull Two-wire serial (master)bull Push out SPI master for IEEE 1588 time stamp databull GPIObull JTAGThe VSC8490-17 device supports three different interfaces for accessing status and configuration registers MDIO SPI slave and two-wire serial slave Only one of the interfaces can be active at a time The VSC8490-17 device doesnt arbitrate between these interfaces

Note Users must exercise caution and ensure that multiple interfaces are not active at the same time The SPI slave interface is the recommended interface for accessing the status and configuration registers of the 1588 block the IEEE 1588 time stamp data and the MACsec key and classification updates

3151 MDIO InterfaceThe MDIO interface in the VSC8490-17 device complies with IEEE 8023ae Clause 45 For more information see the IEEE standard The MDIO management interface consists of a bi-directional data path (MDIO) and a clock reference (MDC)

MDIO instructions can be used to read registers write registers and perform post-read-increment-address instructions Due to its slow bandwidth and high latency the MDIO interface is not recommended as the only interface to access the VSC8490-17 device

Note The maximum data rate of the MDIO interface is 25 Mbps

The PADDR[41] pins select the MDIO port addresses to which the VSC8490-17 device will respond A single VSC8490-17 device requires the use of two MDIO port addresses one for each channel The port address transmitted in MDIO readwrite commands to access registers in a particular VSC8490-17 channel is shown in the following table The port address is a function of the PADDR pins and a

1GSGMII 125 Gbps

HOST1 GbE

XRX[3] or

XRX[0]TXOUT

TXIN

LINESFP

SerDes

1GSGMII 125 Gbps

SerDes

XTX[3] or

XTX[0]

Flow Control Buffer

Line MAC

Flow Control Buffer

Line MAC

pre-programmed number indicating the channel number Up to sixteen VSC8490-17 devices can be controlled by a single MDIO host

31511 Accessing 32-Bit Data RegistersEven though the MDIO interface is defined to access 16-bit data registers 32-bit configuration and status registers are present in the line and host MACs MACsec 1588 and line-side SerDes Use the following steps when accessing registers in 32-bit blocks

315111 Write to 32-Bit Register1 Issue address instruction specifying the MDIO address for bits [3116]2 Issue write instruction to write data to register bits [3116]3 Issue address instruction specifying the MDIO address for bits [150]4 Issue write instruction to write data to register bits [150]

Note Writing to the two halves of the 32-bit register in the opposite order is not permitted Nor is it possible to write to only one-half of the register All four MDIO instructions must be issued to write to a 32-bit register

315112 Read 32-Bit Register1 Issue address instruction specifying the MDIO address for bits [150]2 Issue read-increment instruction The data read is the contents of register bits [150]3 Issue read instruction The data read is the contents of register bits [3116]

Note Perform all three steps to read a 32-bit register even when reading consecutive addresses Issuing back-to-back read-increment instructions to read consecutive 32-bit register addresses is not supported

Register addresses listed for the line and host MACs MACsec 1588 and line-side SerDes apply to the SPI slave and two-wire serial slave interfaces which support direct access to 32-bit data registers There are two MDIO addresses for each of these 32-bit data registers one address to access data bits [3116] and one address to access data bits [150] Contact Microsemi for support using the MDIO interface to access line and host MACs MACsec 1588 and line-side SerDes registers

31512 MDIO Device and Register AddressesThe VSC8490-17 device registers are arranged according to the MDIO devices as defined in IEEE 8023 clause 45 as shown in the following list

bull Device 1 PMA and line-side interface registersbull Device 2 WIS registersbull Device 3 10G PCS 1G PCS FC buffers line MAC and host MAC registersbull Device 4 XGXS PCS and host-side interface registersbull Device 1E Global SFP+ PLLs and 1588 registersbull Device 1F MACsec registers

3152 SPI Slave InterfaceThe VSC8490-17 device supports the serial parallel interface (SPI) for reading and writing registers for high bandwidth tasks such as reading IEEE 1588 time stamp data and performing MACsec key and classification updates for all secure associations (SAs) in a timely manner The SPI interface is also capable of accessing all status and configuration registers The SPI slave port consists of a clock input (SCK) data input (MOSI) data output (MISO) and slave select input (SSN)

Note The SPI slave interface is the recommended interface to access status and configuration registers for the rest of the device

Drive the SSN pin low to enable the interface The interface is disabled when SSN is high and MISO is placed into a high impedance state The VSC8490-17 device captures the state of the MOSI pin on the rising edge of SCK 56 data bits are captured on the MOSI pin and transmitted on the MISO pin for each

Table 66 bull MDIO Port Addresses Per Channel

Channel Number Channelrsquos Port Address10

PADDR[41] 1PADDR[41] 0

SPI instruction The serial data bits consist of 1 readwrite command bit 23 address bits and 32 register data bits

The 23-bit addressing scheme consists of a 2-bit channel number a 5-bit MDIO device number and a 16-bit register number For example the 23-bit register address for accessing the GPIO_0_Config_Status register in channel 1 (device number is 0x1E and register number is 0x0100) is 0x3E0100 The notion of device number conforms to MDIO register groupings For example device 2 is assigned to WIS registers

The following table shows the order in which the bits are transferred on the interface Bit 55 is transferred first and bit 0 is transferred last This sequence applies to both the MOSI and MISO pins

The register data received on the MOSI pin during a write operation is the data value to be written to a VSC8490-17 register Register data received on the MOSI pin during a read operation is not used but must still be delivered to the device

The VSC8490-17 device SPI slave has a pipelined read process Two read instructions must be sent to read a single register The first read instruction identifies the register address to be read The MISO data transmitted on the second read instruction contains the register contents from the address specified in the first instruction While a pipelined read implementation is not the most efficient use of bandwidth to read a single register it is very efficient when performing multiple back-to-back reads (as would be the case when reading 1588s TSFIFO_ registers) The second read instruction contains the address for the second register to be read plus the data read from the first register The third read instruction contains the address for the third register to be read plus the data read from the second register Register reads can continue in this fashion indefinitely The following illustrations show the situations where back-to-back read instructions are issued

Figure 108 bull SPI Single Register Read

Table 67 bull SPI Slave Instruction Bit Sequence

Bit Name Description55 ReadWrite 0 Read

1 Write

5453 PortChannel Number 00 PortChannel 001 PortChannel 110 11 Reserved

5248 Device Number 5 bit device numberBit 4 corresponds to SPI instruction bit 52Bit 0 corresponds to SPI instruction bit 48

4732 Register Number 16 bit register numberBit 15 corresponds to SPI instruction bit 47Bit 0 corresponds to SPI instruction bit 32

310 Data 32 bit dataBit 31 corresponds to SPI instruction bit 31Bit 0 corresponds to SPI instruction bit 0

R ADDR A(Don t care)

Depends on previous instruction

MOSI

MISO

R ADDR B(Don t care)

R ADDR ARead

DATA A

SPI Read Instruction

1

SPI Read Instruction 2

Figure 109 bull SPI Multiple Register Reads

The SPI read instruction illustrations also point out the readwrite state and address bits on the MISO output match the information received in the previous instruction The SPI master could use this data to verify the device captured the previous instruction properly or simply ignore the data The following illustration shows the MISO output during write instructions reporting the previous instructions readwrite state address and register write data

Figure 110 bull SPI Multiple Register Writes

The following illustration shows that when a read instruction followings a write instruction the MISO data during the read instruction is the data field from the previous write

Figure 111 bull SPI Read Following Write

The following illustration shows that when a write instruction followings a read instruction the MISO data during the write instruction is not pipelined read data MISO contains all 0s in the data field

Figure 112 bull SPI Write Following Read

Some VSC8490-17 registers are made up of less than 32 data bits Any bits not defined for a register will return a 0 when the register is read Reading an invalid register address will return 0x0

There is one hazard condition to be aware of when issuing two read instructions to read a single clear-on-read register Issuing two read instructions internally fetches data twice even though valid read data is present only in the second instruction Fetching data also resets a clear-on-read register The address specified in the second read instruction should be something other than the clear-on-read register address This prevents an event causing register re-assertion occurring between the two read instructions from being cleared and never detected The address in the second instruction can be any register not having a clear-on-read function Device_ID is one example The same address can be used in each read instruction when continuously polling a clear-on-read register This works because subsequently fetched data is transmitted from the interface allowing assertion between reads to be detected Only the last read instruction where fetched data is not transmitted should some other address in the instruction be used

R ADDR A(Dont care)

R ADDR B(Dont care)

R ADDR D(Dont care)

R ADDR ARead

DATA AR ADDR C

ReadDATA C

MOSI

MISO

R ADDR C(Dont care)

R ADDR BRead

DATA B

W ADDR AWriteDATA A

W ADDR BWriteDATA B

W ADDR AWriteDATA A

W ADDR CWriteDATA C

W ADDR BWriteDATA B

MOSI

MISO

W ADDR AWriteDATA A

W ADDR BWriteDATA B

W ADDR AWriteDATA A

R ADDR C(Dont care)

W ADDR BWriteDATA B

MOSI

MISO

R ADDR A(Dont care)

R ADDR B(Dont care)

R ADDR ARead

DATA A

W ADDR CWriteDATA C

R ADDR B 0s

MOSI

MISO

31521 MISO Output Timing ModesMISO changes state when SCK transitions from high to low in the default SPI operating mode This aids in meeting hold time at the SPI master assuming the master captures the data on the rising SCK edge The SPI port can run up to a maximum of 30 Mbps depending upon the VSC8490-17 device SCK-to-MISO timing SCK duty cycle the board layout and the external SPI masters interface timing requirements For more information about SPI timing see Table 93 page 172

The SPI slave port has an alternate operating mode that allows the interface to run faster Setting register bit SPI_CTRLFAST_MODE=1 configures the SPI slave such that MISO changes state when SCK transitions from low to high Thus data is both transmitted from the SPI slave and captured by the SPI master on a rising SCK edge The interface can run faster in this mode by using the entire SCK clock period instead of half the period to transfer data from the slave to the master Care must be taken to ensure the SPI masters hold time requirement is met The maximum data transfer rate for the SPI slave in this mode is 30 Mbps The following illustrations show MISO timing in the default and slave modes

Figure 113 bull SPI Slave Default Mode

Figure 114 bull SPI Slave Fast Mode

MISO output timing is the only difference between the two SPI modes Sampling of MOSI on the rising SCK clock edge remains the same so writing to the VSC8490-17 device registers is identical in both modes Thus the SPI_CTRLFAST_MODE register setting may be modified using the SPI slave port to change the ports MISO output timing

3153 Two-Wire Serial (Slave) InterfaceThe VSC8490-17 device registers may be read and written using a two-wire serial slave interface The two-wire serial slave SCL and SDA pins are multifunction general purpose IO (GPIO) pins GPIO_3 and GPIO_2 respectively The GPIO pins are configured to serve SCL and SDA functions following device reset

The slave address assigned to the VSC8490-17 device is a function of four fixed values and the MDIO port address pins The 7-bit slave address is 1000 PADDR4 PADDR3 PADDR2 The use of the port address pins allows multiple VSC8490-17 devices to be serviced by a single two-wire serial (master) The maximum data transfer rate for the interface is 400 kbps

MOSI

SCK

SSN

MISO

ADDR[22]

ADDR[21]

DATA[1] DATA[0]DATA[31]RW

DATA[30]RW

ADDR[0]

RWDATA[0]DATA[31]ADDR[22]

MISO data based on previous instruction

RW data matches this instruction and carries over to next instruction

MOSI

SCK

SSN

MISO

ADDR[22]

ADDR[21]

DATA[30]RW

ADDR[0]

Note The two-wire serial slave interface does not work with two-wire serial masters using 10-bit slave addresses

A valid START condition is generated by a two-wire serial master device by transitioning the SDA line from high to low while the SCL line is high Data is then transferred on the SDA line most significant bit (MSB) first with the SCL line clocking data Data transitions during SCL low periods are valid (read) or latched (write) when SCL pulses high then low Data transfers are acknowledged (ACK) by the receiving device for data writes and by the master for data reads An acknowledge is signaled by holding the SDA signal low while pulsing SCL high then low The master terminates data transfer by generating a STOP condition by transitioning SDA low to high while SCL is high

Note If the external two-wire serial master device gets out of sync with the two-wire serial slave interface the master device must issue a bus reset sequence This puts the two-wire serial slave interface back into a state that allows it to receive future two-wire serial instructions The external two-wire serial master device and the two-wire serial slave interface can become out-of-sync and freeze the bus if either device is reset during an instruction

The following illustration shows a two-wire serial bus reset sequence The reset sequence consists of a START symbol nine SCK clock pulses while SDA is high another START symbol and a STOP symbol

Figure 115 bull Two-Wire Serial Bus Reset Sequence

Registers in the VSC8490-17 device are accessed using the 24-bit addressing scheme The first 8 bits consist of one logic LOW the channel number (00 01 10 11) and the 5-bit MDIO device number of the register to be accessed The next 16 bits are the register number For example the 24-bit register address for accessing the GPIO_0_Config_Status register in channel 1 (device number 0x1E and register number 0x0100) is 0x3E0100 The notion of device number conforms to MDIO register groupings For example device 2 is assigned to WIS registers The following illustration shows the 24-bit addressing scheme used to access registers

Figure 116 bull Two-Wire Serial Slave Register Address Format

An illegal two-wire serial slave read instruction to an invalid channel number device number or register address will return a read value of 0x0000 when the slave address matches this device

Four bytes of data are transferred on the two-wire serial bus after the address when a register is read or written Data register bits [3124] are transferred first followed by bits [2316] bits [158] and finally bits [70] An ACK symbol is sent between each byte of data Any bits not defined in a register will return a 0 when the register is read

The following illustration shows the data transferred on the SDA pin during a register write operation The RW bit following the slave address is set to logic low to specify a write operation

Nine Clock PulseSTART START STOP

SCL

SDA

1 2 8 9

S slv_addr[60] W ldquo0rdquo ch[10] dev[40] reg_addr[158] reg_addr[70]

Figure 117 bull Two-Wire Serial Write Instruction

The register address to be accessed is specified by initiating a write operation After the slave address and three register address bytes are sent to the VSC8490-17 device a START condition must be re-sent followed by the slave address with the readwrite bit set to logic high The four-byte data register contents are then transmitted from the VSC8490-17 device The two-wire serial (master) sends NO ACK after the fourth data byte to indicate it has finished reading data The following illustration shows data transferred on the SDA pin during a register read operation

Figure 118 bull Two-Wire Serial Read Instruction

The two-wire serial slave interface supports sequential read and sequential write instructions

3154 Two-Wire Serial (Master) InterfaceA two-wire serial master interface in the VSC8490-17 channel is available for SFP+XFP module management A two-wire serial master interface per channel is required because the slave address in the optics modules are identical Two-wire serial interface instructions used to access optics module registers are initiated by writing to VSC8490-17 registers The two-wire serial interface busses are brought out through GPIO pins Channel 0s two-wire serial interface is enabled by configuring GPIO_6

START Slave Address

WRITE

RW

ACK

0

ACK

Register Address

01 0 0 0

ACK

STOP

BIT

31

BIT

0

Data Written to Register

START Slave Address

WRITE

RW

ACK

0 0

ACK

Register Address

01 0 0 0

ACK

NO

ACK

STOP

BIT

31

BIT

0

Data Read from Register

START Slave Address

ACK

1 0 0 0

READ

RW

1

Dummy Write to set Read Address

to function as SDA and GPIO_7 to function as SCL Channel 1s two-wire serial interface is enabled by configuring GPIO_10 to function as SDA and GPIO_11 to function as SCL

The two-wire serial master interface must be configured before initiating any instructions The slave ID to be transmitted in the first byte of every instruction is selectable in the SLAVE_ID register The default setting is 0x50 The interfaces data rate is determined by the PRESCALE register The default data rate is 400 kbps

The two-wire serial master transmits instructions for slave devices with 8-bit data registers and 256 register addresses per slave ID Always read register I2C_BUS_STATUSI2C_BUS_BUSY or I2C_READ_STATUS_DATAI2C_BUS_BUSY to verify the previous instruction has finished prior to initiating a new instruction Instructions initiated when the interface is busy will be ignored Both registers report the same interface busy status The same busy status is reported in two registers for user convenience

The two-wire serial master initiates a write instruction when the I2C_WRITE_CTRL register is written The value written to I2C_WRITE_CTRLWRITE_ADDR is the register address to be modified in the slave device The value written to I2C_WRITE_CTRLWRITE_DATA is the data to be written to the slave devices register The I2C_BUS_STATUS register reports the status of the write instruction I2C_BUS_STATUSI2C_BUS_BUSY indicates when the instruction has finished I2C_BUS_STATUSI2C_WRITE_ACK=1 means the two-wire serial master received ACKs from the slave at appropriate times I2C_BUS_STATUSI2C_WRITE_ACK is cleared each time a new instruction is issued If the two-wire serial master did not receive ACKs from the slave at appropriate times (I2C_BUS_STATUSI2C_WRITE_ACK=0) the interface is likely stuck in a state waiting for the ACK Writing a 1 to the BLOCK_LEVEL_RESET1I2CM_RESET register will reset the two-wire serial master and release it from its stuck state The slave device should then be put into a known state by writing any value to the I2C_RESET_SEQ register The two-wire serial master issues a bus reset sequence when this register is written For more information see Two-Wire Serial (Slave) Interface page 151

The two-wire serial master initiates a read instruction when the I2C_READ_ADDR register is written The value written to I2C_READ_ADDRREAD_ADDR is the register address to be accessed in the slave device I2C_READ_STATUS_DATAREAD_DATA contains the data read from the slave device READ_DATA is not valid until I2C_READ_STATUS_DATAI2C_BUS_BUSY=0 to indicate the instruction completed The two-wire serial master does not support read-increment instructions

3155 Push Out SPI Master InterfaceTo overcome MDIO speed limitations for faster or large amounts of time stamp reads the VSC8490-17 device supports a push out SPI master interface The SPI output is used to push out time stamp information to an external device only and does not provide readwrite to the rest of the status and configuration registers For more information see Serial Time Stamp Output Interface page 89

The push out SPI master interface consist of an SPI clock output (SPI_CLK) an SPI data output (SPI_DO) and an SPI chip select output (SPI_CS)

3156 GPIOGeneral purpose inputoutput (GPIO) pins in the VSC8490-17 device serve multiple functions The GPIO pins are bidirectional where the driver portion is an open-drain buffer The following table shows the functions that each pin supports and the registers used to configure the pin functions Leave GPIO pins

unconnected when not in use When configured as output they are open-drained and a pull-up is required

Table 68 bull GPIO Functions

Pin Configuration Registers FunctionsGPIO_0 GPIO_0_Config_Status

GPIO_0_Config2Traditional IO (default)Observed internal signalsMOD_ABS_Channel_0 PMTICKROSI frame pulse 0Tx Activity LEDWIS_INTB1588-1PPS channel 0Leave unconnected when not used

GPIO_1 GPIO_1_Config_StatusGPIO_1_Config2

Traditional IO (default)Observed internal signalsROSI_CLK_0Rx Activity LEDWIS_INTA1588-LoadSaveLeave unconnected when not used

Traditional IOObserved internal signalsSlave two-wire serial - SDA (default)ROSI_DATA_0Tx Activity LEDWIS_INTB

Traditional IOObserved internal signalsSlave two-wire serial - SCL (default)TOSI_FRAME_PULSE_0Rx Activity LEDWIS_INTB

Traditional IO (default)Observed internal signalsTOSI_CLK_0Tx Activity LEDWIS_INTB1588-1PPS channel 1

Traditional IO (default)Observed internal signalsTOSI_INPUT_0Rx Activity LEDWIS_INTA1588-PPS RILeave unconnected when not used

Traditional IO (default)Observed internal signalsCh0 SFP I2C SDAROSI_FRAME_PULSE_1Tx Activity LEDWIS_INTB

Traditional IO (default)Observed internal signalsCh0 SFP I2C SCLROSI_CLK_1Rx Activity LEDWIS_INTA

Traditional IO (default)Observed internal signalsMOD_ABS_Channel_0 PMTICKROSI_DATA_1Tx Activity LEDWIS_INTA

Traditional IO (default)Observed internal signalsMod_ABS channel 1PMTICKTOSI_FRAME_PULSE_1Rx Activity LEDWIS_INTA1588-1PPS channel 1

Traditional IO (default)Observed internal signalsCh1 SFP I2C SDATOSI_CLK_1Tx Activity LEDWIS_INSTB

Traditional IO (default)Observed internal signalsCh1 SFP I2C SCLTOSI_INPUT_1Rx Activity LEDWIS_INTA1588-1PPS channel 1

Traditional IO (default)Observed internal signalsTx Activity LEDWIS_INTA

Traditional IO (default)Observed internal signalsRx Activity LEDWIS_INTA

Table 68 bull GPIO Functions (continued)

Pin Configuration Registers Functions

When a GPIO pin is programmed to be a traditional IO the pin may be driven high or low It may also serve as an input and an LED driver capable of blinking at various rates An interrupt pending register may optionally be asserted when the pin is in input mode and the pin changes state All of these functions are configured using the pin configuration register settings shown in the preceding table

The GPIO pins output driver is automatically enabled when the pin function is set to observe internal signals The second configuration register listed for each pin selects which internal signal is transmitted from the pin

3157 JTAG The VSC8490-17 device has a IEEE 11491ndash2001 compliant JTAG interface The following table shows the supported instructions and corresponding instruction register codes The codes least significant bit is shifted into TDI first when loading an instruction (the 0 is shifted in first when loading the IDCODE instruction)

Table 69 bull JTAG Instructions and Register Codes

Instruction Register Code NotesIDCODE 111111111111111111111110

BYPASS 111111111111111111111111

EXTEST 111111111111111111101000

EXTEST_PULSE 111111101111111111101000

EXTEST_TRAIN 111111011111111111101000

SAMPLE 111111111111111111111000

PRELOAD 111111111111111111111000

LV_HIGHZ 111111111111111111001111 Provides the ability to place outputs in a high impedance state to facilitate manufacturing test and PC board diagnostics The XAUI and SFP+ serial data outputs are not put into the high impedance state when this instruction is loaded in the JTAG TAP controller

CLAMP 111111111111111111101111 Provides the ability to place all outputs in a predefined state when the scan process is being used to test other devices on a PC board

Registers

4 Registers

Information about the registers for this product is available in the attached Adobe Acrobat file To view or print the information double-click the attachment icon

VSC8490-17 RegistersDual Channel WANLANBackplane RXAUIXAUI toSFP+KR 10 GbE SerDes PHY with IntelliSectrade and

VeriTimetrade

Attachment to VMDS-10505 20 1118

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 iii

Contents

1 Revision History 111 Revision 20 1

2 Registers 221 PMA Channel (Device 0x1) 3

211 Device 1 IEEE PMA Control 6212 Device 1 IEEE PMA Status 7213 Device 1 IEEE PMA Device ID 7214 Device 1 IEEE PMAPMD Status 10215 Device 1 IEEE PMD Control and Status 12216 Device 1 IEEE PMAPMD Package ID 13217 KR FEC Ability 13218 KR FEC Control 1 14219 KR FEC Status 142110 KR FEC Control 2 162111 Rx Alarm Control 172112 Tx Alarm Control 182113 Rx Alarm Status 182114 Tx Alarm Status 192115 Clock Output Control 192116 Data Path Control 222117 Data Path Loopback Control 222118 Enable MAC in the Data Path 232119 Write RCOMP 4-bit Resistor Calibration Value into SD10G 232120 Configuration Registers for Clock Output Buffer 232121 Vendor-Specific PMA Control 2 242122 Vendor-Specific PMA Status 2 262123 Vendor-Specific LOPC Status 262124 Vendor-Specific LOPC Control 272125 Block-Level Reset 282126 Spare RW 302127 SD10G65 VScope Configuration and Status 342128 SD10G65 DFT Configuration and Status 392129 ROM Engine 1 472130 ROM Engine 2 482131 ROM Engine Status 492132 SYNC_CTRL Configuration and Status 50

22 KR Channel (Device 0x1) 52221 KR PMD Control 53222 KR PMD Status 53223 KR LP Coefficient Update 54224 KR LP Status Report 54225 KR LD Coefficient Update 54226 KR LD Status Report 54227 VS Training Configuration 0 54228 VS Training Configuration 1 55229 VS Training Configuration 2 552210 VS Training Configuration 3 562211 VS Training Configuration 4 562212 VS Training Configuration 5 562213 VS Training Configuration 6 562214 VS Training Configuration 7 572215 VS Training Configuration 8 57

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 iv

2216 VS Training Configuration 9 572217 VS Training Gain Target and Margin Values 582218 VS Training Coefficient Update Override 582219 VS Training Status Report Override 582220 VS Training Override 582221 VS Training State Step 592222 VS Training Method 592223 VS Training BER Threshold Settings 592224 VS Training BER Offset Setting 602225 VS Training LUT Selection 602226 KR Training Breakpoints 602227 KR Training ROM Address 612228 VS Training apc_timer 622229 VS Training wait_timer 622230 KR Training Maximum Wait Timer 632231 VS Training Status 1 632232 VS Training Status 2 632233 KR Tap Values 642234 KR Training Frame Counter 642235 KR Training LUT Counter 652236 KR Training PBRS11 error_count 65

23 SFP TWS Channel (Device 0x1) 66231 I2C Write Control 66232 I2C Bus Status 66233 I2C Read Address 66234 I2C Read Status and Data 67235 I2C Reset Sequence 67

24 PMA 32-Bit Channel (Device 0x1) 68241 SD10G65 APC Configuration and Status 70242 SD10G65 DES Configuration and Status 103243 SD10G65 OB Configuration and Status 104244 SD10G65 IB Configuration and Status 107245 SD10G65 Rx RCPLL Configuration and Status 121246 SD10G65 Rx SYNTH Configuration and Status 123247 SD10G65 Tx SYNTH Configuration and Status 128248 SD10G65 Tx RCPLL Configuration and Status 131

25 WIS Channel (Device 0x2) 133251 WIS Status 1 139252 WIS Device Identifier 140253 WIS Speed Capability 140254 WIS Devices 141255 WIS Control 2 142256 WIS Status 2 143257 WIS Test Pattern Error Counter 143258 WIS Package Identifier 144259 WIS Status 3 1442510 WIS Far-End Path Block Error Count 1462511 Transmitted Path Trace Message Octets 1462512 Received Path Trace Message Octets 1492513 WIS Line Counters 1512514 Transmitted Section Trace Message Octets 1542515 Received Section Trace Message Octets 1562516 EWIS Tx Control 1592517 H4 Loopback FIFO Status 1602518 E-WIS Tx Octets 1612519 E-WIS Tx Trace Message Length Control 1652520 Transmitted Section Trace Message Octets 1662521 Received Section Trace Message Octets 173

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 v

2522 Transmitted Path Trace Message Octets 1802523 Received Path Trace Message Octets 1872524 E-WIS Rx Framer Control 1942525 E-WIS Rx Control 1 1962526 E-WIS Rx Trace Message Length Control 1972527 E-WIS Rx Error Force Control 1972528 E-WIS Mode Control 2002529 E-WIS PRBS31 Analyzer 2012530 E-WIS Performance Monitor Control 2022531 E-WIS Counter Configuration 2032532 E-WIS Counter Status 2042533 E-WIS P-REI Counter 2042534 E-WIS L-REI Counter 2052535 E-WIS S-BIP Error Counter 2052536 E-WIS L-BIP Error Counter 2062537 E-WIS P-BIP Error Counter 2072538 E-WIS Rx to Tx Control 2072539 E-WIS Interrupt Pending 1 2092540 E-WIS Interrupt Mask 1 2112541 E-WIS Interrupt Status 2 2132542 E-WIS Interrupt Pending 2 2152543 E-WIS Interrupt Mask 2 2182544 WIS Fault Mask 2222545 E-WIS Interrupt Pending 3 2232546 E-WIS Interrupt Mask 3 2242547 Threshold Error Status 2262548 E-WIS Thresholds 227

26 PCS10G Channel (Device 0x3) 230261 PCS Control 1 231262 PCS Status 1 232263 PCS Device Identifier 233264 PCS Speed Ability 233265 PCS Devices in Package 1 233266 PCS Control 2 234267 PCS Status 2 235268 PCS Package Identifier 235269 10GBase-X Status 2362610 10GBase-X Control 2362611 10GBase-R PCS Status 1 2362612 10GBase-R PCS Test Pattern Seed A 2382613 10GBase-R PCS Test Pattern Seed B 2392614 10GBase-R PCS Test Pattern Control 2392615 10GBase-R PCS Test Pattern Counter 2402616 User Test Pattern 2402617 Square Wave Pulse Width 2412618 PCS Control 3 2412619 Test Error Counter 2422620 PCS Tx Sequencing Error Count 2432621 PCS Rx Sequencing Error Count 2432622 PCS Tx Block Encode Error Count 2432623 PCS Rx Block Decode Error Count 2432624 PCS Tx Character Encode Error Count 2442625 PCS Rx Character Decode Error Count 2442626 Loopback FIFOs StatCtrl 2442627 PCS Control 4 2452628 PCS Interrupt Pending 1 2452629 PCS Interrupt WIS_INT0 Mask 2472630 PCS Interrupt Error Status 249

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 vi

2631 PCS Error Count Thresholds 25027 PCS1G Host Channel (Device_0x3) 253

271 PCS 1G Configuration Status 253272 PCS1G Test Pattern Configuration and Status 259273 PCS1G XGMII Configuration 260

28 PCS1G Line Channel (Device 0x3) 261281 PCS 1G Configuration Status 261282 PCS1G Test Pattern Configuration and Status 267283 PCS1G XGMII Configuration 268

29 Flow Control Buffer Channel (Device 0x3) 269291 Flow Control Buffer Configuration 269292 Flow Control Buffer Status 272

210 10G Host MAC Channel (Device 0x3) 2772101 10G MAC Configuration 2782102 10G MAC Pause Configuration 2842103 10G MAC Status 2872104 10G MAC Frame Counters (32 Bits) 2892105 10G MAC Frame Counters (40 Bits) 297

211 10G Line MAC Channel (Device 0x3) 2992111 10G MAC Configuration 3012112 10G MAC Pause Configuration 3062113 10G MAC Status 3082114 10G MAC Frame Counters (32 Bits) 3112115 10G MAC Frame Counters (40 Bits) 318

212 PHY XS Channel (Device 0x4) 3212121 PHY XS Control 1 3222122 PHY XS Status 1 3232123 PHY XS Device Identifier 3232124 PHY XS Speed Capability 3242125 PHY XS Devices in Package 3242126 PHY XS Status 2 3252127 PHY XS Package Identifier 3262128 PHY XS Status 3 3262129 PHY XGXS Test Control 1 32721210 SERDES6G Digital Configuration 32821211 SERDES6G Analog Configuration Status 32921212 SERDES6G Analog Status 34021213 MACRO_CTRL Configuration 34421214 MACRO_CTRL Status 345

213 FIFO BIST Channel (Device 0x4) 3472131 BIST Generator Configuration 3482132 Self-Clearing Pulse to Latch All Counters 3482133 Packet Length 3492134 IPG Length 3492135 PTP Timestamp 3492136 Ethernet Type 3492137 BIST Source Address 3492138 BIST Destination Address 3502139 BIST Sent Packet Counter 35121310 Monitor Configuration 35121311 Self-Clearing Monitor Counters Reset 35121312 BIST Received Good CRC Counter 35221313 BIST Received Bad CRC Counter 35221314 BIST Received Fragment Counter 35321315 BIST Received Local Fault Counter 35321316 BIST Received BER Counter 35421317 BIST Last Received Timestamp 354

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 vii

21318 Rate Compensation FIFO Status 35521319 Rate Compensation Counters 35621320 Datapath Control 357

214 PCS XAUI Channel (Device_0x4) 3592141 PCS XAUI Configuration Registers 3602142 PCS XAUI Status 3642143 PCS Error Counters 3692144 XAUI PRBS Test Pattern Generator 3712145 ANEG Configuration 3752146 ANEG Status 377

215 KR DEVICE7 Channel (Device_0x7) 3812151 AN Control 3822152 AN Status 3822153 KR AN Advertised Abilities Local Device (LD) 3832154 KR AN Next Page to Transmit 3842155 KR AN Next Page Ability Link Partner 3842156 Backplane Ethernet status 3852157 KR AN Configuration 3862158 KR AN Break Link Timer 3862159 KR AN ANEG Wait Timer 38721510 KR AN Link Fail Inhibit Timer 38721511 KR AN Link Fail Inhibit Short Timer 38721512 KR AN Link Pass Inhibit Timer 38821513 KR AN Page Detect Timer 38821514 KR AN Rate Detect 10G Timer 38921515 KR AN Rate Detect 3G Timer 38921516 KR AN Rate Detect 1G Timer 39021517 VS AN Arbitrary State Machine History 39021518 VS AN Arbitrary State Machine 39021519 VS AN Status 0 39121520 KR AN ROM Instructions 391

216 Global Channel 0 (Device_0x1E) 3922161 Device ID and Revision 3942162 Block-Level Software Reset 3942163 Data Switches and Clock Control 3952164 Pin Status 3962165 Interrupt Pending De-assertion Time 3962166 GPIO Configuration and Status Group 1 3972167 GPIO Configuration and Status Group 2 4422168 Temperature Monitor 5152169 Device Revision II 51721610 Power On Done 51721611 Select Line-Side Reference Clock Source 51721612 F2DF DFT Configuration and Status 51721613 Device Feature Status 52421614 SPI Mode Control 52421615 RCOMP Status 52421616 Synchronous Ethernet Configuration 0 525

217 Global Reset Channel 0 (Device_0x1E) 5262171 Fast Reset Registers Not On CSR Ring 526

218 Host PLL5G Global Channel 0 (Device_0x1E) 5272181 H_PLL5G Configuration 527

219 Line PLL5G Global Channel 0 (Device_0x1E) 5342191 L_PLL5G Configuration 534

220 Global 32-Bit Channel 0 (Device 0x1E) 5452201 F2DF DES Configuration and Status 5452202 F2DF IB Configuration and Status 547

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 viii

2203 F2DF RX RCPLL Configuration and Status Registers 5582204 F2DF Rx Synthesizer Configuration and Status Registers 561

Revision History

Attachment to VMDS-10505 VSC8490-17 Registers Revision 20 1

1 Revision History

11 Revision 20Revision 20 of this document was published in September 2018 This was the first publication of the registers

Registers

2 Registers

This section provides information about the programming interface register maps register descriptions and register tables of the device

Note This register map is provided as a reference only It is intended for use as a reference during debug activity Unless expressly indicated production designs that include the VSC8489 VSC8490 or VSC8491 devices should utilize the API for configuration and all device interaction

Important Not all register functionality is tested supported or guaranteed

Note Registers pertaining to feature additions such as 1588 and MACsec are excluded at this time

For information about register addresses when using the MDIO interface see the Management Interfaces functional descriptions in the VSC8489-17 datasheet and the API or contact your Microsemi representative

Registers

21 PMA Channel (Device 0x1)Table 1 bull PMA Channel (Device 0x1)

Address Short Description Register Name Details0x00 PMA Control Register 1 PMA_CONTROL_1 Page 6

0x01 PMA Status Register 1 PMA_STATUS_1 Page 7

0x02 PMA Device Identifier 1 PMA_DEVICE_ID_1 Page 7

0x04 PMAPMD Speed Ability PMA_PMD_SPEED_ABILITY Page 8

0x05 PMAPMD Devices in Package 1 PMA_PMD_DEV_IN_PACKAGE_1 Page 8

0x07 PMAPMD Control 2 PMA_PMD_CONTROL_2 Page 9

0x08 PMAPMD Status 2 PMA_PMD_STATUS_2 Page 10

0x09 PMD Transmit Disable PMD_TRANSMIT_DISABLE Page 12

0x0A PMD Receive Signal Detect PMD_RECEIVE_SIGNAL_DETECT Page 12

0x1E PMAPMD Package Identifier 1 PMA_PMD_PACKAGE_ID_1 Page 13

0x1F PMAPMD Package Identifier 2 PMA_PMD_PACKAGE_ID_2 Page 13

0xAA KR FEC Ability KR_FEC_ABILITY Page 13

0xAB KR FEC Control 1 KR_FEC_CONTROL_1 Page 14

0xAC KR FEC Corrected Lower KR_FEC_CORRECTED_LOWER Page 14

0xAD KR FEC Corrected Upper KR_FEC_CORRECTED_UPPER Page 15

0xAE KR FEC Uncorrected Lower KR_FEC_UNCORRECTED_LOWER Page 15

0xAF KR FEC Uncorrected Upper KR_FEC_UNCORRECTED_UPPER Page 16

0x8300 KR FEC Control 2 KR_FEC_Control_2 Page 16

0x9000 Rx Alarm Control RX_ALARM_Control_Register Page 17

0x9001 Tx Alarm Control TX_ALARM_Control_Register Page 18

0x9003 Rx Alarm Status RX_ALARM_Status_Register Page 18

0x9004 Tx Alarm Status TX_ALARM_Status_Register Page 19

0xA000 Interfaces RXCKOUT Configuration RXCK_CFG Page 19

0xA001 Interfaces TXCKOUT Configuration TXCK_CFG Page 21

0xA002 10G or 1G Mode in Datapath DATAPATH_MODE Page 22

0xA003 Datapath Loopback Control PMA_LOOPBACK_CONTROL Page 22

0xA006 Enable MAC in the Datapath MAC_ENA Page 23

0xA007 Write RCOMP 4-bit Resistor Calibration Value into SD10G

RCOMP Page 23

0xA00C Clock Output Buffer Bias Control OB_BIAS_CTRL Page 23

0xA00D Clock Output Buffer Control OB_CTRL Page 24

0xA100 Vendor-Specific PMA Control 2 Vendor_Specific_PMA_Control_2 Page 24

0xA101 Vendor-Specific PMA Status 2 Vendor_Specific_PMA_Status_2 Page 26

0xA200 Vendor-Specific LOPC Status Vendor_Specific_LOPC_Status Page 26

Registers

0xA201 Vendor-Specific LOPC Control Vendor_Specific_LOPC_Control Page 27

0xAE00 Block-Level Soft Reset1 BLOCK_LEVEL_RESET1 Page 28

0xAEF0 Device1 Spare RW 0 DEV1_SPARE_RW0 Page 30

0xAEFA Device1 Spare RW 10 DEV1_SPARE_RW10 Page 32

0xAEFB Device1 Spare RW 11 DEV1_SPARE_RW11 Page 33

0xAEFC Device1 Spare RW 12 DEV1_SPARE_RW12 Page 33

0xAEFD Device1 Spare RW 13 DEV1_SPARE_RW13 Page 33

0xAEFE Device1 Spare RW 14 DEV1_SPARE_RW14 Page 33

0xAEFF Device1 Spare RW 15 DEV1_SPARE_RW15 Page 33

0xB000 VScope Main Configuration Register A VScope_MAIN_CFG_A Page 34

0xB001 VScope Main Configuration Register B VScope_MAIN_CFG_B Page 34

0xB002 VScope Main Configuration Register C VScope_MAIN_CFG_C Page 35

0xB003 VScope Pattern Lock Configuration Register A VScope_PAT_LOCK_CFG_A Page 36

0xB004 VScope Pattern Lock Configuration Register B VScope_PAT_LOCK_CFG_B Page 36

0xB005 VScope HW Scan Configuration Register 1A VScope_HW_SCAN_CFG_1A Page 36

0xB006 VScope HW Scan Configuration Register 1B VScope_HW_SCAN_CFG_1B Page 36

0xB007 VScope HW Configuration Register 2A VScope_HW_SCAN_CFG_2A Page 37

0xB008 VScope HW Configuration Register 2B VScope_HW_SCAN_CFG_2B Page 37

0xB009 VScope Status VScope_STAT Page 38

0xB00A VScope Counter Register A VScope_CNT_A Page 38

0xB00B VScope Counter Register B VScope_CNT_B Page 38

0xB00C VScope General Purpose Register A VScope_DBG_LSB_A Page 39

0xB00D VScope General Purpose Register A VScope_DBG_LSB_B Page 39

0xB100 SD10G65 DFT Main Configuration Register 1 DFT_RX_CFG_1 Page 39

0xB102 SD10G65 DFT Pattern Mask Configuration Register 1 DFT_RX_MASK_CFG_1 Page 41

Table 1 bull PMA Channel (Device 0x1) (continued)

Address Short Description Register Name Details

Registers

0xB104 SD10G65 DFT Pattern Checker Configuration Register 1

DFT_RX_PAT_CFG_1 Page 41

0xB106 SD10G65 DFT BIST Configuration Register 0A DFT_BIST_CFG0A Page 42

0xB107 SD10G65 DFT BIST Configuration Register 0B DFT_BIST_CFG0B Page 42

0xB10A SD10G65 DFT BIST Configuration Register 2A DFT_BIST_CFG2A Page 43

0xB10B SD10G65 DFT BIST Configuration Register 2B DFT_BIST_CFG2B Page 43

0xB10C SD10G65 DFT BIST Configuration Register 3A DFT_BIST_CFG3A Page 43

0xB10D SD10G65 DFT BIST Configuration Register 3B DFT_BIST_CFG3B Page 44

0xB10E SD10G65 DFT Error Status Register 1 DFT_ERR_STAT_1 Page 44

0xB10F SD10G65 DFT Error Status Register 2 DFT_ERR_STAT_2 Page 44

0xB110 SD10G65 DFT PRBS Status Register 1 DFT_PRBS_STAT_1 Page 44

0xB112 SD10G65 DFT Miscellaneous Status Register 1 DFT_MAIN_STAT_1 Page 45

0xB114 SD10G65 DFT Main Configuration DFT_TX_CFG Page 46

0xB115 SD10G65 DFT Tx Constant Pattern Configuration Register 1

DFT_TX_PAT_CFG_1 Page 47

0xB117 SD10G65 DFT Tx Constant Pattern Status DFT_TX_CMP_DAT_STAT Page 47

0xB200ndash0xB2A9

SPI Address Field of ROM Table Entry (replication_count= 170)

spi_adr Page 47

0xB300ndash0xB3A9

Lower 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)

data_lsw Page 48

0xB400ndash0xB4A9

Upper 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)

data_msw Page 48

0xB600 ROM Table StartEnd Addresses of Tx 10G Setting Routine

adr_tx10g Page 48

0xB601 ROM Table StartEnd Addresses of Rx 10G Setting Routine

adr_rx10g Page 48

adr_tx1g Page 49

adr_rx1g Page 49

0xB604 ROM Table StartEnd Addresses of WAN Setting Routine

adr_wan Page 49

0xB6FF ROM Engine Status ROMENG_STATUS Page 49

0xB700 SYNC_CTRL Configuration SYNC_CTRL_CFG Page 50

Registers

211 Device 1 IEEE PMA Control2111 PMA Control 1

Short NamePMA_CONTROL_1

Address0x00

0xB701 SYNC_CTRL Status SYNC_CTRL_STAT Page 51

Table 2 bull PMA Control Register 1

Bit Name Access Description Default15 RST One-shot MDIO manageable device (MMD) software reset

This register resets all portions of the channel on the line side of the failover mux Data path logic and configuration registers are reset This register is self-clearing0 Normal operation1 Reset

0x0

13 SPEED_SEL_A RO Indicates if the device operates at 10 Gbps and above0 Unspecified1 Operation at 10 Gbps and above

0x1

11 LOW_PWR_PMA RW The channels data path is placed into low power mode with this register The PMA in this channel is also placed into low power mode regardless of the channel cross-connect configuration The PMD_TRANSMIT_DISABLEGLOBAL_PMD_TRANSMIT_DISABLE register state can be transmitted from a GPIO pin to shut off an optics modules Tx driver1 Low power mode0 Normal operation

0x0

6 SPEED_SEL_B RO Indicates if the device operates at 10 Gbps and above0 Unspecified1 10 Gbps and above

0x1

52 SPEED_SEL_C RO Device speed selection1xxx Reservedx1xx Reservedxx1x Reserved0001 Reserved0000 10 Gbps

0x0

0 EN_PAD_LOOP RW Enable PMA pad loopback H50 Disable1 Enable

0x0

Registers

212 Device 1 IEEE PMA Status2121 PMA Status 1

Short NamePMA_STATUS_1

Address0x01

213 Device 1 IEEE PMA Device ID2131 PMA Device Identifier 1

Short NamePMA_DEVICE_ID_1

Address0x02

2132 PMA Device Identifier 2Short NamePMA_DEVICE_ID_2

Table 3 bull PMA Status Register 1

Bit Name Access Description Default7 FAULT RO Indicates a fault condition for this interface in

either the transmit or the receive paths0 Fault condition not detected Latch-high alarm status bits TRANSMIT_FAULT= 0 and RECEIVE_FAULT= 01 Fault condition detected Latch-high alarm status bits TRANSMIT_FAULT= 1 or RECEIVE_FAULT= 1

0x0

2 RECEIVE_LINK_STATUS RO Indicates the receive link status for this interfaceThis is a sticky bit that latches the low state The latch-low bit is cleared when the register is read0 PMAPMD receive link down1 PMAPMD receive link up

0x1

1 LOW_POWER_ABILITY RO Indicates PMAPMD supports low power mode0 PMAPMD does not support low power mode1 PMAPMD supports low power mode

0x1

Table 4 bull PMA Device Identifier 1

Bit Name Access Description Default150 PMA_DEVICE_ID_1 RO Upper 16 bits of a 32-bit unique PMA device

identifier Bits 3ndash18 of the device manufacturers OUI

0x0007

Registers

Address0x03

2133 PMAPMD Speed AbilityShort NamePMA_PMD_SPEED_ABILITY

Address0x04

2134 PMAPMD Devices in Package 1Short NamePMA_PMD_DEV_IN_PACKAGE_1

Address0x05

Bit Name Access Description Default150 PMA_DEVICE_ID_2 RO Lower 16 bits of a 32-bit unique PMA device

identifier Bits 19ndash24 of the device manufacturers OUI 6-bit model number and a 4-bit revision number

0x0400

Table 6 bull PMAPMD Speed Ability

Bit Name Access Description Default0 ETH_10G_CAPABLE RO Indicates PMAPMD capability to run at 10 Gbps

0 PMAPMD is not capable of operating at 10 Gbps1 PMAPMD is capable of operating at 10 Gbps

0x1

Table 7 bull PMAPMD Devices In Package 1

Bit Name Access Description Default5 DTE_XS_PRESENT RO Indicates if the DTE XS is present

0 DTE XS is not present in package1 DTE XS is present in package

0x0

4 PHY_XS_PRESENT RO Indicates if the PHY XS is present0 PHY XS is not present in package1 PHY XS is present in package

0x1

3 PCS_PRESENT RO Indicates if the PCS is present0 PCS is not present in package1 PCS is present in package

0x1

2 WIS_PRESENT RO Indicates if the WIS is present0 WIS is not present in package1 WIS is present in package

0x1

1 PMD_PMA_PRESENT RO Indicates if the PMAPMD is present0 PMDPMA is not present in package1 PMDPMA is present in package

0x1

Registers

Address0x06

2136 PMAPMD Control 2Short NamePMA_PMD_CONTROL_2

0 CLAUSE_22_REG_PRESENT RO Indicates if the clause 22 registers are present0 Clause 22 registers are not present in package1 Clause 22 registers are present in package

0x0

Bit Name Access Description Default15 VENDOR_SPECIFIC_DEV2_PRESENT RO Indicates if the vendor-specific device 2 is

present0 Vendor-specific device 2 is not present in package1 Vendor-specific device 2 is present in package

0x0

14 VENDOR_SPECIFIC_DEV1_PRESENT RO Indicates if the vendor-specific device 1 is present0 Vendor-specific device 1 is not present in package1 Vendor-specific device 1 is present in package

0x0

Table 7 bull PMAPMD Devices In Package 1 (continued)

Bit Name Access Description Default

Registers

Address0x07

214 Device 1 IEEE PMAPMD Status2141 PMAPMD Status 2

Short NamePMA_PMD_STATUS_2

Address0x08

Table 9 bull PMAPMD Control 2

Bit Name Access Description Default30 VENDOR_SPECIFIC_DEV2_PRESENT_CTRL RW Indicates the PMA type selected

WAN mode is enabled when 10GBASE-SW 10GBASE-LW or 10GBASE-EW is selected1111 10BASE-T (not supported)1110 100BASE-TX (not supported)1101 1000BASE-KX1100 1000BASE-T (not supported)1011 10GBASE-KR1010 10GBASE-KX4 (not supported)1001 10GBASE-T (not supported)1000 10GBASE-LRM0111 10GBASE-SR0110 10GBASE-LR0101 10GBASE-ER0100 10GBASE-LX-40011 10GBASE-SW0010 10GBASE-LW0001 10GBASE-EW0000 Reserved

0xB

Table 10 bull PMAPMD Status 2

Bit Name Access Description Default1514 DEVICE_PRESENT RO Indicates if the PMA device is present

00 Device not present01 Reserved10 Device present11 Reserved

0x2

13 TRANSMIT_FAULT_ABILITY RO PMAPMD transmit path fault detection ability0 PMAPMD does not have the ability to detect a fault condition on the transmit path1 PMAPMD has the ability to detect a fault condition on the transmit path

0x1

12 RECEIVE_FAULT_ABILITY RO PMAPMD receive path fault detection ability0 PMAPMD does not have the ability to detect a fault condition on the receive path1 PMAPMD has the ability to detect a fault condition on the receive path

0x1

Registers

11 TRANSMIT_FAULT RO Indicates a fault condition on this interfaces transmit path This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No fault condition on transmit path1 Fault condition on transmit path

0x0

10 RECEIVE_FAULT RO Indicates a fault condition on this interfaces receive path This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No fault condition on receive path1 Fault condition on receive path

0x0

8 PMD_TRANSMIT_DISABLE_ABILITY RO Disable the PMAPMD transmit path ability0 PMD does not have the ability to disable the transmit path1 PMD has the ability to disable the transmit path

0x1

7 ETH_10GBASE_SR_ABILITY RO 10GBASE-SR ability0 PMAPMD is not able to perform 10GBASE-SR1 PMAPMD is able to perform 10GBASE-SR

0x1

6 ETH_10GBASE_LR_ABILITY RO 10GBASE-LR ability0 PMAPMD is not able to perform 10GBASE-LR1 PMAPMD is able to perform 10GBASE-LR

0x1

5 ETH_10GBASE_ER_ABILITY RO 10GBASE-ER ability0 PMAPMD is not able to perform 10GBASE-ER1 PMAPMD is able to perform 10GBASE-ER

0x1

4 ETH_10GBASE_LX4_ABILITY RO 10GBASE-LX4 ability0 PMAPMD is not able to perform 10GBASE-LX41 PMAPMD is able to perform 10GBASE-LX4

0x0

3 ETH_10GBASE_SW_ABILITY RO 10GBASE-SW ability0 PMAPMD is not able to perform 10GBASE-SW1 PMAPMD is able to perform 10GBASE-SW

0x1

2 ETH_10GBASE_LW_ABILITY RO 10GBASE-LW ability0 PMAPMD is not able to perform 10GBASE-LW1 PMAPMD is able to perform 10GBASE-LW

0x1

Table 10 bull PMAPMD Status 2 (continued)

Registers

215 Device 1 IEEE PMD Control and StatusConfiguration and status register set for Device 1 IEEE MDIO

2151 PMD Transmit DisableShort NamePMD_TRANSMIT_DISABLE

Address0x09

2152 PMD Receive Signal Detect Short NamePMD_RECEIVE_SIGNAL_DETECT

1 ETH_10GBASE_EW_ABILITY RO 10GBASE-EW ability0 PMAPMD is not able to perform 10GBASE-EW1 PMAPMD is able to perform 10GBASE-EW

0x1

0 PMA_LOOPBACK_ABILITY RO Ability to perform a loopback function0 PMA does not have the ability to perform a loopback function1 PMA has the ability to perform a loopback function

0x1

Table 11 bull PMD Transmit Disable

Bit Name Access Description Default4 PMD_TRANSMIT_DISABLE_3 RO Value always 0 writes ignored

0 Normal operation1 Transmit disable

0x0

3 PMD_TRANSMIT_DISABLE_2 RO Value always 0 writes ignored0 Normal operation1 Transmit disable

0x0

0 GLOBAL_PMD_TRANSMIT_DISABLE RW PMD transmit disable This register bit can be transmitted from a GPIO pin to shut off an optics modules Tx driver This TXEN signal automatically disables the Tx driver when the channel is in low power mode The GPIO configuration controls whether the transmitted signal is active high or active low0 Transmit enabled1 Transmit disabled

0x0

Registers

Address0x0A

216 Device 1 IEEE PMAPMD Package ID2161 PMAPMD Package Identifier 1

Short NamePMA_PMD_PACKAGE_ID_1

Address0x1E

2162 PMAPMD Package Identifier 2Short NamePMA_PMD_PACKAGE_ID_2

Address0x1F

217 KR FEC AbilityShort NameKR_FEC_ABILITY

Table 12 bull PMD Receive Signal Detect

Bit Name Access Description Default4 PMD_RECEIVE_SIGNAL_DETECT_3 RO Do not support this function value always 0 0x0

3 PMD_RECEIVE_SIGNAL_DETECT_2 RO Do not support this function value always 0 0x0

0 GLOBAL_PMD_RECEIVE_SIGNAL_DETECT RO PMD receiver signal detect0 Signal not detected by receiver1 Signal detected by receiver

0x0

Table 13 bull PMAPMD Package Identifier 1

Bit Name Access Description Default150 PMA_PMD_PACKAGE_ID_1 RO PMAPMD package identifier 1 0x0000

Registers

Address0xAA

218 KR FEC Control 1Short NameKR_FEC_CONTROL_1

Address0xAB

219 KR FEC Status2191 KR FEC Corrected Lower

Short NameKR_FEC_CORRECTED_LOWER

Table 15 bull KR FEC Ability

Bit Name Access Description Default1 FEC_error_indication_ability RO FEC error reporting ability

0 This PHY device is not able to report FEC decoding errors to the PCS layer1 This PHY device is able to report FEC decoding errors to the PCS layer

0x1

0 FEC_ability RO FEC ability0 This PHY device does not support FEC1 This PHY device supports FEC

0x1

Table 16 bull KR FEC Control 1

Bit Name Access Description Default1 FEC_enable_error_indication RW 0 Decoding errors have no effect on PCS sync

bits1 Enable decoder to indicate errors to PCS sync bits

0x1

0 FEC_enable RW FEC enable0 Disable FEC1 Enable FEC

0x0

Registers

Address0xAC

2192 KR FEC Corrected UpperShort NameKR_FEC_CORRECTED_UPPER

Address0xAD

2193 KR FEC Uncorrected LowerShort NameKR_FEC_UNCORRECTED_LOWER

Table 17 bull KR FEC corrected lower

Bit Name Access Description Default150 FEC_CORRECTED_BLOCKS_LOWER RO The FEC corrected block count is split across

two registers KR_FEC_corrected_lower and KR_FEC_corrected_upper KR_FEC_corrected_lower contains the least significant 16 bits of the count KR_FEC_corrected_upper contains the most significant 16 bits of the countReading address KR_FEC_corrected_lower latches the 16 most significant bits of the counter in KR_FEC_corrected_upper for future read out The block count register is cleared when KR_FEC_corrected_lower is read

0x0000

Table 18 bull KR FEC Corrected Upper

Bit Name Access Description Default150 FEC_CORRECTED_BLOCKS_UPPER RO The FEC corrected block count is split across

0x0000

Registers

Address0xAE

2194 KR FEC Uncorrected UpperShort NameKR_FEC_UNCORRECTED_UPPER

Address0xAF

2110 KR FEC Control 2Short NameKR_FEC_Control_2

Table 19 bull KR FEC Uncorrected Lower

Bit Name Access Description Default150 FEC_UNCORRECTED_BLOCKS_LOWER RO The FEC uncorrectable block count is split

across two registers KR_FEC_uncorrected_lower and KR_FEC_uncorrected_upper KR_FEC_uncorrected_lower contains the least significant 16 bits of the count KR_FEC_uncorrected_upper contains the most significant 16 bits of the countReading address KR_FEC_uncorrected_lower latches the 16 most significant bits of the counter in KR_FEC_uncorrected_upper for future read out The block count register is cleared when KR_FEC_uncorrected_lower is read

0x0000

Table 20 bull KR FEC Uncorrected Upper

Bit Name Access Description Default150 FEC_UNCORRECTED_BLOCKS_UPPER RO The FEC uncorrectable block count is split

0x0000

Registers

Address0x8300

2111 Rx Alarm ControlShort NameRX_ALARM_Control_Register

Address0x9000

Bit Name Access Description Default1 fec_inframe RO FEC in frame lock indication This is a sticky bit

that latches the low state The latch-low bit is cleared when the register is read0 FEC has not achieved lock1 FEC has achieved lock

0x1

0 fec_rstmon RW FEC counters reset0 No effect1 Reset FEC counters

0x0

Table 22 bull Rx Alarm Control

Bit Name Access Description Default10 Vendor_Specific RW Vendor specific

0 Disable1 Enable

0x0

9 WIS_Local_Fault_Enable RW WIS local fault enable0 Disable1 Enable

0x0

85 Vendor_Specific_idx2 RW Vendor specific0 Disable1 Enable

0x0

4 PMA_PMD_Receiver_Local_Fault_Enable RW PMAPMD receiver local fault enable0 Disable1 Enable

0x1

3 PCS_Receive_Local_Fault_Enable RW PCS receive local fault enable0 Disable1 Enable

0x1

0x0

0 PHY_XS_Receive_Local_Fault_Enable RW PHY XS receive local fault enable0 Disable1 Enable

0x0

Registers

2112 Tx Alarm ControlShort NameTX_ALARM_Control_Register

Address0x9001

2113 Rx Alarm StatusShort NameRX_ALARM_Status_Register

Address0x9003

Table 23 bull Tx Alarm Control

0 Disable1 Enable

0x00

4 PMA_PMD_Transmitter_Local_Fault_Enable RW PMAPMD transmitter local fault enable0 Disable1 Enable

0x1

3 PCS_Transmit_Local_Fault_Enable RW PCS transmit local fault enable0 Disable1 Enable

0x1

0x0

0 PHY_XS_Transmit_Local_Fault_Enable RW PHY XS transmit local fault enable0 Disable1 Enable

0x1

Table 24 bull Rx Alarm Status

Bit Name Access Description Default10 Vendor_Specific RO For future use 0x0

9 WIS_Local_Fault RO WIS local faultThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No WIS local fault1 WIS local fault

0x0

85 Vendor_Specific_idx2 RO For future use 0x0

4 PMA_PMD_Receiver_Local_Fault RO PMAPMD receiver local faultThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PMAPMD receiver local fault1 PMAPMD receiver local fault

0x0

Registers

2114 Tx Alarm StatusShort NameTX_ALARM_Status_Register

Address0x9004

2115 Clock Output Control21151 Interfaces RXCKOUT Configuration

Short NameRXCK_CFG

3 PCS_Receive_Local_Fault RO PCS receive local faultThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PCS receive local fault1 PCS receive local fault

0x0

0 PHY_XS_Receive_Local_Fault RO PHY XS receive local faultThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PHY XS receive local fault1 PHY XS receive local fault

0x0

Table 25 bull Tx Alarm Status

4 PMA_PMD_Transmitter_Local_Fault RO PMAPMD transmitter local fault enableThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PMAPMD transmitter local fault1 PMAPMD transmitter local fault

0x0

3 PCS_Transmit_Local_Fault RO PCS transmit local fault enableThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PCS transmit local fault1 PCS transmit local fault

0x0

0 PHY_XS_Transmit_Local_Fault RO PHY XS transmit local fault enableThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 No PHY XS transmit local fault1 PHY XS transmit local fault

0x0

Table 24 bull Rx Alarm Status (continued)

Registers

Address0xA000

Table 26 bull Interfaces RXCKOUT Configuration

Bit Name Access Description Default7 RXCK_RXPLLF_LOCK_MASK RW Mask RXPLLF_LOCK from affecting the

RXCK64 auto-squelch at the RXCKOUT and TXCKOUT pins0 RXPLLF_LOCK does not affect RXCK64 auto-squelch1 RXPLLF_LOCK affects RXCK64 auto-squelch

0x0

6 RXCK_PCS_FAULT_MASK RW Mask PCS_FAULT from affecting the RXCK64 auto-squelch at the RXCKOUT and TXCKOUT pins0 PCS_FAULT does not affect RXCK64 auto-squelch1 PCS_FAULT affects RXCK64 auto-squelch

0x0

5 RXCK_LOPC_MASK RW Mask LOPC from affecting the RXCK64 auto-squelch at the RXCKOUT and TXCKOUT pins0 LOPC does not affect RXCK64 auto-squelch1 LOPC affects RXCK64 auto-squelch

0x0

4 RXCK_IB_SIGNAL_DETECT_MASK RW Mask IB_SIGNAL_DETECT from affecting the RXCK64 auto-squelch at the RXCKOUT and TXCKOUT pins0 IB_SIGNAL_DETECT does not affect RXCK64 auto-squelch1 IB_SIGNAL_DETECT affects RXCK64 auto-squelch

0x0

3 RXCKOUT_ENABLE RW Enable the interfaces RXCKOUT pinRXCKOUT is also affected by TXCKOUT_ENABLE bit and OB_TST_OUT_CFGOB_CTRL[10]To enable the RXCKOUT pin either RXCKOUT_ENABLE or TXCKOUT_ENABLE must be set to 1 and OB_CTRL[10] must be set to 10= RXCKOUT disable1= RXCKOUT enable

0x0

Registers

21152 Interfaces TXCKOUT ConfigurationShort NameTXCK_CFG

Address0xA001

20 RXCKOUT_SEL RW Configure the interfaces RXCKOUT pin000= Line-side Rx recovered clock (LAN 32226 MHz WAN 31104 MHz 1G 125 MHz)001= Line-side Rx recovered clock divide by 2 (LAN 16113 MHz WAN 15552 MHz 1G 625 MHz)010= Line-side Tx clock (LAN 32226 MHz WAN 31104 MHz 1G 125 MHz)011= Line-side Tx clock divide by 2 (LAN 16113 MHz WAN 15552 MHz 1G 625 MHz)100= Line-side PLL test clock101= Factory test110= Host-side Rx recovered clock (LANWAN 3125 MHz 78125 MHz or 625 MHz 1G 125 MHz 3125 MHz or 25 MHz)111= Host-side PLL test clock

0x0

Table 27 bull Interfaces TXCKOUT Configuration

Bit Name Access Description Default3 TXCKOUT_ENABLE RW Enable the interfaces TXCKOUT pin

TXCKOUT is also affected by RXCKOUT_ENABLE bit and OB_TST_OUT_CFGOB_CTRL[10]To enable the TXCKOUT pin either TXCKOUT_ENABLE or RXCKOUT_ENABLE must be set to 1 and OB_CTRL[10] must be set to 10= TXCKOUT disable1= TXCKOUT enable

0x0

20 TXCKOUT_SEL RW Configure the interfaces TXCKOUT pin000= Line-side Tx clock (LAN 32226 MHz WAN 31104 MHz 1G 125 MHz)001= Line-side Tx clock divide by 2 (LAN 16113 MHz WAN 15552 MHz 1G 625 MHz)010= Line-side Rx recovered clock (LAN 32226 MHz WAN 31104 MHz 1G 125 MHz)011= Line-side Rx recovered clock divide by 2 (LAN 16113 MHz WAN 15552 MHz 1G 625 MHz)100= Line-side PLL test clock101= Factory test110= Host-side Rx recovered clock (LANWAN 3125 MHz 78125 MHz or 625 MHz 1G 125 MHz 3125 MHz or 25 MHz)111= Host-side PLL test clock

0x0

Table 26 bull Interfaces RXCKOUT Configuration (continued)

Registers

2116 Data Path Control21161 10G or 1G Mode in Data Path

Short NameDATAPATH_MODE

Address0xA002

2117 Data Path Loopback ControlShort NamePMA_LOOPBACK_CONTROL

Address0xA003

Table 28 bull 10G or 1G Mode in Datapath

Bit Name Access Description Default6 USR_10G_WAN One-shot Configure line-side SerDes to 10G WAN mode

with the ROM engine This register is self-clearing0= Do nothing1= Configure line-side SerDes to 10G WAN mode with the ROM engine

0x0

5 USR_10G_LAN One-shot Configure line-side SerDes to 10G LAN mode with the ROM engine This register is self-clearing0= Do nothing1= Configure line-side SerDes to 10G LAN mode with the ROM engine

0x0

4 USR_1G One-shot Configure line-side SerDes to 1G mode with the ROM engine This register is self-clearing0= Do nothing1= Configure line-side SerDes to 1G mode with the ROM engine

0x0

1 SEL_1G_LANE_3 RW In 1G mode of operation select the lane used for data on the client-side interface0= Lane 0 is used for 1G data1= Lane 3 is used for 1G data

0x0

0 ETH_1G_ENA RW Configure datapath and host-side SerDes into 1G mode0= 10G LAN or WAN1= 1G

0x0

Table 29 bull Datapath Loopback Control

Bit Name Access Description Default0 L3_CONTROL RW Loopback L3 enable

0= Normal operation1= Enable L3 loopback

0x0

Registers

2118 Enable MAC in the Data PathShort NameMAC_ENA

Address0xA006

2119 Write RCOMP 4-bit Resistor Calibration Value into SD10GShort NameRCOMP

Address0xA007

2120 Configuration Registers for Clock Output Buffer21201 Clock Output Buffer Bias Control

Short NameOB_BIAS_CTRL

Table 30 bull Enable MAC in the Datapath

Bit Name Access Description Default1 MACSEC_CLK_ENA RW Clock enable for the MACsec logic De-asserting

this bit when MACsec is disabled and MACs are enabled will save power Note The CLK_EN register bits within the MACsec register space must be asserted along with this bit when the MACsec logic is to be used This bit usage applies to the VSC8490 and VSC8491 products only0= MACsec clock is squelched1= MACsec clock is enabled

0x0

0 MAC_ENA RW Enable MAC in the datapath0= MAC is not in the datapath1= MAC is in the datapath

0x0

Table 31 bull Write RCOMP 4-bit Resistor Calibration Value into SD10G

Bit Name Access Description Default0 RCOMP_WRITE One-shot Write RCOMP 4-bit resistor calibration value into

SD10G0= Do nothing1= Start RCOMP event

0x0

Registers

Address0xA00C

21202 Clock Output Buffer ControlShort NameOB_CTRL

Address0xA00D

2121 Vendor-Specific PMA Control 2Short NameVendor_Specific_PMA_Control_2

Address0xA100

Table 32 bull Clock Output Buffer Bias Control

Bit Name Access Description Default70 OB_BIAS_CTRL RW Clock output buffer bias control

20= Sets the class AB bias current in the common mode control circuit 05 mA is expected to give sufficient performance and is default Other settings are for debug Current range is 0 mA to 175 mA in 025 mA steps Default is set to 0 (disable)3= Enable internal CML to CMOS converter for input to test output path54= Reserved76= Slopeslew rate control 0 45 ps 1 85 ps 2 105 ps 3 115 ps risefall time (all values are typical)

0x08

Table 33 bull Clock Output Buffer Control

Bit Name Access Description Default150 OB_CTRL RW Clock output buffer control registers

30= Value for resistor calibration (RCOMP) 15 lowest value 0 highest value74= Adjustment for common mode voltage 0 off --gt results in a value around 500 mV 1 440 mV 2 480 mV 3 460 mV 4 530 mV 6 500 mV 8 570 mV 12 550 mV8= Disable VCM control 1 disable 0 enable9= Enable VREG measure 1 enable 0 disable10= Enable output buffer 1 enable 0 disable (power down)11= Reserved1512= Select output level 400 mVppd (0) to 1100 mVppd (15) in 50 mVppd steps

0x5464

Table 34 bull Vendor-Specific PMA Control 2

Bit Name Access Description Default15 wis_intb_activeh RW WIS_INTB active edge

0 WIS_INTB is active low1 WIS_INTB is active high

0x0

14 wis_inta_activeh RW WIS_INTA active edge0 WIS_INTA is active low1 WIS_INTA is active high

0x0

Registers

10 Suppress_LOS_detection RW LOS circuitry is driven by a signal detection status signal in the line-side input buffer The signal detection alarm driving the LOS circuitry can be squelched with this register bitLOS detection is0 Allowed1 Suppressed

0x0

9 Suppress_LOL_detection RW LOL circuitry is driven by a status signal in the line-side CRU The status signal driving the LOL circuitry can be squelched with this register bitLOL detection is0 Allowed1 Suppressed

0x0

8 TX_LED_BLINK_TIME RW Tx data activity LED blink time0 50 ms interval1 100 ms interval

0x1

7 RX_LED_BLINK_TIME RW Rx data activity LED blink time0 50 ms interval1 100 ms interval

0x1

65 TX_LED_MODE RW Tx LED mode control00 Display Tx link status01 Reserved10 Display combination of Tx link and Tx data activity status11 Reserved

0x2

43 RX_LED_MODE RW Rx LED mode control00 Display Rx link status01 Reserved10 Display combination of Rx link and Rx data activity status11 Reserved

0x2

2 Override_system_loopback_data RW System loopback data override0 Data sent out XFI output matches default1 Use PMA system loopback data select to select XFI output data

0x0

10 PMA_system_loopback_data_select RW When override system loopback data (bit 2) is set and the data channel is in 10G mode the data transmitted from Tx PMA is determined by these register bits00 Repeating 0x00FF pattern01 Continuously send 0s10 Continuously send 1s11 Data from Tx WIS block

0x0

Table 34 bull Vendor-Specific PMA Control 2 (continued)

Registers

2122 Vendor-Specific PMA Status 2Short NameVendor_Specific_PMA_Status_2

Address0xA101

2123 Vendor-Specific LOPC StatusShort NameVendor_Specific_LOPC_Status

Table 35 bull Vendor Specific PMA Status 2

Bit Name Access Description Default3 WAN_ENABLED_status RO Indicates if the device is in WAN mode

0 Not in WAN mode1 WAN modeWAN mode is enabled whenWIS_CTRL2WAN_MODE= 1 or PCS_Control_2Select_WAN_mode_or_10GBASE_R= 2 or PMA_PMD_CONTROL_2VENDOR_SPECIFIC_DEV2_PRESENT_CTRL= 1 or PMA_PMD_CONTROL_2VENDOR_SPECIFIC_DEV2_PRESENT_CTRL= 2 or PMA_PMD_CONTROL_2VENDOR_SPECIFIC_DEV2_PRESENT_CTRL= 3

0x0

2 WIS_INTA_pin_status RO WIS_INTA pin status0 WIS_INTA pin is low1 WIS_INTA pin is high

0x0

1 WIS_INTB_pin_status RO WIS_INTB pin status0 WIS_INTB pin is low1 WIS_INTB pin is high

0x0

0 PMTICK_pin_status RO PMTICK pin status0 PMTICK pin is low1 PMTICK pin is high

0x0

Registers

Address0xA200

2124 Vendor-Specific LOPC ControlShort NameVendor_Specific_LOPC_Control

Address0xA201

Table 36 bull Vendor-Specific LOPC Status

Bit Name Access Description Default2 Present_state_of_the_LOPC_pin_with_reginv RO Present state of the LOPC pin taking into

account the LOPC logic inversion register bit (Vendor_Specific_LOPC_ControlLOPC_state_inversion_select)0 LOPC pin is low when Vendor_Specific_LOPC_ControlLOPC_state_inversion_select= 0 LOPC is high when Vendor_Specific_LOPC_ControlLOPC_state_inversion_select= 11 LOPC pin is high when Vendor_Specific_LOPC_ControlLOPC_state_inversion_select= 0 LOPC is low when Vendor_Specific_LOPC_ControlLOPC_state_inversion_select= 1

0x0

1 Present_state_of_the_LOPC_pin_without_reginv RO Present state of the LOPC pin does not take into account the LOPC logic inversion register bit (Vendor_Specific_LOPC_ControlLOPC_state_inversion_select)0 LOPC pin is low1 LOPC pin is high

0x0

0 Interrupt_pending_bit RO LOPC interrupt pending status The latch-high bit is cleared when the register is read0 An interrupt event has not occurred since the last time this bit was read1 An interrupt event determined by lopc_intr_mode has occurred

0x0

Table 37 bull Vendor-Specific LOPC Control

Bit Name Access Description Default2 LOPC_state_inversion_select RW LOPC pin polarity

0 The part is in a LOPC alarm state when the LOPC pin is logic low1 The part is in a LOPC alarm state when the LOPC pin is logic high

0x0

Registers

2125 Block-Level ResetReset the data path of various blocks Configuration registers in the blocks are not reset to default states

21251 Block-Level Soft Reset1Short NameBLOCK_LEVEL_RESET1

Address0xAE00

10 lopc_intr_pend_bit_select RW This bit group determines how the LOPC interrupt pending register bit in Vendor_Specific_LOPC_StatusInterrupt_pending_bit is asserted00 Interrupt generation is disabled01 lopc_intr_pend is set on a rising edge of the LOPC pin regardless of the Vendor_Specific_LOPC_ControlLOPC_state_inversion_select setting10 lopc_intr_pend is set on a falling edge of the LOPC pin regardless of the Vendor_Specific_LOPC_ControlLOPC_state_inversion_select setting11 lopc_intr_pend is set on both edges of the LOPC pin

0x0

Table 38 bull Block-Level Soft Reset1

Bit Name Access Description Default15 I2CM_RESET One-shot Reset the I2C (master) used to communicate with an

optics module0 Normal operation1 Reset

0x0

9 WIS_INTR_TREE_RESET One-shot Reset WIS interrupt tree logic0 Normal operation1 Reset

0x0

8 XGXS_INGR_RESET One-shot Reset the chips ingress data path in the XGXS block0 Normal operation1 Reset

0x0

7 HOST_1G_PCS_INGR_RESET One-shot Reset the chips ingress data path in the host 1G PCS block0 Normal operation1 Reset

0x0

6 FIFO_INGR_RESET One-shot Reset the rate-compensating FIFO in the chips ingress data path The FIFO is used when the MACs are disabled0 Normal operation1 Reset

0x0

Table 37 bull Vendor-Specific LOPC Control (continued)

Registers

Address0xAE01

5 HOST_MAC_INGR_RESET One-shot Reset the chips ingress data path in the host MAC and flow control buffer0 Normal operation1 Reset

0x0

4 LINE_MAC_INGR_RESET One-shot Reset the chips ingress data path in the line MAC MACsec (applies to VSC849091) and flow control buffer0 Normal operation1 Reset

0x0

3 LINE_10G_PCS_INGR_RESET One-shot Reset the chips ingress data path in the 10G PCS blocks when the part is operating mode in 10G mode0 Normal operation1 Reset

0x0

1 WIS_INGR_RESET One-shot Reset the chips ingress data path in the WIS block0 Normal operation1 Reset

0x0

0 PMA_INGR_RESET One-shot Reset the chips ingress data path in the PMA and PMA_INT blocks0 Normal operation1 Reset

0x0

Bit Name Access Description Default10 CLIENT_SERDES_RESET One-shot Reset both the egress and ingress data paths in the

HSIO_MACRO_HOST block (client-side SerDes)0 Normal operation1 Reset

0x0

8 XGXS_EGR_RESET One-shot Reset the chips egress data path in the XGXS block0 Normal operation1 Reset

0x0

Table 38 bull Block-Level Soft Reset1 (continued)

Registers

2126 Spare RWSpare RW registers intended to be used by firmware

21261 Device1 Spare RW 0Short NameDEV1_SPARE_RW0

7 HOST_1G_PCS_EGR_RESET One-shot Reset the chips egress data path in the host 1G PCS block0 Normal operation1 Reset

0x0

6 FIFO_EGR_RESET One-shot Reset the rate-compensating FIFO in the chips egress data path The FIFO is used when the MACs are disabled0 Normal operation1 Reset

0x0

5 HOST_MAC_EGR_RESET One-shot Reset the chips egress data path in the host MAC and flow control buffer0 Normal operation1 Reset

0x0

4 LINE_MAC_EGR_RESET One-shot Reset the chips egress data path in the line MAC MACsec (applies to 849091) and flow control buffer0 Normal operation1 Reset

0x0

3 LINE_10G_PCS_EGR_RESET One-shot Reset the chips egress data path in the 10G PCS blocks when the part is operating in 10G mode0 Normal operation1 Reset

0x0

1 WIS_EGR_RESET One-shot Reset the chips egress data path in the WIS block0 Normal operation1 Reset

0x0

0 PMA_EGR_RESET One-shot Reset the chips egress data path in the PMA and PMA_INT blocks0 Normal operation1 Reset

0x0

Registers

Address0xAEF0

Address0xAEF1

Address0xAEF2

Address0xAEF3

Address0xAEF4

Table 40 bull Device1 Spare RW 0

Bit Name Access Description Default150 dev1_spare_rw0 RW Spare 0x0000

Registers

Address0xAEF5

Address0xAEF6

Address0xAEF7

Address0xAEF8

Address0xAEF9

Registers

Address0xAEFA

Address0xAEFB

Address0xAEFC

Address0xAEFD

Address0xAEFE

Registers

Address0xAEFF

2127 SD10G65 VScope Configuration and Status21271 VScope Main Configuration A

Short NameVScope_MAIN_CFG_A

Address0xB000

21272 VScope Main Configuration Register BShort NameVScope_MAIN_CFG_B

Table 56 bull VScope Main Configuration Register A

Bit Name Access Description Default8 SYN_PHASE_WR_DIS RW Disables writing of synth_phase_aux in

synthesizer0x0

7 IB_AUX_OFFS_WR_DIS RW Disables writing of ib_auxl_offset and ib_auxh_offset in IB

0x0

6 IB_JUMP_ENA_WR_DIS RW Disables writing of ib_jumpl_ena and ib_jumph_ena in IB

0x0

53 CNT_OUT_SEL RW Counter output selection0ndash3 Error counter 0ndash34 Hit counter5 Clock counter6 8 LSBs of error counter 3ndash1 and hit counter7 8 LSBs of error counter 3ndash0

0x0

20 COMP_SEL RW Comparator input selection[REF] 01 auxL45 auxH27 Main [SUB] 57 auxL02 auxH14 Main (36 Reserved)

0x0

Registers

Address0xB001

21273 VScope Main Configuration Register CShort NameVScope_MAIN_CFG_C

Address0xB002

Table 57 bull VScope Main Configuration Register B

Bit Name Access Description Default98 GP_SELECT RW Select GP reg input

0 Rx (main)0x0

7 GP_REG_FREEZE RW Allows freezing the GP register value to assure valid reading

0x0

65 SCAN_LIM RW Scan limit Selects which counter saturation limits the other counters0 Clock counter1 Hit counter2 Error counters3 No limit

0x0

40 PRELOAD_VAL RW Preload value for error counter 0x00

Table 58 bull VScope Main Configuration Register C

Bit Name Access Description Default12 INTR_DIS RW Disable interrupt output 0x0

11 TRIG_ENA RW Enable trigger 0x0

10 QUICK_SCAN RW Counter enable (bit 4) implicitly done by reading the counter unused in HW-scan mode

0x0

95 COUNT_PER RW Counter period preload value for clock counter 0x00

4 CNT_ENA RW Enable counting unused in HW-scan mode 0x0

31 IF_MODE RW Interface width0 8 bit1 10 bit2 16 bit3 20 bit4 32 bit5 40 bitOthers reserved

0x0

0 VScope_ENA RW Enable VScope 0x0

Registers

21274 VScope Pattern Lock Configuration Register AShort NameVScope_PAT_LOCK_CFG_A

Address0xB003

21275 VScope Pattern Lock Configuration Register BShort NameVScope_PAT_LOCK_CFG_B

Address0xB004

21276 VScope HW Scan Configuration Register 1AShort NameVScope_HW_SCAN_CFG_1A

Address0xB005

21277 VScope HW Scan Configuration Register 1BShort NameVScope_HW_SCAN_CFG_1B

Table 59 bull VScope Pattern Lock Configuration Register A

Bit Name Access Description Default1410 PRELOAD_HIT_CNT RW Preload value for hit counter 0x00

90 DC_MASK RW Dont care mask Enables history mask usage0 Enables history mask bit1 History mask bit is ldquodont carerdquo

0x3FF

Table 60 bull VScope Pattern Lock Configuration Register B

Bit Name Access Description Default90 HIST_MASK RW History mask respective sequence is expected

in reference input (comp_sel) if enabled (dc_mask) before hit and error counting is enabled

0x000

Table 61 bull VScope HW Scan Configuration Register 1A

Bit Name Access Description Default13 PHASE_JUMP_INV RW Invert the jumph_ena and jumpl_ena bit in HW-

scan mode0x0

128 AMPL_OFFS_VAL RW Offset between AuxL amplitude (reference) and AuxH amplitude signed (2s-complement) plusmn14 amplitude max

0x00

70 MAX_PHASE_INCR_VAL RW Maximum phase increment value before wrapping

0xFF

Registers

Address0xB006

21278 VScope HW Configuration Register 2AShort NameVScope_HW_SCAN_CFG_2A

Address0xB007

21279 VScope HW Configuration Register 2BShort NameVScope_HW_SCAN_CFG_2B

Table 62 bull VScope HW Scan Configuration Register 1B

Bit Name Access Description Default1510 MAX_AMPL_INCR_VAL RW Maximum amplitude increment value before

wrapping0x3F

97 PHASE_INCR RW Phase increment per scan stepIncrement= phase_incr + 1

0x0

64 AMPL_INCR RW Amplitude increment per scan stepIncrement= ampl_incr + 1

0x0

32 NUM_SCANS_PER_ITR RW Number of scans per iteration in N-point-scan mode0 11 22 43 8

0x2

10 HW_SCAN_ENA RW Enables HW scan with N results per scan or fast-scan0 Off1 N-point scan2 Fast-scan (sq)3 Fast-scan (diag)

0x0

Table 63 bull VScope HW Configuration Register 2A

Bit Name Access Description Default1513 FAST_SCAN_THRES RW Threshold for error_counter in fast-scan mode

N+10x0

128 FS_THRES_SHIFT RW Left shift for threshold of error_counter in fast-scan modeThreshold= (fast_scan_thres+1) shift_left fs_thres_shift

0x00

70 PHASE_JUMP_VAL RW Value at which jumpl_ena and jumph_ena in IB must be toggled

0x00

Registers

Address0xB008

212710 VScope StatusShort NameVScope_STAT

Address0xB009

212711 VScope Counter Register AShort NameVScope_CNT_A

Address0xB00A

212712 VScope Counter Register BShort NameVScope_CNT_B

Address0xB00B

Table 64 bull VScope HW Configuration Register 2B

Bit Name Access Description Default15 AUX_AMPL_SYM_DIS RW Disable IB amplitude symmetry compensation for

AuxH and AuxL0x0

138 AMPL_START_VAL RW Start value for VScope amplitude in N-point-scan mode and fast-scan mode (before IB amplitude symmetry compensation)

0x00

70 PHASE_START_VAL RW Start value for VScope phase in N-point-scan mode and fast-scan mode

0x00

Table 65 bull VScope Status Register

Bit Name Access Description Default158 GP_REG_MSB RO 8 MSBs of general purpose register 0x00

74 FAST_SCAN_HIT RO Fast scan mode indicator per cursor position whether threshold was reached

0x0

0 DONE_STICKY RO Done sticky 0x0

Table 66 bull VScope Counter Register A

Bit Name Access Description Default150 COUNTER_MSB RO Counter value higher 16-bit MSB [3116] 0x0000

Table 67 bull VScope Counter Register B

Bit Name Access Description Default150 COUNTER_LSB RO Counter value lower 16-bit LSB [150] 0x0000

Registers

212713 VScope General Purpose Register AShort NameVScope_DBG_LSB_A

Address0xB00C

212714 VScope General Purpose Register AShort NameVScope_DBG_LSB_B

Address0xB00D

2128 SD10G65 DFT Configuration and Status21281 SD10G65 DFT Main Configuration 1

Short NameDFT_RX_CFG_1

Address0xB100

Table 68 bull VScope General Purpose Register A

Bit Name Access Description Default150 GP_REG_LSB_A RO 16-bit MSB of a 32-bit general purpose register [3116] 0x0000

Bit Name Access Description Default150 GP_REG_LSB_B RO 16-bit LSB of a 32-bit general purpose register [150] 0x0000

Table 70 bull SD10G65 DFT Main Configuration Register 1

Bit Name Access Description Default10 DIRECT_THROUGH_ENA_CFG RW Enables data through from gearbox to gearbox 0x0

9 ERR_CNT_CAPT_CFG RW Captures data from error counter to allow reading of stable data

0x0

87 RX_DATA_SRC_SEL RW Data source selection0 Main path1 VScope high path2 VScope low path

0x0

65 BIST_CNT_CFG RW States in which error counting is enabled3 All but IDLE2 Check1 Stable + check0 Wait_stable + stable+check

0x0

4 FREEZE_PATTERN_CFG RW Disable change of stored patterns (for example to avoid changes during read-out)

0x0

Registers

21282 SD10G65 DFT Main Configuration Register 2Short NameDFT_RX_CFG_2

Address0xB101

3 CHK_MODE_CFG RW Selects pattern to check0 PRBS pattern1 Constant pattern

0x0

20 RX_WID_SEL_CFG RW Selects DES interface width0 81 102 163 204 325 40 (default)

0x4

Bit Name Access Description Default14 RX_WORD_MODE_CFG RW Pattern generator

0 Bytes mode 1 10-bits word mode

0x0

1311 RX_PRBS_SEL_CFG RW Selects PRBS check0 PRBS71 PRBS152 PRBS233 PRBS114 PRBS31 (default)5 PRBS9

0x4

10 INV_ENA_CFG RW Enables PRBS checker input inversion 0x0

9 CMP_MODE_CFG RW Selects compare mode0 Compare mode possible1 Learn mode is forced

0x0

86 LRN_CNT_CFG RW Number of consecutive errorsnon-errors before transitioning to respective stateValue =

0x0

5 CNT_RST RW SW reset of error counter rising edge activates reset

0x0

Table 70 bull SD10G65 DFT Main Configuration Register 1 (continued)

Registers

21283 SD10G65 DFT Pattern Mask Configuration Register 1 Short NameDFT_RX_MASK_CFG_1

Address0xB102

Configuration register 1 for SD10G65 DFT to mask data bits preventing error counting for these bits

21284 SD10G65 DFT Pattern Mask Configuration Register 2Short NameDFT_RX_MASK_CFG_2

Address0xB103

21285 SD10G65 DFT Pattern Checker Configuration Register 1Short NameDFT_RX_PAT_CFG_1

Address0xB104

43 CNT_CFG RW Selects modes in which error counter is active0 Learn and compare mode1 Transition between modes2 Learn mode3 Compare mode

0x0

21 BIST_MODE_CFG RW BIST mode0 Pff1 BIST2 BER3 CONT (infinite mode)

0x3

0 DFT_RX_ENA RW Enable Rx DFT capability0 Disable DFT1 Enable DFT

0x0

Table 72 bull SD10G65 DFT Pattern Mask Configuration Register 1

Bit Name Access Description Default150 LSB_MASK_CFG_1 RW Mask out (active high) errors in 16-bit MSB data bits [3116] 0x0000

Bit Name Access Description Default150 LSB_MASK_CFG_2 RW Mask out (active high) errors in 16 LSB data bits [150] 0x0000

Registers

Pattern checker configuration register 1 for SD10G65 DFT

Address0xB105

21287 SD10G65 DFT BIST Configuration Register 0AShort NameDFT_BIST_CFG0A

Address0xB106

BIST configuration register A for SD10G65 DFT controlling check and wait-stable mode

21288 SD10G65 DFT BIST Configuration Register 0BShort NameDFT_BIST_CFG0B

Address0xB107

BIST configuration register B for SD10G65 DFT controlling check and wait-stable mode

Address0xB108

Table 74 bull SD10G65 DFT Pattern Checker Configuration Register 1

Bit Name Access Description Default158 MSB_MASK_CFG RW Mask out (active high) errors in 8 MSB data bits 0x00

0 PAT_READ_CFG RW Pattern read enable 0x0

Bit Name Access Description Default118 MAX_ADDR_CHK_CFG RW Maximum address in checker (before continuing

with address 0)0x0

30 READ_ADDR_CFG RW Address to read patterns from used by SW 0x0

Table 76 bull SD10G65 DFT BIST Configuration Register 0A

Bit Name Access Description Default150 WAKEUP_DLY_CFG RW BIST FSM threshold to leave DOZE state 0x0000

Table 77 bull SD10G65 DFT BIST Configuration Register 0B

Bit Name Access Description Default150 MAX_BIST_FRAMES_CFG RW BIST FSM threshold to enter FINISHED state 0x0000

Registers

BIST configuration register A for SD10G65 DFT controlling stable mode

Address0xB109

BIST configuration register B for SD10G65 DFT controlling stable mode

Address0xB10A

BIST configuration register B for SD10G65 DFT controlling frame length in check mode

Address0xB10B

Address0xB10C

Bit Name Access Description Default150 MAX_UNSTABLE_CYC_CFG RW BIST FSM threshold to iterate counter for

max_stable_attempts0x0000

Bit Name Access Description Default150 STABLE_THRES_CFG RW BIST FSM threshold to enter CHECK state 0x0000

Bit Name Access Description Default150 FRAME_LEN_CFG_MSB RW BIST FSM threshold to iterate counter for

max_bist_frames [3116]0x0000

Bit Name Access Description Default150 FRAME_LEN_CFG_LSB RW BIST FSM threshold to iterate counter for

Registers

BIST configuration register A for SD10G65 DFT controlling stable attempts in wait-stable mode

Address0xB10D

BIST configuration register B for SD10G65 DFT controlling stable attempts in wait-stable mode

212815 SD10G65 DFT Error Status Register 1Short NameDFT_ERR_STAT_1

Address0xB10E

Status register 1 for SD10G65 DFT containing the error counter value

Address0xB10F

Status register B2 for SD10G65 DFT containing the error counter value

212817 SD10G65 DFT PRBS Status Register 1Short NameDFT_PRBS_STAT_1

Address0xB110

Bit Name Access Description Default150 MAX_STABLE_ATTEMPTS_CFG_MSB RW BIST FSM threshold to enter SYNC_ERR state

[3116]0x0000

Bit Name Access Description Default150 MAX_STABLE_ATTEMPTS_CFG_LSB RW BIST FSM threshold to enter SYNC_ERR state

[150]0x0000

Table 84 bull SD10G65 DFT Error Status Register 1

Bit Name Access Description Default150 ERR_CNT_MSB RO Counter output depending on cnt_cfg_i [3116] 0x0000

Bit Name Access Description Default150 ERR_CNT_LSB RO Counter output depending on cnt_cfg_i [150] 0x0000

Registers

Status register 1 for SD10G65 DFT containing the PRBS data related to the first sync lost event

Address0xB111

212819 SD10G65 DFT Miscellaneous Status Register 1Short NameDFT_MAIN_STAT_1

Address0xB112

Address0xB113

Table 86 bull SD10G65 DFT PRBS Status Register 1

Bit Name Access Description Default150 PRBS_DATA_STAT_MSB RO PRBS data after first sync lost [3116] 0x0000

Bit Name Access Description Default150 PRBS_DATA_STAT_LSB RO PRBS data after first sync lost [150] 0x0000

Table 88 bull SD10G65 DFT Miscellaneous Status Register 1

Bit Name Access Description Default90 CMP_DATA_STAT RO 10-bit data word at address read_addr_cfg used

for further observation by SW0x000

Bit Name Access Description Default4 STUCK_AT RO Data input unchanged for at least 7 clock cycles

(defined by c_STCK_CNT_THRES)0x0

3 NO_SYNC RO BIST no sync found since BIST enabled 0x0

2 INSTABLE RO BIST input data not stable 0x0

1 INCOMPLETE RO BIST not complete (that is not reached stable state or following)

0x0

0 ACTIVE RO BIST is active (that is left DOZE but did not enter a final state)

0x0

Registers

212821 SD10G65 DFT Main ConfigurationShort NameDFT_TX_CFG

Address0xB114

Table 90 bull SD10G65 DFT Main Configuration

Bit Name Access Description Default13 TX_STUCK_AT_CLR_CFG RW Clears the tx_stuck_at_sticky status bit

0 Keep sticky bit value1 Clear sticky bitNote While 1 each write access to any register of this SPI clears the sticky bit

0x0

12 RST_ON_STUCK_AT_CFG RW Enables (1) reset of PRBS generator in case of unchanged data (stuck-at) for at least 511 clock cycles Can be disabled (0) for example in scrambler mode to avoid the very rare case that input patterns allow to keep the generators shift register filled with a constant value

0x1

119 TX_WID_SEL_CFG RW Selects SER interface width0 81 102 163 204 325 40 (default)

0x4

86 TX_PRBS_SEL_CFG RW Selects PRBS generator0 PRBS71 PRBS152 PRBS233 PRBS114 PRBS31 (default)5 PRBS9

0x4

5 SCRAM_INV_CFG RW Inverts the scrambler output 0x0

4 IPATH_CFG RW Selects PRBS generator input0 Pat-gen1 Core

0x0

32 OPATH_CFG RW Selects DFT-TX output0 PRBSscrambler (default)1 Bypass

0x0

1 TX_WORD_MODE_CFG RW Word width of constant pattern generator0 Bytes mode1 10-bits word mode

0x0

0 DFT_TX_ENA RW Enable Tx DFT capability0 Disable DFT1 Enable DFT

0x0

Registers

212822 SD10G65 DFT Tx Constant Pattern Configuration Register 1Short NameDFT_TX_PAT_CFG_1

Address0xB115

Tx constant MSB pattern configuration register 1 for SD10G65 DFT

Address0xB116

212824 SD10G65 DFT Tx Constant Pattern StatusShort NameDFT_TX_CMP_DAT_STAT

Address0xB117

Status register for SD10G65 DFT containing the constant patterns used for comparison (last in LEARN mode)

2129 ROM Engine 121291 SPI Address Field of ROM Table Entry (replication_count= 170)

Short Namespi_adr

Table 91 bull SD10G65 DFT Tx Constant Pattern Configuration Register 1

Bit Name Access Description Default4 PAT_VLD_CFG RW Constant patterns are valid to store 0x0

30 MAX_ADDR_GEN_CFG RW Maximum address in generator (before continuing with address 0)

0x0

Bit Name Access Description Default1310 STORE_ADDR_CFG RW Current storage address for patterns in generator 0x0

90 PATTERN_CFG RW 10-bit word of constant patterns for transmission 0x000

Table 93 bull SD10G65 DFT Tx Constant Pattern Status

Bit Name Access Description Default12 TX_STUCK_AT_STICKY RO ScramblerPRBS generator output unchanged

for at least 511 clock cycles0x0

90 PAT_STAT RO 10-bit data word at address store_addr_cfg used for further observation by SW

0x000

Registers

Addresses0xB200ndash0xB2A9

21292 Lower 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)Short Namedata_lsw

21293 Upper 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)Short Namedata_msw

2130 ROM Engine 221301 ROM Table StartEnd Addresses of Tx 10G Setting Routine

Short Nameadr_tx10g

Address0xB600

21302 ROM Table StartEnd Addresses of Rx 10G Setting RoutineShort Nameadr_rx10g

Address0xB601

Table 94 bull SPI Address Field of ROM Table Entry (replication_count= 170)

Bit Name Access Description Default60 spi_adr RW SPI address to write 0x00

Table 95 bull Lower 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)

Bit Name Access Description Default150 spi_dat_lsw RW SPI data LSW 0x0000

Table 96 bull Upper 16 bits of SPI Data Field of ROM Table Entry (replication_count= 170)

Bit Name Access Description Default150 spi_dat_msw RW SPI data MSW 0x0000

Table 97 bull ROM Table StartEnd Addresses of Tx 10G Setting Routine

Bit Name Access Description Default158 adr_tx10g_start RW Starting ROM address of Tx 10G routine 0x00

70 adr_tx10g_end RW Ending ROM address of Tx 10G routine 0x00

Table 98 bull ROM Table StartEnd Addresses of Rx 10G Setting Routine

Bit Name Access Description Default158 adr_rx10g_start RW Starting ROM address of Rx 10G routine 0x00

Registers

21303 ROM Table StartEnd Addresses of Tx 1G Setting RoutineShort Nameadr_tx1g

Address0xB602

Address0xB603

21305 ROM Table StartEnd Addresses of WAN Setting RoutineShort Nameadr_wan

Address0xB604

2131 ROM Engine StatusShort NameROMENG_STATUS

70 adr_rx10g_end RW Ending ROM address of Rx 10G routine 0x00

Table 101 bull ROM Table StartEnd Addresses of WAN Setting Routine

Bit Name Access Description Default158 adr_wan_start RW Starting ROM address of WAN routine 0x00

70 adr_wan_end RW Ending ROM address of WAN routine 0x00

Table 98 bull ROM Table StartEnd Addresses of Rx 10G Setting Routine (continued)

Registers

Address0xB6FF

2132 SYNC_CTRL Configuration and Status Configuration and status registers for SYNC_CTRL-related digital logic

21321 SYNC_CTRL ConfigurationShort NameSYNC_CTRL_CFG

Address0xB700

Table 102 bull ROM Engine Status

Bit Name Access Description Default51 exe_last RO ROM engine last routine executed

00000 10Gmdashconfigured for 10G mode00001 TX10GmdashTx configured for 10G mode00010 RX10GmdashRx configured for 10G mode00011 1Gmdashconfigured for 1G mode00100 TX1GmdashRx configured for 1G mode00101 RX1GmdashRx configured for 1G mode00110 3Gmdashconfigured for 3G mode00111 TX3GmdashRx configured for 3G mode01000 RX3GmdashRx configured for 3G mode01001 WANmdashconfigured for WAN mode01010 RSTmdashconfigured to reset condition01011 LBONmdashconfigured for loopback enabled01100 LBOFFmdashconfigured for loopback disabled01101 LPONmdashlow power mode enabled01110 LPOFFmdashlow power mode disabled01111 RCmdashRCOMP routine10000 LRONmdashLock2Ref enabled10001 LROFFmdashLock2Ref disabledOthers invalid

0x00

0 exe_done RO ROM engine statusThis is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 ROM engine has not executed a new routine since the last time this bit was read1 ROM engine has executed a new routine since the last time this bit was read

0x0

Table 103 bull SYNC_CTRL Configuration

Bit Name Access Description Default4 CLR_SYNC_STAT RW Clear SYNC_CTRL status register

0 Idle1 Clear

0x0

Registers

21322 SYNC_CTRL Status Short NameSYNC_CTRL_STAT

Address0xB701

10 LANE_SYNC_SRC RW Source selection for lane synchronization0 Select DES_01 Select DES_12 Select F to Delta F3 Synchronization disabled

0x3

Table 104 bull SYNC_CTRL Status

Bit Name Access Description Default0 LANE_SYNC_FIFO_OF RO Lane synchronization FIFO overflow

0 FIFO normal1 FIFO overflow

0x0

Table 103 bull SYNC_CTRL Configuration (continued)

Registers

22 KR Channel (Device 0x1)Table 105 bull KR Channel (Device 0x1)

Address Short Description Register Name Details0x96 KR PMD Control KR_1x0096 Page 53

0x97 KR PMD Status KR_1x0097 Page 53

0x98 KR LP Coefficient Update KR_1x0098 Page 54

0x99 KR LP Status Report KR_1x0099 Page 54

0x9A KR LD Coefficient Update KR_1x009A Page 54

0x9B KR LD Status Report KR_1x009B Page 54

0x8200 VS Training Configuration 0 tr_cfg0 Page 54

0x8208 VS Training Configuration8 tr_cfg8 Page 57

0x820A VS Training Gain Target and Margin Values tr_gain Page 58

0x820B VS Training Coefficient Update Override tr_coef_ovrd Page 58

0x820C VS Training Status Report Override tr_stat_ovrd Page 58

0x820D VS Training Override tr_ovrd Page 58

0x820E VS Training State Step tr_step Page 59

0x820F VS Training Method tr_mthd Page 59

0x8210 VS Training BER Threshold Settings tr_ber_thr Page 59

0x8211 VS Training BER Offset Setting tr_ber_ofs Page 60

0x8212 VS Training LUT Selection tr_lutsel Page 60

0x8213 VS Training break_mask LSW brkmask_lsw Page 60

0x8214 VS Training break_mask MSW tr_brkmask_msw Page 61

0x8220 VS Training ROM Address for Gain romadr1 Page 61

0x8221 VS Training ROM Address for DFE romadr2 Page 61

0x8222 VS Training ROM Address for BER romadr3 Page 61

0x8223 VS Training ROM Address for Post Routine romadr4 Page 62

0x8230 VS Training ROM Address for OBCFG obcfg_addr Page 62

0x8240 VS Training apc_timer apc_tmr Page 62

0x8241 VS Training wait_timer wt_tmr Page 62

0x8242 VS Training maxwait_timer LSW mw_tmr_lsw Page 63

0x8243 VS Training maxwait_timer MSW mw_tmr_msw Page 63

Registers

221 KR PMD ControlShort NameKR_1x0096

Address0x96

222 KR PMD StatusShort NameKR_1x0097

Address0x97

0x8250 VS Training Status 1 tr_sts1 Page 63

0x8254 VS Tap CM Value tr_cmval Page 64

0x8255 VS Tap C0 Value tr_c0val Page 64

0x8256 VS Tap CP value tr_cpval Page 64

0x8260 VS Training frames_sent LSW frsent_lsw Page 64

0x8261 VS Training frames_sent MSW frsent_msw Page 65

0x8270 VS Training lut_read LSW lut_lsw Page 65

0x8271 VS Training lut_read MSW lut_msw Page 65

0x8272 VS Training PRBS11 error_count tr_errcnt Page 65

Table 106 bull KR PMD Control

Bit Name Access Description Default1 tr_enable RW Training enable

1 Enable KR start-up protocol 0 Disable KR start-up protocol

0x0

0 tr_restart RW Restart training (SC)1 Reset KR start-up protocol 0 Normal operation

0x0

Table 107 bull KR PMD Status

Bit Name Access Description Default3 tr_fail RO Training failure

1 Training failure has been detected 0 Training failure has not been detected

0x0

2 stprot RO Startup protocol status1 Start-up protocol in progress 0 Start-up protocol complete

0x0

1 frlock RO Frame lock1 Training frame delineation detected 0 Training frame delineation not detected

0x0

Table 105 bull KR Channel (Device 0x1) (continued)

Registers

223 KR LP Coefficient UpdateShort NameKR_1x0098

Address0x98

224 KR LP Status ReportShort NameKR_1x0099

Address0x99

225 KR LD Coefficient UpdateShort NameKR_1x009A

Address0x9A

226 KR LD Status ReportShort NameKR_1x009B

Address0x9B

227 VS Training Configuration 0Short Nametr_cfg0

0 rcvr_rdy RO Receiver status1 Receiver trained and ready to receive data 0 Receiver training

0x0

Table 108 bull KR LP Coefficient Update

Bit Name Access Description Default150 lpcoef RO Received coefficient update field

Table 109 bull KR LP Status Report

Bit Name Access Description Default150 lpstat RO Received status report field

Table 110 bull KR LD Coefficient Update

Bit Name Access Description Default150 ldcoef RO Transmitted coefficient update field

Table 111 bull KR LD Status Report

Bit Name Access Description Default150 ldstat RO Transmitted status report field

Table 107 bull KR PMD Status (continued)

Registers

Address0x8200

Address0x8201

Table 112 bull VS Training Configuration 0

Bit Name Access Description Default1512 tmr_dvdr RW Clock divider value for timer clocks 0x4

11 apc_drct_en RW Use directly connected APC signals 0x0

10 rx_inv RW Invert received PRBS11 within training frame 0x0

9 tx_inv RW Invert transmitted PRBS11 within training frame 0x0

4 ld_pre_init RW Set local taps starting point 0 Set to INITIALIZE 1 Set to PRESET

0x1

3 lp_pre_init RW Send first LP request 0 Send INITIALIZE 1 Send PRESET

0x1

2 nosum RW Update taps regardless of v2vp sum 0x0

1 part_cfg_en RW Enable partial OB tap configuration 0x1

0 tapctl_en RW Allow LP to control tap settings 0x1

Bit Name Access Description Default80 tmr_hold RW Freeze timers Bit set

0 Wait 1 max_wait 2 1G 3 3G 4 10G 5 pgdet 6 link_fail 7 an_wait 8 break_link

0x000

Registers

Address0x8202

Address0x8203

Address0x8204

Address0x8205

Bit Name Access Description Default116 vp_max RW Maximum settings for vp sum 0x1F

50 v2_min RW Minimum settings for v2 sum 0x01

Bit Name Access Description Default116 cp_max RW Maximum settings for local transmitter 0x00

50 cp_min RW Minimum settings for local transmitter 0x34

Bit Name Access Description Default116 c0_max RW Maximum settings for local transmitter 0x1F

50 c0_min RW Minimum settings for local transmitter 0x11

Bit Name Access Description Default116 cm_max RW Maximum settings for local transmitter 0x00

50 cm_min RW Minimum settings for local transmitter 0x3A

Registers

Address0x8206

Address0x8207

Address0x8208

Address0x8209

Bit Name Access Description Default116 cp_init RW Initial settings for local transmitter 0x38

50 c0_init RW Initial settings for local transmitter 0x14

Bit Name Access Description Default116 cm_init RW Initial settings for local transmitter 0x3E

50 dfe_ofs RW Signed value to adjust final LP C(+1) tap position from calculated optimal setting

0x00

Bit Name Access Description Default76 wt1 RW Weighted average calculation of DFE tap 1 0x1

54 wt2 RW Weighted average calculation of DFE tap 2 0x1

Bit Name Access Description Default150 frcnt_ber RW Number of training frames used for BER

calculation0x0014

Registers

2217 VS Training Gain Target and Margin ValuesShort Nametr_gain

Address0x820A

2218 VS Training Coefficient Update OverrideShort Nametr_coef_ovrd

Address0x820B

2219 VS Training Status Report OverrideShort Nametr_stat_ovrd

Address0x820C

2220 VS Training OverrideShort Nametr_ovrd

Address0x820D

Table 122 bull VS Training Gain Target and Margin Values

Bit Name Access Description Default1510 gain_marg RW LP C(0) optimized when GAIN is gain_targ

plusmn2gain_marg0x28

90 gain_targ RW Target value of GAIN setting during LP C(0) optimization

0x000

Table 123 bull VS Training Coefficient Update Override

Bit Name Access Description Default150 coef_ovrd RW Override Coef_update field to transmit 0x0000

Table 124 bull VS Training Status Report Override

Bit Name Access Description Default150 stat_ovrd RW Override Stat_report field to transmit 0x0000

Table 125 bull VS Training Override

Bit Name Access Description Default4 ovrd_en RW Enable manual training 0x0

3 rxtrained_ovrd RW Control of rx_trained variable for training SM 0x0

2 ber_en_ovrd RW Generate BER enable pulse (SC) 0x0

1 coef_ovrd_vld RW Generate Coef_update_valid pulse (SC) 0x0

Registers

2221 VS Training State StepShort Nametr_step

Address0x820E

2222 VS Training MethodShort Nametr_mthd

Address0x820F

2223 VS Training BER Threshold SettingsShort Nametr_ber_thr

0 stat_ovrd_vld RW Generate Stat_report_valid pulse (SC) 0x0

Table 126 bull VS Training State Step

Bit Name Access Description Default0 step RW Step to next lptrain state (if at breakpoint) (SC) 0x0

Table 127 bull VS Training Method

Bit Name Access Description Default1110 mthd_cp RW Training method for remote C(+1)

0 BER method1 Gain method2 DFE method

0x2

98 mthd_c0 RW Training method for remote C(0) 0x1

76 mthd_cm RW Training method for remote C(-1) 0x0

54 ord1 RW Remote tap to optimize first0 C(-1)1 C(0)2 C(+1)

0x1

32 ord2 RW Remote tap to optimize second 0x2

10 ord3 RW Remote tap to optimize third 0x0

Table 125 bull VS Training Override (continued)

Registers

Address0x8210

2224 VS Training BER Offset SettingShort Nametr_ber_ofs

Address0x8211

2225 VS Training LUT SelectionShort Nametr_lutsel

Address0x8212

2226 KR Training Breakpoints22261 VS Training break_mask LSW

Short Namebrkmask_lsw

Table 128 bull VS Training BER Threshold Settings

Bit Name Access Description Default158 ber_err_th RW Only consider error count gt ber_err_th 0x00

70 ber_wid_th RW Only consider errored range gt ber_wid_th 0x00

Table 129 bull VS Training BER Offset Setting

Bit Name Access Description Default50 ber_ofs RW Signed value to adjust final tap position from

calculated optimal setting0x00

Table 130 bull VS Training LUT Selection

Bit Name Access Description Default83 lut_row RW Selects LUT table entry (0 to 63) 0x00

20 lut_sel RW Selects LUT for lut_o0 Gain 1 DFE_12 DFE_23 DFE_avg_1 4 DFE_avg_2 5 BER_16 BER_27 BER_3

0x0

Registers

Address0x8213

22262 VS Training break_mask MSWShort Nametr_brkmask_msw

Address0x8214

2227 KR Training ROM Address22271 VS Training ROM Address for Gain

Short Nameromadr1

Address0x8220

22272 VS Training ROM Address for DFEShort Nameromadr2

Address0x8221

22273 VS Training ROM Address for BERShort Nameromadr3

Table 131 bull VS Training break_mask LSW

Bit Name Access Description Default150 brkmask_lsw RW Select lptrain state machine breakpoints Each

bit corresponds to a state (see design doc)0x0000

Table 132 bull VS Training break_mask MSW

Bit Name Access Description Default150 brkmask_msw RW Select lptrain state machine breakpoints Each

Table 133 bull VS Training ROM Address for Gain

Bit Name Access Description Default137 romadr_gain1 RW ROM starting address of initial gain routine 0x00

60 romadr_gain2 RW ROM starting address of iterative gain routine 0x01

Table 134 bull VS Training ROM Address for DFE

Bit Name Access Description Default137 romadr_dfe1 RW ROM starting address of initial DFE routine 0x00

60 romadr_dfe2 RW ROM starting address of iterative DFE routine 0x02

Registers

Address0x8222

22274 VS Training ROM Address for Post RoutineShort Nameromadr4

Address0x8223

22275 VS Training ROM Address for OBCFGShort Nameobcfg_addr

Address0x8230

2228 VS Training apc_timerShort Nameapc_tmr

Address0x8240

2229 VS Training wait_timerShort Namewt_tmr

Address0x8241

Table 135 bull VS Training ROM Address for BER

Bit Name Access Description Default137 romadr_ber1 RW ROM starting address of initial BER routine 0x00

60 romadr_ber2 RW ROM starting address of iterative BER routine 0x00

Table 136 bull VS Training ROM Address for Post Routine

Bit Name Access Description Default60 romadr_end RW ROM starting address of post-training routine 0x00

Table 137 bull VS Training ROM Address for OBCFG

Bit Name Access Description Default60 obcfg_addr RW Address of OB tap configuration settings 0x00

Table 138 bull VS Training apc_timer

Bit Name Access Description Default150 apc_tmr RW Delay between LP tap update and capture of

direct-connect APC values0x0000

Table 139 bull VS Training wait_timer

Bit Name Access Description Default150 wt_tmr RW wait_timer for training state machine to allow

extra training frames to be exchanged0x0A08

Registers

2230 KR Training Maximum Wait Timer22301 VS Training maxwait_timer LSW

Short Namemw_tmr_lsw

Address0x8242

22302 VS Training maxwait_timer MSWShort Namemw_tmr_msw

Address0x8243

2231 VS Training Status 1Short Nametr_sts1

Address0x8250

Table 140 bull VS Training maxwait_timer LSW

Bit Name Access Description Default150 mw_tmr_lsw RW maxwait_timer when training expires and failure

declared 500 ms0xA30A

Table 141 bull VS Training maxwait_timer MSW

Bit Name Access Description Default150 mw_tmr_msw RW maxwait_timer when training expires and failure

declared 500 ms0x0133

Table 142 bull VS Training Status 1

Bit Name Access Description Default12 ber_busy RO Indicates PRBS11 checker is active

119 tr_sm RO Training state machine

84 lptrain_sm RO LP training state machine

3 gain_fail RO Indicates gain_target was not reached during LP training

2 training RO Training variable from training state machine

1 dme_viol RO Indicates a DME violation has occurred (LH)

0 tr_done RO Indicates that local and remote training has completed

Registers

Address0x8251

2233 KR Tap Values22331 VS Tap CM Value

Short Nametr_cmval

Address0x8254

22332 VS Tap C0 ValueShort Nametr_c0val

Address0x8255

22333 VS Tap CP ValueShort Nametr_cpval

Address0x8256

2234 KR Training Frame Counter22341 VS Training frames_sent LSW

Short Namefrsent_lsw

Bit Name Access Description Default2 cp_range_err RO CP range error (LH)

1 c0_range_err RO C0 range error (LH)

0 cm_range_err RO CM range error (LH)

Table 144 bull VS Tap CM Value

Bit Name Access Description Default60 cm_val RO CM value 0x00

Table 145 bull VS Tap C0 Value

Bit Name Access Description Default60 c0_val RO C0 value 0x00

Table 146 bull VS Tap CP Value

Bit Name Access Description Default60 cp_val RO CP value 0x00

Registers

Address0x8260

22342 VS Training frames_sent MSWShort Namefrsent_msw

Address0x8261

2235 KR Training LUT Counter22351 VS Training lut_read LSW

Short Namelut_lsw

Address0x8270

22352 VS Training lut_read MSWShort Namelut_msw

Address0x8271

2236 KR Training PBRS11 error_countShort Nametr_errcnt

Address0x8272

Table 147 bull VS Training frames_sent LSW

Bit Name Access Description Default150 frsent_lsw RO Number of training frames sent to complete

training

Table 148 bull VS Training frames_sent MSW

Bit Name Access Description Default150 frsent_msw RO Number of training frames sent to complete

training

Table 149 bull VS Training lut_read LSW

Bit Name Access Description Default150 lut_lsw RO Measured value of selected LUT 0x0000

Table 150 bull VS Training lut_read MSW

Bit Name Access Description Default150 lut_msw RO Measured value of selected LUT 0x0000

Table 151 bull VS Training PRBS11 error_count

Bit Name Access Description Default150 errcnt RO Bit error count of PRBS11 checker 0x0000

Registers

23 SFP TWS Channel (Device 0x1)

231 I2C Write ControlShort NameI2C_WRITE_CTRL

Address0xC002

232 I2C Bus StatusShort NameI2C_BUS_STATUS

Address0xC003

233 I2C Read AddressShort NameI2C_READ_ADDR

Table 152 bull SFP TWS Channel (Device 0x1)

Address Short Description Register Name Details0xC002 I2C Write Control I2C_WRITE_CTRL Page 66

0xC003 I2C Bus Status I2C_BUS_STATUS Page 66

0xC004 I2C Read Address I2C_READ_ADDR Page 66

0xC005 I2C Read Status and Data I2C_READ_STATUS_DATA Page 67

0xC006 I2C Reset Sequence I2C_RESET_SEQ Page 67

Table 153 bull I2C Write Control

Bit Name Access Description Default158 WRITE_DATA RW I2C write data A write to I2C_WRITE_CTRL

register will trigger I2C master to write the value in WRITE_DATA register to address specified in WRITE_ADDR register of slave ID specified in SLAVE_ID register

0x00

70 WRITE_ADDR RW I2C write address A write to I2C_WRITE_CTRL register will trigger I2C master to write the value in WRITE_DATA register to address specified in WRITE_ADDR register of slave ID specified in SLAVE_ID register

0x00

Table 154 bull I2C Bus Status

Bit Name Access Description Default1 I2C_WRITE_ACK RO I2C write acknowledge

0 Idle1 Write acknowledge

0x0

0 I2C_BUS_BUSY RO I2C bus busy0 I2C bus is not busy1 I2C bus is busy

0x0

Registers

Address0xC004

234 I2C Read Status and DataShort NameI2C_READ_STATUS_DATA

Address0xC005

235 I2C Reset SequenceShort NameI2C_RESET_SEQ

Address0xC006

Table 155 bull I2C Read Address

Bit Name Access Description Default70 READ_ADDR RW I2C read address A write to READ_ADDR

register will trigger I2C master to read the value from the address specified in READ_ADDR register of slave ID specified in SLAVE_ID register and stores the value at READ_DATA register

0x00

Table 156 bull I2C Read Status and Data

Bit Name Access Description Default15 I2C_BUS_BUSY RO I2C bus busy

0 I2C bus is not busy data updated1 I2C bus is busy data not updated

0x0

70 READ_DATA RO I2C read data A write to READ_ADDR register will trigger I2C master to read the value from the address specified in READ_ADDR register of slave ID specified in SLAVE_ID register and stores the value at READ_DATA register

0x00

Table 157 bull I2C Reset Sequence

Bit Name Access Description Default0 RESET_SEQ RW I2C reset sequence A write to RESET_SEQ

register (any value) will trigger I2C master to issue a reset sequence

0x0

Registers

24 PMA 32-Bit Channel (Device 0x1)Table 158 bull PMA 32-Bit Channel (Device 0x1)

Address Short Description Register Name Details0xF000 APC Top Control Configuration APC_TOP_CTRL_CFG Page 70

0xF001 APC Common Configuration Register 0 APC_COMMON_CFG0 Page 70

0xF002 APC Parameter Control Synchronization APC_PARCTRL_SYNC_CFG Page 73

0xF003 APC Parameter Control FSM1 Timer Configuration APC_PARCTRL_FSM1_TIMER_CFG Page 74

0xF005 APC FLEXCTRL Read Counter APC_FLEXCTRL_CNT_STATUS Page 75

0xF006 APC Level Detect Calibration Configuration APC_LD_CAL_CFG Page 75

0xF007 APC Sampling Stage Calibration Configuration Register 0

APC_IS_CAL_CFG0 Page 76

0xF009 APC EQZ Common CTRL Configuration APC_EQZ_COMMON_CFG Page 78

0xF00A APC EQZ CTRL Configuration APC_EQZ_GAIN_CTRL_CFG Page 79

0xF00B APC EQZ ADJ CTRL Configuration APC_EQZ_GAIN_ADJ_CTRL_CFG Page 79

0xF00C APC EQZ CTRL Status APC_EQZ_CTRL_STATUS Page 80

0xF00D APC EQZ LD Control APC_EQZ_LD_CTRL Page 80

0xF00E APC EQZ LD CTRL Configuration Register 0 APC_EQZ_LD_CTRL_CFG0 Page 81

0xF00F APC EQZ LD CTRL Configuration Register 1 APC_EQZ_LD_CTRL_CFG1 Page 81

0xF010 APC EQZ Pattern Matching Configuration Register 0 APC_EQZ_PAT_MATCH_CFG0 Page 82

0xF012 APC EQZ_OFFS Control APC_EQZ_OFFS_CTRL Page 83

0xF013 APC EQZ_OFFS Timer Configuration APC_EQZ_OFFS_TIMER_CFG Page 84

0xF014 APC EQZ_OFFS Parameter Control APC_EQZ_OFFS_PAR_CFG Page 84

0xF015 APC EQZ_C Control APC_EQZ_C_CTRL Page 85

0xF016 APC EQZ_C Timer Configuration APC_EQZ_C_TIMER_CFG Page 86

0xF017 APC EQZ_C Parameter Control APC_EQZ_C_PAR_CFG Page 87

0xF018 APC EQZ_L Control APC_EQZ_L_CTRL Page 87

0xF019 APC EQZ_L Timer Configuration APC_EQZ_L_TIMER_CFG Page 89

0xF01A APC EQZ_L Parameter Control APC_EQZ_L_PAR_CFG Page 89

0xF01B APC EQZ_AGC Control APC_EQZ_AGC_CTRL Page 90

0xF01C APC EQZ_AGC Timer Configuration APC_EQZ_AGC_TIMER_CFG Page 91

0xF01D APC EQZ_AGC Parameter Control APC_EQZ_AGC_PAR_CFG Page 91

0xF01E APC DFE1 Control APC_DFE1_CTRL Page 92

0xF01F APC DFE1 Timer Configuration APC_DFE1_TIMER_CFG Page 93

0xF020 APC DFE1 Parameter Control APC_DFE1_PAR_CFG Page 93

0xF021 APC DFE2 Control APC_DFE2_CTRL Page 94

0xF022 APC DFE2 Timer Configuration APC_DFE2_TIMER_CFG Page 95

Registers

0xF02A APC LC Softcontrol Configuration Register 0 APC_LC_SOFTCTRL_CFG Page 101

0xF02B APC LC Softcontrol Configuration Register 1 APC_LC_SOFTCTRL_CFG1 Page 102

0xF100 SD10G65 DES Configuration Register 0 SD10G65_DES_CFG0 Page 103

0xF101 SD10G65 MOEBDIV Configuration Register 0 SD10G65_MOEBDIV_CFG0 Page 103

0xF110 SD10G65 OB Configuration Register 0 SD10G65_OB_CFG0 Page 104

0xF113 SD10G65 OB Configuration Register 3 Access to Receiver Detect Functionality

SD10G65_OB_CFG3 Page 106

0xF120 SD10G65 IB Configuration Register 0 SD10G65_IB_CFG0 Page 107

0xF129 SD10G65 IB Configuration Register 9 Automatically Adapted DFE Coefficients

SD10G65_IB_CFG9 Page 118

0xF12A SD10G65 IB Configuration Register 10 JTAG-Related Settings

0xF12B SD10G65 IB Configuration Register 11 JTAG-Related Settings

0xF12C SD10G65 SBUS Rx CFG Service Bus-Related Settings

SD10G65_SBUS_RX_CFG Page 120

0xF130 SD10G65 RX RCPLL Configuration Register 0 SD10G65_RX_RCPLL_CFG0 Page 121

0xF133 SD10G65 RX RCPLL Status Register 0 SD10G65_RX_RCPLL_STAT0 Page 123

0xF140 SD10G65 RX Synthesizer Configuration Register 0 SD10G65_RX_SYNTH_CFG0 Page 123

Table 158 bull PMA 32-Bit Channel (Device 0x1) (continued)

Registers

241 SD10G65 APC Configuration and Status2411 APC Top Control Configuration

Short NameAPC_TOP_CTRL_CFG

Address0xF000

2412 APC Common Configuration Register 0Short NameAPC_COMMON_CFG0

0xF145 SD10G65 RX Synthesizer Register CDR Loopfilter Control

SD10G65_RX_SYNTH_CDRLF Page 126

0xF146 SD10G65 RX Synthesizer Register 0 for Qualifier Access

SD10G65_RX_SYNTH_QUALIFIER0 Page 126

0xF148 SD10G65 RX Synthesizer Register for Sync Control Data

SD10G65_RX_SYNTH_SYNC_CTRL Page 127

0xF149 F2DF ConfigurationStatus F2DF_CFG_STAT Page 127

0xF150 SD10G65 Tx Synthesizer Configuration Register 0 SD10G65_TX_SYNTH_CFG0 Page 128

0xF154 SD10G65 SSC Generator Configuration Register 0 SD10G65_SSC_CFG0 Page 130

0xF160 SD10G65 Tx RCPLL Configuration Register 0 SD10G65_TX_RCPLL_CFG0 Page 131

0xF163 SD10G65 Tx RCPLL Status Register 0 SD10G65_TX_RCPLL_STAT0 Page 132

Table 159 bull APC Top Control Configuration

Bit Name Access Description Default3124 PWR_UP_TIME RW Delay time required to power up auxiliary

channels0x0F

2316 PWR_DN_TIME RW Delay time required to power down auxiliary channels

0x05

150 SLEEP_TIME RW APC top-control sleep-time (power-down) Given in number of clock cycles (typically 25 5 ns)

0xC350

Registers

Address0xF001

Note For HML error correction logic HML= 000001011111 are considered valid 010 and 101 are considered correctable (010 correctable to 011 101 correctable to 001) and 100 and 110 are considered uncorrectable

Table 160 bull APC Common Configuration Register 0

Bit Name Access Description Default31 HML_CLR_CNT RW Clear HML sampling error counter

1 Clear counter0x0

30 HML_ERRCORR_MODE RW HML sampling error correction mode Correctable sampling errors can be automatically corrected0 Disable auto-correction1 Enable auto-correction

0x1

29 HML_ERRCORR_ENA RW HML sampling error correction enable Invalid samples are not used for parameter control (smart sampling)0 Disable smart sampling1 Enable smart sampling

0x0

28 HML_SWAP_HL RW HL swapping in HML sampling error correction logic0 No HL swapping1 HL swapped

0x1

2726 APC_FSM_RECOVER_MODE RW Top-ctrl FSM recovery behavior0 No auto-recovery1 Auto-restart on missing input signal after Restart-Delay-Timer has expired2 Auto-restart on missing input signal

0x0

25 SIG_DET_VALID_CFG RW Signal detect valid configuration (OffsAGCLCDFE)0 Signal_detect input directly used1 Signal_detect input gated with gain_ctrl ramp-up done (EQZ_GAIN_CTRL_DONE)

0x0

2420 SIG_LOST_DELAY_TIME RW Signal lost delay timer configuration used for APC recovery The signal lost delay time specifies the time when a missing input signal is considered a lost input signal on sig_det= 0 The delay time is T= (2^sig_lost_delay_time) T_rx_clk_per

0x14

Registers

1916 TOP_CTRL_STATE RO Current state of APC top control state machine0 Off1 Power-up2 Power-down3 Manual mode4 Calibrate IS5 Calibrate LD6 Not used7 Gain-control ramp-up8 Mission mode (FSM1 controlled)9 Mission mode (FSM2 controlled)10ndash12 Debug states13 Snooze14ndash15 Not used

0x0

1512 BLOCK_READ_SEL RW Select flexctrl block in order to read internal counters Counter values readable from APC_FLEXCTRL_CNT_STATUS0 Offset-ctrl1 L-ctrl2 C-ctrl3 AGC-ctrl4 DFE1-ctrl5 DFE2-ctrl6 DFE3-ctrl7 DFE4-ctrl8 SAM_Offset-cal9 Level-cal10 HML sampling errors

0x0

11 RESET_APC RW Reset APC core logic (configuration registers are not reset)1 Reset APC0 Normal operation (mission mode)

0x0

10 FREEZE_APC RW Freeze current state0 Normal operation1 Freeze APC

0x0

86 IF_WIDTH RW Interface bit-width0 8-bit1 10-bit2 16-bit3 20-bit4 32-bit5 40-bit

0x4

5 RESERVED RW Must be set to its default 0x1

Table 160 bull APC Common Configuration Register 0 (continued)

Registers

2413 APC Parameter Control Synchronization Short NameAPC_PARCTRL_SYNC_CFG

Address0xF002

Configuration register for common flexible parameter control FSMs

4 THROTTLE_MODE RW APC throttling mode0 DisableNo power reduction (continuous operation)1 EnablePower reduced operation (pulsed operation)

0x0

3 APC_DIRECT_ENA RW Enable APC direct connections instead of local IB configuration registers

0x0

20 APC_MODE RW APC operation mode0 Off1 Manual mode2 Perform calibration and run FSM13 Perform calibration and run FSM24 Perform calibration and run FSM1 and FSM2 in ping-pong operation5 Perform calibration and then enter manual mode

0x0

Table 161 bull APC Parameter Control Synchronization

Bit Name Access Description Default3128 RESERVED RW Must be set to its default 0x3

15 FSM2_CTRL_MODE RW Parameter control mode for FSM20 Discrete1 Continuous

0x1

1311 FSM2_RECOVER_MODE RW FSM2 recovery behavior0 No auto-recovery1 Freeze FSM2 on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze FSM2 on weak signal and restart on missing input signal3 Freeze FSM2 on missing input signal4 Freeze FSM2 on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart FSM2 on missing input signal6-7 Reserved

0x0

Registers

2414 APC Parameter Control FSM1 Timer ConfigurationShort NameAPC_PARCTRL_FSM1_TIMER_CFG

Address0xF003

108 FSM1_RECOVER_MODE RW FSM1 recovery behavior0 No auto-recovery1 Freeze FSM1 on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze FSM1 on weak signal and restart on missing input signal3 Freeze FSM1 on missing input signal4 Freeze FSM1 on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart FSM1 on missing input signal6ndash7 Reserved

0x0

7 FSM2_CTRL_DONE RO Parameter control state of FSM2 in one-time mode1 Finished

0x0

6 FSM2_START_CTRL RW Start operation of FSM2 (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

54 FSM2_OP_MODE RW Operation mode of FSM20 Off1 One-time2 Non-stop3 Paused

0x0

Table 161 bull APC Parameter Control Synchronization (continued)

Registers

Timing configuration register for common flexible parameter control FSM1

Address0xF004

2416 APC FLEXCTRL Read CounterShort NameAPC_FLEXCTRL_CNT_STATUS

Address0xF005

Observation register for multiple counters The selection is done through APC_COMMON_CFGBLOCK_READ_SEL (select flexctrl block to be read) and APC_XXX_CTRLXXX_READ_CNT_SEL (counter within flexctrl block XXX) or APC_COMMON_CFGOFFSCAL_READ_CNT_SEL

Note The EQZ and DFE counters hit_cnt and err_cnt only make sense in DISCRETE control mode

2417 APC Level Detect Calibration ConfigurationShort NameAPC_LD_CAL_CFG

Table 162 bull APC Parameter Control FSM1 Timer Configuration

Bit Name Access Description Default3116 FSM1_PS_TIME RW FSM1 pause time (in number of rx_clk cycles) 0x0064

150 FSM1_OP_TIME RW FSM1 operation time (in number of rx_clk cycles) 0x03E8

Table 164 bull APC FLEXCTRL Read Counter

Bit Name Access Description Default310 APC_CTRL_CNTVAL RO Current counter value 0x00000000

Registers

Address0xF006

2418 APC Sampling Stage Calibration Configuration Register 0Short NameAPC_IS_CAL_CFG0

Address0xF007

Table 165 bull APC Level Detect Calibration Configuration

Bit Name Access Description Default3028 CAL_CLK_DIV RW Calibration clock divider Clock used in

calibration blocks is divided by 2^(2CAL_CLK_DIV)0 No clock division1 Clock is divided by 42 Clock is divided by 167 Clock is divided by 16384

0x3

19 DETLEV_CAL_DONE RO Detect level calibration state1 Finished

0x0

12 SKIP_SDET_CAL RW Skip signal detect calibration 0x0

11 SKIP_LD_CAL RW Skip level detect calibration 0x0

105 IE_SDET_LEVEL RW Level for IE signal detect (when controlled by APC)0 20 mV

0x02

41 DETLVL_TIMER RW Timer for calibration process14 Use for 400 MHz rx_clk

0xE

0 START_DETLVL_CAL RW Start signal and level detect calibration process (sampling stage only in manual mode see apc_mode)

0x0

Table 166 bull APC Sampling Stage Calibration Configuration Register 0

Bit Name Access Description Default2520 IB_DFE_GAIN_ADJ RW Gain adjustment for DFE amplifier 0x24

1914 CPMD_THRES_INIT RW Initial value for CPMD FF threshold calibration 0x00

138 VSC_THRES_INIT RW Initial value for VScope FF threshold calibration 0x00

7 SKIP_OBSERVE_INIT RW Skip observe block initialization 0x0

6 SKIP_OFFSET_INIT RW Skip sample FF offset initialization 0x0

Registers

Address0xF008

5 SKIP_THRESHOLD_INIT RW Skip sample FF threshold initialization 0x1

4 SKIP_DFE_BUFFER_INIT RW Skip DFE buffer 0db initialization 0x0

3 SKIP_OBSERVE_CAL RW Skip observe block calibration 0x0

2 SKIP_OFFSET_CAL RW Skip sample FF offset calibration 0x0

1 SKIP_THRESHOLD_CAL RW Skip sample FF threshold calibration 0x1

0 SKIP_DFE_BUFFER_CAL RW Skip DFE buffer 0db calibration 0x0

Bit Name Access Description Default3124 EQZ_AGC_DAC_VAL RW AGC-DAC value used for DFE 0dB calibration

during IB-calibration process0x58

23 USE_AGC_DAC_VAL RW Enable use of EQZ_AGC_DAC_VAL instead of EQZ_AGC_INI during DFE 0dB IB calibration

0x0

1916 CAL_NUM_ITERATIONS RW Controls number of calibrations iterations to settle values that depend on each other (offset vs threshold) Coding number of iterations= cal_num_iterations + 1

0x1

139 PAR_DATA_NUM_ONES_THRES RW Selects the number of ones threshold when using parallel data Value for rising ramp from zero to one The value for the falling ramp (one -gt zero) is half the interface width minus par_data_num_ones_thres

0x08

8 PAR_DATA_SEL RW Controls whether the parallel data from the deserializer or the signal from the observe multiplexer in the sample stage is used 0 Observe multiplexer1 Parallel data

0x1

73 OFFSCAL_READ_CNT_SEL RW Select offset calibration result to be read (BLOCK_READ_SEL= 8 required)

0x00

Table 166 bull APC Sampling Stage Calibration Configuration Register 0 (continued)

Registers

24110 APC EQZ Common CTRL ConfigurationShort NameAPC_EQZ_COMMON_CFG

Address0xF009

Configuration register for gain control logic

2 OFFSCAL_DIS_SWAP RW Swaps disp with disn used during calibration 0x0

1 OFFSCAL_DONE RO Offset calibration state1 finished

0x0

0 START_OFFSCAL RW Start offset calibration process (sampling stage only in manual mode see apc_mode)

0x0

Table 168 bull APC EQZ Common CTRL Configuration

Bit Name Access Description Default2213 EQZ_GAIN_FREEZE_THRES RW Gain freeze threshold used in APC recovery

mode for low input signals0x37A

1211 EQZ_GAIN_RECOVER_MODE RW Gain recovery behavior0 No auto-recovery1 Freeze gain on missing input signal and auto-restart after Restart-Delay-Timer has expired2 Auto-restart gain control on missing input signal3 Reserved

0x0

10 EQZ_GAIN_ADJ_HALT RW Stop update of gain_adj 0x0

9 EQZ_GAIN_CAL_MODE RW Gain calibration mode0 Use successive approximation to find required gain1 Use max gain and reduce linearly to find required gain

0x0

8 EQZ_GAIN_ADJ_START_UPDATE RW Start (initiate) gain_adj update process (on rising edge of cfg bit)

0x0

7 EQZ_GAIN_START_UPDATE RW Start (initiate) gain update process (on rising edge of cfg bit)

0x0

6 EQZ_GAIN_START_CTRL RW (Re-)start (initiate) main gaingain_adj calibration process (on rising edge of cfg bit)

0x0

Registers

24111 APC EQZ CTRL ConfigurationShort NameAPC_EQZ_GAIN_CTRL_CFG

Address0xF00A

Configuration register for gain

24112 APC EQZ ADJ CTRL ConfigurationShort NameAPC_EQZ_GAIN_ADJ_CTRL_CFG

Address0xF00B

Configuration register for gain_adj

54 EQZ_GAIN_OP_MODE RW Operation mode (only when EQZ_GAIN_STOP_CTRL= 1)0 Idle1 Calibrate and work2 Work

0x0

3 EQZ_GAIN_STOP_CTRL RW Stop main gain control machine immediately 0x0

2 EQZ_GAIN_AUTO_RESTART RW Restart gaingain_adj calibration automatically on rising edge of signal_detect

0x1

10 EQZ_GAIN_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use PAR_INI as fix valueinternal processing continues)2 Freeze (internal processing stopsparameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

Table 169 bull APC EQZ CTRL Configuration

Bit Name Access Description Default2920 EQZ_GAIN_MAX RW Maximum gain in normal operation (should be

not greater then 895 (512+3128-1)0x37F

1910 EQZ_GAIN_MIN RW Minimum gain in normal operation 0x000

90 EQZ_GAIN_INI RW Gain initial value (used if EQZ_GAIN_CHG_MODE= 1)

0x000

Table 170 bull APC EQZ ADJ CTRL Configuration

Bit Name Access Description Default2620 EQZ_GAIN_ADJ_MAX RW Maximum gain_adj in normal operation 0x7F

Table 168 bull APC EQZ Common CTRL Configuration (continued)

Registers

24113 APC EQZ CTRL StatusShort NameAPC_EQZ_CTRL_STATUS

Address0xF00C

Observation register for controlled settings

24114 APC EQZ LD ControlShort NameAPC_EQZ_LD_CTRL

Address0xF00D

Configuration register for level-detect (LD) control timing and behavior (timing number of rx_clk cycles used for LD toggling)

1610 EQZ_GAIN_ADJ_MIN RW Minimum gain_adj in normal operation 0x00

60 EQZ_GAIN_ADJ_INI RW Gain_adj initial value (used if EQZ_GAIN_CHG_MODE= 1)

0x00

Table 171 bull APC EQZ CTRL Status

Bit Name Access Description Default23 EQZ_GAIN_CTRL_DONE RO Status flag indicating main gaingain_adj ramp-

up process has finished0x0

2216 EQZ_GAIN_ADJ_ACTVAL RO Parameter value (controlledcomputed gain adjustment value)

0x00

156 EQZ_GAIN_ACTVAL RO Parameter value (controlledcomputed gain value)

0x000

50 LD_LEV_ACTVAL RO Parameter value (controlledcomputed level for level-detect logic)

0x00

Table 172 bull APC EQZ LD Control

Bit Name Access Description Default31 LD_EQ_TOGGLE RO Captured toggling of LD-EQ 0x0

30 LD_IB_TOGGLE RO Captured toggling of LD-IB 0x0

29 LD_CATCH_BYPASS RW Bypass LD catch circuitry (allows capturing pulses shorter then one rx_clk cycle)

0x1

2826 LD_WD_CNT_MAX RW Maximum value for LD updates in gain_adjust (watch-dog prevent endless loop of LD adjustment max is 2^value - 1)

0x3

Table 170 bull APC EQZ ADJ CTRL Configuration (continued)

Registers

24115 APC EQZ LD CTRL Configuration Register 0Short NameAPC_EQZ_LD_CTRL_CFG0

Address0xF00E

Configuration register 0 for level-detect (LD) controller timing (number of rx_clk cycles used for operation timing)

Note For small ld_t_ values it might be necessary to change IB configuration bit-group IB_LDSD_DIVSEL to higher values

Address0xF00F

Configuration register 1 for level-detect (LD) controller timing (number of rx_clk cycles used for calibration timing)

2522 LD_TOG_THRESHOLD RW Number of required toggles before toggling is considered valid

0x2

2114 LD_T_TOGGLE_DEADTIME RW Sensitivity deadtime between two toggles (value is multiplied by 2)

0x02

8 LD_LEV_UPDATE RW Update internal LD_lev value with LD_LEV_INI 0x0

7 LD_EQ_START_TOG_CHK RW Start (initiate) a LD-EQ toggle check (for present LD-level)

0x0

6 LD_IB_START_TOG_CHK RW Start (initiate) a LD-IB toggle check (for present LD-level)

0x0

50 LD_LEV_INI RW LD_lev initial value (used as preset value if EQZ_GAIN_CHG_MODE= 1)

0x28

Table 173 bull APC EQZ LD CTRL Configuration Register 0

Bit Name Access Description Default3116 LD_T_DEADTIME_WRK RW Minimum activity for LD in work mode (value is

multiplied by 8)0x0064

150 LD_T_TIMEOUT_WRK RW Activity timeout threshold for LD in work mode (value is multiplied by 8)

0x03E8

Table 172 bull APC EQZ LD Control (continued)

Registers

24117 APC EQZ Pattern Matching Configuration Register 0Short NameAPC_EQZ_PAT_MATCH_CFG0

Address0xF010

Pattern matching configuration register for eqz_c and eqz_l control

Address0xF011

Pattern matching configuration register for eqz_offs and eqz_agc control

Note If mask is set to 0 all bits are ldquomatchingrdquo and taken into account for parameter control

Bit Name Access Description Default3116 LD_T_DEADTIME_CAL RW Minimum activity for LD in calibration mode

(value is multiplied by 8)0x0064

150 LD_T_TIMEOUT_CAL RW Activity timeout threshold for LD in calibration mode (value is multiplied by 8)

0x03E8

Table 175 bull APC EQZ Pattern Matching Configuration Register 0

Bit Name Access Description Default3124 EQZ_C_PAT_MASK RW EQZ-C-control pattern mask (only those bits are

used for pattern matching whose mask bit is set)0x00

2316 EQZ_C_PAT_MATCH RW EQZ-C-control pattern used for pattern matching (corresponding mask bits must be set)

0x00

158 EQZ_L_PAT_MASK RW EQZ-L-control pattern mask (only those bits are used for pattern matching whose mask bit is set)

0x00

70 EQZ_L_PAT_MATCH RW EQZ-L-control pattern used for pattern matching (corresponding mask bits must be set)

0x00

Bit Name Access Description Default3124 EQZ_OFFS_PAT_MASK RW EQZ-offset-control pattern mask (only those bits

are used for pattern matching whose mask bit is set)

0x00

2316 EQZ_OFFS_PAT_MATCH RW EQZ-offset-control pattern used for pattern matching (corresponding mask bits must be set)

0x00

Registers

24119 APC EQZ_OFFS Control Short NameAPC_EQZ_OFFS_CTRL

Address0xF012

General behavior control for EQZ_OFFS parameter control

158 EQZ_AGC_PAT_MASK RW EQZ-AGC-control pattern mask (only those bits are used for pattern matching whose mask bit is set)

0x00

70 EQZ_AGC_PAT_MATCH RW EQZ-AGC-control pattern used for pattern matching (corresponding mask bits must be set)

0x00

Table 177 bull APC EQZ_OFFS Control

Bit Name Access Description Default2927 EQZ_OFFS_RECOVER_MODE RW EQZ_OFFS recovery behavior

0 No auto-recovery1 Freeze EQZ_OFFS on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze EQZ_OFFS on weak signal and restart on missing input signal3 Freeze EQZ_OFFS on missing input signal4 Freeze EQZ_OFFS on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart EQZ_OFFS on missing input signal6-7 Reserved

0x0

26 EQZ_OFFS_CTRL_DONE RO Parameter control state in one-time mode1 Finished

0x0

2516 EQZ_OFFS_ACTVAL RO Parameter value (controlledcomputed value) 0x000

1514 EQZ_OFFS_SYNC_MODE RW Synchronization mode0 Independent1 Attached to parctrl FSM 12 Attached to parctrl FSM 23 Attached to both parctrl FSMs

0x0

1312 EQZ_OFFS_READ_CNT_SEL RW Select counter to be read0 eqz_offs_value1 Hit counter2 Error counter

0x0

Table 176 bull APC EQZ Pattern Matching Configuration Register 1 (continued)

Registers

24120 APC EQZ_OFFS Timer ConfigurationShort NameAPC_EQZ_OFFS_TIMER_CFG

Address0xF013

Configuration registers for EQZ_OFFS controller timing

24121 APC EQZ_OFFS Parameter ControlShort NameAPC_EQZ_OFFS_PAR_CFG

Address0xF014

Configuration register for controlled EQZ_OFFS parameter

10 EQZ_OFFS_CTRL_MODE RW Parameter control mode for EQZ_OFFS parameter0 Discrete1 Continuous

0x1

94 EQZ_OFFS_CTRL_THRES RW Alternative threshold for EQZ_OFFS parameter (controller goal err_cnt= 05EQZ_OFFS_THRES)

0x28

3 EQZ_OFFS_CTRL_THRES_ENA RW Enable use of alternative threshold for EQZ_OFFS parameter0 Use default threshold1 Use alternative threshold

0x0

2 EQZ_OFFS_START_CTRL RW Start operation (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

10 EQZ_OFFS_OP_MODE RW Operation mode0 Off1 One-time2 Non-stop3 Paused

0x0

Table 178 bull APC EQZ_OFFS Timer Configuration

Bit Name Access Description Default3116 EQZ_OFFS_PS_TIME RW Pause time

(in number of rx_clk cycles)0x0064

150 EQZ_OFFS_OP_TIME RW Operation time (in number of rx_clk cycles) 0x03E8

Table 177 bull APC EQZ_OFFS Control (continued)

Registers

Note For parameters larger than 8 bits iniminmax values are shifted to the left For parameters smaller than 8 bits only the lower bits of iniminmax are used

24122 APC EQZ_C ControlShort NameAPC_EQZ_C_CTRL

Address0xF015

General behavior control for EQZ_C parameter control

Table 179 bull APC EQZ_OFFS Parameter Control

Bit Name Access Description Default31 EQZ_OFFS_DIR_SEL RW Select parameter update direction

0 Normal1 Inverted

0x0

3026 EQZ_OFFS_RANGE_SEL RW Parameter range selection (only when CTRL_MODE= continuous) Value complies to number of left-shifts

0x00

2524 EQZ_OFFS_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use EQZ_OFFS_INI as fix value and internal processing continues)2 Freeze (internal processing stops and parameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

2316 EQZ_OFFS_MAX RW Maximum value of parameter 0x00

158 EQZ_OFFS_MIN RW Minimum value of parameter 0x00

70 EQZ_OFFS_INI RW Parameter initial value 0x00

Table 180 bull APC EQZ_C Control

Bit Name Access Description Default2927 EQZ_C_RECOVER_MODE RW EQZ_C recovery behavior

0 No auto-recovery1 Freeze EQZ_C on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze EQZ_C on weak signal and restart on missing input signal3 Freeze EQZ_C on missing input signal4 Freeze EQZ_C on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart EQZ_C on missing input signal6ndash7 Reserved

0x0

Registers

24123 APC EQZ_C Timer ConfigurationShort NameAPC_EQZ_C_TIMER_CFG

Address0xF016

26 EQZ_C_CTRL_DONE RO Parameter control state in one-time mode1 Finished

0x0

2516 EQZ_C_ACTVAL RO Parameter value (controlledcomputed value) 0x000

1514 EQZ_C_SYNC_MODE RW Synchronization mode0 Independent1 Attached to parctrl FSM 12 Attached to parctrl FSM 23 Attached to both parctrl FSMs

0x0

1312 EQZ_C_READ_CNT_SEL RW Select counter to be read0 eqz_c_value1 Hit counter2 Error counter

0x0

10 EQZ_C_CTRL_MODE RW Parameter control mode for EQZ_C parameter0 Discrete1 Continuous

0x1

94 EQZ_C_CTRL_THRES RW Alternative threshold for EQZ_C parameter (controller goal err_cnt= 05EQZ_C_THRES)

0x28

3 EQZ_C_CTRL_THRES_ENA RW Enable use of alternative threshold for EQZ_C parameter0 Use default threshold1 Use alternative threshold

0x0

2 EQZ_C_START_CTRL RW Start operation (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

10 EQZ_C_OP_MODE RW Operation mode0 Off1 One-time2 Non-stop3 Paused

0x0

Table 180 bull APC EQZ_C Control (continued)

Registers

Configuration registers for EQZ_C controller timing

24124 APC EQZ_C Parameter ControlShort NameAPC_EQZ_C_PAR_CFG

Address0xF017

Configuration register for controlled EQZ_C parameter

24125 APC EQZ_L Control Short NameAPC_EQZ_L_CTRL

Address0xF018

Table 181 bull APC EQZ_C Timer Configuration

Bit Name Access Description Default3116 EQZ_C_PS_TIME RW Pause time

150 EQZ_C_OP_TIME RW Operation time (in number of rx_clk cycles) 0x03E8

Table 182 bull APC EQZ_C Parameter Control

Bit Name Access Description Default31 EQZ_C_DIR_SEL RW Select parameter update direction

0 Normal1 Inverted

0x0

3026 EQZ_C_RANGE_SEL RW Parameter range selection (only when CTRL_MODE= continuous) Value complies to number of left-shifts

0x00

2524 EQZ_C_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use EQZ_C_INI as fix value and internal processing continues)2 Freeze (internal processing stops and parameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

2316 EQZ_C_MAX RW Maximum value of parameter 0x00

158 EQZ_C_MIN RW Minimum value of parameter 0x00

70 EQZ_C_INI RW Parameter initial value 0x00

Registers

General behavior control for EQZ_L parameter control

Table 183 bull APC EQZ_L Control

Bit Name Access Description Default2927 EQZ_L_RECOVER_MODE RW EQZ_L recovery behavior

0 No auto-recovery1 Freeze EQZ_L on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze EQZ_L on weak signal and restart on missing input signal3 Freeze EQZ_L on missing input signal4 Freeze EQZ_L on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart EQZ_L on missing input signal6ndash7 Reserved

0x0

26 EQZ_L_CTRL_DONE RO Parameter control state in one-time mode1 Finished

0x0

2516 EQZ_L_ACTVAL RO Parameter value (controlledcomputed value) 0x000

1514 EQZ_L_SYNC_MODE RW Synchronization mode0 Independent1 Attached to parctrl FSM 12 Attached to parctrl FSM 23 Attached to both parctrl FSMs

0x0

1312 EQZ_L_READ_CNT_SEL RW Select counter to be read0 eqz_l_value1 Hit counter2 Error counter

0x0

10 EQZ_L_CTRL_MODE RW Parameter control mode for EQZ_L parameter0 Discrete1 Continuous

0x1

94 EQZ_L_CTRL_THRES RW Alternative threshold for EQZ_L parameter (controller goal err_cnt= 05EQZ_L_THRES)

0x28

3 EQZ_L_CTRL_THRES_ENA RW Enable use of alternative threshold for EQZ_L parameter0 Use default threshold1 Use alternative threshold

0x0

2 EQZ_L_START_CTRL RW Start operation (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

Registers

24126 APC EQZ_L Timer ConfigurationShort NameAPC_EQZ_L_TIMER_CFG

Address0xF019

Configuration registers for EQZ_L controller timing

24127 APC EQZ_L Parameter ControlShort NameAPC_EQZ_L_PAR_CFG

Address0xF01A

Configuration register for controlled EQZ_L parameter

10 EQZ_L_OP_MODE RW Operation mode0 Off1 One-time2 Non-stop3 Paused

0x0

Table 184 bull APC EQZ_L Timer Configuration

Bit Name Access Description Default3116 EQZ_L_PS_TIME RW Pause time

150 EQZ_L_OP_TIME RW Operation time (in number of rx_clk cycles) 0x03E8

Table 185 bull APC EQZ_L Parameter Control

Bit Name Access Description Default31 EQZ_L_DIR_SEL RW Select parameter update direction

0 Normal1 Inverted

0x0

3026 EQZ_L_RANGE_SEL RW Parameter range selection (only when CTRL_MODE= continuous) Value complies to number of left-shifts

0x00

2524 EQZ_L_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use EQZ_L_INI as fix value and internal processing continues)2 Freeze (internal processing stops and parameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

Table 183 bull APC EQZ_L Control (continued)

Registers

24128 APC EQZ_AGC Control Short NameAPC_EQZ_AGC_CTRL

Address0xF01B

General behavior control for EQZ_AGC parameter control

2316 EQZ_L_MAX RW Maximum value of parameter 0x00

158 EQZ_L_MIN RW Minimum value of parameter 0x00

70 EQZ_L_INI RW Parameter initial value 0x00

Table 186 bull APC EQZ_AGC Control

Bit Name Access Description Default2927 EQZ_AGC_RECOVER_M

ODERW EQZ_AGC recovery behavior

0 No auto-recovery1 Freeze EQZ_AGC on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze EQZ_AGC on weak signal and restart on missing input signal3 Freeze EQZ_AGC on missing input signal4 Freeze EQZ_AGC on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart EQZ_AGC on missing input signal6-7 Reserved

0x0

26 EQZ_AGC_CTRL_DONE RO Parameter control state in one-time mode1 Finished

0x0

2516 EQZ_AGC_ACTVAL RO Parameter value (controlledcomputed value) 0x000

1514 EQZ_AGC_SYNC_MODE RW Synchronization mode0 Independent1 Attached to parctrl FSM 12 Attached to parctrl FSM 23 Attached to both parctrl FSMs

0x0

1312 EQZ_AGC_READ_CNT_SEL

RW Select counter to be read0 eqz_agc_value1 Hit counter2 Error counter

0x0

10 EQZ_AGC_CTRL_MODE RW Parameter control mode for EQZ_AGC parameter0 Discrete1 Continuous

0x1

Table 185 bull APC EQZ_L Parameter Control (continued)

Registers

24129 APC EQZ_AGC Timer ConfigurationShort NameAPC_EQZ_AGC_TIMER_CFG

Address0xF01C

Configuration registers for EQZ_AGC controller timing

24130 APC EQZ_AGC Parameter ControlShort NameAPC_EQZ_AGC_PAR_CFG

Address0xF01D

Configuration register for controlled EQZ_AGC parameter

For parameters larger than 8 bits iniminmax values are shifted to the left For parameters smaller than 8 bits only the lower bits of iniminmax are used

94 EQZ_AGC_CTRL_THRES RW Alternative threshold for EQZ_AGC parameter (controller goal err_cnt= 05EQZ_AGC_THRES)

0x28

3 EQZ_AGC_CTRL_THRES_ENA

RW Enable use of alternative threshold for EQZ_AGC parameter0 Use default threshold1 Use alternative threshold

0x0

2 EQZ_AGC_START_CTRL RW Start operation (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

10 EQZ_AGC_OP_MODE RW Operation mode0 Off1 One-time2 Non-stop3 Paused

0x0

Table 187 bull APC EQZ_AGC Timer Configuration

Bit Name Access Description Default3116 EQZ_AGC_PS_TIME RW Pause time

150 EQZ_AGC_OP_TIME RW Operation time (in number of rx_clk cycles) 0x03E8

Table 188 bull APC EQZ_AGC Parameter Control

Bit Name Access Description Default31 EQZ_AGC_DIR_SEL RW Select parameter update direction

0 Normal1 Inverted

0x0

Table 186 bull APC EQZ_AGC Control (continued)

Registers

24131 APC DFE1 Control Short NameAPC_DFE1_CTRL

Address0xF01E

General behavior control for DFE1 parameter control

3026 EQZ_AGC_RANGE_SEL RW Parameter range selection (only when CTRL_MODE= continuous) Value complies to number of left-shifts

0x00

2524 EQZ_AGC_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use EQZ_AGC_INI as fix value and internal processing continues)2 Freeze (internal processing stops and parameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

2316 EQZ_AGC_MAX RW Maximum value of parameter 0x00

158 EQZ_AGC_MIN RW Minimum value of parameter 0x00

70 EQZ_AGC_INI RW Parameter initial value 0x00

Table 189 bull APC DFE1 Control

Bit Name Access Description Default2927 DFE1_RECOVER_MODE RW DFE1 recovery behavior

0 No auto-recovery1 Freeze DFE1 on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze DFE1 on weak signal and restart on missing input signal3 Freeze DFE1 on missing input signal4 Freeze DFE1 on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart DFE1 on missing input signal6-7 Reserved

0x0

26 DFE1_CTRL_DONE RO Parameter control state in one-time mode1 Finished

0x0

2516 DFE1_ACTVAL RO Parameter value (controlledcomputed value) 0x000

Table 188 bull APC EQZ_AGC Parameter Control (continued)

Registers

24132 APC DFE1 Timer ConfigurationShort NameAPC_DFE1_TIMER_CFG

Address0xF01F

Configuration registers for DFE1 controller timing

24133 APC DFE1 Parameter ControlShort NameAPC_DFE1_PAR_CFG

1514 DFE1_SYNC_MODE RW Synchronization mode0 Independent1 Attached to parctrl FSM 12 Attached to parctrl FSM 23 Attached to both parctrl FSMs

0x0

1312 DFE1_READ_CNT_SEL RW Select counter to be read0 dfe1_value1 Hit counter2 Error counter

0x0

10 DFE1_CTRL_MODE RW Parameter control mode for DFE1 parameter0 Discrete1 Continuous

0x1

94 DFE1_CTRL_THRES RW Alternative threshold for DFE1 parameter (controller goal err_cnt= 05DFE1_THRES)

0x28

3 DFE1_CTRL_THRES_ENA RW Enable use of alternative threshold for DFE1 parameter0 Use default threshold1 Use alternative threshold

0x0

2 DFE1_START_CTRL RW Start operation (parameter update) Should be cleared afterwards in one-time mode and stay set in non-stop and paused mode

0x0

10 DFE1_OP_MODE RW Operation mode0 Off1 One-time2 Non-stop3 Paused

0x0

Table 190 bull APC DFE1 Timer Configuration

Bit Name Access Description Default3116 DFE1_PS_TIME RW Pause time (in number of rx_clk cycles) 0x0064

150 DFE1_OP_TIME RW Operation time (in number of rx_clk cycles) 0x03E8

Table 189 bull APC DFE1 Control (continued)

Registers

Address0xF020

Configuration register for controlled DFE1 parameter

Address0xF021

Table 191 bull APC DFE1 Parameter Control

Bit Name Access Description Default31 DFE1_DIR_SEL RW Select parameter update direction

0 Normal1 Inverted

0x0

3026 DFE1_RANGE_SEL RW Parameter range selection (only when CTRL_MODE= continuous) Value complies to number of left-shifts

0x00

2524 DFE1_CHG_MODE RW Parameter change mode0 Automatic update1 Preset (use DFE1_INI as fix value and internal processing continues)2 Freeze (internal processing stops and parameter stays at current value)3 No update (internal processing continues but parameter is not updated)

0x0

2316 DFE1_MAX RW Maximum value of parameter 0x00

158 DFE1_MIN RW Minimum value of parameter 0x00

70 DFE1_INI RW Parameter initial value 0x00

0 No auto-recovery1 Freeze DFE2 on weak (eqz_gain gt eqz_gain_freeze_thres) or missing input signal2 Freeze DFE2 on weak signal and restart on missing input signal3 Freeze DFE2 on missing input signal4 Freeze DFE2 on missing input signal and auto-restart after Restart-Delay-Timer has expired5 Auto-restart DFE2 on missing input signal6ndash7 Reserved

0x0

Registers

Address0xF022

0x0

0x1

0x28

0x0

Registers

24136 APC DFE2 Parameter Control Short NameAPC_DFE2_PAR_CFG

Address0xF023

Address0xF024

Bit Name Access Description Default3116 DFE2_PS_TIME RW Pause time

Table 194 bull APC DFE2 Parameter control register

0 Normal1 Inverted

0x0

0x00

0x0

Registers

0x0

0x1

0x28

3 DFE3_CTRL_THRES_ENA

RW Enable use of alternative threshold for DFE3 parameter0 Use default threshold1 Use alternative threshold

0x0

Registers

Address0xF025

Address0xF026

0x0

0 Normal1 Inverted

0x0

0x00

0x0

Registers

Address0xF027

0x0

0x1

0x28

Table 197 bull APC DFE3 Parameter Control (continued)

Registers

Address0xF028

Address0xF029

0x0

Bit Name Access Description Default3116 DFE4_PS_TIME RW Pause time in number of rx_clk cycles) 0x0064

0 Normal1 Inverted

0x0

0x00

Registers

24143 APC LC Softcontrol Configuration Register 0Short NameAPC_LC_SOFTCTRL_CFG

Address0xF02A

Configuration register 0 for the LC-Softcontrol logic block The L and C parameters can be controlled depending on DFE1 and DFE2 and EQZ_AGC parameters instead of pattern matching

0x0

Table 201 bull APC LC Softcontrol Configuration Register 0

Bit Name Access Description Default3128 LC_SC_TIMER RW Operation timer configuration LC-control

operates in every 2^(2LC_SC_TIMER)-th clock cycle0 Operate every clock cycle1 Operate every 4th clock cycle2 Operate every 16th clock cycle

0x0

2724 LC_SC_AVGSHFT RW DFE12 and EQZ_AGC averaging behavior DFEAGC parameters are averaged over 2^(8+LC_SC_AVGSHFT) input values0 Average over 256 values1 Average over 512 values

0x8

2320 LC_SC_DFE1_THRESHOLD RW DFE1 comparison threshold for L-control used in mode 2 EQZ_L is increaseddecreased if DFE1 differs from neutral value by more than LC_SC_DFE1_THRESHOLD

0x8

1916 LC_SC_DFE2_THRESHOLD RW DFE2 comparison threshold for C-control used in mode 2 EQZ_C is increaseddecreased if DFE1 differs from neutral value by more than LC_SC_DFE2_THRESHOLD

0x4

Registers

24144 APC LC Softcontrol Configuration Register 1Short NameAPC_LC_SOFTCTRL_CFG1

Address0xF02B

Configuration register 1 for the LC-Softcontrol logic block

159 LC_SC_AGC_THRESHOLD RW EQZ_AGC threshold for mandatory increase of L and C If EQZ_AGC gt (128+LC_SC_AGC_THRESHOLD) then L and C control values are increased0 1281 129127 255

0x7D

8 LC_SC_DIV_C_SEL RW Define DFE2 comparison parameter for EQZ_C control in mode 10 EQZ_L1 EQZ_C

0x0

75 LC_SC_DIV_L RW Select divider for L-control used in mode 1 (Divider= 4+LC_SC_DIV_L)0 Divide by 41 Divide by 57 Divide by 11

0x4

42 LC_SC_DIV_C RW Select divider for C-control used in mode 1 (Divider= 4+LC_SC_DIV_C)0 Divide by 41 Divide by 57 Divide by 11

0x4

10 LC_SC_MODE RW Select LC soft-control mode LC soft-control modes must be enabled first after INIMINMAX values of all parameters have been programmed0 Disabled1 Mode 12 Mode 23 Reserved

0x0

Bit Name Access Description Default138 LC_SC_DFE2_TARGET RW Target value for DFE2 during LC-control

operation0x20

60 LC_SC_DFE1_TARGET RW Target value for DFE1 during LC-control operation

0x3F

Table 201 bull APC LC Softcontrol Configuration Register 0 (continued)

Registers

242 SD10G65 DES Configuration and Status2421 SD10G65 DES Configuration 0

Short NameSD10G65_DES_CFG0

Address0xF100

2422 SD10G65 MOEBDIV Configuration 0Short NameSD10G65_MOEBDIV_CFG0

Address0xF101

Configuration register 0 for SD10G65 MoebiusDivider

Table 203 bull SD10G65 DES Configuration Register 0

Bit Name Access Description Default7 DES_INV_H RW Invert output of high auxiliary deserializer 0x0

6 DES_INV_L RW Invert output of low auxiliary deserializer 0x0

5 DES_INV_M RW Invert output of main deserializer 0x0

42 DES_IF_MODE_SEL RW Interface width0 81 102 16 (energy efficient)3 20 (energy efficient)4 325 406 16 bit (fast)7 20 bit (fast)

0x4

1 DES_VSC_DIS RW Auxiliary deserializer channels disable 0x1

0 DES_DIS RW Deserializer disable 0x0

Table 204 bull SD10G65 MOEBDIV Configuration Register 0

Bit Name Access Description Default119 MOEBDIV_BW_CDR_SEL_A RW Bandwidth selection for cpmd of cdr loop when

core NOT flags valid data detected0x3

86 MOEBDIV_BW_CDR_SEL_B RW Bandwidth selection for cpmd of cdr loop when core flags valid data detected

0x3

53 MOEBDIV_BW_CORE_SEL RW Bandwidth selection for cpmd signals towards core

0x0

2 MOEBDIV_CPMD_SWAP RW CPMD swapping 0x0

1 MOEBDIV_DIV32_ENA RW MD divider enable 0x0

Registers

243 SD10G65 OB Configuration and Status2431 SD10G65 OB Configuration 0

Short NameSD10G65_OB_CFG0

Address0xF110

0 MOEBDIV_DIS RW Divider disable 0x0

Table 205 bull SD10G65 OB Configuration Register 0

Bit Name Access Description Default23 SER_INV RW Invert input to serializer 0x0

2221 CLK_BUF_CMV RW Control of common mode voltage of clock buffer between synthesizer and OB

0x0

17 RST RW Set digital part into pseudo reset 0x0

16 EN_PAD_LOOP RW Enable pad loop 0x0

15 EN_INP_LOOP RW Enable input loop 0x0

14 EN_DIRECT RW Enable direct path 0x0

13 EN_OB RW Enable output buffer and serializer 0x0

8 INCR_LEVN RW Selects amplitude range controlled through levn See description of levn

0x1

75 SEL_IFW RW Interface width0 81 102 163 204 325 406-7 Reserved

0x4

Table 204 bull SD10G65 MOEBDIV Configuration Register 0 (continued)

Registers

2432 SD10G65 OB Configuration 1Short NameSD10G65_OB_CFG1

Address0xF111

40 LEVN RW Amplitude control value Step size is 25 mVpp decreasing amplitude with increasing control value Range depends on incr_levn Coding for incr_levn= 0 is31 500 mVpp 30 525 mVpp 29 550 mVpp0= 1275 mVppCoding for incr_levn= 1 is31 300 mVpp 30 325 mVpp 29 350 mVpp0 1075 mVpp

Note Maximum achievable amplitude depends on the supply voltage

0x07

Bit Name Access Description Default26 AB_COMP_EN RW Enable amplitude compensation of AB bleed

current0x1

2523 DIODE_CUR RW Bleed current for class AB operation of driver0 11 052 23 reserved

0x0

2221 LEV_SHFT RW Level shift ctrl of class AB bias generator0 50 mV1 100 mV2150 mV3 200 mV

0x1

1918 PREDRV_R_CTRL RW Slew rate ctrl of OB (R) encoding (see PREDRV_C_CTRL)

0x3

1716 PREDRV_C_CTRL RW Slew rate ctrl of OB (C)C=3 R=3 25psC=3 R=0 35psC=0 R=3 55psC=1 R=0 70psC=0 R=0 120 ps

0x3

Table 205 bull SD10G65 OB Configuration Register 0 (continued)

Registers

Address0xF112

Configuration register 2 for SD10G65 OB D_filter contains four 6-bit pre-calculated DA input values Please note the differences in programming for various interface (IF) bit widths For calculation details see documentation of OB10G

2434 SD10G65 OB Configuration 3 Access to Receiver Detect FunctionalityShort NameSD10G65_OB_CFG3

Address0xF113

1510 VTAIL RW Tail voltage driver settings0 reserved1 75 mV2 100 mV4 125 mV8 150 mV16 175 mV32 200 mVIntermediate values possible when setting two bits

0x02

95 VCAS RW Ctrl of cascade volt in drv stage0 Reserved1 02 1124 2128 31216 412Intermediate values possible when setting two bits

0x01

4 R_COR RW Additional resistor calibration trim 0x0

30 R_I RW Offset resistance adjustment for CML cells (two-complement)1000 ndash81111 ndash10000 00111 7

0x0

Bit Name Access Description Default230 D_FILTER RW Transmit filter coefficients for FIR taps

Suggested start value (no emphasis max amplitude)0x820820 for IF width 810 bits0x7DF820 for IF width 16203240 bits

0x7DF820

Registers

Configuration register 3 for SD10G65 OB

244 SD10G65 IB Configuration and Status 2441 SD10G65 IB Configuration 0

Short NameSD10G65_IB_CFG0

Address0xF120

Configuration register 0 for SD10G65 IB

Note Configuration bit-grp IB_CLKDIV_ENA was named IB_VScope_CLK_ENA in an early revision of the input buffer

Table 208 bull SD10G65 OB Configuration Register 3 Access to Receiver Detect Functionality

Bit Name Access Description Default18 REC_DET_DONE RO Indicates a completed receiver detect

measurement Should be one few us after rec_det_start is set

0x0

17 REC_DET_START RW Rising edge starts receiver detect measurement Has to be kept set until rec_det_value has been read

0x0

16 REC_DET_ENABLE RW Enable receiver detect function Note MUST be disabled for normal

operation

0x0

110 REC_DET_VALUE RO Holds the time between the start and the flag of the receiver detect measurement Time [ns plusmn4 ns]= 8 value - 12

0x000

Table 209 bull SD10G65 IB Configuration Register 0

Bit Name Access Description Default3027 IB_RCML_ADJ RW Offset resistance adjustment for CML cells (two-

complement)1000 ndash81111 ndash10000 00111 7

0x0

2623 IB_TERM_V_SEL RW Select termination voltage 0x8

22 IB_TERM_VDD_ENA RW Enable common mode termination0 No common mode termination (only AC-common mode termination)1Termination to VDDI

0x0

Registers

21 IB_RIB_SHIFT RW Shifts resistance adjustment value ib_rib_adj by +1

0x0

2017 IB_RIB_ADJ RW Offset resistance adjustment for termination (two-complement)1000 -81111 -10000 00111 7

0x0

14 IB_DFE_ENA RW Enable DFE stage (gates IB_ISEL_DFE)0 Disable1 Enable

0x0

1312 IB_SIG_SEL RW Select input buffer input signal0 Normal operation1 ndash6 dB input2 OB-gtIB data loop or test signal3 RESERVED

0x0

11 IB_VBULK_SEL RW Controls bulk voltage of high-speed cells0 High1 Low (mission mode)

0x1

10 IB_IA_ENA RW Enable for IA including ACJTAG0 Disable1 Enable

0x1

9 IB_IA_SDET_ENA RW Enable for IA signal detect circuit (IB_SDET_SEL = 0 required)0 Disable1 Enable

0x0

8 IB_IE_SDET_ENA RW Enable for IA signal detect circuit (IB_SDET_SEL = 1 required)0 Disable1 Enable

0x0

7 IB_LD_ENA RW Enable for level detect circuit0 Disable1 Enable

0x0

6 IB_1V_ENA RW Enable for 1 V mode0 VDDI= 12 V1 VDDI= 10 V

0x0

5 IB_CLKDIV_ENA RW Enable clock dividers in sampling stage0 Disable (use in double rate mode)1 Enable (use in full rate mode)

0x0

Table 209 bull SD10G65 IB Configuration Register 0 (continued)

Registers

2442 SD10G65 IB Configuration 1Short NameSD10G65_IB_CFG1

Address0xF121

3 IB_VScope_ENA RW Enable VScope path of sampling stage0 Disable1 Enable

0x0

2 IB_SAM_ENA RW Enable sampling stage0 Disable1 Enable (mission mode)

0x0

1 IB_EQZ_ENA RW Enable equalization stage0 Disable1 Enable (mission mode)

0x0

Bit Name Access Description Default3128 IB_AMP_L RW Inductor peaking of 1 Stage Input buffer

0 No peaking15 Max peakingMax peaking gt 3 db at 8 GHz

0x8

2724 IB_EQZ_L0 RW Inductor peaking of EQ-Buffer0 (over all 2 stage)0 No peaking15 Max peakingMax peaking gt 3 db at 8 GHz

0x8

1512 IB_AGC_L RW Inductor peaking of EQ-Buffer3 (over all 5 stage)0 No peaking15 Max peakingMax peaking gt 3 db at 8 GHz

0x8

Registers

Address0xF122

119 IB_AMP_C RW C-gain peaking for IB-stage0 No peaking7 Max peakingCorner frequency adjustment with ib_eqz_c_adj_ib

0x4

86 IB_EQZ_C0 RW C-gain peaking for EQ-stage00 No peaking7 Max peakingCorner frequency adjustment with ib_eqz_c_adj_es0

0x4

Bit Name Access Description Default2718 IB_EQZ_GAIN RW Gain of Input Buffer

0ndash511 gain adjustment only in first stage gt 511 gain in first stage at max512ndash639 gain in 2stage increased from 1 to 2 gt 639 gain= 2640ndash767 gain in 3stage increased from 1 to 2 gt 767 gain = 2768ndash895 gain in 4stage increased from 1 to 2gt895 gain at max

0x040

1710 IB_EQZ_AGC RW Amplification (gain) of AGC in Input Buffer (normal operation)after gain calibration0 Gain = 03255 Gain = 15If dispdisn is active DAC function for DFE gain calibration

0x80

Registers

Address0xF123

Note The behavior of IB_EQ_LD1_OFFSET changes when APC is disabled In this case IB_EQ_LD1_OFFSET directly controls the level for Level-Detect circuitry 1 Coding= 0 20 mV 1 25 mV63 340 mV

90 IB_EQZ_OFFSET RW Offset value for IB-stage of Input Buffer512 neutralgt 512 positivelt 512 negativeRange plusmn 600 mV (low gain) to plusmn30 mV (high gain)Gain dependent offset sensitivity required for baseline wander compensation not supported in test chip

0x200

Bit Name Access Description Default3130 IB_LDSD_DIVSEL RW Dividing factor for SDET and LD circuits of IE

0 1281 322 83 4

0x1

2927 IB_SDET_CLK_DIV RW Clock dividing factor for Signal Detect circuit of IA0 27 256

0x5

26 IB_SET_SDET RW Force Signal-Detect output to high level0 Normal operation1 Force sigdet high

0x0

24 IB_SDET_SEL RW Selects source of signal detect (ib_X_sdet_ena must be enabled accordingly)0 IA1 IE

0x0

23 IB_DIRECT_SEL RW Selects source of direct data path to core0 IE1 IA

0x0

Registers

Address0xF124

2217 IB_EQ_LD1_OFFSET RW With APC enabled level offset (6bit-signed) compared to IB_EQ_LD0_LEVEL for Level-Detect circuitry 1 Saturating between 20 mV and 340 mV See also note in register description0 No offset1 +5 mV31 +155 mV63(= ndash1) ndash5 mV32(= ndash32) ndash160 mV

0x00

1611 IB_EQ_LD0_LEVEL RW Level for Level-Detect circuitry 00 20 mV1 25 mV40 220 mV63 340 mV

0x28

105 IB_IE_SDET_LEVEL RW Threshold value for IE Signal-Detect0 20 mV1 25 mV2 30 mV63 340 mV

0x02

40 IB_IA_SDET_LEVEL RW Threshold value for IA Signal-Detect0 0 mV8 80 mV31 310 mV

0x08

Bit Name Access Description Default3130 IB_EQZ_C_ADJ_IB RW Corner frequency selection for c-gain peaking

1stage0 Lowest corner frequency3 Highest corner frequency

0x2

2928 IB_EQZ_C_ADJ_ES2 RW Corner frequency selection for c-gain peaking 2stage0 Lowest corner frequency3 Highest corner frequency

0x2

Registers

0x2

2321 IB_EQZ_L_MODE RW Coder mode APC L value to IE inductance0 Equ distributed (double step 3-gt4)1 Equ distributed (no change 6+7)2 1st buffer max - 2nd buffer max -

0x0

2018 IB_EQZ_C_MODE RW Coder mode APC C value to IE capacitance0 Equ distributed2 1st buffer max - 2nd buffer max -

0x0

1712 IB_VScope_H_THRES RW Threshold value (offset) for VScope-high sampling path0 -max31 -032 +063 +max (depending on calibration)

0x30

116 IB_VScope_L_THRES RW Threshold value (offset) for VScope-low sampling path0 -max31 -032 +063 +max (depending on calibration)

0x0F

50 IB_MAIN_THRES RW Threshold value (offset) for main sampling path0 -max31 -032 +063 +max (depending on calibration)

0x20

Registers

Address0xF125

Bit Name Access Description Default3128 IB_TSTGEN_AMPL RW Test generator amplitude setting

0 0 mV15 150 mV

0x0

27 IB_TSTGEN_ENA RW Test generator enable but data path selected with ib_sig_sel (disable input loop if test generator is used)0 Inactive1 Active

0x0

26 IB_TSTGEN_DATA RW Test generator data0 Low1 High

0x0

25 IB_TSTGEN_TOGGLE_ENA

RW Test generator data toggle enable0 Inactive1 Active

0x0

22 IB_JUMPH_ENA RW Enable jump to opposite half of h-channel0 Post main sampler1 Pre main sampler

0x0

21 IB_JUMPL_ENA RW Enable jump to opposite half of l-channel0 Post main sampler1 Pre main sampler

0x0

2019 IB_DFE_DIS RW DFE output disable required to calibrate IS0 mission mode3 Vout = 0 V1 Vout= xxampldfe642 Vout=-xxampldfe64

ampldfe=196 mV if ena1V = 1 (1 V mode)ampldfe=260 mV if ena1V = 0 (12 V mode)

xx= TBD

0x0

1817 IB_AGC_DIS RW AGC output disable required to calibrate DFE-gain0 Mission mode3 Vout = 0 V1 Vout= xxampldfe642 Vout=-xxampldfe64

ampldfe= 270 mV if ena1V= 1 (1 V mode)ampldfe= 360 mV if ena1V= 0 (12 V mode)

xx=

0x0

Registers

16 IB_EQ_LD_CAL_ENA RW Selects EQ Level Detect for calibration 0x0

15 IB_THRES_CAL_ENA RW Selects IS threshold circuit for calibration 0x0

14 IB_IS_OFFS_CAL_ENA RW Selects IS offset circuit for calibration 0x0

13 IB_IA_OFFS_CAL_ENA RW Selects IA offset circuit for calibration 0x0

12 IB_IE_SDET_CAL_ENA RW Selects IE Signal Detect for calibration 0x0

11 IB_HYS_CAL_ENA RW Enable calibration in order to eliminate hysteresis1 Enable0 Disable

0x0

10 IB_CALMUX_ENA RW Enables IS MUX in detblk1 0x1

96 IB_OFFS_BLKSEL RW Selects calibration target (sample stage threshold sample stage offset aux-stage offset) dependent on calibration group see encodingWhen ib_thres_cal_ena= 10 MD0 threshold1 MD1 threshold2 CP0 threshold3 CP1 threshold4 VH0 threshold5 VH1 threshold6 VL0 threshold7 VL1 thresholdWhen ib_is_offs_cal_ena= 10 MD0 offset1 MD1 offset2 CP0 offset3 CP1 offset4 VH0 offset5 VH1 offset6 VL0 offset7 VL1 offsetWhen ib_ia_offs_cal_ena= 10 Observe0 offset1 Observe1 offset2 Observe0 threshold3 Observe1 threshold(MSB not used)

0x0

Registers

Address0xF126

Address0xF127

50 IB_OFFS_VALUE RW Calibration value for IAIS Values for threshold calibration get inverted for negative threshold voltages (ib_VScope_h_thres ib_VScope_l_thres or ib_main_thres)For offset calibration0 -max_offset 323231 -max_offset 13232 +max_offset 13263 +max_offset 3232For threshold calibration0 min_threshold63 max_threshold

0x1F

Bit Name Access Description Default2216 IB_EQZ_GAIN_ADJ RW 0 dB Gain adjustment for EQZ-stages of Input

BufferLevel at LD0 = LD1 -gt 0d BLevel range 160 mVndash220 mV

0x2A

12 IB_AUTO_AGC_ADJ RW Enable automatic AGC adjustment1 AGC is adjusted automatically (IB_EQZ_AGC_ADJ value is not used)0 AGC is adjusted with value stored in IB_EQZ_AGC_ADJ

0x0

115 IB_EQZ_AGC_ADJ RW Gain adjustment of AGC-amplifierBitgroup should be set to 2IB_DFE_GAIN_ADJ

0x3E

40 IB_SAM_OFFS_ADJ RW Range for offset calibration of all sampling paths0 0 mV32 80 mV

0x10

Bit Name Access Description Default2823 IB_MAIN_THRES_CAL RW Initial value for calibration of main sampling path 0x30

Registers

Address0xF128

22 IB_DFE_OFFSET_H_L RW Selects higher or lower DFE offset for IS calibration0 ib_dfe_offset_l1 ib_dfe_offset_h

0x0

2116 IB_DFE_GAIN_ADJ RW Gain adjustment of DFE amplifierDFE Gain 1 Volt mode= 0 dB12 V mode 1 dBMeasurement with int DAC and VScope channels

0x24

116 IB_DFE_OFFSET_H RW Higher threshold offset of DFE buffer for IS calibration0 0 mv63 200 mV

0x17

50 IB_DFE_OFFSET_L RW Lower sample offset of DFE buffer for IS calibration0 0 mv63 200 mV

0x06

Bit Name Access Description Default20 IB_SEL_VCLK RW Use separate VScope clock for VScope-

channels0x0

19 IB_BIAS_MODE RW Bias regulation mode0 constant resistor1 constant current

0x1

18 IB_LAT_NEUTRAL RW Enables neutral setting of latches1 Reset to mid values0 Normal operation

0x0

1210 IB_CML_AMPL RW Amplitude of cml stages inside IS0 200 mVppd7 240 mVppd

0x4

94 IB_BIAS_ADJ RW Gain of cml stages inside IS0 3 dB31 6 dB63 9 dB

0x1F

Registers

24410 SD10G65 IB Configuration 9 Automatically Adapted DFE CoefficientsShort NameSD10G65_IB_CFG9

Address0xF129

24411 SD10G65 IB Configuration 10 JTAG-Related SettingsShort NameSD10G65_IB_CFG10

Address0xF12A

30 IB_CML_CURR RW Current through CML cells0 1505 10015 50

0x5

Table 218 bull SD10G65 IB Configuration Register 9 Automatically Adapted DFE Coefficients

Bit Name Access Description Default2824 IB_DFE_COEF4 RW Weighting for fourth DFE coefficient 0x10

2016 IB_DFE_COEF3 RW Weighting for third DFE coefficient 0x10

138 IB_DFE_COEF2 RW Weighting for second DFE coefficient 0x20

60 IB_DFE_COEF1 RW Weighting for first DFE coefficient 0x40

Table 219 bull SD10G65 IB Configuration Register 10 JTAG-Related Settings

Bit Name Access Description Default31 IB_IA_DOFFS_CAL RO Data offset calibration result IA stage 0x0

30 IB_IS_DOFFS_CAL RO Data offset calibration result IS stage 0x0

29 IB_IE_SDET_PEDGE RO Detection of toggling signal at PADP and PADN 0x0

28 IB_IE_SDET_NEDGE RO Detection of toggling signal at PADP and PADN 0x0

27 IB_IE_SDET RO Result signal detect of IE stage 0x0

26 IB_IA_SDET RO Result signal detect of IA stage 0x0

Registers

25 IB_EQZ_LD1_PEDGE RO Result of Level-Detect1 (after ES2-stage of EQZ) circuitry1 Input level above threshold defined by IB_EQ_LD_LEV

0x0

24 IB_EQZ_LD1_NEDGE RO Result of Level-Detect1 (after ES2-stage of EQZ) circuitry1 Input level above threshold defined by IB_EQ_LD_LEV

0x0

23 IB_EQZ_LD0_PEDGE RO Result of Level-Detect0 (after IB-stage of EQZ) circuitry1 Input level above threshold defined by IB_EQ_LD_LEV

0x0

22 IB_EQZ_LD0_NEDGE RO Result of Level-Detect0 (after IB-stage of EQZ) circuitry1 Input level above threshold defined by IB_EQ_LD_LEV

0x0

21 IB_IE_DIRECT_DATA RO Direct Data output from IE block 0x0

20 IB_IA_DIRECT_DATA RO Direct Data output from IA block 0x0

17 IB_LOOP_REC RW Receive enable for BiDi loop (aka PAD loop o Tx-gtRx loop) Is ord with primary input ib_pad_loop_ena_i Disable testgenerator ib_tstgen_ena if input loop is used

0x0

16 IB_LOOP_DRV RW Drive enable for BiDi loop (aka input loop o Rx-gtTx loop) Is ord with primary input ib_inp_loop_ena_i Is overruled by PAD loop

0x0

10 IB_JTAG_OUT_P RO JTAG debug p-output 0x0

9 IB_JTAG_OUT_N RO JTAG debug n-output 0x0

84 IB_JTAG_THRES RW JTAG debug threshold0 0mV1 10mV31 310mV

0x08

3 IB_JTAG_IN_P RW JTAG debug p-input 0x0

2 IB_JTAG_IN_N RW JTAG debug n-input 0x0

1 IB_JTAG_CLK RW JTAG debug clk 0x0

Table 219 bull SD10G65 IB Configuration Register 10 JTAG-Related Settings (continued)

Registers

Address0xF12B

24413 SD10G65 SBUS Rx CFG Service Bus-Related SettingsShort NameSD10G65_SBUS_RX_CFG

Address0xF12C

Configuration register for service bus-related settings

Note SBUS configuration applies for RXTX aggregates only any configuration applied to SBUS_TX_CFG (output buffer cfg space) will be ignored

0 IB_JTAG_ENA RW JTAG debug enable 0x0

Bit Name Access Description Default1512 IB_DFE_ISEL RW DFE bias current settings (bit-group is gated with

IB_DFE_ENA)0 DFE disabled1 Minimum current15 Maximum current

0x7

11 IB_ENA_400_INP RW Increase current in first stage (only available in 12 V mode)

0x0

106 IB_TC_DFE RW Gain temperature coefficient for DFE stage 0x0C

51 IB_TC_EQ RW Gain temperature coefficient for AGC stage 0x0C

Table 221 bull SD10G65 SBUS Rx CFG Service Bus-Related Settings

Bit Name Access Description Default12 SBUS_LOOPDRV_ENA RW Enable BiDi loop driver for F2DF testing 0x0

Registers

245 SD10G65 Rx RCPLL Configuration and Status 2451 SD10G65 Rx RCPLL Configuration 0

Short NameSD10G65_RX_RCPLL_CFG0

Address0xF130

118 SBUS_ANAOUT_SEL RW Analog test output0 l0_ctrlspeed[0]1 vbulk2 nref3 vref820m4 vddfilt5 vddfilt6 ie_aout7 ib_aout8 ob_aout29 pll_frange10 pll_srange11 pll_vreg820m_tx12 pll_vreg820m_rx13 ob_aout_n14 ob_aout_p15 vddfilt

0x0

7 SBUS_ANAOUT_EN RW Enable analog test output multiplexer 0x0

63 SBUS_RCOMP RW Offset value for BIAS resistor calibration (2-complement)1000 ndash81111 ndash10000 00111 7

0x0

21 SBUS_BIAS_SPEED_SEL RW Bias speed selection0 Below 4 Gbps1 4 Gbps to 6 Gbps2 6 Gbps to 9 Gbps3 Above 9 Gbps

0x3

0 SBUS_BIAS_EN RW Bias enable1 Enable0 Disable

0x0

Table 222 bull SD10G65 Rx RCPLL Configuration Register 0

Bit Name Access Description Default2516 PLLF_START_CNT RW Preload value of the ramp up counter reduces

ramp up time for higher frequencies0x002

Table 221 bull SD10G65 SBUS Rx CFG Service Bus-Related Settings (continued)

Registers

2452 SD10G65 Rx RCPLL Configuration 1Short NameSD10G65_RX_RCPLL_CFG1

Address0xF131

Address0xF132

97 PLLF_RAMP_MODE_SEL RW Sets the ramp characteristic of the FSM Higher values give faster ramp up but less accuracy0 Normal (default) ramping1 Faster ramping2 Fastest ramping3 Slow rampingUses all possible values of r_ctrl

0x0

0 PLLF_ENA RW Enable RCPLL FSM 0x0

Bit Name Access Description Default3116 PLLF_REF_CNT_END RW Target value 1vco_frq parbitwidth 512

ref_clk_frq0x00C6

1211 PLL_LPF_CUR RW Select chargepump current0 50 microA1 100 microA2 150 microA3 200 microA

0x3

Table 222 bull SD10G65 Rx RCPLL Configuration Register 0 (continued)

Registers

2454 SD10G65 Rx RCPLL Status 0Short NameSD10G65_RX_RCPLL_STAT0

Address0xF133

246 SD10G65 Rx SYNTH Configuration and Status 2461 SD10G65 Rx Synthesizer Configuration 0

Short NameSD10G65_RX_SYNTH_CFG0

Address0xF140

107 PLL_LPF_RES RW Select loop filter resistor value0 Not allowed1 24002 16003 9604 12005 8006 6857 5338 8009 60010 53311 43612 48013 40014 36915 320

0xA

62 RESERVED RW Must be set to its default 0x1F

0 PLL_ENA RW Enable analog RCPLL part 0x0

Table 225 bull SD10G65 Rx RCPLL Status Register 0

Bit Name Access Description Default31 PLLF_LOCK_STAT RO PLL lock status

0 Not locked1 Locked

0x0

Table 226 bull SD10G65 Rx Synthesizer Configuration Register 0

Bit Name Access Description Default2118 RESERVED RW Must be set to its default 0xF

1716 SYNTH_FBDIV_SEL RW Selects feedback divider setting0 divide by 11 divide by 22 divide by 43 reserved

0x1

Registers

2462 SD10G65 Rx Synthesizer Configuration 1Short NameSD10G65_RX_SYNTH_CFG1

Address0xF141

Address0xF142

1514 SYNTH_FB_STEP RW Selects step width for sync output 0x0

1211 SYNTH_I2_STEP RW Selects step width for integrator2 0x0

9 SYNTH_I2_ENA RW Enable contribution of integral2 part 0x1

6 SYNTH_P_STEP RW Selects step width for proportional 0x0

4 SYNTH_SPEED_SEL RW Selects circuit speed0 For settings with synth_fbdiv_sel= 21 For setting with synth_fbdiv_sel less than 2

0x1

3 SYNTH_HRATE_ENA RW Enables half rate mode 0x0

0 SYNTH_ENA RW Synthesizer enable 0x0

Table 227 bull SD10G65 RX Synthesizer Configuration Register 1

218 SYNTH_FREQ_MULT RW Frequency multiplier 0x2100

74 SYNTH_FREQM_1 RW Frequency m setting bits 3532 0x0

30 SYNTH_FREQN_1 RW Frequency n setting bits 3532 0x8

Bit Name Access Description Default31 SYNTH_SKIP_BIT_FWD RW Rising edge triggers bit skip forward in serial data

stream Used to align data to parallel interface boundaries

0x0

Table 226 bull SD10G65 Rx Synthesizer Configuration Register 0 (continued)

Registers

Address0xF143

2465 SD10G65 RX Synthesizer Configuration 4Short NameSD10G65_RX_SYNTH_CFG4

30 SYNTH_SKIP_BIT_REV RW Rising edge triggers bit skip reverse in serial data stream Used to align data to parallel interface boundaries

0x0

2726 SYNTH_DV_CTRL_I2E RW Controls the data valid behavior for the CDRLF I2 enable function b0 = 0 =gt external signal controls 1 =gt b1 controls

0x0

2524 SYNTH_DV_CTRL_I1M RW Controls the data valid behavior for the CDRLF I1 max function b0 = 0 =gt external signal controls 1 =gt b1 controls

0x0

2120 SYNTH_DV_CTRL_MD RW Controls the data valid behavior for the moebdiv select function b0 = 0 =gt external signal controls 1 =gt b1 controls

0x0

18 SYNTH_CPMD_DIG_SEL RW Cpmd dig select 0 Select bit 05 as cpmd (FX100 mode) 1 Use cpmd from core

0x0

17 SYNTH_CPMD_DIG_ENA RW Uses cpmd selected through synth_cpmd_dig_sel instead of cpmd from sample stage

0x0

16 SYNTH_AUX_ENA RW Enables clock for VScopeAPC auxiliary data chanels

0x1

148 SYNTH_PHASE_DATA RW Relationship phase centeredge 0x08

60 SYNTH_PHASE_AUX RW Relationship phase centeraux 0x08

Bit Name Access Description Default310 SYNTH_FREQM_0 RW Frequency m setting bits 310 0x00000000

Registers

Address0xF144

2466 SD10G65 Rx Synthesizer Register CDR Loopfilter ControlShort NameSD10G65_RX_SYNTH_CDRLF

Address0xF145

Register for CDR loopfilter control for SD10G65 RX SYNTH

2467 SD10G65 Rx Synthesizer 0 for Qualifier AccessShort NameSD10G65_RX_SYNTH_QUALIFIER0

Bit Name Access Description Default310 SYNTH_FREQN_0 RW Frequency n setting bits 310 0x00000000

Table 231 bull SD10G65 Rx Synthesizer Register CDR Loopfilter Control

Bit Name Access Description Default31 SYNTH_INTEG3_ENA RW Enables integrator 3 0x0

3026 SYNTH_INTEG3_DSEL RW Select filter dampinggain peaking when integrator 3 is enabled The control value is interpreted as signed value Positive values increase the damping (that is lowering the gain peaking) Negative values decease the damping (that is raising the gain peaking) The allowed programming range depends on the SYNTH_INTEG2_FSEL setting 0 lt= (SYNTH_INTEG2_FSEL - SYNTH_INTEG3_DSEL) lt= 53 SYNTH_INTEG2_FSEL - SYNTH_INTEG3_DSEL= 0 and SYNTH_INTEG2_FSEL - SYNTH_INTEG3_DSEL= 1 gives the same damping

0x00

2521 SYNTH_INTEG1_MAX1 RW Max value of integrator 1 during normal operation 0x02

2016 SYNTH_INTEG1_MAX0 RW Max value of integrator 1 during init phase 0x00

1511 SYNTH_INTEG1_LIM RW Limit of integrator 1 0x02

106 SYNTH_INTEG1_FSEL RW Frequency select of integrator 1 0x02

Registers

Address0xF146

Address0xF147

2469 SD10G65 Rx Synthesizer for Sync Control DataShort NameSD10G65_RX_SYNTH_SYNC_CTRL

Address0xF148

24610 F2DF ConfigurationStatusShort NameF2DF_CFG_STAT

Address0xF149

Configurationstatus register for the F2DF control logic

Table 232 bull SD10G65 Rx Synthesizer Register 0 for qualifier access

Bit Name Access Description Default20 SYNTH_CAPTURE_QUAL RW Rising edge captures qualifier for readback 0x0

1916 SYNTH_QUAL_I2_MSB RO MS bits of captured integrator 2 0x0

150 SYNTH_QUAL_I1 RO Captured integrator 1 value 0x0000

Table 233 bull SD10G65 Rx Synthesizer Register 1 for Qualifier Access

Bit Name Access Description Default310 SYNTH_QUAL_I2_LSB RO LS bits of captured integrator 2 0x00000000

Table 234 bull SD10G65 Rx Synthesizer Register for Sync Control Data

Bit Name Access Description Default30 SYNTH_SC_SYNC_TIMER_SEL RW Selects the synchronization period for the I2

value via sync control bus Must be disabled (0) when sync control test generator is used Coding in 3125 MHz clock cycles 0 disabled 1 2^6 2 2^715 2^20

0xF

Table 235 bull F2DF ConfigurationStatus

Bit Name Access Description Default2725 F2DF_SAMPLE_DIV RW Sampling divider sample every

2^f2df_sample_div parallel data word0x0

Registers

247 SD10G65 Tx SYNTH Configuration and Status 2471 SD10G65 Tx Synthesizer Configuration 0

Short NameSD10G65_TX_SYNTH_CFG0

Address0xF150

2117 F2DF_SIDE_DET_BIT_SEL RW Select bit from input data used for side detection Debug feature 31 select constant zero 30 select constant one

0x00

1614 F2DF_SIDE_DET_ONES_WEIGHT RW Sample 1 =gt increment 8-bit filter saturating counter by 2n Cnt gt= 0xC0 =gt ProperSide detected

0x0

1311 F2DF_SIDE_DET_ZEROS_WEIGHT RW Sample 0 =gt decrement 8-bit filter saturating counter by 2n Cnt lt0x40 =gt WrongSide detected

0x0

94 F2DF_TOG_DET_CNT RW Determines the number of samples that have to show at least one toggle

0x00

3 F2DF_DATA_VALID_PROPPER_SIDE RW Data valid value in ProperSide state 0 Data valid flagged only in Lock state1 Data valid also flagged in ProperSide state

0x0

0 F2DF_ENABLE RW F2df enable Enabling the f2df circuit automatically switches the input of the CDR-loop to the f2df control block (overrules synth_cpmd_dig_sel and synth_cpmd_dig_ena) and replaces the data valid signal from the core logic by the data valid signal generated by the f2df control logic

0x0

Table 236 bull SD10G65 Tx Synthesizer Configuration Register 0

1716 SYNTH_FBDIV_SEL RW Selects feedback divider setting 0x2

1311 SYNTH_CS_SPEED RW Common sync speed 0x0

10 SYNTH_LS_SPEED RW Lane sync speed 0x0

8 SYNTH_LS_ENA RW Lane sync enable 0x1

Table 235 bull F2DF ConfigurationStatus (continued)

Registers

2472 SD10G65 Tx Synthesizer Configuration 1Short NameSD10G65_TX_SYNTH_CFG1

Address0xF151

Address0xF152

7 SYNTH_DS_SPEED RW Dig sync speed 0x0

5 SYNTH_DS_ENA RW Dig sync enable 0x0

4 SYNTH_SPEED_SEL RW Selects circuit speed 0 For settings with synth_fbdiv_sel= 21 For setting with synth_fbdiv_sel smaller than 2

0x0

3 SYNTH_HRATE_ENA RW Half rate enable 0x0

Table 236 bull SD10G65 Tx Synthesizer Configuration Register 0 (continued)

Registers

Address0xF153

2475 SD10G65 SSC Generator Configuration 0Short NameSD10G65_SSC_CFG0

Address0xF154

Address0xF155

Table 240 bull SD10G65 SSC Generator Configuration Register 0

Bit Name Access Description Default3119 SSC_MOD_LIM RW SSC modulation amplitude limiter 0x0000

187 SSC_MOD_PERIOD RW SSC modulation periodamplitude 0x000

61 SSC_MOD_FREQ RW SSC modulation frequency fine tuning control 0x00

0 SSC_ENA RW SSC generator enable 0x0

Bit Name Access Description Default29 MLD_SYNC_SRC_SEL RW Select between the internal and external MLD

phase detector0 Internal1 External

0x0

2825 MLD_SYNC_CTRL RW Control of the internal MLD phase detector0 Enable1 Enable hyst 2 Enable window function3 Select window size

0x0

2423 MLD_SYNC_CLK_SEL RW Select the MLD clock source for the internal MLD phase detector

0x0

22 SYNC_CTRL_WRAP_INHIBIT RW Controls integrator 2 replica behavior0 Wrapping1 Saturating

0x0

2116 SYNC_CTRL_FSEL RW Frequency select of integrator 2 replica used for lane sync

0x31

Registers

248 SD10G65 Tx RCPLL Configuration and Status2481 SD10G65 Tx RCPLL Configuration 0

Short NameSD10G65_TX_RCPLL_CFG0

Address0xF160

2482 SD10G65 Tx RCPLL Configuration 1Short NameSD10G65_TX_RCPLL_CFG1

Address0xF161

10 SMOOTH_ENA RW Enables smooth generator 0x0

95 SSC_SD_GAIN RW SSC sigma delta gain 0x00

43 SSC_SYNC_POS RW SSC modulation start position on synchronization trigger

0x0

20 SSC_MOD_MUL RW SSC modulation period multiplier encoded 2n 0 =gt 1 1 =gt 2 2 =gt 4 3 =gt 8

0x0

Table 242 bull SD10G65 Tx RCPLL Configuration Register 0

0x0

ref_clk_frq0x00C6

Table 241 bull SD10G65 SSC Generator Configuration Register 1 (continued)

Registers

Address0xF162

2484 SD10G65 Tx RCPLL Status 0Short NameSD10G65_TX_RCPLL_STAT0

Address0xF163

0x3

0xA

Table 245 bull SD10G65 Tx RCPLL Status Register 0

0x0

Registers

25 WIS Channel (Device 0x2)Table 246 bull WIS Channel (Device 0x2)

Address Short Description Register Name Details0x00 WIS Control 1 WIS_CTRL1 Page 138

0x01 WIS Status 1 WIS_STAT1 Page 139

0x02 WIS Device Identifier 1 WIS_DEVID1 Page 140

0x04 WIS Speed Capability WIS_SPEED Page 140

0x05 WIS Devices in Package 1 WIS_DEVPKG1 Page 141

0x07 WIS Control 2 WIS_CTRL2 Page 142

0x09 WIS Test Pattern Error Counter WIS_TSTPAT_CNT Page 143

0x0E WIS Package Identifier 1 WIS_PKGID1 Page 144

0x0F WIS Package Identifier 2 WIS_PKGID2 Page 144

0x25 WIS Far-End Path Block Error Count WIS_REIP_CNT Page 146

0x27 WIS Tx J1 Octets 1ndash0 WIS_Tx_J1_Octets_1_0 Page 146

0x2A WIS Tx J1 Octets 7ndash6 WIS_Tx_J1_Octets_7_6 Page 147

0x2B WIS Tx J1 Octets 9ndash8 WIS_Tx_J1_Octets_9_8 Page 147

0x2C WIS Tx J1 Octets 11ndash10 WIS_Tx_J1_Octets_11_10 Page 148

0x2D WIS Tx J1 Octets 13ndash12 WIS_Tx_J1_Octets_13_12 Page 148

0x2E WIS Tx J1 Octets 15ndash14 WIS_Tx_J1_Octets_15_14 Page 148

0x2F WIS Rx J1 Octets 1ndash0 WIS_Rx_J1_Octets_1_0 Page 149

0x30 WIS Rx J1 Octets 3ndash2 WIS_Rx_J1_Octets_3_2 Page 149

0x37 WIS Far-End Line BIP Errors 1 WIS_REIL_CNT1 Page 151

0x39 WIS L-BIP Error Count 1 WIS_B2_CNT1 Page 152

0x3A WIS L-BIP Error Count 0 WIS_B2_CNT0 Page 153

0x3B WIS P-BIP Block Error Count WIS_B3_CNT Page 153

0x3C WIS S-BIP Error Count WIS_B1_CNT Page 153

Registers

0x4A WIS Rx J0 Octets 5ndash4 WIS_Rx_J0_Octets_5_4 Page 157

0x4B WIS Rx J0 Octets 7ndash6 WIS_Rx_J0_Octets_7_6 Page 157

0x4C WIS Rx J0 Octets 9ndash8 WIS_Rx_J0_Octets_9_8 Page 158

0x4D WIS Rx J0 Octets 11ndash10 WIS_Rx_J0_Octets_11_10 Page 158

0x4E WIS Rx J0 Octets 13ndash12 WIS_Rx_J0_Octets_13_12 Page 158

0xE5FF WIS Tx Control 1 EWIS_TXCTRL1 Page 159

0xE600 WIS Tx Control 2 EWIS_TXCTRL2 Page 159

0xE606 H4 Loopback FIFO Status LOOP_H4_FIFO_STAT Page 160

0xE611 E-WIS Tx A1A2 Octets EWIS_TX_A1_A2 Page 161

0xE612 E-WIS Tx Z0E1 Octets EWIS_TX_Z0_E1 Page 161

0xE613 E-WIS Tx F1D1 Octets EWIS_TX_F1_D1 Page 161

0xE614 E-WIS Tx D2D3 Octets EWIS_TX_D2_D3 Page 162

0xE615 E-WIS Tx C2H1 Octets EWIS_TX_C2_H1 Page 162

0xE616 E-WIS Tx H2H3 Octets EWIS_TX_H2_H3 Page 162

0xE617 E-WIS Tx G1K1 Octets EWIS_TX_G1_K1 Page 163

0xE618 E-WIS Tx K2F2 Octets EWIS_TX_K2_F2 Page 163

0xE61A E-WIS Tx D6H4 Octets EWIS_TX_D6_H4 Page 163

0xE61B E-WIS Tx D7D8 Octets EWIS_TX_D7_D8 Page 164

0xE61C E-WIS Tx D9Z3 Octets EWIS_TX_D9_Z3 Page 164

0xE61D E-WIS Tx D10D11 Octets EWIS_TX_D10_D11 Page 164

0xE61E E-WIS Tx D12Z4 Octets EWIS_TX_D12_Z4 Page 164

0xE61F E-WIS Tx S1Z1 Octets EWIS_TX_S1_Z1 Page 165

0xE621 E-WIS Tx N1 Octet EWIS_TX_N1 Page 165

0xE700 E-WIS Tx Trace Message Length Control EWIS_TX_MSGLEN Page 165

0xE800 E-WIS Tx J0 Octets 17ndash16 EWIS_Tx_J0_Octets_17_16 Page 166

Table 246 bull WIS Channel (Device 0x2) (continued)

Registers

0xE80A E-WIS Tx J0 Octets 37ndash36 EWIS_Tx_J0_Octets_37_36 Page 169

0xE80B E-WIS Tx J0 Octets 39ndash38 EWIS_Tx_J0_Octets_39_38 Page 169

0xE80C E-WIS Tx J0 Octets 41ndash40 EWIS_Tx_J0_Octets_41_40 Page 169

0xE80D E-WIS Tx J0 Octets 43ndash42 EWIS_Tx_J0_Octets_43_42 Page 170

0xE80E E-WIS Tx J0 Octets 45ndash44 EWIS_Tx_J0_Octets_45_44 Page 170

0xE80F E-WIS Tx J0 Octets 47ndash46 EWIS_Tx_J0_Octets_47_46 Page 170

0xE900 E-WIS Rx J0 Octets 17ndash16 EWIS_Rx_J0_Octets_17_16 Page 173

0xE90A E-WIS Rx J0 Octets 37ndash36 EWIS_Rx_J0_Octets_37_36 Page 176

0xE90B E-WIS Rx J0 Octets 39ndash38 EWIS_Rx_J0_Octets_39_38 Page 176

0xE90C E-WIS Rx J0 Octets 41ndash40 EWIS_Rx_J0_Octets_41_40 Page 176

0xE90D E-WIS Rx J0 Octets 43ndash42 EWIS_Rx_J0_Octets_43_42 Page 177

0xE90E E-WIS Rx J0 Octets 45ndash44 EWIS_Rx_J0_Octets_45_44 Page 177

Registers

0xE90F E-WIS Rx J0 Octets 47ndash46 EWIS_Rx_J0_Octets_47_46 Page 177

0xEA00 E-WIS Tx J1 Octets 17ndash16 EWIS_Tx_J1_Octets_17_16 Page 180

0xEA0A E-WIS Tx J1 Octets 37ndash36 EWIS_Tx_J1_Octets_37_36 Page 183

0xEA0B E-WIS Tx J1 Octets 39ndash38 EWIS_Tx_J1_Octets_39_38 Page 183

0xEA0C E-WIS Tx J1 Octets 41ndash40 EWIS_Tx_J1_Octets_41_40 Page 183

0xEA0D E-WIS Tx J1 Octets 43ndash42 EWIS_Tx_J1_Octets_43_42 Page 184

0xEA0E E-WIS Tx J1 Octets 45ndash44 EWIS_Tx_J1_Octets_45_44 Page 184

0xEA0F E-WIS Tx J1 Octets 47ndash46 EWIS_Tx_J1_Octets_47_46 Page 184

0xEB00 E-WIS Rx J1 Octets 17ndash16 EWIS_Rx_J1_Octets_17_16 Page 187

Registers

0xEB0A E-WIS Rx J1 Octets 37ndash36 EWIS_Rx_J1_Octets_37_36 Page 190

0xEB0B E-WIS Rx J1 Octets 39ndash38 EWIS_Rx_J1_Octets_39_38 Page 190

0xEB0C E-WIS Rx J1 Octets 41ndash40 EWIS_Rx_J1_Octets_41_40 Page 190

0xEB0D E-WIS Rx J1 Octets 43ndash42 EWIS_Rx_J1_Octets_43_42 Page 191

0xEB0E E-WIS Rx J1 Octets 45ndash44 EWIS_Rx_J1_Octets_45_44 Page 191

0xEB0F E-WIS Rx J1 Octets 47ndash46 EWIS_Rx_J1_Octets_47_46 Page 191

0xEC00 E-WIS Rx Framer Control 1 EWIS_RX_FRM_CTRL1 Page 194

0xEC02 E-WIS Loss of Frame Control 1 EWIS_LOF_CTRL1 Page 195

0xEC10 E-WIS Rx Control 1 EWIS_RX_CTRL1 Page 196

0xEC20 E-WIS Rx Trace Message Length Control EWIS_RX_MSGLEN Page 197

0xEC30 E-WIS Rx Error Force Control 1 EWIS_RX_ERR_FRC1 Page 197

0xEC40 E-WIS Mode Control EWIS_MODE_CTRL Page 200

0xEC50 E-WIS PRBS31 Analyzer Control EWIS_PRBS31_ANA_CTRL Page 201

0xEC51 E-WIS PRBS31 Analyzer Status EWIS_PRBS31_ANA_STAT Page 202

0xEC60 E-WIS Performance Monitor Control EWIS_PMTICK_CTRL Page 202

0xEC61 E-WIS Counter Configuration EWIS_CNT_CFG Page 203

0xEC62 E-WIS Counter Status EWIS_CNT_STAT Page 204

0xEC80 E-WIS P-REI Counter 1 MSW EWIS_REIP_CNT1 Page 204

0xEC81 E-WIS P-REI Counter 0 LSW EWIS_REIP_CNT0 Page 205

0xEC90 E-WIS L-REI Counter 1 MSW EWIS_REIL_CNT1 Page 205

0xEC91 E-WIS L-REI Counter 0 LSW EWIS_REIL_CNT0 Page 205

0xECB0 E-WIS S-BIP Error Counter 1 MSW EWIS_B1_ERR_CNT1 Page 205

Registers

WIS Control 1Short NameWIS_CTRL1

Address0x00

0xECB1 E-WIS S-BIP Error Counter 0 LSW EWIS_B1_ERR_CNT0 Page 206

0xECB2 E-WIS L-BIP Error Counter 1 MSW EWIS_B2_ERR_CNT1 Page 206

0xECB3 E-WIS L-BIP Error Counter 0 LSW EWIS_B2_ERR_CNT0 Page 206

0xECB4 E-WIS P-BIP Error Counter 1 MSW EWIS_B3_ERR_CNT1 Page 207

0xECB5 E-WIS P-BIP Error Counter 0 LSW EWIS_B3_ERR_CNT0 Page 207

0xEDFF E-WIS Rx to Tx Control EWIS_RXTX_CTRL Page 207

0xEE00 E-WIS Interrupt Pending 1 EWIS_INTR_PEND1 Page 209

0xEE01 E-WIS Interrupt Mask A 1 EWIS_INTR_MASKA_1 Page 211

0xEE02 E-WIS Interrupt Mask B 1 EWIS_INTR_MASKB_1 Page 212

0xEE03 E-WIS Interrupt Status 2 EWIS_INTR_STAT2 Page 213

0xEE07 WIS Fault Mask WIS_FAULT_MASK Page 222

0xEE0A E-WIS Interrupt Mask B 3 EWIS_INTR_MASKB_3 Page 225

0xEE0B Threshold Error Status THRESH_ERR_STAT Page 226

0xEE10 WIS REI-P Threshold Level 1 WIS_REIP_THRESH_LVL1 Page 227

0xEE12 WIS REI-L Threshold Level 1 WIS_REIL_THRESH_LVL1 Page 228

0xEE14 WIS B1 Threshold Level 1 WIS_B1_THRESH_LVL1 Page 228

Table 247 bull WIS Control 1

Bit Name Access Description Default15 SOFT_RST One-shot MDIO manageable device (MMD) software reset

This register resets all portions of the channel on the host side of the failover mux Data path logic and configuration registers are reset0= Normal operation1= Reset

0x0

Registers

251 WIS Status 1Short NameWIS_STAT1

Address0x01

14 LPBK_H4 RW Enables WIS system loopback (loopback H4)0= Disable1= Enable

0x0

13 SPEED_SEL_A RO Speed selection0= Unspecified1= Operates at 10 Gbps or above

0x1

11 LOW_PWR_WIS RW The channels data path is placed into low power mode with this register The PMA in this channel is also placed into low power mode regardless of the channel cross connect configuration The PMD_TRANSMIT_DISABLEGLOBAL_PMD_TRANSMIT_DISABLE register state can be transmitted from a GPIO pin to shut off an optics modules Tx driver0= Normal operation1= Low power mode

0x0

6 SPEED_SEL_B RO Speed selection0= Unspecified1= Operates at 10 Gbps or above

0x1

52 SPEED_SEL_C RO Speed selection1xxx Reservedx1xx Reservedxx1x Reserved0001 Reserved0000 10 Gbps

0x0

Table 248 bull WIS Status 1

Bit Name Access Description Default7 FAULT RO WIS fault status The alarm conditions that cause

the WIS fault status to be asserted are configured in the WIS_FAULT_MASK register Based on the WIS_FAULT_MASK setting the WIS fault status can be asserted when the following alarm conditions exist OOF LOS LOF LOP-P AIS-L AIS-P LCD-P PLM-P RDI-L far-end AIS-P and far-end PLM-P This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= No faults asserted1= Fault asserted

0x0

Table 247 bull WIS Control 1 (continued)

Registers

252 WIS Device Identifier2521 WIS Device Identifier 1

Short NameWIS_DEVID1

Address0x02

2522 WIS Device Identifier 2Short NameWIS_DEVID2

Address0x03

253 WIS Speed CapabilityShort NameWIS_SPEED

2 LNK_STAT RO WIS receive link status Link up means no AIS-P AIS-L PLM-P LOP-P or SEF alarms This is a sticky bit that latches the low state The latch-low bit is cleared when the register is read0= WIS link down (AIS-P= 1 or AIS-L= 1 or PLM-P= 1 or WIS SEF= 1 or LOP-P= 1)1= WIS link up (AIS-P= 0 and AIS-L= 0 and PLM-P= 0 and SEF= 0 and LOP-P= 0)

0x1

1 LOW_PWR_ABILITY RO Low power mode support0= Supported1= Not supported

0x1

Table 249 bull WIS Device Identifier 1

Bit Name Access Description Default150 DEV_ID_MSW RO Upper 16 bits of a 32-bit unique WIS device

0x0007

Bit Name Access Description Default150 DEV_ID_LSW RO Lower 16 bits of a 32-bit unique WIS device

0x0400

Table 248 bull WIS Status 1 (continued)

Registers

Address0x04

254 WIS Devices2541 WIS Devices in Package 1

Short NameWIS_DEVPKG1

Address0x05

2542 WIS Devices in Package 2Short NameWIS_DEVPKG2

Table 251 bull WIS Speed Capability

Bit Name Access Description Default0 RATE_ABILITY RO WIS rate capability

0= Not capable of 10 Gbps1= Capable of 10 Gbps

0x1

Table 252 bull WIS Devices in Package 1

Bit Name Access Description Default5 DTE_XS_PRES RO Indicates if DTE XS is present in the package

0= Not present1= Present

0x0

4 PHY_XS_PRES RO Indicates if PHY XS is present in the package 0= Not present1= Present

0x1

3 PCS_PRES RO Indicates if PCS is present in the package0= Not present1= Present

0x1

2 WIS_PRES RO Indicates if WIS is present in the package0= Not present1= Present

0x1

1 PMD_PMA_PRES RO Indicates if PMAPMD is present in the package0= Not present1= Present

0x1

0 CLS22_PRES RO Indicates if Clause 22 registers are present in the package0= Not present1= Present

0x0

Registers

Address0x06

255 WIS Control 2Short NameWIS_CTRL2

Address0x07

Bit Name Access Description Default15 Vendor_spec_dev_2_present RO Indicates if vendor-specific device 2 is present in

the package0= Not present1= Present

0x0

14 Vendor_spec_dev_1_present RO Indicates if vendor-specific device 1 is present in the package0= Not present1= Present

0x0

Bit Name Access Description Default5 TEST_PRBS31_ANA RW Enable WIS PRBS31 test pattern checking

function0= Disable1= Enable

0x0

4 TEST_PRBS31_GEN RW Enable WIS PRBS31 test pattern generation function Transmission of the PRBS31 pattern has priority over the square wave and mixed frequency test patterns if TEST_PAT_GEN in this register is also high0= Disable1= Enable

0x0

3 TEST_PAT_SEL RW Selects the pattern type sent by the transmitter when bit TEST_PAT_GEN in this register is high0= Mixed frequency test pattern1= Square wave

0x0

2 TEST_PAT_ANA RW Enables the WIS test pattern checker Doing so prevents the loss of code-group delineation (LCD-P) alarm from being set while the WIS is receiving the mixed frequency test pattern0= Disable1= Enable

0x0

1 TEST_PAT_GEN RW Enable WIS test pattern generation0= Disable1= Enable

0x0

Registers

Address0x08

257 WIS Test Pattern Error CounterShort NameWIS_TSTPAT_CNT

0 WAN_MODE RW Enable 10GBASE-W logic and sets the speed of the WIS-PMA interface to 995328 Gbps The proper reference clock frequency must be provided to set the data rate

Note There are multiple ways to enable WAN mode

0= Disable1= Enable

0x0

Bit Name Access Description Default1514 DEV_PRES RO Reflects the presence of a MMD responding at

this address00 No device responding at this address01 No device responding at this address10 Device responding at this address11 No device responding at this address

0xA

1 PRBS31_ABILITY RO Indicates if WIS supports PRBS31 pattern testing0= Not supported1= Supported

0x1

0 BASE_R_ABILITY RO Indicates if WIS supports a bypass to allow support of 10GBASE-R0= Not supported1= Supported

0x1

Registers

Address0x09

258 WIS Package Identifier2581 WIS Package Identifier 1

Short NameWIS_PKGID1

Address0x0E

2582 WIS Package Identifier 2Short NameWIS_PKGID2

Address0x0F

Table 256 bull WIS Test Pattern Error Counter

Bit Name Access Description Default150 TSTPAT_CNT RO PRBS31 test pattern error counter The saturating

counter is cleared when the register is read The error count is not valid until the sync status in register bit EWIS_PRBS31_ANA_STATPRBS31_ANA_STATE is asserted The error count in this register can be incremented while the checker is acquiring sync Read this register to clear the invalid error count when sync is achieved Once synchronization is achieved any future loss of synchronization will not prevent the error counter from accumulating

0x0000

Table 257 bull WIS Package Identifier 1

Bit Name Access Description Default150 PKG_ID_MSW RO Upper 16 bits of a 32-bit unique WIS package

0x0000

Bit Name Access Description Default150 PKG_ID_LSW RO Lower 16 bits of a 32-bit unique WIS package

0x0000

Registers

Address0x21

Bit Name Access Description Default11 SEF RO Severely errored frame This is a sticky bit that

latches the high state The latch-high bit is cleared when the register is read0= No SEF detected1= SEF detected

0x0

10 FEPLMP_LCDP RO Indicates far-end PLM-PLCD-P defect in WIS Rx The latch-high bit is cleared when the register is read0= No far-end path label mismatchloss of code-group delineation1= Far-end path label mismatchloss of code-group delineation

0x0

9 FEAISP_LOPP RO Indicates far-end AIS-PLOP-P defect in WIS Rx The latch-high bit is cleared when the register is read0= Far-end path alarm indication signalpath loss of pointer1= No far-end path alarm indication signalpath loss of pointer

0x0

7 LOF RO Loss of frame The latch-high bit is cleared when the register is read0= Loss of frame flag lowered1= Loss of frame flag raised

0x0

6 LOS RO Loss of signal The latch-high bit is cleared when the register is read0= Loss of signal flag lowered1= Loss of signal flag raised

0x0

5 RDIL RO Line remote defect indication The latch-high bit is cleared when the register is read0= Line remote defect flag lowered1= Line remote defect flag raised

0x0

4 AISL RO Line alarm indication signal The latch-high bit is cleared when the register is read0= Line alarm indication flag lowered1= Line alarm indication flag raised

0x0

3 LCDP RO Path loss of code-group delineation The latch-high bit is cleared when the register is read0= Path loss of code-group delineation flag lowered1= Path loss of code-group delineation flag raised

0x0

Registers

2510 WIS Far-End Path Block Error CountShort NameWIS_REIP_CNT

Address0x25

2511 Transmitted Path Trace Message OctetsThe number of octets present in the transmitted path trace message is determined by EWIS_TX_MSGLENJ1_TXLEN Octet 0 is used when the trace message length is 1 byte When a 16-byte trace message length is selected octet 0 is the first octet transmitted and octet 15 is the last octet When a 64-byte trace message length is selected octet 0 is the first octet transmitted and octet 63 is the last octet Octets 16 to 63 are located in registers EWIS_Tx_J1_Octets_17_16 to EWIS_Tx_J1_Octets_63_62

25111 WIS Tx J1 Octets 1ndash0Short NameWIS_Tx_J1_Octets_1_0

Address0x27

2 PLMP RO Path label mismatch The latch-high bit is cleared when the register is read0= Path label mismatch flag lowered1= Path label mismatch flag raised

0x0

1 AISP RO Path alarm indication signal The latch-high bit is cleared when the register is read0= Path alarm indication signal lowered1= Path alarm indication signal raised

0x0

0 LOPP RO Loss of pointer The latch-high bit is cleared when the register is read0= Loss of pointer flag lowered1= Loss of pointer flag raised

0x0

Table 260 bull WIS Far-End Path Block Error Count

Bit Name Access Description Default150 REIP_CNT RO Far-end path block error count Counter wraps

around to 0 when it is incremented beyond its maximum error count of 65535 Cleared on channel reset

0x0000

Table 261 bull WIS Tx J1 Octets 1ndash0

Bit Name Access Description Default158 TX_J1_octet_1 RW Contains octet 1 of the transmitted path trace

message0x00

70 TX_J1_octet_0 RW Contains octet 0 of the transmitted path trace message

0x00

Registers

Address0x28

Address0x29

Address0x2A

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0x2B

Address0x2C

Address0x2D

Address0x2E

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x89

Registers

2512 Received Path Trace Message OctetsThe number of octets present in the received path trace message is determined by EWIS_RX_MSGLENJ1_RX_LEN Octet 0 is used when the trace message length is 1 byte When a 16- byte trace message length is selected octet 0 is the first octet received and octet 15 is the last octet When a 64-byte trace message length is selected octet 0 is the first octet received and octet 63 is the last octet Octets 16 to 63 are located in registers EWIS_Rx_J1_Octets_17_16 to EWIS_Rx_J1_Octets_63_62

25121 WIS Rx J1 Octets 1ndash0Short NameWIS_Rx_J1_Octets_1_0

Address0x2F

Address0x30

0x00

Table 269 bull WIS Rx J1 Octets 1ndash0

Bit Name Access Description Default158 RX_J1_octet_1 RO Contains octet 1 of the received path trace

message0x00

70 RX_J1_octet_0 RO Contains octet 0 of the received path trace message

0x00

message0x00

0x00

Table 268 bull WIS Tx J1 Octets 15ndash14 (continued)

Registers

Address0x31

Address0x32

Address0x33

Address0x34

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0x35

Address0x36

2513 WIS Line Counters25131 WIS Far-End Line BIP Errors 1

Short NameWIS_REIL_CNT1

0x00

message0x00

0x00

message0x00

0x00

Table 274 bull WIS Rx J1 Octets 11ndash10 (continued)

Registers

Address0x37

25132 WIS Far-End Line BIP Errors 0Short NameWIS_REIL_CNT0

Address0x38

25133 WIS L-BIP Error Count 1Short NameWIS_B2_CNT1

Table 277 bull WIS Far-End Line BIP Errors 1

Bit Name Access Description Default150 REIL_ERR_CNT_MSW RO Most significant word of the WIS far end line BIP

error counter The counter does not saturate when the maximum count has been exceeded Reading register WIS_REIL_CNT1 latches the 32-bit counter value into a pair of 16-bit registers The most significant counter bits are located in WIS_REIL_CNT1 The least significant bits are located in WIS_REIL_CNT0 Subsequent reads of address WIS_REIL_CNT0 will return the latched value and will not change the latched register contents The counter can only be cleared by resetting the WIS logic block

0x0000

Bit Name Access Description Default150 REIL_ERR_CNT_LSW RO Least significant word of the WIS far end line BIP

0x0000

Registers

Address0x39

Address0x3A

25135 WIS P-BIP Block Error CountShort NameWIS_B3_CNT

Address0x3B

25136 WIS S-BIP Error CountShort NameWIS_B1_CNT

Table 279 bull WIS L-BIP Error Count 1

Bit Name Access Description Default150 B2_CNT_MSW RO Most significant word of the WIS line BIP error

counter The counter does not saturate when the maximum count has been exceeded Reading register WIS_B2_CNT1 latches the 32-bit counter value into a pair of 16-bit registers The most significant counter bits are associated with WIS_B2_CNT1 The least significant bits appear in WIS_B2_CNT0 Subsequent reads of address WIS_B2_CNT0 will return the latched value and will not change the latched register contents The counter can only be cleared by resetting the WIS logic block

0x0000

Bit Name Access Description Default150 B2_CNT_LSW RO Least significant word of the WIS line BIP error

0x0000

Table 281 bull WIS P-BIP Block Error Count

Bit Name Access Description Default150 B3_CNT RO Path block error count The counter does not

saturate when the maximum count has been exceeded The counter can only be cleared by resetting the WIS logic block

0x0000

Registers

Address0x3C

2514 Transmitted Section Trace Message OctetsThe number of octets present in the transmitted section trace message is determined by EWIS_TX_MSGLENJ0_TXLEN Octet 0 is used when the trace message length is 1 byte When a 16- byte trace message length is selected octet 0 is the first octet transmitted and octet 15 is the last octet When a 64-byte trace message length is selected octet 0 is the first octet transmitted and octet 63 is the last octet Octets 16 to 63 are located in registers EWIS_Tx_J0_Octets_17_16 to EWIS_Tx_J0_Octets_63_62

Address0x40

Address0x41

Table 282 bull WIS S-BIP Error Count

Bit Name Access Description Default150 B1_CNT RO Section BIP error count The counter does not

0x0000

Bit Name Access Description Default158 TX_J0_octet_1 RW Contains octet 1 of the transmitted section trace

message0x00

70 TX_J0_octet_0 RW Contains octet 0 of the transmitted section trace message

0x00

message0x00

0x00

Registers

Address0x42

Address0x43

Address0x44

Address0x45

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0x46

Address0x47

2515 Received Section Trace Message OctetsThe number of octets present in the received section trace message is determined by EWIS_RX_MSGLENJ0_RX_LEN Octet 0 is used when the trace message length is 1 byte When a 16- byte trace message length is selected octet 0 is the first octet received and octet 15 is the last octet When a 64-byte trace message length is selected octet 0 is the first octet received and octet 63 is the last octet Octets 16 to 63 are located in registers EWIS_Rx_J0_Octets_17_16 to EWIS_Rx_J0_Octets_63_62

0x00

message0x00

0x00

message0x89

0x00

Registers

Address0x48

Address0x49

Address0x4A

Address0x4B

Bit Name Access Description Default158 RX_J0_octet_1 RO Contains octet 1 of the received section trace

message0x00

70 RX_J0_octet_0 RO Contains octet 0 of the received section trace message

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0x4C

Address0x4D

Address0x4E

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0x4F

2516 EWIS Tx Control25161 WIS Tx Control 1

Short NameEWIS_TXCTRL1

Address0xE5FF

25162 WIS Tx Control 2Short NameEWIS_TXCTRL2

Address0xE600

message0x00

0x00

Table 299 bull WIS Tx Control 1

Bit Name Access Description Default0 TX_SS RW Contents of SS bits in transmitted H1 overhead

bytes 2ndash192 (State of SS bits in the first H1 byte is determined by EWIS_TX_C2_H1TX_H1)0= SS bits set to 2b001= SS bits set to 2b10

0x0

Bit Name Access Description Default15 REIL_TXBLK_MODE RW Selects use of B2 block error count or bit error

count mode to generate the M0M1 bytes for REI-L back reporting0= Bit error mode1= Block error mode

0x0

14 REIP_TXBLK_MODE RW Selects use of B3 block error count or bit error count mode to generate the G1 byte for REI-P back reporting0= Bit error mode1= Block error mode

0x0

12 SCR RW Enable transmit WIS scrambler0= Disable1= Enable

0x1

Registers

2517 H4 Loopback FIFO StatusShort NameLOOP_H4_FIFO_STAT

11 FRC_TX_TIMP RW Force transmission of a TIM-P condition within the G1 byte0= Normal operation1= Force TIM-P

0x0

10 ERDI_TX_MODE RW Selects ERDI as the transmit WIS G1 byte mode0= RDI mode1= ERDI mode

0x1

9 SDH_TX_MODE RW Selects the format of the WIS frame structure0= SONET mode1= SDH mode

0x1

8 TX_CLEAR_B RW WIS transmit clear B 0x0

74 SQ_WV_PW RW Select the transmit WIS square wave test pattern length0000ndash0011 Invalid0100 4 zeros and 4 ones0101 5 zeros and 5 ones0110 6 zeros and 6 ones0111 7 zeros and 7 ones1000 8 zeros and 8 ones1001 9 zeros and 9 ones1010 10 zeros and 10 ones1011 11 zeros and 11 ones1100ndash1111 Invalid

0x4

3 TX_PERF_MON RW Performance monitor0= Normal operation1= Disable AIS-L

0x0

2 FRC_TX_RDI RW Force transmission of RDI-L in the K2 byte0= Normal operation1= Force RDI-L

0x0

1 FRC_TX_AISL RW Force transmission of AIS-L in the K2 byte AIS-L will take precedence over RDI-L if both are asserted0= Normal operation1= Force AIS-L

0x0

Table 300 bull WIS Tx Control 2 (continued)

Registers

Address0xE606

2518 E-WIS Tx Octets25181 E-WIS Tx A1A2 Octets

Short NameEWIS_TX_A1_A2

Address0xE611

25182 E-WIS Tx Z0E1 OctetsShort NameEWIS_TX_Z0_E1

Address0xE612

25183 E-WIS Tx F1D1 OctetsShort NameEWIS_TX_F1_D1

Table 301 bull LOOP_H4_FIFO_STAT

Bit Name Access Description Default1 Loop_H4_FIFO_Overflow RO Loopback H4 FIFO overflow status This is a

sticky bit that latches the high state The latch-high bit is cleared when the register is read0= Normal operation1= Overunder flow condition

0x0

0 Loop_H4_FIFO_Sync_Inhibit RW Selects if FIFOs sync inhibit feature is enabled0= Disabled1= Enabled

0x0

Table 302 bull E-WIS Tx A1A2 Octets

Bit Name Access Description Default158 TX_A1 RW A1 byte to be transmitted when the TOSI data is

inactive0xF6

70 TX_A2 RW A2 byte to be transmitted when the TOSI data is inactive

0x28

Table 303 bull E-WIS Tx Z0E1 Octets

Bit Name Access Description Default158 TX_Z0 RW Z0 byte to be transmitted when the TOSI data is

inactive0xCC

70 TX_E1 RW E1 byte to be transmitted when the TOSI data is inactive

0x00

Registers

Address0xE613

25184 E-WIS Tx D2D3 OctetsShort NameEWIS_TX_D2_D3

Address0xE614

25185 E-WIS Tx C2H1 OctetsShort NameEWIS_TX_C2_H1

Address0xE615

25186 E-WIS Tx H2H3 OctetsShort NameEWIS_TX_H2_H3

Address0xE616

Table 304 bull E-WIS Tx F1D1 Octets

Bit Name Access Description Default158 TX_F1 RW F1 byte to be transmitted when the TOSI data is

inactive0x00

70 TX_D1 RW D1 byte to be transmitted when the TOSI data is inactive

0x00

Table 305 bull E-WIS Tx D2D3 Octets

Bit Name Access Description Default158 TX_D2 RW D2 byte to be transmitted when the TOSI data is

inactive0x00

0x00

Table 306 bull E-WIS Tx C2H1 Octets

Bit Name Access Description Default158 TX_C2 RW C2 byte to be transmitted 0x1A

70 TX_H1 RW H1 byte to be transmitted 0x62

Table 307 bull E-WIS Tx H2H3 Octets

Bit Name Access Description Default158 TX_H2 RW H2 byte to be transmitted when the TOSI data is

inactive0x0A

70 TX_H3 RW H3 byte to be transmitted when the TOSI data is inactive

0x00

Registers

25187 E-WIS Tx G1K1 OctetsShort NameEWIS_TX_G1_K1

Address0xE617

25188 E-WIS Tx K2F2 OctetsShort NameEWIS_TX_K2_F2

Address0xE618

Address0xE619

251810 E-WIS Tx D6H4 OctetsShort NameEWIS_TX_D6_H4

Address0xE61A

Table 308 bull E-WIS Tx G1K1 Octets

Bit Name Access Description Default158 TX_G1 RW G1 byte to be transmitted when the TOSI data is

inactive0x00

70 TX_K1 RW K1 byte to be transmitted when the TOSI data is inactive

0x00

Table 309 bull E-WIS Tx K2F2 Octets

Bit Name Access Description Default158 TX_K2 RW K2 byte to be transmitted when the TOSI data is

inactive0x00

70 TX_F2 RW F2 byte to be transmitted 0x00

inactive0x00

0x00

Table 311 bull E-WIS Tx D6H4 Octets

inactive0x00

Registers

Address0xE61B

251812 E-WIS Tx D9Z3 OctetsShort NameEWIS_TX_D9_Z3

Address0xE61C

Address0xE61D

inactive0x00

0x00

Table 313 bull E-WIS Tx D9Z3 Octets

inactive0x00

70 TX_Z3 RW Z3 byte to be transmitted 0x00

inactive0x00

0x00

Table 311 bull E-WIS Tx D6H4 Octets (continued)

Registers

Address0xE61E

251815 E-WIS Tx S1Z1 OctetsShort NameEWIS_TX_S1_Z1

Address0xE61F

Address0xE620

251817 E-WIS Tx N1 OctetShort NameEWIS_TX_N1

Address0xE621

2519 E-WIS Tx Trace Message Length ControlShort NameEWIS_TX_MSGLEN

inactive0x00

Table 316 bull E-WIS Tx S1Z1 Octets

Bit Name Access Description Default158 TX_S1 RW S1 byte to be transmitted when the TOSI data is

inactive0x0F

70 TX_Z1 RW Z1 byte to be transmitted when the TOSI data is inactive

0x00

inactive0x00

0x00

Table 318 bull E-WIS Tx N1 Octet

Bit Name Access Description Default158 TX_N1 RW N1 byte to be transmitted 0x00

Registers

Address0xE700

2520 Transmitted Section Trace Message OctetsTransmitted section trace message octets 16 to 63 are used when a 64-byte section trace message is selected in EWIS_TX_MSGLENJ0_TXLEN Octet 0 is the first octet transmitted and octet 63 is the last octet Octets 0 to 15 are located in registers WIS_Tx_J0_Octets_1_0 to WIS_Tx_J0_Octets_15_14

25201 E-WIS Tx J0 Octets 17ndash16Short NameEWIS_Tx_J0_Octets_17_16

Address0xE800

Address0xE801

Table 319 bull E-WIS Tx Trace Message Length Control

Bit Name Access Description Default32 J0_TXLEN RW Selects length of transmitted section trace

message (J0)Trace length00 16 bytes01 64 bytes10 1 byte11 1 byte

0x0

10 J1_TXLEN RW Selects length of transmitted path trace message (J1)Trace length00 16 bytes01 64 bytes10 1 byte11 1 byte

0x0

Table 320 bull E-WIS Tx J0 Octets 17ndash16

message 0x00

0x00

message 0x00

Registers

Address0xE802

Address0xE803

Address0xE804

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Table 321 bull E-WIS Tx J0 Octets 19ndash18 (continued)

Registers

Address0xE805

Address0xE806

Address0xE807

Address0xE808

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xE809

Address0xE80A

Address0xE80B

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Registers

Address0xE80C

Address0xE80D

Address0xE80E

Address0xE80F

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xE810

Address0xE811

Address0xE812

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Registers

Address0xE813

Address0xE814

Address0xE815

Address0xE816

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xE817

2521 Received Section Trace Message OctetsReceived section trace message octets 16 to 63 are used when a 64-byte section trace message is selected in EWIS_RX_MSGLENJ0_RX_LEN Octet 0 is the first octet received and octet 63 is the last octet Octets 0 to 15 are located in registers WIS_Rx_J0_Octets_3_2 to WIS_Rx_J0_Octets_15_14

25211 E-WIS Rx J0 Octets 17ndash16Short NameEWIS_Rx_J0_Octets_17_16

Address0xE900

Address0xE901

0x00

message 0x00

0x00

Table 344 bull E-WIS Rx J0 Octets 17ndash16

message0x00

0x00

message0x00

Registers

Address0xE902

Address0xE903

Address0xE904

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Table 345 bull E-WIS Rx J0 Octets 19ndash18 (continued)

Registers

Address0xE905

Address0xE906

Address0xE907

Address0xE908

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xE909

Address0xE90A

Address0xE90B

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0xE90C

Address0xE90D

Address0xE90E

Address0xE90F

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xE910

Address0xE911

Address0xE912

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0xE913

Address0xE914

Address0xE915

Address0xE916

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xE917

2522 Transmitted Path Trace Message OctetsTransmitted path trace message octets 16 to 63 are used when a 64-byte path trace message is selected in EWIS_TX_MSGLENJ1_TXLEN Octet 0 is the first octet transmitted and octet 63 is the last octet Octets 0 to 15 are located in registers WIS_Tx_J1_Octets_1_0 to WIS_Tx_J1_Octets_15_14

Address0xEA00

Address0xEA01

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xEA02

Address0xEA03

Address0xEA04

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0xEA05

Address0xEA06

Address0xEA07

Address0xEA08

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xEA09

Address0xEA0A

Address0xEA0B

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0xEA0C

Address0xEA0D

Address0xEA0E

Address0xEA0F

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xEA10

Address0xEA11

Address0xEA12

0x00

message0x00

0x00

message0x00

0x00

message0x00

0x00

Registers

Address0xEA13

Address0xEA14

Address0xEA15

Address0xEA16

message0x00

0x00

message0x00

0x00

message0x00

0x00

message0x00

Registers

Address0xEA17

2523 Received Path Trace Message OctetsReceived path trace message octets 16 to 63 are used when a 64-byte path trace message is selected in EWIS_RX_MSGLENJ1_RX_LEN Octet 0 is the first octet received and octet 63 is the last octet Octets 0 to 15 are located in registers WIS_Rx_J1_Octets_1_0 to WIS_Rx_J1_Octets_15_14

Address0xEB00

Address0xEB01

0x00

message0x00

0x00

message0x00

0x00

message 0x00

Registers

Address0xEB02

Address0xEB03

Address0xEB04

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Registers

Address0xEB05

Address0xEB06

Address0xEB07

Address0xEB08

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xEB09

Address0xEB0A

Address0xEB0B

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Registers

Address0xEB0C

Address0xEB0D

Address0xEB0E

Address0xEB0F

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xEB10

Address0xEB11

Address0xEB12

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

Registers

Address0xEB13

Address0xEB14

Address0xEB15

Address0xEB16

message 0x00

0x00

message 0x00

0x00

message 0x00

0x00

message 0x00

Registers

Address0xEB17

2524 E-WIS Rx Framer Control25241 E-WIS Rx Framer Control 1

Short NameEWIS_RX_FRM_CTRL1

Address0xEC00

25242 E-WIS Rx Framer Control 2Short NameEWIS_RX_FRM_CTRL2

0x00

message 0x00

0x00

Table 416 bull E-WIS Rx Framer Control 1

Bit Name Access Description Default1410 HUNT_A1 RW The number of consecutive A1 octets the receive

framer must find before it can exit the HUNT state0 Undefined1ndash16 1ndash1617ndash31 Undefined

0x04

95 PRESYNC_A1 RW The number of consecutive A1 octets in the pre-sync pattern preceding the first A2 octet0 11ndash16 1ndash1617ndash31 16

0x10

40 PRESYNC_A2 RW The number of consecutive A2 octets in the pre-sync pattern following the last A1 octet0 Only the four MSB of the first A2 byte are compared1ndash16 1ndash1617ndash31 16

0x10

Registers

Address0xEC01

25243 E-WIS Loss of Frame Control 1Short NameEWIS_LOF_CTRL1

Address0xEC02

Bit Name Access Description Default128 SYNC_PAT RW Synchronization pattern to be used after the pre-

sync pattern has been detected0 Sync pattern is A1 plus 4 most significant bits of A21 Sync pattern is 2 A1s plus 1 A2 (A1A1A2)2ndash16 Sync pattern is the number of consecutive A1s followed by the same number of A2s (that is the sync pattern is A1A1A2A2 when 2 is the setting)17ndash31 Undefined

0x02

74 SYNC_ENTRY_CNT RW Number of consecutive frame boundaries to be detected after finding the pre-sync pattern before the framer can enter the SYNC state0 11ndash15 1ndash15

0x4

30 SYNC_EXIT_CNT RW Number of consecutive frame boundary location errors tolerateddetected before exiting the SYNC state0 11ndash15 1ndash15

0x4

Table 418 bull E-WIS Loss of Frame Control 1

Bit Name Access Description Default116 LOF_T1 RW Defines the number of frames periods (nominally

125 microS) during which OOF must persist to trigger LOF This is not a count of continuous frames An integrating counter is used0x0 Undefined0x1 1 frame time (125 micros)0x2 2 frame times 250 micros)0x18 24 frame times 3 ms)0x3F 63 frame times 7875 ms)

0x18

Registers

Address0xEC03

2525 E-WIS Rx Control 1Short NameEWIS_RX_CTRL1

Address0xEC10

50 LOF_T2 RW Defines the number of consecutive frame periods (nominally 125 microS) during which OOF status must not be true in order to clear loss of frame set count (the counter associated with EWIS_LOF_CTRL1LOF_T1)0x0 Undefined0x1 1 frame time (125 micros)0x2 2 frame times 250 micros) 0x18 24 frame times 3 ms)0x3F 63 frame times 7875 ms)

0x18

Bit Name Access Description Default61 LOF_T3 RW Defines number of consecutive frames

(nominally 125 microS) for which the receive framer must be in its sync state in order to clear the LOF status0x0 Undefined0x1 1 frame time (125 micros)0x2 2 frame times 250 micros) 0x18 24 frame times 3 ms)0x3F 63 frame times 7875 ms)

0x18

Table 420 bull E-WIS Rx Control 1

Bit Name Access Description Default1 DSCR_ENA RW Enable the WIS descrambler

0= Disable1= Enable

0x1

0 B3_CALC_MODE RW Selects whether or not the fixed stuff bytes are included in the receive path BIP error calculation0= The fixed stuff bytes are excluded from the B3 calculation1= The fixed stuff bytes are included in the B3 calculation

0x1

Table 418 bull E-WIS Loss of Frame Control 1 (continued)

Registers

2526 E-WIS Rx Trace Message Length ControlShort NameEWIS_RX_MSGLEN

Address0xEC20

2527 E-WIS Rx Error Force Control25271 E-WIS Rx Error Force Control 1

Short NameEWIS_RX_ERR_FRC1

Address0xEC30

Table 421 bull E-WIS Rx Trace Message Length Control

Bit Name Access Description Default32 J0_RX_LEN RW Selects the expected length of the received

section trace message (J0)Trace length00 16 bytes01 64 bytes10 1 byte11 1 byte

0x0

10 J1_RX_LEN RW Selects the length of the expected path trace message (J1)Trace length00 16 bytes01 64 bytes10 1 byte11 1 byte

0x0

Table 422 bull E-WIS Rx Error Force Control 1

Bit Name Access Description Default12 FRC_LOPC RW Force a loss of optical carrier (LOPC) condition

The LOPC alarm state is asserted in EWIS_INTR_STAT2LOPC_STAT when this bit is set The LOPC status bits in the Vendor_Specific_LOPC_Status register are not modified when this bit is set0= Normal operation1= Force LOPC

0x0

11 FRC_LOS RW Force a loss of signal (LOS) condition in the WIS receive data path0= Normal operation1= Forced receive LOS

0x0

10 FRC_OOF RW Force the receive framer into the out-of-frame (OOF) state0= Normal operation1= Force receive OOF

0x0

Registers

25272 E-WIS Rx Error Force Control 2Short NameEWIS_RX_ERR_FRC2

Address0xEC31

8 RXLOF_ON_LOPC RW Selects whether or not the LOPC input has any effect on alarm conditions detected by the device0= A LOPC condition does not effect the state of the LOF or SEF status nor the state of the receive path framer1= LOF and SEF are asserted and the receive path framer is put into its out-of-frame state during a LOPC condition

0x0

74 APS_THRES RW The number of consecutive frames required to qualify the setting and clearing of AIS-L and RDI-L flags received in the K1K2 overhead bytes3ndash15 Threshold valueAll others Reserved

0x5

3 FRC_RX_AISL RW Force a line alarm indication signal (AIS-L) condition in the WIS receive data path0= Normal operation1= Device forced into Rx AIS-L condition

0x0

2 FRC_RX_RDIL RW Force a line remote defect identifier (RDI-L) condition in the WIS receive data path0= Normal operation1= Device forced into Rx RDI-L condition

0x0

1 FRC_RX_AISP RW Force a path alarm indication signal (AIS-P) condition in the WIS receive data path0= Normal operation1= Device forced into Rx AIS-P condition

0x0

0 FRC_RX_LOP RW Force a loss of pointer (LOP) condition to the starting location of the frames SPE (synchronous payload envelope) in the WIS receive data path0= Normal operation1= Device forced into Rx LOP condition

0x0

Bit Name Access Description Default15 FRC_RX_UNEQP RW Force a unequipped path (UNEQ-P) defect in the

WIS receive data path0= Normal operation1= Device forced into Rx UNEQ-P condition

0x0

Table 422 bull E-WIS Rx Error Force Control 1 (continued)

Registers

14 FRC_RX_PLMP RW Force a payload label mismatch (PLM-P) defect in the WIS receive data path0= Normal operation1= Device forced into Rx PLM-P condition

0x0

13 FRC_RX_RDIP RW Force a far-end path remote defect identifier condition in the WIS receive data path0= Normal operation1= Device forced into Rx far-end RDI-P condition

0x0

12 FRC_RX_FE_AISP RW Force a far-end path alarm indication signal condition in the WIS receive data path0= Normal operation1= Device forced into Rx far-end AIS-P condition

0x0

11 FRC_RX_FE_UNEQP RW Force a far-end unequipped path defect in the WIS receive data path0= Normal operation1= Device forced into Rx far-end UNEQ-P condition

0x0

10 FRC_RX_FE_PLMP RW Force a far-end payload label mismatch defect in the WIS receive data path0= Normal operation1= Device forced into Rx far-end PLM-P condition

0x0

9 FRC_RX_REIP RW Force a path remote error indication (REI-P) condition in the WIS receive data path The error is reflected in register EWIS_INTR_STAT2REIP_STAT0= Normal operation1= Device forced into Rx REI-P condition

0x0

8 FRC_RX_REIL RW Force a line remote error indication (REI-L) condition in the WIS receive data path The error is reflected in register EWIS_INTR_STAT2REIL_STAT0= Normal operation1= Device forced into Rx REI-L condition

0x0

7 FRC_RX_SEF RW Force a severely errored frame (SEF) condition in the WIS receive data path0= Normal operation1= Device forced into Rx SEF condition

0x0

6 FRC_RX_LOF RW Force a loss of frame (LOF) condition in the WIS receive data path0= Normal operation1= Device forced into Rx LOF condition

0x0

Registers

2528 E-WIS Mode ControlShort NameEWIS_MODE_CTRL

Address0xEC40

5 FRC_RX_B1 RW Force a PMTICK B1 BIP error condition (B1NZ) in the WIS receive data path0= Normal operation1= Device forced into PMTICK B1 BIP error condition

0x0

2 FRC_LCDP RW Force a loss of code-group delineation (LCD-P) defect in the WIS receive data path0= Normal operation1= Device forced into Rx LCD-P condition

0x0

1 FRC_REIL RW Force a far-end line BIP error condition (far-end B2NZ) in the WIS receive data path0= Normal operation1= Device forced into Rx far-end line BIP error condition

0x0

0 FRC_REIP RW Force a far-end path BIP error condition (far-end B3NZ) in the WIS receive data path0= Normal operation1= Device forced into Rx far-end path BIP error condition

0x0

Table 424 bull E-WIS Mode Control

Bit Name Access Description Default14 PTR_MODE RW Selects pointer type interpretation mode

0= SONET mode All 192 H1 and H2 bytes are used to determine the pointer type1= SDH mode Only the first 64 H1 and H2 bytes are used to determine the pointer type

0x0

Registers

2529 E-WIS PRBS31 Analyzer25291 E-WIS PRBS31 Analyzer Control

Short NameEWIS_PRBS31_ANA_CTRL

Address0xEC50

13 PTR_RULES RW Selects pointer incrementdecrement rules0= Pointer increment decrement is declared when 8 of the 10 DI bits in the H1 and H2 bytes match1= Pointer incrementdecrement is declared by majority rules

0x0

12 REI_MODE RW Selects how REI is extracted from the M0M1 bytes in the WIS receive data path0= SONET mode enabled Uses M0 only1= SDH mode enabled Uses M0 and M1

0x0

11 RX_SS_MODE RW Determines whether the SS bits in the H1 byte are checked when processing the received H1H2 pointer0= SS bits are ignored1= SS bits must match 2b10 to be considered a valid H1 byte

0x0

8 RX_ERDI_MODE RW Selects how ERDI-PRDI-P is extracted from the G1 byte in the WIS received data0= RDI-P is reported in bit 5 Bits 6 and 7 are unused1= ERDI is reported in bits 5ndash7

0x1

70 C2_EXP RW Expected C2 receive octet A PLM-P alarm is generated if this octet value is not received

0x1A

Table 425 bull E-WIS PRBS31 Analyzer Control

Bit Name Access Description Default1 PRBS31_FRC_ERR One-shot Inject a single bit error into the WIS PRBS31

pattern checker A single bit error injected in the data stream will result in the error counter incrementing by 3 (1 error for each tap of the checker)0= Normal operation1= Inject error

0x0

Table 424 bull E-WIS Mode Control (continued)

Registers

25292 E-WIS PRBS31 Analyzer StatusShort NameEWIS_PRBS31_ANA_STAT

Address0xEC51

2530 E-WIS Performance Monitor ControlShort NameEWIS_PMTICK_CTRL

Address0xEC60

0 PRBS31_FRC_SAT One-shot Force the PRBS31 pattern error counter (WIS_TSTPAT_CNT) to a value of 65528 This can be useful for testing the saturating feature of the counter Forcing the counter to 65528 with this bit has no affect on register EWIS_PRBS31_ANA_STATPRBS31_ERR0 Normal operation1= Force the PRBS31 error counter to a value of 65528

0x0

Table 426 bull E-WIS PRBS31 Analyzer Status

Bit Name Access Description Default1 PRBS31_ERR RO Status bit indicating if the WIS PRBS31 error

counter is non-zero0= Counter is zero1= Counter is non-zero

0x0

0 PRBS31_ANA_STATE RO Indicates when the Rx WIS PRBS31 pattern checker is synchronized to the incoming data0= PRBS31 pattern checker is not synchronized to the data PRBS31 error counter value is not valid1= PRBS31 pattern checker is synchronized to the data

0x0

Table 427 bull E-WIS Performance Monitor Control

Bit Name Access Description Default153 PMTICK_DUR RW Sets the interval for updating the PMTICK error

counters when the PMTICK_SRC bit is 1 The value represents the number of 125 microS increments between PMTICK events0 Undefined1 Undefined2 250 microS 8 1 mS8000 1 sec8191 1024 sec

0x1F40

Table 425 bull E-WIS PRBS31 Analyzer Control (continued)

Registers

2531 E-WIS Counter ConfigurationShort NameEWIS_CNT_CFG

Address0xEC61

2 PMTICK_ENA RW Enable the PMTICK counters to be updated on a PMTICK event The source of the PMTICK event is determined by the PMTICK_SRC bit0= Disable1= Enable

0x0

1 PMTICK_SRC RW Selects how the PMTICK counters are updated The PMTICK counters are updated with the selected source only if the PMTICK enable bit is set0= PMTICK counters updated on a rising edge of the (GPIO) PMTICK pin1= PMTICK counters updated when the PMTICK counter reaches its terminal count (PMTICK_DUR)

0x1

0 PMTICK_FRC One-shot Force the PMTICK counters to update regardless of the PMTICK_ENA or PMTICK_SRC settings0= Normal operation1= Forces PMTICK event

0x0

Table 428 bull E-WIS Counter Configuration

Bit Name Access Description Default11 B1_BLK_MODE RW Enable block mode (increment once for each

errored frame) counting for the B1 BIP PMTICK counter0= Bit mode1= Block mode

0x0

10 B2_BLK_MODE RW Enable block mode (increment once for each errored frame) counting for the B2 BIP PMTICK counter0= Bit mode1= Block mode

0x0

Table 427 bull E-WIS Performance Monitor Control (continued)

Registers

2532 E-WIS Counter StatusShort NameEWIS_CNT_STAT

Address0xEC62

2533 E-WIS P-REI Counter25331 E-WIS P-REI Counter 1 MSW

Short NameEWIS_REIP_CNT1

Address0xEC80

5 REIP_BLK_MODE RW Enable block mode (increment once for each errored frame) counting for the REI-P (far-end B3 error count in the G1 byte) PMTICK counter0= Bit mode1= Block mode

0x0

4 REIL_BLK_MODE RW Enable block mode (increment once for each errored frame) counting for the REI-L (far-end B2 error count in the M0M1 byte) PMTICK counter0= Bit mode1= Block mode

0x0

Table 429 bull E-WIS Counter Status

Bit Name Access Description Default2 REIP_CNT_STAT RO Status bit indicating if the REI-P (far-end B3)

PMTICK counter is non-zero0= Counter is zero1= Counter is non-zero

0x0

1 REIL_CNT_STAT RO Status bit indicating if the REI-L (far-end B2) PMTICK counter is non-zero0= Counter is zero1= Counter is non-zero

0x0

0 B2_statistical_error_event RO 0= B2 error counter is zero1= B2 error counter is non zero

0x0

Table 430 bull E-WIS P-REI Counter 1 MSW

Bit Name Access Description Default150 REIP_ERR_CNT_MSW RO PMTICK statistical error count of the far-end B3

errors reported in the G1 byte 16 MSB are in this register 16 LSB are in the next register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Table 428 bull E-WIS Counter Configuration (continued)

Registers

25332 E-WIS P-REI Counter 0 LSWShort NameEWIS_REIP_CNT0

Address0xEC81

2534 E-WIS L-REI Counter25341 E-WIS L-REI Counter 1 MSW

Short NameEWIS_REIL_CNT1

Address0xEC90

25342 E-WIS L-REI Counter 0 LSWShort NameEWIS_REIL_CNT0

Address0xEC91

2535 E-WIS S-BIP Error Counter25351 E-WIS S-BIP Error Counter 1 MSW

Short NameEWIS_B1_ERR_CNT1

Table 431 bull E-WIS P-REI Counter 0 LSW

Bit Name Access Description Default150 REIP_ERR_CNT_LSW RO PMTICK statistical error count of the far-end B3

errors reported in the G1 byte 16 LSB are in this register 16 MSB are in the previous register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Table 432 bull E-WIS L-REI Counter 1 MSW

Bit Name Access Description Default150 REIL_ERR_CNT_MSW RO PMTICK statistical error count of the far-end B2

errors reported in the M0M1 bytes 16 MSB are in this register 16 LSB are in the next register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Table 433 bull E-WIS L-REI Counter 0 LSW

Bit Name Access Description Default150 REIL_ERR_CNT_LSW RO PMTICK statistical error count of the far-end B2

errors reported in the M0M1 bytes 16 LSB are in this register 16 MSB are in the previous register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Registers

Address0xECB0

25352 E-WIS S-BIP Error Counter 0 LSWShort NameEWIS_B1_ERR_CNT0

Address0xECB1

2536 E-WIS L-BIP Error Counter25361 E-WIS L-BIP Error Counter 1 MSW

Address0xECB2

25362 E-WIS L-BIP Error Counter 0 LSWShort NameEWIS_B2_ERR_CNT0

Table 434 bull E-WIS S-BIP Error Counter 1 MSW

Bit Name Access Description Default150 B1_ERR_CNT_MSW RO PMTICK statistical error count of the B1 BIP

errors 16 MSB are in this register 16 LSB are in the next register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Table 435 bull E-WIS S-BIP Error Counter 0 LSW

Bit Name Access Description Default150 B1_ERR_CNT_LSW RO PMTICK statistical error count of the B1 BIP

errors 16 LSB are in this register 16 MSB are in the previous register The count is updated only on a PMTICK event The counter saturates when the maximum error count is exceeded

0x0000

Table 436 bull E-WIS L-BIP Error Counter 1 MSW

0x0000

Registers

Address0xECB3

2537 E-WIS P-BIP Error Counter25371 E-WIS P-BIP Error Counter 1 MSW

Address0xECB4

25372 E-WIS P-BIP Error Counter 0 LSWShort NameEWIS_B3_ERR_CNT0

Address0xECB5

2538 E-WIS Rx to Tx ControlShort NameEWIS_RXTX_CTRL

Table 437 bull E-WIS L-BIP Error Counter 0 LSW

0x0000

Table 438 bull E-WIS P-BIP Error Counter 1 MSW

0x0000

Table 439 bull E-WIS P-BIP Error Counter 0 LSW

0x0000

Registers

Address0xEDFF

Table 440 bull E-WIS Rx to Tx Control

Bit Name Access Description Default6 RXAISL_ON_LOPC RW Select if a LOPC condition contributes to the Rx

AIS-L alarm0= A LOPC condition does not cause the AIS-L alarm to be set1= A LOPC condition will cause the AIS-L alarm to be set

0x0

5 RXAISL_ON_LOS RW Selects if a LOS condition contributes to the Rx AIS-L alarm0= A LOS condition does not cause the AIS-L alarm to be set1= A LOS condition will cause the AIS-L alarm to be set

0x0

4 RXAISL_ON_LOF RW Select if a LOF condition contributes to the Rx AIS-L alarm0= A LOF condition does not cause the AIS-L alarm to be set1= A LOF condition will cause the AIS-L alarm to be set

0x0

3 TXRDIL_ON_LOPC RW Select if a RDI-L is reported in the Tx frames K2 byte when a LOPC condition is detected0= RDI-L will not be reported when LOPC is detected1= RDI-L will be reported when LOPC is detected

0x0

2 TXRDIL_ON_LOS RW Selects whether or not RDI-L is reported in the Tx frames K2 byte when a LOS condition is detected0= RDI-L will not be reported when LOS is detected1= RDI-L will be reported when LOS is detected

0x0

1 TXRDIL_ON_LOF RW Selects whether or not RDI-L is reported in the Tx frames K2 byte when a LOF condition is detected0= RDI-L will not be reported when LOF is detected1= RDI-L will be reported when LOF is detected

0x0

0 TXRDIL_ON_AISL RW Selects whether or not RDI-L is reported in the Tx frames K2 byte when a Rx AIS-L condition is detected0= RDI-L will not be reported when a Rx AIS-L condition is detected1= RDI-L will be reported when a Rx AIS-L condition is detected

0x0

Registers

2539 E-WIS Interrupt Pending 1Short NameEWIS_INTR_PEND1

Address0xEE00

Table 441 bull E-WIS Interrupt Pending 1

Bit Name Access Description Default11 SEF_PEND RO Interrupt pending SEF has changed state since

this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= SEF condition has not changed state1= SEF condition has changed state

0x0

10 FEPLMP_LCDP_PEND RO Interrupt pending far-end path label mismatch (PLM-P)loss of code-group delineation (LCD-P) condition has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= PLM-PLCD-P has not changed state1= PLM-PLCD-P condition has changed state

0x0

9 FEAISP_LOPP_PEND RO Interrupt pending far-end path alarm indication signal (AIS-P)path loss of pointer (LOP) condition has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= Far-end AIS-PLOP-P condition has not changed state1= Far-end AIS-PLOP-P condition has changed state

0x0

7 LOF_PEND RO Interrupt pending loss of frame (LOF) condition has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= LOF condition has not changed state1= LOF condition has changed state

0x0

6 LOS_PEND RO Interrupt pending loss of signal (LOS) condition has changed state since this register was last read This bit does not assert if LOPC is active at the LOS changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0 = LOS condition has not changed state1 = LOS condition has changed state

0x0

Registers

5 RDIL_PEND RO Interrupt pending line remote defect indication (RDI-L) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= RDI-L condition has not changed state1= RDI-L condition has changed state

0x0

4 AISL_PEND RO Interrupt pending line alarm indication signal (AIS-L) has changed state since this register was last read This bit does not assert if LOPC LOS LOF or SEF are asserted at the time AIS-L changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= AIS-L condition has not changed state 1= AIS-L condition has changed state

0x0

3 LCDP_PEND RO Interrupt pending loss of code-group delineation (LCD-P) has changed state since this register was last read This bit will not assert if AIS-L AIS-P UNEQ-P or PLM-P are asserted at the time LCD-P changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= LCD-P condition has not changed state1= LCD-P condition has changed state

0x0

2 PLMP_PEND RO Interrupt pending path label mismatch (PLM-P) has changed state since this register was last read This bit will not assert if LOP-P or AIS-P are asserted at the time PLM-P changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= PLM-P condition has not changed state1= PLM-P condition has changed state

0x0

1 AISP_PEND RO Interrupt pending path alarm indication signal (AIS-P) has changed state since this register was last read This bit will not assert if LOPC LOS SEF LOF or AIS-L are asserted at the time AIS-P changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= AIS-P condition has not changed state1= AIS-P condition has changed state

0x0

Table 441 bull E-WIS Interrupt Pending 1 (continued)

Registers

2540 E-WIS Interrupt Mask 125401 E-WIS Interrupt Mask A 1

Short NameEWIS_INTR_MASKA_1

Address0xEE01

0 LOPP_PEND RO Interrupt pending path loss of pointer (LOP-P) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= LOP-P condition has not changed state1= LOP-P condition has changed state

0x0

Table 442 bull E-WIS Interrupt Mask A 1

Bit Name Access Description Default11 SEF_MASKA RW Enable propagation of SEF_PEND to the

WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

10 FEPLMP_LCDP_MASKA RW Enable propagation of FEPLMP_LCDP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

9 FEAISP_LOPP_MASKA RW Enable propagation of FEAISP_LOPP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

7 LOF_MASKA RW Enable propagation of LOF_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

6 LOS_MASKA RW Enable propagation of LOS_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

5 RDIL_MASKA RW Enable propagation of RDIL_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Registers

25402 E-WIS Interrupt Mask B 1Short NameEWIS_INTR_MASKB_1

Address0xEE02

4 AISL_MASKA RW Enable propagation of AISL_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

3 LCDP_MASKA RW Enable propagation of LCDP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

2 PLMP_MASKA RW Enable propagation of PLMP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

1 AISP_MASKA RW Enable propagation of AISP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

0 LOPP_MASKA RW Enable propagation of LOPP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Table 443 bull E-WIS Interrupt Mask B 1

Bit Name Access Description Default11 SEF_MASKB RW Enable propagation of SEF_PEND to the

WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

10 FEPLMP_LCDP_MASKB RW Enable propagation of FEPLMP_LCDP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

9 FEAISP_LOPP_MASKB RW Enable propagation of FEAISP_LOPP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

Table 442 bull E-WIS Interrupt Mask A 1 (continued)

Registers

2541 E-WIS Interrupt Status 2Short NameEWIS_INTR_STAT2

7 LOF_MASKB RW Enable propagation of LOF_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

6 LOS_MASKB RW Enable propagation of LOS_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

5 RDIL_MASKB RW Enable propagation of RDIL_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

4 AISL_MASKB RW Enable propagation of AISL_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

3 LCDP_MASKB RW Enable propagation of LCDP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

2 PLMP_MASKB RW Enable propagation of PLMP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

1 AISP_MASKB RW Enable propagation of AISP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

0 LOPP_MASKB RW Enable propagation of LOPP_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

Table 443 bull E-WIS Interrupt Mask B 1 (continued)

Registers

Address0xEE03

Table 444 bull E-WIS Interrupt Status 2

Bit Name Access Description Default15 MODULE_STAT RO GPIO pin state being driven by optics module

0= Module status pin is low1= Module status pin is high

0x0

13 TXLOL_STAT RO PMA CMU loss of lock status0= No PMA CMU lock error1= PMA CMU lock error

0x0

12 RXLOL_STAT RO PMA CRU loss of lock status0= No PMA CRU lock error1= PMA CRU lock error

0x0

11 LOPC_STAT RO Loss of optical carrier (LOPC) status0= The LOPC input pin is de-asserted1= The LOPC input pin is asserted

0x0

10 UNEQP_STAT RO Unequipped path (UNEQ-P) status0= UNEQ-P is de-asserted1= UNEQ-P is asserted

0x0

9 FEUNEQP_STAT RO Far-end unequipped path (UNEQ-P) status0= Far-end UNEQ-P is de-asserted1= Far-end UNEQ-P is asserted

0x0

8 FERDIP_STAT RO Far-end path remote defect identifier (RDI-P) status0= Far-end RDI-P is de-asserted1= Far-end RDI-P is asserted

0x0

7 B1_NZ_STAT RO PMTICK B1 BIP (B1_ERR_CNT) counter status0= B1_ERR_CNT is zero1= B1_ERR_CNT is non-zero

0x0

4 REIL_STAT RO Line remote error indication (REI-L) value status0= The REI-L value in the last received frame reported no errors1= The REI-L value in the last received frame reported errors

0x0

Registers

Address0xEE04

3 REIP_STAT RO Path remote error indication (REI-P) value status0= The REI-P value in the last received frame reported no errors1= The REI-P value in the last received frame reported errors

0x0

2 REIL_NZ_STAT RO PMTICK REI-L (REIL_ERR_CNT) counter status0= REIL_ERR_CNT is zero1= REIL_ERR_CNT is non-zero

0x0

1 REIP_NZ_STAT RO PMTICK REI-P (REIP_ERR_CNT) counter status0= REIP_ERR_CNT is zero1= REIP_ERR_CNT is non-zero

0x0

0 HIGH_BER_STAT RO PCS high bit error rate (BER) status0= No high BER1= The PCS block indicates a high bit error rate

0x0

Bit Name Access Description Default15 MODULE_PEND RO Interrupt pending Module status input pin state

(MODULE_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= MODULE_STAT has not changed state1= MODULE_STAT has changed state

0x0

14 PMTICK_PEND RO Interrupt pending a PMTICK event (regardless of the source) has occurred since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= A PMTICK event has not occurred1= A PMTICK event occurred

0x0

Table 444 bull E-WIS Interrupt Status 2 (continued)

Registers

13 TXLOL_PEND RO Interrupt pending PMA CMU lock signal (TXLOL_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= TXLOL_STAT has not changed state1= TXLOL_STAT has changed state

0x0

12 RXLOL_PEND RO Interrupt pending PMA CRU lock signal (RXLOL_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= RXLOL_STAT has not changed state1= RXLOL_STAT has changed state

0x0

11 LOPC_PEND RO Interrupt pending loss of optical carrier (LOPC) input pin (LOPC_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= LOPC_STAT has not changed state1= LOPC_STAT has changed state

0x0

10 UNEQP_PEND RO Interrupt pending unequipped path (UNEQP_STAT) has changed state since this register was last read This bit does not assert if LOP-P or AIS-P are asserted at the time UNEQ-P changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= UNEQP_STAT has not changed state1= UNEQP_STAT has changed state

0x0

9 FEUNEQP_PEND RO Interrupt pending far-end unequipped path (FEUNEQP_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= FEUNEQP_STAT has not changed state1= FEUNEQP_STAT has changed state

0x0

8 FERDIP_PEND RO Interrupt pending far-end path remote defect identifier (FERDIP_STAT) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= FERDIP_STAT has not changed state1= FERDIP_STAT has changed state

0x0

Registers

7 B1_NZ_PEND RO Interrupt pending PMTICK B1 error counter (B1_ERR_CNT) has changed from zero to a non-zero value since this register was last read This bit will not assert if LOS or LOF are asserted at the time B1_NZ_STAT changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= B1_NZ_STAT has not changed from a 0 to 1 state1= B1_NZ_STAT has changed from a 0 to 1 state

0x0

6 B2_NZ_PEND RO Interrupt pending PMTICK B2 error counter (B2_ERR_CNT) has changed from zero to a non-zero value since this register was last read This bit will not assert if AIS-L is asserted at the time B2_NZ_STAT changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= B2_NZ_STAT has not changed from a 0 to 1 state1= B2_NZ_STAT has changed from a 0 to 1 state

0x0

5 B3_NZ_PEND RO Interrupt pending PMTICK B3 error counter (B3_ERR_CNT) has changed from zero to a non-zero value since this register was last read This bit will not assert if LOP-P or AIS-P are asserted at the time B3_NZ_STAT changes state This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= B3_NZ_STAT has not changed from a 0 to 1 state1= B3_NZ_STAT has changed from a 0 to 1 state

0x0

4 REIL_PEND RO Interrupt pending REI-L received a non-zero value since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= REI-L has not received a non-zero value1= REI-L has received a non-zero value

0x0

3 REIP_PEND RO Interrupt pending REI-P received a non-zero value since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= REI-P has not received a non-zero value1= REI-P has received a non-zero value

0x0

Registers

Address0xEE05

2 REIL_NZ_PEND RO Interrupt pending PMTICK far-end B2 error counter (REIL_ERR_CNT) has changed from a zero to a non-zero value since this register was read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= REIL_NZ_STAT has not changed from a 0 to 1 state1= REIL_NZ_STAT has changed from a 0 to 1 state

0x0

1 REIP_NZ_PEND RO Interrupt pending PMTICK far-end B3 error counter (REIP_ERR_CNT) has changed from a zero to a non-zero value since this register was read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= REIP_NZ_STAT has changed from a 0 to 1 state1= REIP_NZ_STAT has changed from a 0 to 1 state

0x0

0 HIGH_BER_PEND RO Interrupt pending PCS high bit error rate (BER) condition has changed state since this register was read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= No change in PCS high BER condition1= PCS high BER condition has changed state

0x0

Bit Name Access Description Default15 MODULE_STAT_MASKA RW Enable propagation of MODULE_PEND to the

0x0

14 PMTICK_MASKA RW Enable propagation of PMTICK_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Registers

13 TXLOL_MASKA RW Enable propagation of TXLOL_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

12 RXLOL_MASKA RW Enable propagation of RXLOL_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

11 LOPC_MASKA RW Enable propagation of LOPC_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

10 UNEQP_MASKA RW Enable propagation of UNEQP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

9 FEUNEQP_MASKA RW Enable propagation of FEUNEQP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

8 FERDIP_MASKA RW Enable propagation of FERDIP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

7 B1_NZ_MASKA RW Enable propagation of B1_NZ_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

4 REIL_MASKA RW Enable propagation of REIL_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Registers

Address0xEE06

3 REIP_MASKA RW Enable propagation of REIP_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

2 REIL_NZ_MASKA RW Enable propagation of REIL_NZ_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

1 REIP_NZ_MASKA RW Enable propagation of REIP_NZ_PEND to the WIS_INTA (GPIO) pin0= Disable1 = Enable

0x0

0 HIGH_BER_MASKA RW Enable propagation of HIGH_BER_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Bit Name Access Description Default15 MODULE_STAT_MASKB RW Enable propagation of MODULE_PEND to the

0x0

14 PMTICK_MASKB RW Enable propagation of PMTICK_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

13 TXLOL_MASKB RW Enable propagation of TXLOL_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

12 RXLOL_MASKB RW Enable propagation of RXLOL_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

Registers

11 LOPC_MASKB RW Enable propagation of LOPC_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

10 UNEQP_MASKB RW Enable propagation of UNEQP_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

9 FEUNEQP_MASKB RW Enable propagation of FEUNEQP_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

8 FERDIP_MASKB RW Enable propagation of FERDIP_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

7 B1_NZ_MASKB RW Enable propagation of B1_NZ_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

4 REIL_MASKB RW Enable propagation of REIL_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

3 REIP_MASKB RW Enable propagation of REIP_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

2 REIL_NZ_MASKB RW Enable propagation of REIL_NZ_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

Registers

2544 WIS Fault MaskShort NameWIS_FAULT_MASK

Address0xEE07

1 REIP_NZ_MASKB RW Enable propagation of REIP_NZ_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

0 HIGH_BER_MASKB RW Enable propagation of HIGH_BER_PEND to the WIS_INTB pin0= Disable1= Enable

0x0

Table 448 bull WIS_FAULT_MASK

Bit Name Access Description Default10 WIS_FAULT_ON_FEPLMP RW Selects if the far-end PLM-P condition triggers

the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x0

9 WIS_FAULT_ON_FEAISP RW Selects if the far-end AIS-P condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x0

8 WIS_FAULT_ON_RDIL RW Selects if the RDI-L condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x0

7 WIS_FAULT_ON_SEF RW Selects if the SEF condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

6 WIS_FAULT_ON_LOF RW Selects if the LOF condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

5 WIS_FAULT_ON_LOS RW Selects if the LOS condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

Registers

Address0xEE08

4 WIS_FAULT_ON_AISL RW Selects if the AIS-L condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

3 WIS_FAULT_ON_LCDP RW Selects if the LCD-P condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

2 WIS_FAULT_ON_PLMP RW Selects if the PLM-P condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

1 WIS_FAULT_ON_AISP RW Selects if the AIS-P condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

0 WIS_FAULT_ON_LOPP RW Selects if the LOP-P condition triggers the WIS fault alarm (WIS_STAT1FAULT register)0= No trigger1= Triggers WIS_FAULT

0x1

Bit Name Access Description Default5 PCS_RECEIVE_FAULT_PEND RO Interrupt pending PCS receive lock status

(Eth_10GBASE_R_PCS_Status_1is_10GBASE_R_receive_lock_status) has changed state since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= PCS receive lock has not changed state1= PCS receive lock has changed state

0x0

4 REIP_THRESH_PEND RO Interrupt pending REIP_THRESH_ERR has been asserted since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= A counter threshold error has not occurred1= A counter threshold error occurred

0x0

Table 448 bull WIS_FAULT_MASK (continued)

Registers

Address0xEE09

3 REIL_THRESH_PEND RO Interrupt pending REIL_THRESH_ERR has been asserted since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= A counter threshold error has not occurred1= A counter threshold error occurred

0x0

2 B1_THRESH_PEND RO Interrupt pending B1_THRESH_ERR has been asserted since this register was last read This is a sticky bit that latches the high state The latch-high bit is cleared when the register is read0= A counter threshold error has not occurred1= A counter threshold error occurred

0x0

Bit Name Access Description Default5 PCS_RECEIVE_FAULT_MASKA RW Enable propagation of

PCS_RECEIVE_FAULT_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

4 REIP_THRESH_MASKA RW Enable propagation of REIP_THRESH_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Registers

Address0xEE0A

3 REIL_THRESH_MASKA RW Enable propagation of REIL_THRESH_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

2 B1_THRESH_MASKA RW Enable propagation of B1_THRESH_PEND to the WIS_INTA (GPIO) pin0= Disable1= Enable

0x0

Bit Name Access Description Default5 PCS_RECEIVE_FAULT_MASKB RW Enable propagation of

PCS_RECEIVE_FAULT_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

4 REIP_THRESH_MASKB RW Enable propagation of REIP_THRESH_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

3 REIL_THRESH_MASKB RW Enable propagation of REIL_THRESH_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0

2 B1_THRESH_MASKB RW Enable propagation of B1_THRESH_PEND to the WIS_INTB (GPIO) pin0= Disable1= Enable

0x0