Ethernet and QSGMII/SGMII/RGMII MAC
VMDS-10401. 4.4 2/19
Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA
Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949)
380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email:
[email protected] www.microsemi.com
©2018 Microsemi, a wholly owned subsidiary of Microchip Technology
Inc. All rights reserved. Microsemi and the Microsemi logo are
registered trademarks of Microsemi Corporation. All other
trademarks and service marks are the property of their respective
owners.
Microsemi makes no warranty, representation, or guarantee regarding
the information contained herein or the suitability of its products
and services for any particular purpose, nor does Microsemi assume
any liability whatsoever arising out of the application or use of
any product or circuit. The products sold hereunder and any other
products sold by Microsemi have been subject to limited testing and
should not be used in conjunction with mission-critical equipment
or applications. Any performance specifications are believed to be
reliable but are not verified, and Buyer must conduct and complete
all performance and other testing of the products, alone and
together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters
provided by Microsemi. It is the Buyer’s responsibility to
independently determine suitability of any products and to test and
verify the same. The information provided by Microsemi hereunder is
provided “as is, where is” and with all faults, and the entire risk
associated with such information is entirely with the Buyer.
Microsemi does not grant, explicitly or implicitly, to any party
any patent rights, licenses, or any other IP rights, whether with
regard to such information itself or anything described by such
information. Information provided in this document is proprietary
to Microsemi, and Microsemi reserves the right to make any changes
to the information in this document or to any products and services
at any time without notice.
About Microsemi Microsemi, a wholly owned subsidiary of Microchip
Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of
semiconductor and system solutions for aerospace & defense,
communications, data center and industrial markets. Products
include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management
products; timing and synchronization devices and precise time
solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and
communication solutions, security technologies and scalable
anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs
and midspans; as well as custom design capabilities and services.
Learn more at www.microsemi.com.
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1
Revision 4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 1 1.2 Revision 4.3 . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Revision 4.2 .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 1 1.4 Revision 4.1 . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 1 1.5 Revision 4.0 . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.6
Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 2
2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Key
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 4
2.1.1 Low Power . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 4 2.1.2 Advanced Carrier Ethernet Support . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 4 2.1.3 Wide Range of Support . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 4 2.1.4 Flexibility . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 4
2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 5
3.1.1 QSGMII/SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.2
QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 8 3.1.3 QSGMII/SGMII
MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . .
. . . . . . . . . . 8 3.1.4 QSGMII/SGMII MAC-to-AMS and 100BASE-FX
Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.5 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . .
. . . . . . . . . . . . . . . . . . . . . . 10 3.1.6 QSGMII/SGMII
MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 11 3.1.7 QSGMII/SGMII
MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 11 3.1.8 1000BASE-X MAC-to-Cat5
Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 12
3.2 RGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 12 3.3 SerDes MAC Interface . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 13
3.3.1 SerDes MAC . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 13 3.3.2 SGMII MAC . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 13 3.3.3 QSGMII MAC . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 14
3.4 SerDes Media Interface . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 14 3.4.1 QSGMII/RGMII/SGMII to 1000BASE-X . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 15 3.4.2 QSGMII/RGMII/SGMII to 100BASE-FX . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.3 QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.4
Unidirectional Transport for Fiber Media . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 PHY Addressing and Port Mapping . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 15 3.5.1 PHY Addressing . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 16 3.5.2 SerDes Port Mapping . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 16
3.6 Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 16 3.6.1 Voltage Mode Line Driver . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 16 3.6.2 Cat5 Autonegotiation and Parallel Detection . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 17 3.6.3 Automatic Crossover and Polarity Detection . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.4 Manual HP Auto-MDIX Setting . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.5 Link Speed Downshift . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 18 3.6.6 Energy Efficient Ethernet . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 18 3.6.7 Ring Resiliency . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 19
3.7 Automatic Media Sense Interface Mode . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 19 3.8 Reference Clock . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 20
3.8.1 Configuring the Reference Clock . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 iv
3.8.2 Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8.3 Differential REFCLK Input . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
3.9 Ethernet Inline Powered Devices . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 21 3.10 IEEE 802.3af PoE Support . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 23 3.11 ActiPHY Power Management . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 23
3.11.1 Low Power State . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 24 3.11.2 Link Partner Wake-Up State . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 24 3.11.3 Normal Operating State . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 24
3.12 Media Recovered Clock Outputs . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 24 3.12.1 Clock Selection Settings . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 24 3.12.2 Clock Output Squelch . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 25
3.13 Serial Management Interface . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 25 3.13.1 SMI Frames . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 25 3.13.2 SMI Interrupt . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 26
3.14 LED Interface . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 27 3.14.1 LED Modes . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 27 3.14.2 Extended LED Modes . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 29 3.14.3 LED Behavior . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 29 3.14.4 Basic
Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.5
Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.6
LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
3.15 Fast Link Failure Indication . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 31 3.16 Integrated Two-Wire Serial Multiplexer . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 31
3.16.1 Read/Write Access Using the Two-Wire Serial MUX . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17 GPIO Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 33 3.18 Testing Features . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 33
3.18.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33 3.18.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 33 3.18.3 Far-End Loopback . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 34 3.18.4 Near-End Loopback . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 34 3.18.5 Connector Loopback . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 34 3.18.6 SerDes Loopbacks . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 35 3.18.7 VeriPHY Cable
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 38 3.18.8 JTAG
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18.9
JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.18.10 Boundary Scan Register Cell Order . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.19 100BASE-FX Halt Code Transmission and Reception . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 42
3.20.1 Initialization . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 43
4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1
Register and Bit Conventions . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 44 4.2 IEEE 802.3 and Main Registers . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 45
4.2.1 Mode Control . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 46 4.2.2 Mode Status . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 47 4.2.3 Device Identification . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 48 4.2.4 Autonegotiation Advertisement .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 48 4.2.5 Link Partner Autonegotiation
Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 49 4.2.6 Autonegotiation Expansion . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 49 4.2.7 Transmit Autonegotiation Next
Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 50 4.2.8 Autonegotiation Link Partner
Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 50 4.2.9 1000BASE-T Control . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 50 4.2.10 1000BASE-T Status . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 51 4.2.11 MMD Access Control Register . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 52 4.2.12 MMD Address or Data Register . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 52 4.2.13 1000BASE-T Status Extension 1 . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 52
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 v
4.2.14 100BASE-TX/FX Status Extension . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 54 4.2.17 Error Counter 1 . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 55 4.2.18 Error Counter 2 . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 55 4.2.19 Error Counter 3 . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 55 4.2.20 Extended Control and
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 55 4.2.21 Extended PHY
Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 56 4.2.22 Extended
PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.23
Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 58 4.2.24 Interrupt Status . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 59 4.2.25 Device Auxiliary Control and Status . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 59 4.2.26 LED Mode Select . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 60 4.2.27 LED Behavior . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 61 4.2.28 Extended Page Access . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 62
4.3 Extended Page 1 Registers . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 62 4.3.1 SerDes Media Control . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 63 4.3.2 Cu Media CRC Good Counter . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 63 4.3.3 Extended Mode Control . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 64 4.3.4 ActiPHY Control . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 64 4.3.5 PoE and Miscellaneous
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 66 4.3.6 Ethernet Packet Generator
Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 66 4.3.7 Ethernet Packet Generator
Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 67
4.4 Extended Page 2 Registers . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 67 4.4.1 Cu PMD Transmit Control . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 67 4.4.2 EEE Control . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 69 4.4.3 RGMII Settings . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 70 4.4.4 Ring Resiliency Control .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 71
4.5 Extended Page 3 Registers . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 71 4.5.1 MAC SerDes PCS Control . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 72 4.5.2 MAC SerDes PCS Status . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 73 4.5.3 MAC SerDes Clause 37 Advertised Ability . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 73 4.5.4 MAC SerDes Clause 37 Link Partner Ability . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.5.5 MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74 4.5.6 Media SerDes Transmit Good Packet Counter . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.7
Media SerDes Transmit CRC Error Counter . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.8 Media
SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.9
Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.10
Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.11 Media
SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 76 4.5.12 Media SerDes
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.13 Fiber
Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.14 Fiber
Media CRC Error Counter . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6 General Purpose Registers . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 77 4.6.1 Reserved General Purpose Address Space . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78 4.6.2 SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 78 4.6.3 GPIO Control 2 . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 79 4.6.4 GPIO Input . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 80 4.6.5 GPIO Output . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 80 4.6.6 GPIO Pin Configuration .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 81 4.6.7 Microprocessor
Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 81 4.6.8 MAC
Configuration and Fast Link . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.9
Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.10
Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.6.11
Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.6.12
Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.6.13 Recovered Clock 2 Control . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84 4.6.14 Enhanced LED Control . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 85
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 vi
4.6.15 Global Interrupt Status . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 86 4.7 Clause 45 Registers to Support Energy Efficient
Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . .
. 86
4.7.1 PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 87 4.7.2 EEE Capability . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 88 4.7.3 EEE Wake Error Counter . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 88 4.7.4 EEE Advertisement . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 88 4.7.5 EEE Link Partner Advertisement . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 88
5 Electrical Specifications . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.1 DC
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 90
5.1.1 VDD25 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 90 5.1.2 LED and GPIO . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 90 5.1.3 Internal Pull-Up or Pull-Down Resistors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 90 5.1.4 Reference Clock . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 91 5.1.5 SerDes Interface (SGMII) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 91 5.1.6 Enhanced SerDes Interface (QSGMII)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 93 5.1.7 Current Consumption . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 94 5.1.8 Thermal Diode . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 95
5.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 95 5.2.1 Reference Clock . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 95 5.2.2 Recovered Clock . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 96 5.2.3 SerDes Outputs . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 97 5.2.4 SerDes Driver
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.2.5
SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98 5.2.6 SerDes Receiver Jitter Tolerance . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98 5.2.7 Enhanced SerDes Interface . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98 5.2.8 Basic Serial LEDs . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 101 5.2.9 Enhanced Serial LEDs . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 102 5.2.10 JTAG Interface . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 102 5.2.11 RGMII, Uncompensated . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 103 5.2.12 RGMII, Compensated . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 105 5.2.13 Serial Management Interface . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 106 5.2.14 Reset Timing . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 107
5.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 107 5.4 Stress Ratings . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 108
6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1 Pin
Identifications . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 109 6.2 Pin Diagram . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 109 6.3 Pins by Function . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.1 GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112 6.3.2 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 112 6.3.3 Miscellaneous . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 112 6.3.4 Power Supply . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 113 6.3.5 SGMII/SerDes/QSGMII MAC
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 116 6.3.6 SerDes Media Interface . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 116 6.3.7 Serial Management Interface .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 117 6.3.8 Twisted Pair Interface . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 117
6.4 Pins by Number . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 118 6.5 Pins by Name . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 121
7 Package Information . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 124 7.1 Package
Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 124 7.2 Thermal Specifications . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 125 7.3 Moisture Sensitivity . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 126
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 vii
8 Design Considerations . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 127 8.1 AMS and
100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2 10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 127 8.3 SNR degradation and link drops . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 127 8.4 Clause 45 register 3.22 . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 127 8.5 Clause 45 register 3.1 .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.6 Clause
45 register address post-increment . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.7
Fast link failure indication . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 127 8.8 Near-end loopback with AMS enabled . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 128 8.9 Carrier detect assertion . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 128 8.10 Link status not
correct in register 24E3.2 for 100BASE-FX operation . . . . . . . .
. . . . . . . . . . . . . . . . . 128 8.11 Register 28.14 does not
reflect autonegotiation disabled in 100BASE-FX mode . . . . . . . .
. . . . . . . . 128 8.12 Internal clock disabled when media
switches from fiber to copper with autonegotiation disabled . . . .
128 8.13 Near-end loopback non-functional in protocol transfer mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.14 Fiber-media recovered clock does not squelch based on link
status . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.15
1000BASE-X parallel detect mode with Clause 37 autonegotiation
enabled . . . . . . . . . . . . . . . . . . . . 129 8.16 Anomalous
PCS error indications in Energy Efficient Ethernet mode . . . . . .
. . . . . . . . . . . . . . . . . . . 129 8.17 Station managers
cannot use MDIO address offsets 0x2 and 0x3 with the PHY . . . . .
. . . . . . . . . . . 129
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 130
Figures
Figure 1 Dual Media Application Diagram . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 3 Figure 2 Copper Transceiver Application Diagram . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 3 Figure 3 Fiber Media Transceiver Application Diagram .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 4 Figure 4 Block Diagram . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 5 Figure 5 SGMII MAC-to-1000BASE-X
Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 7 Figure 6 QSGMII
MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7
QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8
QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 8 Figure 9 QSGMII/SGMII
MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . .
. . . . . . . . . . . . . 9 Figure 10 QSGMII/SGMII MAC-to-AMS and
Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 10 Figure 11 QSGMII/SGMII MAC-to-Cat5 Link Partner
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 11 Figure 12 QSGMII/SGMII MAC-to-Protocol
Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 11 Figure 13 1000BASE-X MAC-to-Cat5 Link
Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 12 Figure 14 RGMII MAC Interface . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 13 Figure 15 SerDes MAC
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure
16 SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 14 Figure 17 QSGMII MAC Interface . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 14 Figure 18 Cat5 Media Interface . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 17 Figure 19 Low Power Idle
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20
Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure
21 2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22 3.3 V
CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 21 Figure 23 5 V CMOS
Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 21 Figure 24 AC Coupling for
REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 25 Inline
Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 26
ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 Figure 27 SMI Read Frame . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 25 Figure 28 SMI Write Frame . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 26 Figure 29 MDINT Configured
as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 26 Figure 30 MDINT Configured as an
Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 27 Figure 31 Two-Wire Serial MUX with SFP
Control and Status . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 31 Figure 32 Two-Wire Serial MUX Read and
Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 32 Figure 33 Far-End Loopback Diagram . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 34 Figure 34 Near-End Loopback
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 34 Figure 35
Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 36 Data Loops of the SerDes Macro . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 35 Figure 37 Test Access Port and Boundary Scan Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 39 Figure 38 Register Space Diagram . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 44 Figure 39 SGMII DC Transmit Test Circuit . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 92 Figure 40 SGMII DC Definitions . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 92 Figure 41 SGMII DC
Driver Output Impedance Test Circuit . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 92 Figure 42 SGMII DC
Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 43 Test Circuit for Recovered Clock Output Signals . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96 Figure 44 QSGMII Transient Parameters . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 99 Figure 45 Basic Serial LED Timing . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 101 Figure 46 Enhanced Serial LED Timing .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 102 Figure 47 JTAG Interface
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 48 Test
Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 49 Test Circuit for RGMII Output Signals . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 103 Figure 50 RGMII Uncompensated Timing . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 105 Figure 51 RGMII Compensated Timing . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 106 Figure 52 Serial Management Interface Timing .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 107 Figure 53 Pin Diagram, Top Left . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 110 Figure 54 Pin Diagram,
Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 ix
Figure 55 Package Drawing . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 125
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 x
Tables
Table 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 6 Table 2 MAC Interface Mode Mapping . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 16 Table 3 Supported MDI Pair Combinations . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 18 Table 4 AMS Media Preferences . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 20 Table 5 REFCLK Frequency
Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 20 Table 6 LED Drive
State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7 LED Mode and Function Summary . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 Table 8 Extended LED Mode and Function Summary . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9 LED Serial Bitstream Order . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 30 Table 10 Register Bits for GPIO Control and Status . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 33 Table 11 SerDes Macro Address Map . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 38 Table 12 JTAG Instruction Codes . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 39 Table 13 IDCODE JTAG Device
Identification Register Descriptions . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 40 Table 14 USERCODE JTAG Device
Identification Register Descriptions . . . . . . . . . . . . . . .
. . . . . . . . . . . . 40 Table 15 JTAG Instruction Code IEEE
Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 40 Table 16 Register 18E2 Settings
for RGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 42 Table 17 IEEE 802.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 18 Main Registers . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 45 Table 19 Mode Control, Address 0 (0x00) . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 46 Table 20 Mode Status, Address 1 (0x01)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 47 Table 21 Identifier 1, Address
2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 48 Table 22
Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 48 Table 23 Device Autonegotiation Advertisement, Address 4
(0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 48 Table 24 Autonegotiation Link Partner Ability, Address 5
(0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 49 Table 25 Autonegotiation Expansion, Address 6 (0x06) . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 49 Table 26 Autonegotiation Next Page Transmit, Address 7
(0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 50 Table 27 Autonegotiation LP Next Page Receive, Address 8
(0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 Table 28 1000BASE-T Control, Address 9 (0x09) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 50 Table 29 1000BASE-T Status, Address 10 (0x0A) . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 51 Table 30 MMD EEE Access, Address 13 (0x0D) . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 52 Table 31 MMD Address or Data Register, Address 14 (0x0E) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52 Table 32 1000BASE-T Status Extension 1, Address 15 (0x0F) . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33 100BASE-TX/FX Status Extension, Address 16 (0x10) . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table
34 1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 35
Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 36 Extended Control and Status, Address 19 (0x13) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37 Extended Control and Status, Address 20 (0x14) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 38 Extended Control and Status, Address 21 (0x15) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 39 Extended Control and Status, Address 22 (0x16) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 40 Extended PHY Control 1, Address 23 (0x17) . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56 Table 41 Extended PHY Control 2, Address 24 (0x18) . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57 Table 42 Interrupt Mask, Address 25 (0x19) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 58 Table 43 Interrupt Status, Address 26 (0x1A) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 59 Table 44 Auxiliary Control and Status, Address
28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 59 Table 45 LED Mode Select, Address 29 (0x1D) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 60 Table 46 LED Behavior, Address 30 (0x1E) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 61 Table 47 Extended/GPIO Register Page
Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 62 Table 48 Extended Registers Page 1 Space . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 62 Table 49 SerDes Media Control, Address
16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 63 Table 50 Cu Media CRC Good Counter,
Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 63 Table 51 Extended Mode Control, Address 19E1
(0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 64 Table 52 Extended PHY Control 3, Address 20E1
(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 64 Table 53 Extended PHY Control 4, Address 23E1
(0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 66 Table 54 EPG Control Register 1, Address 29E1
(0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 66
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 xi
Table 55 EPG Control Register 2, Address 30E1 (0x1E) . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 56 Extended Registers Page 2 Space . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 67 Table 57 Cu PMD Transmit Control, Address 16E2 (0x10) . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 68 Table 58 EEE Control, Address 17E2 (0x11) . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 69 Table 59 RGMII Settings, Address 18E2 . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 70 Table 60 Ring Resiliency, Address 30E2 . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 71 Table 61 Extended Registers Page 3
Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 71 Table 62 MAC SerDes PCS
Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 72 Table 63 MAC SerDes PCS
Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 73 Table 64 MAC SerDes Cl37
Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 73 Table 65 MAC SerDes Cl37 LP
Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 74 Table 66 MAC SerDes Status,
Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 74 Table 67 Media SerDes Tx
Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . .
. . . . . . . . . . . . . . 74 Table 68 Media SerDes Tx CRC Error
Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 74 Table 69 Media SerDes PCS Control, Address
23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 75 Table 70 Media SerDes PCS Status, Address 24E3
(0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 75 Table 71 Media SerDes Cl37 Advertised Ability,
Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 76 Table 72 MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 76 Table 73 Media SerDes Status, Address 27E3 (0x1B) . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 76 Table 74 Fiber Media CRC Good Counter, Address 28E3 (0x1C) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 75 Fiber Media CRC Error Counter, Address 29E3 (0x1D) . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table
76 General Purpose Registers Page Space . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 77 SIGDET/GPIO Control, Address 13G (0x0D) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 78 GPIO Control 2, Address 14G (0x0E) . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 79 Table 79 GPIO Input, Address 15G (0x0F) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 80 Table 80 GPIO Output, Address 16G (0x10) . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 80 Table 81 GPIO Input/Output Configuration,
Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 81 Table 82 Microprocessor Command Register,
Address 18G . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 81 Table 83 MAC Configuration and Fast Link
Register, Address 19G (0x13) . . . . . . . . . . . . . . . . . . .
. . . . . . 82 Table 84 Two-Wire Serial MUX Control 1, Address 20G
(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 82 Table 85 Two-Wire Serial MUX Interface Status and
Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . .
83 Table 86 Two-Wire Serial MUX Data Read/Write, Address 22G (0x16)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 87
Recovered Clock 1 Control, Address 23G (0x17) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 88
Recovered Clock 2 Control, Address 24G (0x18) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 89
Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 90
Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table
91 Clause 45 Registers Page Space . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87 Table 92 PCS Status 1, Address 3.1 . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 87 Table 93 EEE Capability, Address 3.20 . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 88 Table 94 EEE Wake Error Counter, Address
3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 88 Table 95 EEE Advertisement, Address
7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 88 Table 96 EEE Advertisement,
Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 89 Table 97 802.3bf
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89 Table 98 VDD25 DC Characteristics . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 90 Table 99 LED and GPIO Characteristics . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 90 Table 100 Internal Pull-Up or Pull-Down
Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 90 Table 101 Reference Clock DC
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 91 Table 102 SerDes
Driver DC Specifications . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table
103 SerDes Receiver DC Specifications . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92 Table 104 Enhanced SerDes Driver DC Specifications . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 93 Table 105 Enhanced SerDes Receiver DC Specifications . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94 Table 106 Current Consumption . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 94 Table 107 Thermal Diode Parameters . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 95 Table 108 Reference Clock AC
Characteristics for QSGMII 125 MHz Differential Clock . . . . . . .
. . . . . . . . . 96 Table 109 Recovered Clock AC Characteristics .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 97 Table 110 SerDes Outputs AC
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 97 Table 111 SerDes
Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table
112 SerDes Input AC Specifications . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 98 Table 113 SerDes Receiver Jitter Tolerance . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 98
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 xii
Table 114 Enhanced SerDes Outputs AC Specifications, SGMII Mode . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 115
Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 99 Table 116 Enhanced
SerDes Driver Jitter Characteristics, QSGMII Mode . . . . . . . . .
. . . . . . . . . . . . . . . . . 100 Table 117 Enhanced SerDes
Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 100 Table 118 Enhanced SerDes Inputs AC
Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 100 Table 119 Enhanced SerDes Receiver Jitter
Tolerance, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 101 Table 120 Basic Serial LEDs AC Characteristics . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 101 Table 121 Enhanced Serial LEDs AC
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 102 Table 122 JTAG Interface AC
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 102 Table 123 AC
Characteristics for RGMII Uncompensated . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 104 Table 124 AC
Characteristics for RGMII Compensated . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 125
Serial Management Interface AC Characteristics . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 126
Reset Timing Specifications . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107 Table 127 Recommended Operating Conditions . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 107 Table 128 Stress Ratings . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 108 Table 129 Pin Type Symbol Definitions .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 109 Table 130 GPIO and SIGDET
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 131
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 112 Table 132 Miscellaneous Pins . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 112 Table 133 Power Supply Pins . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 114 Table 134 RGMII
Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 135 SerDes MAC Interface Pins . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 116 Table 136 SerDes Media Interface Pins . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 116 Table 137 SMI Pins . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 117 Table 138 Twisted Pair
Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table
139 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 126 Table 140 Ordering Information . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 130
Revision History
1 Revision History
This section describes the changes that were implemented in this
document. The changes are listed by revision, starting with the
most current publication.
1.1 Revision 4.4 Revision 4.4 of this datasheet was published in
February 2019. In revision 4.4, VeriPHY descriptions were updated
and VeriPHY register information was deleted. For functional
details of the VeriPHY suite and the operating instructions, see
the ENT-AN0125 PHY, Integrated PHY-Switch VeriPHY - Cable
Diagnostics application note.
1.2 Revision 4.3 Revision 4.2 was published in May 2018. The
following is a summary of the changes in this document.
• Configuration procedure steps were clarified. For more
information, see Configuration, page 42. • The description of bit
10 was updated for register 0. For more information, see Table 19,
page 46. • The description of bit 0 was updated for register 22.
For more information, see Extended Control and
Status, page 55. • Design considerations were updated. For more
information, see Design Considerations, page 127.
1.3 Revision 4.2 Revision 4.2 was published in August 2017. The
following is a summary of the changes in this document.
• All references to LVDS were clarified to reflect LVDS
compatibility. • Operating modes were updated to correctly reflect
available functionality. • A note was added about the use of
recovered clock outputs and fast link failure indication in
EEE
mode. • Data Loops of the SerDes Macro image was updated. • The
equipment loop description was updated to correctly reflect
available functionality. • JTAG ID code was updated. • Timeout
values for ActiPHY link status timeout control registers were
corrected. • The default value for the disable carrier extension
bit of the ActiPHY Control register was corrected
to 1. • EEE Control register descriptions were updated to indicate
sticky bits. • Register 17E3 bit 0 was updated to correctly reflect
available functionality. • Clarification footnotes were added for
register 18G. • Reference clock DC specifications were updated. •
Design considerations were updated. • Temperature specifications
were added to the part ordering information.
1.4 Revision 4.1 Revision 4.1 of this datasheet was published in
July 2013. In revision 4.1 of the document, duplicate entries of
the reserved pins E16 and N3 were removed from the GPIO and SIGDET
pin table. Functionality of these reserved pins remains
unchanged.
1.5 Revision 4.0 Revision 4.0 of this datasheet was published in
January 2013. The following is a summary of the changes implemented
in the datasheet:
• An application diagram was added and existing application
diagrams were updated to accurately reflect the supported
interfaces.
• The block diagram was updated to better represent the functional
blocks. • Configuration information for operating modes was added.
• The RGMII MAC interface illustration was updated to incorporate
appropriate resistance on Rx pins. • Several electrical
specifications were updated.
Revision History
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 2
• Design considerations were added • An illustration showing the
test circuit for the recovered clock output signals was added
1.6 Revision 2.0 Revision 2.0 of this datasheet was published in
November 2012. This was the first publication of the
document.
Product Overview
2 Product Overview
The VSC8552-01 is a low-power, dual-port Gigabit Ethernet
transceiver with two SerDes interfaces for dual-port dual media
capability. It also includes an integrated dual port two-wire
serial multiplexer (MUX) to control SFPs or PoE modules. It has a
low electromagnetic interference (EMI) line driver, and integrated
line side termination resistors that conserve both power and
printed circuit board (PCB) space.
The VSC8552-01 includes dual recovered clock outputs to support
Synchronous Ethernet applications. Programmable clock squelch
control is included to inhibit undesirable clocks from propagating
and to help prevent timing loops. The VSC8552-01 also supports a
ring resiliency feature that allows a 1000BASE-T connected PHY port
to switch between master and slave timing without having to
interrupt the 1000BASE-T link.
Using Microsemi’s EcoEthernet v2.0 PHY technology, the VSC8552-01
supports energy efficiency features such as Energy Efficient
Ethernet (EEE), ActiPHY link down power savings, and PerfectReach
that can adjust power based on the cable length. It also supports
fully optimized power consumption in all link speeds.
Microsemi's mixed signal and digital signal processing (DSP)
architecture is a key operational feature of the VSC8552-01,
assuring robust performance even under less-than-favorable
environmental conditions. It supports both half-duplex and
full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T communication
speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable
at distances greater than 100 m, displaying excellent tolerance to
NEXT, FEXT, echo, and other types of ambient environmental and
system electronic noise. The device also supports two dual media
ports that can support up to two 100BASE-FX, 1000BASE-X fiber,
and/or triple-speed copper SFPs.
The following illustrations show a high-level, general view of
typical VSC8552-01 applications.
Figure 1 • Dual Media Application Diagram
Figure 2 • Copper Transceiver Application Diagram
1.0 V 2.5 V½ QSGMII, 2x RGMII,
2x SGMII, or 2x 1000BASE-X MAC
VSC8552-01 2 ports dual media (fiber or copper)
RGMII, SGMII, half QSGMII
2x 1000BASE-X MAC
SerDes
SCL/SDA
2x SGMII, or 2x 1000BASE-X MAC
VSC8552-01 2 ports copper media RGMII, SGMII, half
QSGMII MAC interface
2x 1000BASE-X MAC
Figure 3 • Fiber Media Transceiver Application Diagram
2.1 Key Features This section lists the main features and benefits
of the VSC8552-01 device.
2.1.1 Low Power • Low power consumption of approximately 425 mW per
port in 1000BASE-T mode, 200 mW per port
in 100BASE-TX mode, 225 mW per port in 10BASE-T mode, and less than
115 mW per port in 100BASE-FX and 1000BASE-X modes
• ActiPHY™ link down power savings • PerfectReach™ smart cable
reach algorithm • IEEE 802.3az-2010 Energy Efficient Ethernet idle
power savings
2.1.2 Advanced Carrier Ethernet Support • Recovered clock outputs
with programmable clock squelch control and fast link failure
indication
(<1 ms; worst-case <3 ms) for G.8261 Synchronous Ethernet
applications • Ring resiliency for maintaining linkup integrity
when switching between 1000BASE-T master and
slave timing • Supports IEEE 802.3bf timing and synchronization
standard • Integrated dual two-wire serial mux to control SFP and
PoE modules • Support for IEEE 802.3ah unidirectional transport for
100BASE-FX and 1000BASE-X fiber media
2.1.3 Wide Range of Support • Compliant with IEEE 802.3 (10BASE-T,
100BASE-TX, 1000BASE-T, 100BASE-FX, and
1000BASE-X) specifications • Support for >16 kB jumbo frames in
all speeds with programmable synchronization FIFOs • Supports Cisco
QSGMII v1.3, Cisco SGMII v1.9, RGMII versions 1.3 and 2.0 (2.5 V),
1000BASE-X
MACs, IEEE 1149.1 JTAG boundary scan, and IEEE 1149.6 AC-JTAG •
Available in a low-cost, 256-pin BGA package with a 17 mm × 17 mm
body size
2.1.4 Flexibility • VeriPHY® cable diagnostics suite provides
extensive network cable operating conditions and status • Patented,
low EMI line driver with integrated line side termination resistors
• Four programmable direct-drive LEDs per port with adjustable
brightness levels using register
controls; bi-color LED support using two LED pins • Serial LED
interface option • Extensive test features including near end, far
end, copper media connector, SerDes MAC/media
loopback, and Ethernet packet generator with CRC error counter to
decrease time-to-market Note: All MAC interfaces must be the same —
all QSGMII, RGMII, or SGMII.
1.0 V 2.5 V½ QSGMII, 2x RGMII,
2x SGMII, or 2x 1000BASE-X MAC
VSC8552-01 2 ports fiber media RGMII, SGMII, half
QSGMII MAC interface
2x 1000BASE-X MAC
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 5
2.2 Block Diagram The following illustration shows the primary
functional blocks of the VSC8552-01 device.
Figure 4 • Block Diagram
Note: All MAC interfaces must be the same—all QSGMII, RGMII, SGMII,
or 1000BASE-X.
LED[3:0]_[0:1]
Q SG
M II/R
G M
II/SG M
LED Interface
SG M
Sync Ethernet
TDP_n TDN_n
RDP_n RDN_n
Q S G
100BASE-FX PCS
3 Functional Descriptions
This section describes the functional aspects of the VSC8552-01
device, including available configurations, operational features,
and testing functionality. It also defines the device setup
parameters that configure the device for a particular
application.
3.1 Operating Modes The following table lists the operating modes
of the VSC8552-01 device.
Note: All MAC interfaces must be the same — all QSGMII, RGMII, or
SGMII.
3.1.1 QSGMII/SGMII MAC-to-1000BASE-X Link Partner The following
illustrations and sections show the register settings used to
configure a QSGMII/SGMII MAC-to-1000BASE-X link partner.
Table 1 • Operating Modes
1000BASE-X See Figure 5, page 7.
QSGMII/RGMII/SGMII MAC-to-100BASE-FX Link Partner
QSGMII/RGMII/SGMII MAC-to-AMS and 1000BASE-X SerDes
1000BASE-X, 10/100/1000BASE-T
100BASE-FX, 10/100/1000BASE-T
QSGMII/RGMII/SGMII MAC-to-AMS and Protocol Transfer mode
SFP/Fiber Protocol Transfer mode (10/100/1000BASE-T Cu SFP),
10/100/1000BASE-T
See Figure 10, page 10.
QSGMII/RGMII/SGMII MAC-to-Cat5 Link Partner
QSGMII/RGMII/SGMII MAC-to-Protocol Transfer mode
See Figure 12, page 11.
1000BASE-X MAC-to-Cat5 Link Partner
Functional Descriptions
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 7
Figure 5 • SGMII MAC-to-1000BASE-X Link Partner
3.1.1.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
Figure 6 • QSGMII MAC-to-1000BASE-X Link Partner
3.1.1.2 MAC interface QSGMII Use the following settings to
configure the QSGMII MAC interface.
• Set register 19G bits 15:14 = 01. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
3.1.1.3 Media interface 1000BASE-X SFP Fiber (1000BASE-X Link
Partner) Use the following settings to configure the 1000BASE-X SFP
fiber media interface.
• Set register 23 bits 10:8 = 010. • Set register 0 bit 12 = 1
(enable autonegotiation). • Set register 18G = 0x8FC1. For more
information, see Table 61, page 71. The F in 0x8FC1 identifies the
port. To exclude a port from the configuration, set its bit to 0.
For example, the configuration of port 0 and port 1 to 1000BASE-X
is 0011 or 3, making the bit setting 0x83C1.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
QSGMII/SGMII, 1000BASE-X,
AutoNeg
4
FIBROP/N_0
FIBRIP/N_0
TXVP_0
TXVN_0
TXVP_3
TXVN_3
Fiber
Fiber
AutoNeg
4
FIBROP/N_0
FIBRIP/N_0
TXVP_0
TXVN_0
TXVP_3
TXVN_3
Fiber
Fiber
3.1.2 QSGMII/SGMII MAC-to-100BASE-FX Link Partner The following
illustration and sections show the register settings used to
configure a QSGMII/SGMII MAC-to-100BASE-FX link partner.
Figure 7 • QSGMII/SGMII MAC-to-100BASE-FX Link Partner
3.1.2.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
3.1.2.2 Media interface 100BASE-FX SFP Fiber (100BASE-FX Link
Partner) Use the following settings to configure the 100BASE-FX SFP
fiber media interface.
• Set register 23 bits 10:8 = 011. • Set register 0 bit 12 = 0
(autonegotiation not present in 100BASE-FX PHY). • Set register 18G
= 0x8FD1. For more information, see Table 61, page 71. For QSGMII
only port 0 is used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.1.3 QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes The
following illustration and sections show the register settings used
to configure a QSGMII/SGMII MAC-to-AMS and 1000BASE-X media
SerDes.
Figure 8 • QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media
SerDes
QSGMII/SGMII, 1000BASE-X,
AutoNeg
4
FIBROP/N_0
FIBRIP/N_0
TXVP_0
TXVN_0
TXVP_3
TXVN_3
Fiber
Fiber
AutoNeg
4
FIBROP/N_0
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 9
3.1.3.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
3.1.3.2 Media interface 1000BASE-X SFP Fiber (1000BASE-X Link
Partner) Use the following settings to configure the 1000BASE-X SFP
fiber media interface.
• Set register 23 bits 10:8 = 010. • Set register 0 bit 12 = 1
(enable autonegotiation).
3.1.3.3 AMS Preference Setup Use the following settings for the AMS
preferences setup.
• Set register 23 bit 10 = 1 (enable AMS). • Set register 23 bit 11
to the port preferences. The media selected by AMS can be read from
register 20E1 bits 7:6. For more information, see Table 4, page
20.
For QSGMII only port 0 is used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.1.4 QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes The
following illustration and sections show the register settings used
to configure a QSGMII/SGMII MAC-to-AMS and 100BASE-FX media
SerDes.
Figure 9 • QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media
SerDes
3.1.4.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
3.1.4.2 Media interface 100BASE-FX SFP Fiber (100BASE-FX Link
Partner) Use the following settings to configure the 100BASE-FX SFP
fiber media interface.
• Set register 23 bits 10:8 = 011. • Set register 0 bit 12 = 1
(enable autonegotiation).
QSGMII/SGMII, 1000BASE-X,
AutoNeg
4
FIBROP/N_0
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 10
3.1.4.3 AMS Preference Setup Use the following settings for the AMS
preferences setup.
• Set register 23 bit 10 = 1 (enable AMS). • Set register 23 bit 11
to the port preferences. The media selected by AMS can be read from
register 20E1 bits 7;6. For more information, see Table 4, page
20.
For QSGMII only port 0 is used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.1.5 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode The
following illustration and sections show the register settings used
to configure a QSGMII/SGMII MAC-to-AMS and Protocol Transfer
mode.
Figure 10 • QSGMII/SGMII MAC-to-AMS and Protocol Transfer
Mode
3.1.5.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
3.1.5.2 Media interface 10/100/1000BASE-T Cu-SFP Use the following
settings to configure the fiber/SFP media interface for protocol
transfer mode.
• Set register 23 bits 10:8 = 001. • Set register 0 bit 12 = 1
(enable autonegotiation).
3.1.5.3 AMS Preference Setup Use the following settings for the AMS
preferences setup.
• Set register 23 bit 10 = 1 (enable AMS). • Set register 23 bit 11
to the port preferences. The media selected by AMS can be read from
register 20E1 bits 7;6. For more information, see Table 4, page
20.
For QSGMII only port 0 is used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
QSGMII/SGMII, 1000BASE-X,
AutoNeg
FIBROP/N_0
3.1.6 QSGMII/SGMII MAC-to-Cat5 Link Partner The following
illustration and sections show the register settings used to
configure a QSGMII/SGMII MAC-to-Cat5 link partner.
Figure 11 • QSGMII/SGMII MAC-to-Cat5 Link Partner
3.1.6.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71. For QSGMII only port 0 is
used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.1.7 QSGMII/SGMII MAC-to-Protocol Transfer Mode The following
illustration and sections show the register settings used to
configure a QSGMII/SGMII MAC-to-Protocol Transfer mode.
Figure 12 • QSGMII/SGMII MAC-to-Protocol Transfer Mode
3.1.7.1 MAC interface SGMII Use the following settings to configure
the SGMII MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 0. • Set register 18G = 0x80F0. For more
information, see Table 61, page 71.
QSGMII/SGMII, 1000BASE-X,
AutoNeg
FIBROP/N_0
AutoNeg
4
4
4
4
FIBROP/N_0
3.1.7.2 Media interface 10/100/1000BASE-T Cu-SFP Use the following
settings to configure the fiber/SFP media interface for protocol
transfer mode.
• Set register 23 bits 10:8 = 001. • Set register 0 bit 12 = 1
(enable autonegotiation). For QSGMII only port 0 is used.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.1.8 1000BASE-X MAC-to-Cat5 Link Partner The following
illustration and sections show the register settings used to
configure a 1000BASE-X MAC- to-Cat5 Link Partner.
Figure 13 • 1000BASE-X MAC-to-Cat5 Link Partner
In this mode the device provides data throughput of 1000 Mbps
only.
3.1.8.1 MAC interface Use the following settings to configure the
MAC interface.
• Set register 19G bits 15:14 = 00. • Set register 23 (main
register) bit 12 = 1.
3.1.8.2 Clause 37 MAC Autonegotiation For clause 37 MAC
autonegotiation, set register 16E3 bit 7 = 1.
Note: Whenever there is a mode change a software reset (register 0
bit 15) is required to make the mode change effective. This
register is cleared when read.
3.2 RGMII MAC The VSC8552-01 device supports RGMII versions 1.3 and
2.0 (2.5 V). The RGMII interface supports all three speeds (10
Mbps, 100 Mbps, and 1000 Mbps) and is used as an interface to an
RGMII-compatible MAC.
QSGMII/SGMII, 1000BASE-X,
AutoNeg
FIBROP/N_0
Figure 14 • RGMII MAC Interface
3.3 SerDes MAC Interface The VSC8552-01 SerDes MAC interface
performs data serialization and deserialization functions using an
integrated SerDes block. The interface operates in 1000BASE-X
compliant mode, QSGMII mode, or SGMII mode. The SerDes and enhanced
SerDes blocks have the termination resistor integrated into the
device. The SerDes block also has the AC decoupling capacitors
integrated in the receive path. Integrated AC decoupling is not
supported in the enhanced SerDes block (QSGMII SerDes). Register
19G is a global register and only needs to be set once to configure
the device. The other register bits are configured on a per-port
basis and the operation either needs to be repeated for each port,
or a broadcast write needs to be used by setting register 22, bit 0
to configure all the ports simultaneously.
3.3.1 SerDes MAC When connected to a SerDes MAC compliant to
1000BASE-X, the VSC8552-01 device provides data throughput at a
rate of 1000 Mbps only; 10 Mbps and 100 Mbps rates are not
supported. To configure the device for SerDes MAC mode, set
register 19G, bits 15:14 = 0, and register 23, bit 12 = 1. The
device also supports 1000BASE-X Clause 37 MAC-side autonegotiation
and is enabled through register 16E3, bit 7. To configure the rest
of the device for 1000 Mbps operation, select 1000BASE-T only by
disabling the 10BASE-T/100BASE-TX advertisements in register
4.
Figure 15 • SerDes MAC Interface
3.3.2 SGMII MAC When configured to detect and switch between
10BASE-T, 100BASE-T, and 1000BASE-T data rates, the VSC8552-01
device can be connected to an SGMII-compatible MAC. To configure
the device for SGMII MAC mode, set register 19G, bits 15:14 = 00
and register 23, bit 12 = 0. In addition, set register 18G as
RGMII MAC
TXC
TX_CLK TX_CTL
RX_CLK RX_CTL
10 Ω
10 Ω
10 Ω
10 Ω
10 Ω
10 Ω
VMDS-10401 VSC8552-01 Datasheet Revision 4.4 14
desired. This device also supports SGMII MAC-side autonegotiation
and is enabled through register 16E3, bit 7.
Figure 16 • SGMII MAC Interface
3.3.3 QSGMII MAC The VSC8552-01 device supports a QSGMII MAC to
convey two ports of network data and port speed between 10BASE-T,
100BASE-T, and 1000BASE-T data rates and operates in both
half-duplex and full- duplex at all port speeds.The MAC interface
protocol for each port within QSGMII can be either 1000BASE-X or
SGMII, if the QSGMII MAC that the VSC8552-01 is connecting to
supports this functionality. To configure the device for QSGMII MAC
mode, set register 19G, bits 15:14 = 01. In addition, set register
18G as desired. The device also supports SGMII MAC-side
autonegotiation on each individual port and is enabled through
register 16E3, bit 7, of that port.
Note: Two of the four QSGMII channels contain data. The windows for
the other two channels remain present and need to be supported in
both directions by the MAC. This support is called “half
QSGMII.”
Figure 17 • QSGMII MAC Interface
3.4 SerDes Media Interface The VSC8552-01 device SerDes media
interface performs data serialization and deserialization functions
using an integrated SerDes block in the SerDes media interface. The
interface operates at 1.25 Gbps speed, providing full-duplex and
half-duplex for 10/100/1000 Mbps bandwidth that can connect
directly to 100BASE-FX/1000BASE-X-compliant optical devices as well
as to 10/100/1000BASE-T copper SFP devices. The interface also
provides support for unidirectional transport as defined in IEEE
802.3-2008, Clause 66. The SerDes interface has the following
operating modes:
SGMII MAC
• QSGMII/RGMII/SGMII to 1000BASE-X • QSGMII/RGMII/SGMII to
100BASE-FX • QSGMII/RGMII/SGMII to SGMII/1000BASE-X protocol
transfer The SerDes media block has the termination resistor
integrated into the device. It also has the AC decoupling
capacitors integrated in the receive path.
A software reset through register 0, bit 15 is required when
changing operating modes between 100BASE-FX and 1000BASE-X.
3.4.1 QSGMII/RGMII/SGMII to 1000BASE-X The 1000BASE-X SerDes media
in QSGMII/RGMII/SGMII mode supports IEEE 802.3 Clause 36 and Clause
37, which describe 1000BASE-X fiber autonegotiation. In this mode,
control and status of the SerDes media is displayed in the
VSC8552-01 device registers 0 through 15 in a manner similar to
what is described in IEEE 802.3 Clause 28. In this mode, connected
copper SFPs can only operate at 1000BASE-T speed. A link in this
mode is established using autonegotiation (enabled or disabled)
between the PHY and the link partner. To configure the PHY in this
mode, set register 23, bits 10:8 = 010. To configure 1000BASE-X
autonegotiation for this mode, set register 0, bit 12. Setting this
mode and configurations can be performed individually on each of
the two ports. Ethernet packet generator (EPG), cyclical redundancy
check (CRC) counters, and loopback modes are supported in
1000BASE-X mode.
3.4.2 QSGMII/RGMII/SGMII to 100BASE-FX The VSC8552-01 supports
100BASE-FX communication speed for connecting to fiber modules such
as GBICs and SFPs. This capability is facilitated by using the
connections on the SerDes pins when connected to a MAC through
QSGMII/RGMII/SGMII. Ethernet packet generator (EPG), cyclical
redundancy check (CRC) counters, and loopback modes are supported
in the 100BASE-FX mode. Setting this mode and configurations can be
performed individually on each of the two ports. To configure the
PHY in this mode, set register 23, bits 10:8 = 011.
3.4.3 QSGMII to SGMII Protocol Conversion QSGMII to SGMII (protocol
transfer) mode is a feature that links a fiber module or triple
speed 10/100/1000-T copper SFP to the QSGMII MAC through the
VSC8552-01 device. SGMII can be converted to QSGMII with protocol
conversion using this mode.
To configure the PHY in this mode, set register 23, bits 10:8 =
001. To establish the link, assert the relevant signal-detect
pin.
All relevant LED modes are supported except for collision, duplex,
and autonegotiation fault. The triple- speed copper SFP’s link
status and data type plugged into the port can be indicated by the
PHY’s LEDs. Setting this particular mode and configuration can be
performed individually on each of the two ports within a QSGMII
grouping.
3.4.4 Unidirectional Transport for Fiber Media The VSC8552-01
device supports IEEE 802.3ah for unidirectional tran