( An X-masking Scheme for Logic Built-In Self-Test Using a Phase-Shifting Network )

( Dong-Sup Song and Sungho Kang )

v+!t$-?h The Institute of Electronics Engineers of Korea h--* " http:llwww.ieek.or.kr

"-mssking. Scheme for Logic Built-In Self-Test Usin, Phase-Shifting Network )

1 L ~ , I I U - ~ U ~ song and a ~ ~ g l l u L W ~ J

ing scheme

Abstrac

ng logic b luilt-in self '-test The new scher ne exploits . .

n this paper, we propose a new X-mash for utilizi the phase-shifting networlc which is based on the shift-and-add property of maximum length pseudorandom bmry sequences(m-sequences). The phase-shifting networlc generates mask-patterns to multiple scan chains by appropriately shifting the m-sequence of an LFSR. The number of shifts required to generate each scan chain mask pattern can be dynamically reconfigured during a test session. An iterative sinidation procedure to synthesize the phase-shifting networlc is proposed. Because the number of candidates for phase-slufting that can generate a scan chain mask pattern are very large, the proposed X-masking scheme reduce the hardware overhead efficiently. Experimental results demonstrate that the proposed X-masldng technique requires less storage and hardware overhead with the conventional methods.

Keyword: 5 : Logic : BIST, res ponse con npaction, g, phase- shifting

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(Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)

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Function phase-nehvork-synthesis Input : mask pattern sets M Output : phase-shift value of each scan chain over all configurations (a) set i =l (b) initialize PP- fable, TP-fable ;

while(M + empty) begin (C) '-..'-a'- a?' for each scan chain; (d) rent mask pattern; (e) ,er-mask-pattern(PFfable. m,)) b (f) ce P;');

e current mask pattern m, from M; (9) te PP table

lnluallze t m, := cur while(cov

redu, dele11 upaa

end whilc store cur i=i+l;

end while - . . . (i) se1ec1-pnase connauratlon(Pir'rIedUce): end phase-nehnrorl

1% 4. + I & ~ O I HIE943 3% g z z ~ g Fig. 4. Phase-shifting network synthesis algor~tnm.

(a) i = l Z 4 x 2 @c).

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@cF.

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@ q .

(1) u;, u ; ~ F EY- ?xJ 2$ 1 ui = vi

(2) U; 7) U-H] E

(3) V; 71 U-HIE

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%& A 4 2 k ] ~ ; j ) ~ %);(I. pj(;' = P/~'-FS 93 gq pjl;'x i ,z. -

2 TL+E+. I,\ D n -table% 9 cilolE@q. (el21 x1zJ 011 Aj 1 SF

2 LFSRO] JJ+IS\+ q+$01 5l.q 3 744 8F%O"Z q + $ 1 9% %* LFSRoll

(A) Mask at tern set . . m ! m2 i m3 I m, / ms 1 m6

Scan chain 1 O U ~ U / UUIU / UUUU! UOUU I UUIU OUUU Scan chain 2 UUIU / UUUO; UOUU / UUUl I UIUU I UUIU Scan chain 3 1UUUi UIUU/ UIUU~ UUOU ~UUUO~UUIU

(5) Phase network synthesis Init. ) (a) ml

PI"': (1, 2, 3,4. 5.6,7,8,9. 10, 11, 12, 13, 14, 15) (4, 6, 9, 10, 1: PZ('': (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) (1,3,5,6,g; P3('': (1, 2, 3,4,5,6, 7, 8, 9, 10, 11, 12, 13, 14, 15) (2, 3, 5, 7, 8 , .

(c) m3 (d) ma (e) None : End of conti. 1.

(9. 10. 12. 14) (12. 14) (12. 14) (3.5) (3. 5) (3. 5) (2, 11) (11) ( )

(C) ~j("rseuce

(a) Init. P$') (b) plU'. P ~ ' ~ ' . pJ2), pJ2) (c) PJ') P : (12. 14) (14) (14) PJ" : (3. 5) (3, 5) (3) ~ $ 1 ' : (11) (1 1) (11) PI"' : (4, 5, 8, 14) (14) (14) ~ 2 " ' : (1. 9. 13. 15 (15) (15) pJ2' :

(D) TP-tt sble and PP-

PP

-table

tahb

- - Pl",cirOl 41E943 3 2 ql Example Fig. 5. of phase-

- - .

shifting ne ttwork synt hesis.

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;r 3. EhtB%kPI EIIZE undoll C H 3 X - n t h 3 g3 ?33t(p=0.2O/) Table 3. Experimental results for pseudorandom test patterns.

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[ll E. H. Volkerink and S. Mitra, "Response compaction with any number of unknowns using a new LFSR archtecture," Proc of Design Automation Conference, pp. 117-122, 2005.

[21 G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proc of International Test Corrference, pp. 358-367, 1999.

131 K. K Saluja and M. Karpovsky, "Testing computer hardware through data compression in space and time," Proc of International Test Gnference, pp. 83-88, 1983.

[41 mt ra and K. S. I(lm, "X-Compact: an efficient response compaction technique for test cost reduction," Proc. $ International Test Conference, pp. 311-320, 2002.

151 J. Rajski, C. Wang, J. yuszer, and S. M. Reddy, "Convolutional compaction of test responses," Proc of International Test Gderence, pp. 745-754, 2003.

[61 C. Barnhart, V. Brunkhorst, F. Distler, 0 . Famsworth, B. Keller, and B. Koenemann, "OPMISR: The foundation for compressed ATPG Vectors," Proc. of International Test Conference, pp. 748-757, 2001.

[71 C. Barnhart, V. Brunkhorst, F. Distler, 0 . Famsworth, A. Ferlco, B. Keller, D. Soctt, and B. Koenemann, "Extending OPMISR beyond lox scan test efficiency," IEEE Design & Test of Computers, Vol. 19, no. 5, Oct., pp. 65-73, 2002.

[81 J. Rajslu, J. Tyszer, M. Kassab, N. Mukherjee,

R. Thompson, K. H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian, "Embedded deterministic test for low cost manufacturing test," Proc. of International Test Conference, pp. 301-310, 2002.

[91 M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu, "On-chip compression of output responses with unknown values using LFSR reseeding," Proc of International Test Conference, pp. 1060-1068, 2003.

[I01 T. Clouq~~eur, K. Zanineh, K K. Saluja, and H. Fujiwara, "Design and analysis of multiple weight linear compactors of responses containing unknown values," Proc of International Test Gderence, pp. 2005.

[Ill Y. Tang, H. J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, "X-Masking During Logic BIST and Its Impact on Defect Coverage," Proc gf International Test Conference, pp. 441-451, 2004.

[I21 P. H. Bardell, W. H. Mcanney, and J. Savir, Built-In Test for VLSI: Pseudorandom Technique, New York: Wiley, 1987.

[I31 J. Rajski and J. Tyszer, "Design of phase shlfters for BIST applications," Proc of VLSI Test Symposium, pp. 218-224, 1998.