WORST-CASE NOISE AREA PREDICTION OF ON-CHIP POWER DISTRIBUTION NETWORK

Xiang Zhang1, Jingwei Lu2, Yang Liu3 and Chung-Kuan Cheng1,2

1 ECE Dept., University of California, San Diego, CA, USA2 CSE Dept., University of California, San Diego , CA, USA3 Institute of Electronic CAD, Xidian University, Xi’an, China

2014-06-01

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EXECUTIVE SUMMARY Problem: Previous works focus on the worst-peak

droop to sign off PDN. Worst-peak noise ≠ Worst timing (delay)

Our goal: To predict a PDN noise for better timing sign off.

Observation: The noise area of PDN => Behavior of circuit delay

Case study: Design the worst-case PDN noise area Provide analytical solution for a lumped PDN model Design an algorithm for general PDN cases

Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path.

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POWER DISTRIBUTION NETWORK (PDN)

Power supply noise Resistive IR drop Inductive Ldi/dt noise

PDN model

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MOTIVATION

Performance sensitivity on PDN voltage drop Increased signal delay [Saint-Laurent’04]

[Jiang’99] Clock jitter [Pialis’03]

Delay vs supply voltage(courtesy of [Saint-Laurent’04])

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PDN NOISE AREA VS DELAY

Delay is measured under a modified C432 of ISCAS85 circuit in 130nm node5

PROBLEM FORMULATION PDN Characterization

Impulse Response h(t)

Voltage Noise:

• Input to PDN system• Transient load current

demand i(t)• Assumption:

• All on-die loads lumped into a single load

• Total current is bounded

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PROBLEM FORMULATION Worst-case peak noise [Hu et al @ SLIP2009]

where the worst-current :

Voltage Noise Area Integral within sliding window Window size T corresponds to

one clock cycle Defined as , a function of

input current

Worst-case optimization Design of current and voltage drop Achieve maximum noise area Aw and interval Can be solved by polynomial-time method

0

( ) ( ) ( )t

peakv t h i t d when when

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PROBLEM SIMPLIFICATION Binary-valued worst current

Can be proved that only switches between 0 and 1 Current decomposition

equals the superposition ofa series of step inputs

Single step input & response Step response Integrate into ramp response Noise area function

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SIMPLIFIED PROBLEM FORMULATION

A linear-constrained linear optimization problem

Input A power network system with impulse response

h(t) Given window size T

Output Window location Phase delay of step inputs,

Objective Maximum noise area Aw within

Constraints , t is

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CASE STUDY: RLC TANK MODEL Impedance Profile: , where

Assume Q>0.5, system is underdamped Step Response :

where

Ramp Response :

where

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WORST NOISE AREA PREDICTION FOR RLC TANK Given a window size T, worst-area noise is

is set to a relatively large value when . is

is the time when local peaks/valleys of occur. Solved by setting since is piecewise-defined func.

Case 1 (): is the solution of , i.e.

Case 2 ():

where.

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CASE STUDY: WORST NOISE AREA PREDICTION FOR GENERAL PDN CASES

Real PDN structure is complicated Consists of multiple frequency components Develop algorithm

Algorithm design for general cases– Given window size T and arbitrary impulse response – Determine the phase delay of each step input – Constructs by superposing – Maximum noise is achieved

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INTUITION Align all together to generate

Select one point from to determine the phase delay Maximize (+) by choosing peak points Minimize (-) by choosing valley points Determine as the last peak of .

= sum of all peaks- sum of all valleys13

ALGORITHM DESIGN Given &

Impulse response and window size

Generate , and Step responses and its

transformation Extract all peaks and valleys of

Linear scanning on Calculate each peak-to-valley

distance Determine phase delay

accordingly Determine (t) by and its sign (±)

Construct adding up all together 14

COMPLEXITY ANALYSIS

Our algorithm consists of finite operations Step response transformation Linear scan for peaks & valleys extraction Worst-case current construction

Overall complexity is O(n) Finite amount of operations Each operation consumes no larger than linear

runtime

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EXPERIMENTAL DESIGN AND RESULTS Setup:

Matlab R2013a HSPICE D-2013.03-SP1 Cadence Allegro Sigrity Power SI 16.6 Ansoft Q3D 12.0 ISCAS85 circuit under 0.13um cell lib Intel i7 Qual-Core 3.4GHz w/16GB PCDDR3

PDN test cases Single RLC tank Cascaded RLC tanks A complete PDN path extracted from industrial design

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WORST-PEAK AND WORST-AREA NOISE OF A SINGLE RLC TANK CASE

Nominal Vdd= 1V, T=17nsBoth load current activities stop at

10mΩ 250pH

33nF

12mΩ

i(t)

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WORST-AREA AND WORST-PEAK NOISE OF MULTI-STAGE CASCADED RLC TANKS Circuit Model

Three Cases Case I can be approximated to three single RLC tanks:

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WORST-AREA AND WORST-PEAK NOISES OF MULTI-STAGE CASCADED RLC TANKS Compare the worst-case noise predcition

from the analytical solution approximations from RLC tank decomposition vs solution of Algorithm 1

for

Prediction Error (on average) : 7.75% for the worst-peak noise 12.3% for the worst-area noise 19

WORST-PEAK AND WORST-AREA NOISE OF A COMPLETE PDN PATH Impedance Profile:

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WORST-PEAK AND WORST-AREA NOISE OF A COMPLETE PDN PATH Worst-peak and worst-area noise solved by Alg. 1 ,

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DELAY MEASUREMENT OF A COMPLETE PDN PATH

Send input pulse every 100ps and record delay of the datapath at the output port of C432 (ISCAS85) case

Compare the delay under worst-peak and worst-area noise

Results:

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CONCLUSIONS Problem: Previous works focus on the worst-peak

droop to sign off PDN. Worst-peak noise ≠ Worst timing (delay)

Our goal: To predict a PDN noise for better timing sign off.

Observation: The noise area of PDN => Behavior of circuit delay

Case study: Design the worst-case PDN noise area Provide analytical solution for a lumped PDN model Design an algorithm for general PDN cases

Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path. 23

Q & A

Thank You!

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Backup Slides

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DELAY MEASUREMENT OF SINGLE RLC TANK CASE Send input pulse every 100ps and record delay of

the datapath at the output port of C432 (ISCAS85) case

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