Wafer level system integration: a review

Wafer Level System Integration: A S. K. Tewksbury and L. A. Hornak

Review

Introduction

The allure of wafer scale integration (WSI) has stimulated continuing evaluations of its potential, starting during the early ages of integrated circuits [l] and continuing aggressively even now [2-51. These evaluations have generally fallen into two categories:

1. Attempts to develop commercial WSI products, allowing introduction of complex monolithic system functions before IC densities became available for those functions 161.

2. Focussed research to develop the fundamental principles which will be needed as an underlying foundation for WSI components when the advantages of WSI become compelling over other alternatives to advanced technologies (2-5, 7-11].

Failures in the first category are most widely known, and have produced a popular view that WSI has been demon- strated to be impractical. Explorers in this category sought the “Seven Cities of Gold” for commercial profits and fi- nanced their quests with grand promises of extraordinary capabilities. Unfortunately, the realities fell far short of promises when practical constraints, for the particular WSI products pursued, severely degraded performance and/or elevated costs. Along with early advocates of GaAs, silicon carbide, superconductors and other advanced technologies, these WSI entrepreneurs found little profit in competing with the rapidly evolving silicon technology.

Efforts in the second category are less well publiciLed. These explorers have sought to provide reasoned and accurate mappings of the frontiers exposed during studies of WSI related components. This background of information will be of considerable importance when WSI’s time arrives and it is this background of design information that is emphasized in this review. However, remaining open is the question of whether WSI will enjoy a time in the sun or whether the commercial failures are harbingers of more serious limitations-

I t appears that a significant opportunity now exists for

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development of one particular wafer-scale commercial product-large semiconductor memories [E]. With I-Mbit RAM IC chips now routinely achieved and 4-Mbit chips expected soon, a single wafer can hold several MByte of memory. Initial WSI memory layouts opted to emulate disk memory systems, though later designs may extend random accessibility to the entire “silicon disk.“ Repair of defective RAM ICs using physical reprogramming has been in routine use since the 64-KByte RAMS and can be directly used within a WSI “silicon” disk, with higher-level repair strat- egies used for the overall array of “memory chips.” Such WSI memory arrays seem likely to be available within a few years.

A second significant development is seen in hybrid circuits using silicon wafers as the hybrid substrate [13, 141. This technology addresses packaging problems in a manner that emulates a wafer scale circuit while relaxing the limits imposed by having to repair defective cells. Silicon wafer hybrid circuits are being aggressively developed by several commercial firms and are also likely to find applications within the next couple of years. In addition, the silicon wafer substrate provides a solid foundation for introduction of advanced interconnection technologies (i.e., distributed drivers, efficiently integrated glue circuitry, optical interconnections [15, 161, etc.).

I n most other potential applications, the continuing advances in silicon VLSI density and performance suggest that general WSI applications will not emerge until rapid development of VLSI densities and performance saturates. Indeed, it is the widely held belief that minimum feature sizes will be encountered in the range 0.2-0.4 pm that provides the basis for most studies of future alternatives to silicon MOS IC technologies. These minimum geometries are not tar from commercial practice, i.e., are about a factor between 2 and 4 smaller than leading edge commercial technologies. To understand the impact of an end to the feature size scaling of silicon circuits, imagine that we have now reached, in the front-line commercial components, the minimum feature size. Inquiries to manufacturers on what’s in store for the “next generation” microprocessor, next generation signal processor, etc. would yield the response that interest has switched to finding previously untapped new functions and that there will be no major advances beyond the VLSI circuit you now hold. We have come to expect routine improvements in the digital electronic systems we purchase, routine improvements driven by the scaling of silicon devices to smaller sizes and introduction of a new generation of VLSI circuits with each new generation of technology. Either the historical development of increasingly powerful digital systems at lower cost and with smaller size each year must be driven by some new technology (GaAs? heterojunction silicon? optical logic? quantum devices? WSI?) or the roller coaster ride of the past 20 years of electronics products comes to a near standstill.

Among the alternative new technologies, we suggest that WSI (or equivalently high density, large area monolithic

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circuits and hybrid substrates) has the best opportunity to become a mainstream electronics technology, fueling the mapping of large, powerful digital systems into future gen- erations of new systems. With the exception of wafer-level components and hybrid substrates, the “new” technologies possibly replacing silicon are all directed primarily at high- speed digital circuit applications in which power dissipation and other practical limitations are likely to assign those technologies to specialized applications until some more distant time in the future. Without demeaning the potential of those new technologies over the long term, minimum feature size silicon devices will be reached far before those technologies can become mainstream replacements for silicon. Even if there is only a temporary, evolutionary exten- sion of silicon technologies into the time gap between the age of silicon and the “age of something else,” that time gap will be considerable and the wafer level technologies will play a critical role.

The time for mainstream WSI silicon circuits is not yet here, aside from some specialized functions such as memory. However, WSI’s “time in the sun” is rapidly approach- ing (arguably within the next five years, more likely by the end of the 1990s) and it is time to get ready. The following sections review several of the critical issues which have been clarified over the past few years. Discussions of the several specific applications investigated for WSI (and potential short term advantages of WSI for those applications) are not included here. Such application issues are very well covered in the proceedings [24 j of recent WSI workshops and these proceedings are highly recommended. The issues discussed below are covered more thoroughly in [SI, where an extensive set of references is provided.

Yield and Reliability Issues

With each new generation of VLSI technology, yields start at relatively low levels and development of the technology leads to improvements in that yield, following a generic learning curve. When the higher levels of yield for a mature learning curve are achieved routinely, it is time to move to the next generation of technology. In this manner, each new generation of technology is based on the solid foundation of a mature, high yield process in the pre- ceding generation. Although wafer-scale circuits extend over such large areas that low yield is almost ensured, the repair and reconfiguration mechanisms are not crutches to sup-

Fig. 1. Yield vs normalized a m for randomly distributed defects (Poisson modell.

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port a low yield IC technology. To remain a member of the expedition to future silicon technologies, a prerequisite is that high yields be achieved for chip-level components at each generation of the technology. Therefore, we empha- size at the onset of this section that the mechanisms for enhancing WSI yield are not substitutes for high IC yields. Instead, these yield-enhancement mechanisms are used to allow areas to grow beyond those that support a high chip yield.

“Classical” IC Yield Models The simplest model of IC yield is the simple Poisson

model, with yield, illustrated in Fig. 1, given by

Y(Poissan) = Y,,c (1)

where Y,, is the “gross yield“ representing unusable wafer area near the wafer edge, A is the defect density (defects/ cm’) and A, is the chip’s active area. This Poisson model presumes that defects are randomly distributed across the area of the wafer and that one or more defects falling within the active area of a given chip will cause that chip to fail. Defect densities are in the range A

Actual yield results show a somewhat slower descent of yield with increasing IC area than predicted by the simple Poisson model (allowing circuit designers to move to somewhat larger chip areas). The physical origin of the specific defects involved can be largely ignored in the VLSI chip yield models and the overall yield results viewed as a char- acteristic “engineering result” asking to be fit to some simple engineering model. Stapper’s model [17], in fact, achieves that end of providing a simple engineering model. Stap- per’s ”negative binomial“ distribution result, analytically obtained using compound Poisson statistics, gives the chip yield as a function of chip area A as

l/cm2.

Fig. 2. Comparison of Poisson modeland Stapper’s negative binomial model.

The clustering parameteds can be readily determined given the average defect density and its first moment. Fig. 2 shows the exponentially decreasing yield predicted by the Poisson model and the more slowly decreasing yield predicted by (2). The Stapper model, widely used for most analyses of wafer-scale circuit yield with repairheconfiguration, reduces to several earlier models (e.g., Seed-Price model, etc.) with the appropriate changes in parameters.

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Whereas the IC yield models above provide a very powerful tool for estimating the number of faulty components as a function of circuit area, they necessarily must mask the multitude of mechanisms that actually cause the defects. Just as CAD tools have allowed optimization of VLSI circuits through automated layout rules and through sim- ulations, so also can computer aided design and simulation provide the basis not only for evaluating yield but also for minimizing the sensitivity of a specific layout to individual defect mechanisms. In particular, one can seek to develop automated VLSI design tools that decrease the circuit’s sensitivity to defects, providing an effective “yield enhancement” optimization strategy. Work at Carnegie-Mellon, for example, has emphasized such tools [18].

Reliability and Failure Mechanisms

Much of the emphasis in wafer-scale integration has been on improving the manufacturing yield of large-area circuits with expected low intrinsic yields. This is certainly essential since the WSI components cannot be placed on distributors’ shelves until they are tested and shown to work. However, WSI will be quickly condemned to an unsightly death if the WSI components do not demonstrate a high reliability in service. Among the many steps between fabrication and sale of a VLSI IC is an extensive effort to separate out those components which, though working at the time of test, are weak and will fail early during service. Reliability issues increasingly confront VLSI 1Cs [19, 201 since several of the failure mechanisms are accelerated as feature dimensions shrink. However, the impact on WSI components is more fundamental. In particular, schemes to fix a WSI circuit with fabrication faults fall into two classes: (1) schemes that physically repair the circuit or restructure the circuit to by- pass faulty components and (2) schemes that provide programmable electronic switches within the circuitry to reconfigure the components, bypassing faulty components. The first scheme is generally restricted to unpackaged components (e.g., wafer-level repair of VLSI ICs such as laser- based connection of spare rows and/or columns in high density RAMS). Once packaged and placed in service, these physical repairhestructuring schemes are no longer available to fix a non-functional component. Failure would then not be corrected while the component is “in the field.” The second class, programmable reconfiguration, provides the option in several cases of repairing a component that has failed while in service (i.e., by programming a new reconfiguration while the component is in the system). If failures become a serious problem, then reliable WSI components might strongly favor electronically programmed reconfiguration schemes rather than wafer-level physical repair for yield enhancement.

The principal failure mechanisms in silicon VLSl are the following:

1. Metal electromigration inducing interconnection shorts

2. Gate oxide breakdown (particularly early wearout) 3. Hot electron injection into the gate oxide 4. Alpha particle-induced transient failures 5. CMOS latchup 6. Metastability failures in synchronihg circuits [21]

and opens and contact shorts and opens [20]

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Fault Modeling and Testing

The task of testing complex VLSl circuits is already recognized as Herculean. However, WSI imposes perhaps even more serious constraints on accurate and reliable early testing since the wasted costs of restructuring and packaging a circuit with an undetected fault is very high. Fortunately for WSI, the problem of testing and the corresponding need for effective fault models in designing the tests also confront VLSI, for which an extensive literature and a wide range of experience has been developed. This strong foundation can be tapped by those seeking efficient but effective testing procedures for WSI circuits. Typically, these powerful techniques, such as built-in-self-test, design-for-testability, functional testing (such as advocated by Abraham and his coworkers [U]), delay-fault testing, etc., impose some circuitry overhead and perhaps some performance overhead on the circuit component. These area and performance penalties place a VLSI chip component designed for testability at a severe disadvantage relative to those which leave the problems posed by full testing of VLSI ICs un- resolved. In contrast to VLSI ICs, WSI long ago had to endure the embarrassment of lowered performance and circuit area overhead as part of its mechanism for handling low yields. In this sense, a WSl circuit may suffer very little additional area or performance overhead for testability over the overhead already added for yield enhancement).

Physical Restructuring Techniques

Assuming that an element of the WSI (or large-area IC) circuit is faulty, that defective element must generally be removed from the circuit. Generally, after removal of the defective circuit, it is necessary to replace the faulty component with a functional spare. Since the spares are located somewhere else on the wafer (hopefully nearby) and cannot themselves be moved, a new set of interconnections must be provided. Physical restructuring, as considered here, often applies the technologist’s skills as a microsurgeon to “cut away“ the defective part and “transplant” a good part into its place. An altemative to this “reconstruction approach’ is the ”constructionist” approach in which nothing is initially connected and the microsurgeon tests and then attaches only the working parts to a set of general purpose interconnection lines embedded throughout the circuit. In neither case is our microsurgeon’s task easy, particularly when combined with the requirement that this set of local microsurgical operations be completed rapidly to avoid ex- cess costs. in particular, the cost of surgically repairing a defective WSI circuit must be sufficiently low that the net cost (initial fabrication + added repair cost of defective units) per final functioning unit is less than the net cost per initially functional unit obtained by simply discarding faulty WSI components. The validity of the principle of restructuring is no longer in question, with high density RAMS

‘Of course, the performance degradation for yield enhancement causes possible disadvantages for WSI relative t o VLSI. Here, it is assumed that WSl has been adopted for reasons which outweigh these performance degradations for yield enhancement or for functions which do not suffer significant desradations with yield en- hancements- e.g., mrmories.

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Fig. 3. Electranic (a) VS physical (b) propamming of interconnections.

generally relying on physical repair to achieve enhanced yields. Physical repair techniques include:

Laser zapping and laser linking Laser-assisted chemical etching and deposition of interconnections [241 Focussed ion beams [E]

9 Electron beam repair

With the vast number of possible microsurgery approaches, there was a clear need for a systematic evaluation of (1) the specific microsurgery techniques, ( 2 ) the potential damage to nearby regions, (3) the yield of such local steps, and (4) the throughput rate at which circuits can be physically altered. The RVLSI (Restructurable VLSI) program at Lincoln Labs (261 has greatly clarified several of these ques- tions, producing not only examples of the local effects of surgery but also functional wafer scale circuits.

Programmable Reconfiguration

Programmable reconfiguration places electronic switches and alternative interconnection paths at critical points in the WSI circuit function to allow "electronic replacement" of a faulty function element with a spare function element. These critical switching points and the alternative interconnections are conceptually similar to the placement of physically programmed fuses and antifuses and routing of spare interconnections for physical restructuring. The electronic switch combines the functions of a fuse and an antifuse, perhaps simplifying the organization of repair points.

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However, at the same time, electronic switches carry the overhead of state control data storage and interconnections to set the desired switch states at each switching site. Fig. 3 illustrates the various circuit and interconnection requirements of the electronic switch relative to a physically programmed fuse/anti-fuse.

The additional circuitry required to store the switch state information (i.e., element "connected" or "disconnected") and tire additional area to distribute that control information to and load it into the switch state store register should be modest relative to the circuit element replaced by reconfiguration. This degrades the advantages of very small serial data replaceable elements (the small elements having been initially chosen to maximize their individual yield and reduce the area overhead of spare data paths for repair). In particular, each such small replaceable element requires addition of the switch state store and the control interconnections to the switch state store. This additional area ouer- head is relatively larger for very small replaceable elements than for larger parallel data replaceable elements. The tradeoffs are quite complicated and there have been only limited studies of the general overhead tradeoffs among the various alternatives of WSI circuit partitioning into different sized replaceable elements and between serial and parallel data interconnections.

Area overhead is not the only issue confronted with "electrical reconfiguration." In many functions, delay of signals on interconnections can seriously impact the performance of the function. Systolic arrays provide a clear example. As delays on interconnections become significant relative to the minimum clock period needed to cycle the individual systolic array cells, the throughput rate of the systolic array decreases. The contrast between physically restructured cells and electronically restructured cells is illustrated in Fig. 3. By providing a high power driver at the outputs o f each cell, a line passing through several physically programmed antifuses can be driven at speeds similar tQ those on an uninterrupted line of the same length (assuming the resistance of the antifuses in the closed state is smaller than the line resistance between antifuses). The electronic reconfiguration switches, on the other hand, if designed as small area switches, are high resistance switches (minimum MOSFET sizes give resistances of several KO). The high resistance switch followed by the line capacitance of line segments between switches has the effect of emulating a very high resistivity interconnection line.

Despite the larger area overhead and possible larger degradation in speed, electronic reconfiguration of a WSI circuit has major system level advantages over physical restructuring as a general means of maintaining the oper- ation of the WSI circuit throughout its useful life. In particular, the repair process is not a one-time act but can be repeated during packaging or during service to repair any faults that appear following fabrication and wafer testing. On the other hand, electronic reconfiguration may not be well suited for some repair problems. One example is the issue of hard faults, e.g., a defective clock distribution network or a faulty power distribution network. Providing electronic repair of such hard faults typically is difficult and physical repair or restructuring of these networks to correct such hard faults may be preferred (presuming, of course, that the defect point can be identified). To provide an op- timal balance among the various repair requirements, it seems likely that repair will evolve to a combination of physical repair of specific critical manufacturing defects and

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electronic reprogramming of the functional configuration to repair manufacturing faults and in-service functional failures.

Small-Gra in Cell, R e p lar A rray Recon f tgura tion

Much of the work on reconfiguration of regular arrays with fine-grain cells draws on the general results developed by Synder and his colleagues in the CHiP parallel computer project 1271. Fig. 4 illustrates three examples of CHiP "lat- tice" arrays. Here, the individual array elements are embedded within a set of regular interconnections and switches, with the desired interconnection patterns in the target array obtained by programming the individual switches of the array. The CHiP architecture is designed to allow a wide variety of point-to-point interconnection networks to be implemented using a single general physical interconnection structure. In addition to the objective of programming a general purpose parallel array of processors to obtain a special purpose point-to-point array matched to the problem being executed, the programmability also al- lows repair of defective arrays, a feature well recognized in the early work on the CHiP computer.

Large-Grain Cell, Regular Array Reconfiguration

Reconfiguration of regular arrays using large-grained cells (i.e., more powerful computation nodes) and parallel data interconnections has received less practical evaluation than arrays of fine-grained cells. However, there may be advantages in using smaller arrays of more complex computing nodes (e.g., parallel data arithmetic functions or microcom- puter nodes) than larger arrays of simpler nodes [28, 291.

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With large-grain cells, the control state circuitry needed to specify whether the node is connected or disconnected is small relative to the functional circuitry of the node. The principal issue is the area overhead required for redundant interconnection paths, now perhaps requiring several lines NI,,,h per path to handle parallel data rather than a single line for serial data, and the circuitry overhead for programmable switching of those paths (Le., N,,,,,,, switches per path rather than a single switch per path). Such large- grained cells would allow the use of WSI to form arrays of powerful computing sites with bus-oriented system level interconnections or with networks connecting those sites. Such architectures would, in turn, extend the advantages of WSI from special purpose signal processing applications to more general purpose computing systems applications.

Switch-Connected Heterogeneous Cells

An interesting example suggested by Chen et al. [30] illustrates application of WSI to heterogeneous system or- ganizations. In this case, a number of resources are provided, with either multiple copies of a given resource provided or different resources able to be programmed to implement the same function as some other resource(s). As shown in Fig. 5, these various resources are interconnected using a programmable switch matrix programmed to inter- connect a particular sequence of modules to execute the application problem. This example avoids the need for separate reconfiguration circuitry, drawing on the natural programmability of the multi-module function itself.

Random Logic: A Personal V i m

Random logic is the dominant model of IC circuitry used for supercomputers. The model spawned the famous Rent's Rule for the number of U 0 connections as a function of the number of gates in a circuit and provides the environment requiring very advanced packaging techniques such as the thermal conduction module developed by IBM. Since supercomputers traditionally have exploited the most advanced technologies available, it is natural that attempts would be pursued to implement the considerable low-level intepated (high speed, high power dissipation) circuitry using WSI to provide compact supercomputer logic. The

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famous Trilogy effort, for example, pursued this objective of implementing a high-end IBM computer using WSI. Random logic functions provide none of the structural con- venience of neighboring array cells serving as replacements for nearby defective cells by a relatively simple, locally con- strained reconnection of a few data paths. Instead, physically nearby gates must be partitioned into a set of physically replaceable random logic functions. Detection of faults is difficult and triple modular redundancy (TMR) provides a convenient universal procedure to combine the requirement for functional spares with the requirement for real time testing. Conceptually, this procedure does not seem unattractive, since one might place the three random logic functions and comparison logic of a TMR cell into a single physical cell. This replacement of each random logic cell with a TMR version of that cell is unreliable, however, when defect clustering is strong. Under those conditions, if one random function unit of a TMR cell is faulty, neighboring cells have a relatively high likelihood of also failing, somewhat defeating the objectives of the single error-detection/ correction capabilities of the TMR approach. To avoid correlated failures of the replicated circuitry forming a TMR module, the set of three random function cells and the comparison circuitry can be scattered over the overall WSI circuit area, separating the individual modules of a TMR cell and avoiding the correlated failures of its identical modules. However, having corrected for the deficiency under defect clustering, one may have forfeited the high speed capability originally assumed in the random logic supercomputer function. In particular, the long interconnection lines to the various triplicated modules and then to the comparison circuit add considerable delays relative to the speed of the targeted system application. This general problem has been reported as one of the principal underlying reasons for the failure of the Trilogy effort.

Theoretical Results

When confronted with a complex system function (e.g., an array of lower level functions) which must be trans- formed into a repairable system function, the design of the WSI implementation is obviously more complex than simply implementing an unrepairable design. In many cases, the problem reduces to a combination of choosing the appropriate placement of reconfiguration points and redundant interconnection paths and then choosing a suitable algorithm for converting a defective circuit into a functional circuit. Often, a5 in the case of regular signal processing arrays such as systolic arrays, the placement of switches and spare interconnections and the reconfiguration algorithm significantly impacts the performance of the array. Fortunately for the WSI designer, a variety of general theoretical results provide a foundation for balancing such layout and performance issues. A major objective of such theoretical studies is precise specification of the algorithms under very general array conditions (e.g., for various size arrays) and proof that the suggested algorithm achieves some well-defined performance under such general conditions. Well publicized results include the following:

1. Rosenberg's Diogenes approach [lo]: The Diogenes approach provides a universal approach for many regular starting arrays while providing a natural mechanism to locally implement reconfiguration depending

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simply on whether the local site is functional or defective. The penalty is longer than necessary interconnection lengths, leading to suboptimum performance in those cases where added interconnection delay degrades performance.

2. Systolic arrays: Green and Gama1 [SJ provided an early analysis for the theoretical issues imposed by such performance degradation. Leighton and Leiserson [9] extended those results, demonstrating limits for linear arrays and rectangular arrays under quite different constraints, i.e., (1) that all functional cells must be used or (2) that specific functional cells forcing exces- sively long interconnections can be discarded.

3. Self-reconfiguration algorithms [ll]: In contrast to the mapping of a general array into an effective linear array, as in the Diogenes approach, the self-reconfiguration algorithm in [ll] retains the two-dimensional array structure while providing locally driven self-organization of a defective array into a functional array.

4. Spare row and column reconfiguration in memories: Memory arrays are repaired through use of spare rows and columns, a technique that can also be applied to regular computation arrays (i.e., if an element in a column is defective, cast aside the entire column and use instead a spare column). Kuo and Fuchs [31] provides a good survey of techniques used for spare row/ column allocation, including heuristic techniques for rapid allocation.

Hybrid Wafer Scale Integration

Silicon Circuit Boards - "Pseudo- WSZ?" WSI requires that the designer presume that cells are

defective and explicitly include mechanisms to convert the faulty circuit into a functional circuit. Having achieved this, WSI then provides the advantages of implementing conventional chip-to-chip interconnections within the more be- nign (in terms of both density and, often, performance) environment of "on-chip" interconnections. Some of the "chigto-chip" interconnection advantages provided by WSI can be achieved, without having to be concerned with using repair mechanisms for yield enhancement, by using a hybrid approach to wafer scale integration, as suggested in the early work of Spielberger et al. 1131. Fig. 6 illustrates their general approach,

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3-0 Wafer-Level Modules

The potential advantages of WSI-level components are considerably increased when one considers stacking wafer- level components prior to packaging them for system level assembly. Workers at Hughes Research I351 first reported such stacking of wafer-level circuits. The work on interconnection issues and technologies for future systems pursued by Hornak and Tewksbury 116,341 has explicitly presumed three-dimensional structures of wafer-level components, using a mixture of monolithic and hybrid WSI components. McDonald et al. (321 have also considered stacked wafers for high-speed, hybrid WSI systems using CaAs ICs as the active circuits and silicon wafers as the substrate. Although successful development of 3-D wafer-level system modules is clearly several years away, the system volume potentially saved is clearly substantial and such structures represent a natural future evolutionary path for individual wafer-level components.

Fig. 7. Reconfigurable army of FIR filter sections [29]. Uppcr ha& monolithic array (2 x 5) with programmable reconfiguration frames around each FIR filfw. Lower hull; silicon circuit board with pmgrammableframes (2 x 4 arruyJ for flip-chip mounting of FIR filter VLSl circuits. Miscellaneous FIR filter sections not in arrays m e included to m i d large unused amas during fabrication.

While later work followed generally similar approaches qualitatively, thicker dielectrics and thicker metallization (with copper replacing aluminum alloys) have become fa- vored. McDonald and his colleagues at RPI [321 have studied a wide variety of issues impacting silicon circuit boards for high speed ICs. The emphasis in their work on achieving transmission lines for high speed signals validates their name-Wafer Transmission Module (WTM). Relatively thick (= 5pm) copper interconnections are used in a multi-level metallization scheme with thick (== 10pm) polyimide dielectrics to provide both signal lines and power/ground planes. The metallization dimensions were chosen on the basis of achieving wideband interconnections and are rep- resentative of dimensions used in other hybrid WSI work.

The several programs aimed a t developing silicon circuit boards for multichip modules must confront many practical issues that are generally accommodated by conventional PC board interconnection systems. Conventional IC packaging schemes are strongly entrenched and system organ- izations strongly reflect the performance limits imposed by conventional IC package constraints. The AT&T Advanced VLSI Packaging (AVP) program [331 was a significant ex- ploratory development program directly addressing the practical issues presented by silicon circuit board technologies.

The examples above use the silicon substrate as a passive layer on which the passive interconnections are placed. Tewksbury e t al. [16, 29, 341 have advocated integration of circuitry in the silicon circuit board, providing, for example, efficient integration of “glue circuitry” and high power drivers directly in the circuit board. This integration of active circuitry in the silicon substrate distinguishes the hybrid WSI approach from other thin film hybrid circuit approaches. Fig. 7 shows a photograph of a two-project wafer, one half of the wafer providing the monolithic WSI array of FIR filter sections discussed in (291 and the other half a hybrid WSI substrate with reconfiguration and driver circuitry on which discrete FIR filter chips are flip-chip mounted.

Optical Interconnects in WSZ Components When interconnection lengths move beyond about 1 cm,

significant performance degradation IS often encountered. As a result, a variety of alternative interconnection schemes have been proposed for such longer distance interconnections (relative to conventional on-chip signal interconnections). Wafer level components provide an environment perhaps better suited for aggressive application of novel interconnection technologies than standard ICs, PC boards, equipment racks, etc. Optical interconnections have received particular interest [15, 16, 36-40] and with the aggressive development of integrated electro-optics for communications purposes, components are appearing which might be suitable for on-wafer optical interconnections. In addition to the appearance of arrays of optoelectronic devices (e.g., suitable for mounting as hybrid components on either monolithic or hybrid WSI components), a variety of new optical waveguide materials based on polymers [39, 401 have recently been reported and might serve as a non- intrusive technology for overlaying optical waveguides on high density VLSI circuits. In addition to such hybrid components and overlaid waveguide structures, several silicon devices can be used as efficient detectors of optical signals (at appropriate wavelengths).

Several “classical” ideas for optical interconnections applied at distances comparable to those seen in wafer-level components are covered in [lS, 36-38]. Not yet clear is the extent to which optical beams can be moved around a silicon wafer, emulating the routing of electrical signals ac- cording to function-specific layout constraints. General routing and layout issues are presently being studied within the wafer-level component environment by one of us (LAH).

Silicon Wafers: Platform for Advanced Technologies

The above discussion concerning optical interconnections applied to wafer-level components and the application of WTMs for GaAs system functions by McDonald illustrate a major advantage of both monolithic and hybrid WSI components- in particular, the monolithic wafer-level environment is well suited as a foundation for mounting (or, as in the case of GaAs-on-silicon, epitaxially growing and fabricating) on silicon a variety of circuit components using novel and advanced technologies. Assembling a sys-

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tem entirely out of any new advanced circuit technology (GaAs or silicon heterojunction components, quantum well devices, etc.) seems unlikely so long as silicon’s simpler technology can provide a significant portion of the required system functions. Using advanced silicon technologies (e.g., to provide high speed, very high density dynamic memories) in combination with more difficult advanced technologies (where such technologies can provide a significantly higher performance) seems to provide a much more realistic model of future system technologies than models presuming the eventual complete dominance by some new emerging device technology. Since such ultra-high performance technologies and components are likely to be ex- pensive relative to silicon CMOS technologies, a reasonable perspective is that “cheap silicon” will provide the packaging and interconnection foundation for selectively intro- ducing those new devices into practical systems. It is this longer term view of systems technologies which highlights the eventual role both of wafer-level silicon components and three-dimensional wafer-level modules.

The Future - A Personal Perspective

In the 1970s, manipulation and generation of light beams was progressing very nicely. By combining lasers with a mirror positioned here, a grating positioned over there, a beamsplitter sitting near the middle and other various me- chanicaVoptical components, exciting results were obtained on the light benches. At the time, Stu Miller of Bell Labs, recognizing the inconvenience of placement and alignment of all these components and the limits imposed by that inconvenience, suggested the concept of integrated optics. Since then, the field of integrated optics has compressed the large light bench of assorted optical components onto single substrates (lithium niobate, CaAs, and others). Al- though there were many exciting new structures to explore in this small world and several significant technological barriers to be overcome, the basic principles of moving light around and otherwise manipulating light beams did not fundamentally change. Instead, possibilities offered by those fundamental principles in the small world of integrated optics were aggressively explored and a mature technology providing much of the current excitement on the potentials of light both in communications and in computing was developed. Without meaning to degrade the incredible ac- complishments achieved in the field of integrated optics, 1 would suggest that the most apparent accomplishment was a revolution in packaging.

1 would extend this analogy to electronics by suggesting that many of the bottlenecks now facing future electronic systems, and similarly the general lack of truly exciting new projections on the future revolution that will be provided by integrated electronics, are direct results of electronics having failed to pass through a revolution in packaging. This may sound drastic. However, in the late 196Ds, the single board “multivibrators” and single board “quad gates” used for custom digital control systems were remarkably similar to the circuit board packaging of large digital systems routinely used today. Granted that the little plastic covered components soldered into those early PC boards (card-cage mounted in equipment racks, much as today) held little electronics relative to today‘s VLSI IC packages. But aside from what was within the plastic, little else has

SEPTEMBER 1989

significantly changed. Monolithic and hybrid wafer-scale integrated systems represent the revolution in packaging needed to sustain the momentum of the electronics revolution which silicon ICs have driven. The emphasis on “packaging” here may seem to highlight a mundane issue. However, this ignores the reality that our present combination of discrete ICs, PC boards, card cages and equipment racks does not provide a suitable platform for introduction of new high-performance device and interconnection technologies into large-scale systems. Forgetting for a moment the great practical obstacles to short term introduction of a major change in system integration and the new architectures supported, reflect for a moment on that time in the future targeted by competing novel technologies such as superconductors, heterojunction bipolar transis- tors, quantum resonant tunneling devices, optical com- puters, neural networks, etc. At that point, a revolution in system packaging and interconnection will necessarily have had to occur. And from that future perspective, drawing on the superb mechanical properties of silicon as a general support medium for microscopic devices and macroscopic components, it is relatively easy to imagine large silicon wafers as the foundation not only for the evolution of today’s silicon VLSI technology but also as the packaging and interconnection foundation for those technologies of the future.

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30 IEEE CIRCUITS AND DEVICES MAGAZINE

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Wafer level system integration: a review

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