WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS

Clemson UniversityTigerPrints

All Theses Theses

12-2007

WAFER PROBE AND PACKAGE TESTFAILURE ANALYSISDeepa KalvaClemson University, [email protected]

Follow this and additional works at: https://tigerprints.clemson.edu/all_theses

Part of the Electrical and Computer Engineering Commons

This Thesis is brought to you for free and open access by the Theses at TigerPrints. It has been accepted for inclusion in All Theses by an authorizedadministrator of TigerPrints. For more information, please contact [email protected].

Recommended CitationKalva, Deepa, "WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS" (2007). All Theses. 258.https://tigerprints.clemson.edu/all_theses/258

https://tigerprints.clemson.edu?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

https://tigerprints.clemson.edu/all_theses?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

https://tigerprints.clemson.edu/theses?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

https://tigerprints.clemson.edu/all_theses?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

http://network.bepress.com/hgg/discipline/266?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

https://tigerprints.clemson.edu/all_theses/258?utm_source=tigerprints.clemson.edu%2Fall_theses%2F258&utm_medium=PDF&utm_campaign=PDFCoverPages

mailto:[email protected]

WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS OF NAND FLASH MEMORY

A Thesis Presented to

the Graduate School of Clemson University

In Partial Fulfillment of the Requirements for the Degree

Master of Science Electrical and Computer Engineering

by Deepa Kalva

December 2007

Accepted by: Dr. William R. Harrell, Committee Chair

Dr. Kelvin Poole Dr. Michael A. Bridgwood

ii

ABSTRACT

In recent years, NAND flash memory has gained a lot of momentum in the

semiconductor industry and has become an ideal choice for many consumer and

communication products. One of the key elements in the successful production of NAND

flash memory is to incorporate elaborate testing methods to ensure functionality and

reliability before the part reaches the customer. This in turn necessitates the evaluation

and understanding of different failure mechanisms, and the development of

methodologies to correct problems.

In this thesis, failure analysis was performed on NAND flash memory at wafer

and package level. This involved massive data collection and evaluation of failures at

both the wafer level and package from several thousand parts using PERL scripts and

software codes. In the process of analysis, a test for reading the flash memory resulted in

unusually high failure rates at the package level. Failure data was collected in order to

study the trends and correlations with various parameters such as applied voltage, the

proximity of failures on a wafer, the cell characteristics of each failing die compared to

good die, and the threshold voltage distribution. A series of tests and experiments

indicated that the reason for the higher failure rate was due to the positioning of the test

for programming time in the package test flow. This altered the threshold voltage

distribution of the flash cells in a way that resulted in higher fails after the test for read.

When the added test for programming time was moved to a different location the result

was a decrease in failure rate. This study resulted in a fundamental understanding of the

iii

key issues in NAND flash memory. Even a very slight shift of the flash cell threshold

voltage distribution can change the operation of the cell. Thus, failure analysis of NAND

flash memory at wafer and package level presents methodologies and corrective actions

which curb the occurrence of those kinds of failures for future products.

iv

DEDICATION

I dedicate this thesis to my parents, my husband, sister and brother; this thesis

would not have been possible without their support.

v

ACKNOWLEDGEMENTS

I am indebted to my advisor, Dr. Harrell for all of his assistance and guidance

throughout this thesis. Working with him helped me acquire invaluable organizational

skills. I am grateful to Dr. Poole for his invaluable contribution towards my education at

Clemson. I wish to thank Dr.Bridgwood for being in my thesis committee. Finally, I am

thankful to my family, my friends and colleagues at Micron who have been tremendous

source of support and encouragement throughout my studies at Clemson University.

vi

TABLE OF CONTENTS

Page

TITLE PAGE....................................................................................................................i

ABSTRACT.....................................................................................................................ii

DEDICATION................................................................................................................iv

ACKNOWLEDGMENTS ...............................................................................................v

LIST OF FIGURES ........................................................................................................ix

LIST OF TABLES........................................................................................................xiii

CHAPTER

1. INTRODUCTION .............................................................................................1

1.1 Motivation..................................................................................................1 1.2 Thesis Organization ....................................................................................2

2. THEORETICAL BACKGROUND...................................................................4

2.1 Overview of Flash memory .......................................................................4 2.1.1 Flash Cell Structure........................................................................6 2.1.2 Memory Array Architecture of NAND Flash Parts .....................11 2.1.3 Operational Modes of the NAND Flash Memory Chip...............14 2.1.3.1 Program Operation.........................................................15 2.1.3.2 Erase Operation..............................................................18 2.1.3.3 Read Operation ..............................................................21 2.2 NAND Flash Memory Chip Fabrication Process ....................................23 2.3 NAND Flash Memory Testing.................................................................30 2.3.1 Wafer Probe/Test on NAND Flash Parts .....................................31 2.3.1.1 Redundancy/Repair strategy in Wafer Probe.................35 2.3.1.2 Overview of Defect Failure Analysis at Wafer Probe ...36 2.3.2 Package Test on NAND flash parts .............................................38 2.3.2.1 Package Tests in Electrical Flash Test Flow..................39 2.3.2.2 Overview of Defect Failure Analysis at Package Test ..............................................................45

vii

Table of Contents (Continued)

Page

2.3.3 Introduction to the Wafer Map Tool Used for Failure Analysis ........................................................................46 2.3 Summary..................................................................................................47

3. FAILURE ANALYSIS OF WAFER PROBE AND PACKAGE TEST.........48

3.1 Analysis at Wafer Probe ..........................................................................48 3.1.1 Procedure for the Extraction of Wafer Probe Repair Data ..........50 3.1.2 Observation of the Trends/Patterns for Repair Data....................51 3.1.3 Explanation for the Cause of the Generated Patterns ..................56 3.2 Analysis at Package Test .........................................................................58 3.2.1 Procedure for the Extraction of Package Test Failure Data.........59 3.2.2 Observation of the Failure Trends/Patterns for Different Package Tests............................................................................61 3.2.3 Explanation for the Cause of the Generated Patterns ..................70 3.2.4 Variation of Trend for the Failure Data of Read1 Test................72 3.3 Summary..................................................................................................74

4. METHODOLOGIES FOR THE DETECTION OF HIGH BLOCK FAILURE RATES AFTER READ1 TEST ................................................75 4.1 First Approach -Extraction of History on Parts with High Failure Rate...........................................................................................76 4.2 Second Approach - Use of Wafer Map Tool to Determine the Causes for Increase in Block Failure Rates ..........................................79 4.3 Third Approach – Package Tests Performed on the Parts With Higher Failure Rate......................................................................82 4.4 Summary..................................................................................................83 5. DETECTION OF HIGHER BLOCK RATE AFTER READ1 PACKAGE TEST ..........................................................................85 5.1 Standard Test Flow Employed for NAND Flash Parts............................86 5.2 Observation of Deviation from Standard Test Flow................................87 5.2.1 Procedure Addition of Test for Programming Time on NAND Flash Parts......................................................88 5.2.2 Variation in Threshold Voltage Distribution of NAND Flash Parts ....................................................................90 5.3 Mechanism for the Increase in Block Failure Rate after Read1 Test ......97 5.4 Summary..................................................................................................99

viii

Table of Contents (Continued)

Page

6. THEORETICAL CALCULATIONS FOR PROGRAMMING AND ERASING A NAND FLASH CELL ................................................101 6.1 Calculation of charge stored on the Floating Gate of a NAND Flash Cell................................................................................101 6.2 Mechanism of Electron Injection into the Floating Gate of a NAND Flash Cell................................................................................107 6.3 Calculation of Tunneling Current (Itun) using Fowler Nordheim Tunneling Mechanism ........................................................................110 6.4 Calculation of Required Energy to Erase a NAND Flash Cell ..............118 7. SUMMARY AND CONCLUSIONS ............................................................125

APPENDICES .............................................................................................................128

A: Block Failure Data after Read1 Test........................................................128 B: Block Failure Data after Read1 Test with Programming Time Test moved in Standard Test Flow .......................................................141 C: NAND Flash Memory Data Sheet ...........................................................154 LIST OF REFERENCES.............................................................................................155

ix

LIST OF FIGURES

Figure Page 2.1 Applications of NAND Flash Memory..............................................................5

2.2 Physical Layout of Single Flash Cell.................................................................7

2.3 Circuit Symbol of Single Flash Cell ..................................................................7

2.4 Energy Band Diagram of a Floating Gate Memory during Programming by

FN Tunneling ..............................................................................................9

2.5 Energy Band Diagram of a Floating Gate Memory during Erasing by

FN Tunneling ............................................................................................10

2.6 NAND Array Architecture...............................................................................12

2.7 Array Architecture of NAND Flash Memory Chip .........................................13

2.8 Array Organization of NAND Flash Memory Chip ........................................14

2.9 Programming of a NAND Cell ........................................................................16

2.10 Programming “0” for a Single Flash Cell ........................................................16

2.11 Programming “1” for a Single Flash Cell ........................................................17

2.12 Threshold Voltage Distribution after Program Operation ...............................18

2.13 (A) Erasing of a NAND Flash Array ...............................................................19

(B) Schematic of Selected NAND Cell for Erase...........................................19

2.14 Threshold Voltage Distribution after Erase Operation ....................................21

2.15 Reading of a NAND Flash Array.....................................................................23

2.16 Schematic of Selected NAND Cell for Read...................................................23

x

List of Figures (Continued)

Figure Page 2.17 (A) Reading “0” Programmed Cell.................................................................23

(B) Reading “1” Erased Cell...........................................................................23

2.18 Epitaxy .............................................................................................................25

2.19 Photolithography..............................................................................................25

2.20 (A) Etch............................................................................................................26

(B) Strip ...........................................................................................................26

2.21 Diffusion and Implantation ..............................................................................27

2.22 Deposition of Oxide Layer...............................................................................27

2.23 NAND Flash Memory Cell..............................................................................27

2.24 Chip Manufacturing Process............................................................................29

2.25 NAND Flash Memory Testing.........................................................................30

2.26 Wafer Probe Set Up .........................................................................................33

2.27 Probe Card .......................................................................................................33

2.28 Fully Automated Wafer Probing System.........................................................33

2.29 (A) Memory Repair for NAND Flash Memory Devices .................................36

(B) Increase of Yield with Memory Repair .....................................................36

2.30 Package Test Set-Up ........................................................................................39

2.31 Logical Checkerboard Test Pattern for Speed Timing Write Test ..................41

2.32 Physical Checkerboard Test Pattern for Speed Timing Write Test .................42

2.33 Checkerboard ‘0’ Test Pattern for Speed Timing Write Test ..........................44

xi

List of Figures (Continued) Figure Page 2.34 Wafer Maps.......................................................................................................47

3.1 Plot of Column Repair Data after Wafer Probe for

2Gb NAND Flash Parts ................................................................................53

3.2 Plot of Block Repair Data after Wafer Probe

for 2Gb NAND Flash Parts...........................................................................55

3.3 Column Fails due to Process Variations ...........................................................57

3.4 Plot of Block Fails after Speed Timing Write Test (High Corner Vcc) ...........63

3.5 Plot of Block fails after Speed Timing Write Test (Low Corner Vcc).............64

3.6 Plot of Block Fails after Speed Timing Read Test ...........................................66

3.7 Plot of Block Fails after Speed Timing Write Test (with logical ‘0’

checkerboard test pattern) .............................................................................68

3.8 Plot of Block fails after Read1 Test ..................................................................69

3.9 Plot of Expected Trend after Read1 Test ..........................................................73

3.10 Plot of Unexpected Trend after Read1 Test......................................................73

4.1 Wafer Map of NAND Flash Parts after Read1 Test .........................................81

5.1 Threshold Voltage Distribution after Erase Operation .....................................93

5.2 Threshold Voltage Distribution after Programming Time Test........................93

5.3 Threshold Voltage Distribution after Block Erase............................................95

5.4 Threshold Voltage Distribution after Read1 Test .............................................96

xii

List of Figures (Continued) Figure Page 5.5 Plot of Block Fails after Read1 Test with Programming Time moved in

Standard Test Flow .....................................................................................98

6.1 Schematic Cross Section of Single NAND Flash Cell with

Intrinsic Capacitances ...............................................................................102

6.2 Number of stored electrons in a NAND Flash cell .........................................107

6.3 Equivalent Circuit of a NAND Flash Cell ......................................................109

6.4 Programming a NAND Flash Cell ..................................................................110

6.5 Erasing a NAND Flash Cell............................................................................111

6.6 Measured I-V Characteristics of NAND Flash Cell .......................................115

6.7 Fowler-Nordheim plot of the FIGURE 6.3

(a) Forward direction (b) Reverse direction..............................................116

6.8 Energy Band Diagram of a Floating Gate Memory during Erasing by FN

Tunneling .................................................................................................119

xiii

LIST OF TABLES

Table Page 3.1 Column Repair Data at Wafer Probe for 2Gb NAND Flash Parts ..........52

3.2 Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts ........54

6.1 Comparison of 2Gb NAND Flash Cell Parameters from Micron

and Research Paper ...................................................................................114

1

CHAPTER 1

INTRODUCTION

1.1 Motivation

NAND Flash memory has become a promising source for the growing memory

storage requirements, and now a days is an ideal choice for applications requiring a large

amount of data storage, such as digital cameras and camcorders, PDA’s, MP3 players,

digital consumer equipment including cell phones, and removable storage media such as

USB disks and Flash Cards. Extensive research efforts are being carried out by the

semiconductor companies to provide quality control of the NAND Flash memory

produced to ensure that good parts are being shipped to the customers. It is profitable and

efficient to detect and eliminate the defective chips at an early stage of production.

Hence, failure analysis forms an integral part of any company’s growth.

In this thesis, we studied and characterized high failure rate observed in a sample

of NAND flash chips. There was an observed increase in the failure rate occurred when

the failure data was extracted for at Package Test 2Gb NAND flash at Micron

Technology, Inc. The investigation into the possible causes for these failures will help to

eliminate the defects in the future, enhance the production cycle, and improve the overall

quality and yield of product.

2

1.2 Thesis Organization

This thesis is divided into seven chapters.

We present in Chapter 2 a theoretical background on NAND flash memory and

provide insight into the NAND cell structure, its memory array architecture, and the

operational modes. This is followed by a discussion of the NAND flash chip fabrication

process and flash memory testing at the wafer level and after packaging. An overview of

the failure analysis is then presented. Towards the end of this chapter, we introduce a

wafer map software tool that is used for failure analysis.

Chapters 3 begins with details on the extraction of large volumes of failure data

before and after the die are packaged. The procedure followed for the extraction of failure

data at wafer level and package level are illustrated in this chapter. Then the failure data

was plotted to look for parts with higher failures. We discuss towards the end of chapter

about the observation of increase in failure rate at package test.

We present in Chapter 4 three different methodologies employed for the

determination of reasons for the higher failure rate in a sample of NAND flash parts after

Read1 Test. We present that the first two methods were not conclusive and the third

method was speculated as the possible reason for higher failure rates. In this chapter, we

also illustrate the need to study the threshold voltage distribution of NAND flash parts

before and after the tests conducted at package level to investigate the reason for increase

in failure rates.

3

We analyze the failure data at package test in Chapter 5 and discuss in detail

about the variation in the threshold voltage distribution of NAND flash parts for the tests

performed in package test flow. We present towards the end of chapter the mechanism

for the increase in failure rates at Package Test and the corrective actions employed for

decreasing the failure rates.

In Chapter 6, details of programming and erasing a NAND flash cell using

Fowler Nordheim (FN) mechanism are illustrated. Tunneling current and minimum

number of electrons injected into the floating gate of a NAND flash cell are calculated

from FN tunneling equation. Also, the minimum energy required to erase a flash cell is

computed in this chapter from minimum count of electrons injected into the floating gate.

Chapter 7 summarizes the results and draws conclusions to this thesis work

which shall be useful for similar kind of failures and yield improvement in the future.

CHAPTER 2

THEORETICAL BACKGROUND

2.1 Overview of Flash Memory

Electronic memory comes in a variety of forms to serve a variety of purposes. The

strong consolidated know-how, the flexibility, and the cost make the Flash memory a

largely utilized, well-consolidated, and mature technology for most of the nonvolatile

memory applications [1]. Flash memory is non-volatile, and thus will retain stored data

even when the system is powered off [2-4]. Flash memory also offers fast write, erase,

and read access times. Even though the volatile memories like SRAM and DRAM are

faster than flash in reading and writing, their contents are lost when power is switched off

[1]. These characteristics explain the popularity of flash memory for applications such as

storage in battery-powered devices and mass-storage devices such as PC cards and

various memory cards.

Low power consumption, small size, and relatively low cost make flash memory

an ideal option for many applications. Flash memory is widely used for easy and fast

information storage in consumer devices such as Notebook computers, Digital Cameras,

Cell phones, Personal Digital Assistants (PDA’s), Solid-state music players such as MP3

players, Pagers, Personal computers, and Global Positioning Systems (GPS) as shown in

FIGURE 2.1. Flash memory also finds use in many industrial applications where

reliability and data retention in power-off situations are key requirements. Typical

industrial applications include Military and Security systems, Embedded computers,

5

Solid-state disk drives, Wireless communication devices, Networking and

Communication products, Medical products such as handheld scanners, and retail

management products. Thus, NAND flash memory is used extensively for applications

requiring large amount of data storage memory.

FIGURE 2.1 Applications of NAND Flash Memory

Source: www.nuhorizons.com/products

Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in

1984. According to Toshiba, the name 'Flash' was suggested by Dr. Masuoka's colleague,

Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of

a flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International

Electron Devices Meeting held in San Jose, California. NAND flash memory from

Samsung and Toshiba followed in 1989 [15].

6

2.1.1 Flash Cell Structure

Flash memory stores information in an array of floating gate transistors, called

"cells", each of which stores one bit of information. Newer flash memory devices,

referred to as multi-level cell devices, can store more than 1 bit per cell, by varying the

number of electrons placed on the floating gate of a cell [7]. A single NAND flash cell is

basically a floating-gate MOS transistor which stores 1 bit of information. The physical

layout of single NAND flash cell is illustrated in FIGURE 2.2, and describes it as an n-

channel transistor with a gate completely surrounded by dielectrics, referred to the

floating gate (FG), and is electrically controlled by a capacitively coupled control gate

(CG) [1]. The circuit symbol of a single NAND flash cell with control gate, floating gate,

and source and drain contacts is as shown in FIGURE 2.3.

The floating gate and the control gate of a NAND flash cell are made of

polysilicon. Polysilicon is the traditional material to use for transistor gates since the

material is stable enough to withstand high temperature process. Using polysilicon for

both the floating gate and control gate simplifies the process, and also stores the charge

quite well. The FG is essentially located between the CG and the substrate, as seen in

FIGURE 2.2, but the FG is isolated by an insulating oxide layer. Any electrons placed on

the FG are trapped there, and thus the storage of the information is achieved.

The interpoly dielectric (IPD) that separates the FG from the CG in FIGURE 2.2

is formed by a triple layer of oxide–nitride–oxide (ONO). The ONO films form a triple

layered capacitor structure, which features the high dielectric constant of silicon nitride

(Si3N4) deposed between two silicon dioxide (SiO2) films. The structure thus can provide

7

higher program/ erase speeds and better data retention characteristic. The ONO thickness

is normally in the range of 15–20 nm. The gate dielectric, i.e., the one between the

transistor channel and the FG in FIGURE 2.2, is an oxide in the range of 9–10 nm. SiO2

is the industry standard material used for the tunnel oxide. The dielectric constant as well

as the work function of silicon dioxide is best suited for the NAND cell transistor. SiO2

is called a tunnel oxide because electrons flow through it via the Fowler Nordheim (FN)

tunneling mechanism [25].

FIGURE 2.2 Physical Layout of Single Flash Cell

FIGURE 2.3 Circuit Symbol of Single Flash Cell

8

Fowler-Nordheim tunneling, also called field emission, is the process by which

electrons tunnel through a barrier of reduced width in the presence of a high electric field.

The charge needed to program the device has to be injected into the floating gate. The FN

tunneling mechanism is used in order to change the charge or the data content of the cell

[5]. Programming and erasing of a flash cell is done by using FN tunneling mechanism

which is explained as follows.

During programming a flash cell, a relatively large voltage of about 20V is

applied at the control gate. The energy band structure will be significantly changed from

the equilibrium state influenced. This band structure gives rise to charge storage.

FIGURE 2.4 illustrates the energy band diagram of a floating gate memory during

programming by FN tunneling. ec and ev are the conduction and valence bands

respectively, Eg is the energy band gap (1.1 eV for silicon), and Øb is the Si-SiO2 energy

barrier (Øb is 3.2 eV for electrons and 4.7 eV for holes). The applied control voltage

creates the electric field which changes the potential barrier. The change in barrier

reduces the width allowing the electrons in the substrate to tunnel through the thin gate

oxide (typically less than 12 nm) and eventually be collected in the n+ poly-Si floating

gate. The collection of electrons on the floating gate increases the threshold voltage as it

requires larger control voltage to turn on the flash cell. The bending of the energy bands

of the IPD and the gate oxide are different due to the thickness differences between them.

Thus, programming a flash cell by FN tunneling puts the electrons into the floating gate

and the cell stores logic ‘0’.

9

FIGURE 2.4 Energy Band Diagram of a Floating Gate Memory during

Programming by FN Tunneling [24]

FN tunneling is also used to erase a flash cell. A large negative voltage is applied

to the control gate and the source and drain are left floating. The energy band structure of

floating gate memory during erasing by FN tunneling is as shown in FIGURE 2.5. The

electric field generated causes the electrons to tunnel away from the floating gate, making

it more positive and turning on the transistor. This decreases the threshold voltage of the

cell as it requires less gate voltage to be applied to turn on the flash cell. Thus, erasing a

flash cell by FN tunneling removes the charge from the floating gate and erased cell

stores logic ‘1’.

10

FIGURE 2.5 Energy Band Diagram of a Floating Gate Memory

during Erasing by FN Tunneling [24]

When electrons are on the FG, they modify the electric field coming from the CG,

which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is "read" by

placing a specific voltage on the CG, electrical current will either flow or not flow,

depending on the Vt of the cell, which is controlled by the number of electrons on the FG.

This presence or absence of current is sensed and translated into 1's and 0's, reproducing

the stored data.

In flash memory lingo, programming (putting electrons into the floating gate)

means writing a 0, erasing (removing the charge from the floating gate) means resetting

11

the flash memory contents to 1; or in other words: a programmed cell stores a logic 0, an

erased cell stores a logic 1. Thus, programming and erasing of a single NAND flash cell

is carried out by using the FN tunneling.

2.1.2 Memory Array Architecture of NAND Flash Parts

The “NAND” Flash name is related to the way the flash cells are arranged in

series in an array. An array is a collection of flash cells arranged in rows and columns

which stores the information. NAND flash cells sharing the same control gate (CG)

constitute the wordline (WL), while those sharing the same drain electrode constitute the

bitline (BL) as shown in FIGURE 2.6. A typical NAND array is formed by 16 or 32

NAND flash cells or transistors connected in series with two select transistors, the ground

select transistor (GSL) and the bitline select transistor (SSL), as shown in FIGURE 2.6.

CG1 to CG16 in FIGURE 2.6 represent the control gates of the NAND flash cells. Each

NAND cell stores one bit of information. The bitline select transistor and the word line

ensure the selectivity of a particular NAND flash cell or bit. The ground select transistor

prevents the cell current from passing during programming. Based on the voltages

applied to the word line and bitline a particular bit can be programmed or erased, thus

storing the data in flash cells.

12

FIGURE 2.6 NAND Array Architecture [11]

The memory array architecture of the 2Gb NAND flash parts used in this thesis

work is discussed in this section. A memory array in a chip can be organized as a single

piece of memory or can be divided into several sets of memory arrays. It is convenient

for the memory chip with a large memory size to be divided into smaller arrays. In a

memory chip with a single memory array, if a particular column of an array is damaged

then the entire part fails to function. But when the memory is divided into sets of array,

the memory chip can be easily repaired. This efficient memory management of an array

provides for easy detection and correction of failures.

A 2Gb NAND flash memory is divided into 2048 blocks. A single block of a

NAND flash chip has 32 word lines/rows and 33792 bit lines/columns of flash cells

arranged as shown in FIGURE 2.7. Each bitline stores 32 bits of information. The size of

a single flash memory block is 32 bits ×33792 bitlines which is about a 1Mb (Mega bit)

13

array size. The total size of the NAND flash memory array shown in FIGURE 2.7 is

1Mb × 2048blocks which is about 2Gb (2 Giga bit).

FIGURE 2.7 Array Architecture of NAND Flash Memory Chip

A NAND flash chip, based on its size; i.e., 2Gb (Giga bit), 4Gb or 8Gb, is divided

into various blocks each of 1Mb (Mega bit) array space. Each block is again subdivided

into pages. The array organization of the 2Gb NAND flash chips used in this research is

as shown in the FIGURE 2.8 and is described as follows:

Array Organization

• Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks; 8Gb: 8,192 blocks

• Block size: 64 pages (128K + 4K bytes)

• Page size: 2,048 + 64 bytes

14

FIGURE 2.8 Array Organization of NAND Flash Memory Chip [12]

A 2Gb NAND flash chip is composed of the blocks. There are 2048 blocks in a

2Gb NAND flash part. One block is composed of 64 pages. The division of the entire

flash memory array into blocks and pages enables easy detection of failures and increases

the yield.

2.1.3 Operational Modes of the NAND Flash Memory Chip

In section 2.1.1 we discussed that a single flash cell can be programmed and

erased using FN tunneling. In this section the operational modes of the whole NAND

flash memory chip are discussed. The characteristics of the flash memory chips vary

based on the voltage applied to the control gates, or word lines (WL) and bit lines (BL).

The principles involved in performing the programming, erase, and read operations are

similar for all NAND flash components. However, the voltages at which they operate

15

differ based on the memory device size. In this thesis, samples of 2Gb NAND flash parts

were investigated using failure analysis techniques. The ensuing subsections describe the

operations and the voltages associated with each of the operational modes for 2Gb

NAND flash parts.

2.1.3.1 Program Operation

Programming a NAND flash memory consists essentially of moving charges onto

the floating gates of the flash cells which are arranged in an array. This changes the

threshold voltage of the FG transistor. A Programmed flash cell stores logic “0”. In the

programming operation as shown in FIGURE 2.9 (“0” data), the substrate is grounded;

20V is applied to the selected gate word line (GWL), the unselected bit line is at Vcc

(Supply Voltage) along with the bitline select transistor (SSL) and 10V applied to all

unselected control gates within the string.

The selected bit line and ground select transistor (GSL) are then grounded and

Vcc is applied to the common source to suppress current flow from the unselected bitline

as shown in FIGURE 2.9. Electrons are injected into the floating gate from the inversion

channel by Fowler-Nordheim tunneling [4] as shown in FIGURE 2.10. The threshold

voltage of the selected cell goes from negative to positive [9].

In the case of programming “1”, the channels of the NAND structured cells are

boosted up to 8V as shown in FIGURE 2.11 and the threshold voltage of the unselected

cells remains negative. No tunneling occurs in the unselected cells because the voltage

difference between the control gate and the source/drain is insufficient to initiate

16

tunneling current [17]. Since the memory cells in the NAND string are connected in

series, the threshold voltage of each programmed cell must be between the selected

control gate voltage and the pass gate voltage in order to read the string. If the threshold

voltage of any pass transistor in the string exceeds the pass control gate voltage, the other

cells in the string cannot be read.

FIGURE 2.9 Programming of a NAND Cell [9]

FIGURE 2.10 Programming “0” for a Single Flash Cell [1]

17

FIGURE 2.11 Programming “1” for a Single Flash Cell [1]

The cells are checked whether they are programmed correctly by performing read

operation on flash cells. The NAND cells have a threshold voltage higher than 0V if they

are programmed. The threshold voltage distribution of the flash cells after program

operation is illustrated in FIGURE 2.12. Here, the X-axis represents the threshold voltage

of the flash cells and y-axis represents the flash cells in blocks of NAND flash array. A

program verify level, is the voltage level applied to the flash cells to obtain required

threshold voltage for programming. Typically its value ranges from 1-1.5V. In FIGURE

2.12, the NAND flash cells above the program verify level are programmed correctly, as

they have a threshold voltage higher than program verify level. Hence, the programmed

flash cells above the program verify level pass when a read operation is performed on the

cells. Distribution of programmed ‘0’ flash cells is above the program verify level as

illustrated in FIGURE 2.12 so that all the flash cells are programmed. The voltage

18

applied to the gate should change the threshold voltage of the flash cells to a verify level

which exceeds the read level to ensure that all of the cells will be able to be properly

read. The read level is a voltage level applied to the flash cells to properly read them.

The read voltage level varies from 0 – 0.5V as shown in FIGURE 2.12. The read level is

set up such that it is able to read the programmed and erased cell. Thus, NAND flash

cells which have a threshold voltage above the program verify level are programmed

properly.

FIGURE 2.12 Threshold Voltage Distribution after Program Operation 2.1.3.2 Erase Operation Erasing a NAND flash memory is basically removing the charges from the

floating gates of the flash cells arranged in an array. This decreases the threshold voltage

of the FG transistor. An erased flash cell stores logic “1”. Erase can be performed on the

whole chip or on a selected block. In a block erase operation (resulting in “1”) of a

19

NAND flash array as shown in FIGURE 2.13 (A), the control gates are grounded, SSL

and GSL are floating and the bitline is left floating. Here, floating refers to the same state

as it was when applied last time.

A schematic of a single NAND flash cell selected for erase operation is shown in

FIGURE 2.13 (B), where the control gate is grounded, 20V applied to the substrate, and

the source and drain are floating. Electrons are removed from the floating gate to the p-

substrate by Fowler-Nordheim tunneling [1, 9], and the threshold voltage of the erased

cells shifts from positive to negative. All cells in the block are erased with a threshold

voltage of –1V. To inhibit erase on unselected blocks, the control gates are biased to

approximately 20V in order to prevent F-N tunneling from occurring.

(A) (B)

FIGURE 2.13 (A) Erasing of a NAND Flash Array

(B) Schematic of Selected NAND Cell for Erase [9]

20

The NAND flash cells have a negative threshold voltage in the erased state and

hence it is conductive. Threshold voltage distribution of the flash cells after erase

operation is as shown in FIGURE 2.14. Here, the threshold voltage distribution of

programmed ‘1’values i.e. erased cells is shifted to the negative values. X-axis represents

the threshold voltage values of the flash cells and the y-axis represents the flash cells in

blocks of NAND flash array. Erase verify level is the threshold voltage required by the

flash cells to be erased. Typically, erase verify level ranges from -0.2V to -0.8V. In

FIGURE 2.14, the NAND flash cells below the erase verify level are erased correctly, as

they have a threshold voltage lower than erase verify level. The NAND flash cells which

have the threshold voltage below the erase verify level are erased properly and pass when

a read operation is performed on the cells. Read level is the voltage level applied to the

flash cells to properly read the cells. Read level is same for program operation and erase

operation. The erase process is similar to that of programming in that the VT that is on the

cell is marginally below that required to read a “1” from the cell [11]. Thus, NAND flash

cells which have the threshold voltage below the erase verify level are erased properly

and read logic “1”.

21

FIGURE 2.14 Threshold Voltage Distribution after Erase Operation 2.1.3.3 Read Operation

A read operation is performed on the NAND flash cells to check if a particular

cell is a programmed cell or an erased cell. The read operation is performed by applying a

gate voltage to the cell that is between the values of the threshold voltages of the erased

and programmed cells and then sensing the channel current flowing through the device

[4]. Figure 2.15 illustrates the voltages applied to the flash cells of selected bitline while

performing a read operation on a NAND flash array. 1.2V is applied to the selected

bitline, 0V is applied to the selected WL and 4.5V is applied to the control gates of the

unselected cells. The unselected bitlines of the array are grounded. The schematic of the

selected NAND cell for read operation is as shown in FIGURE 2.16. Here the control

gate and source are grounded, 4.5V is applied to the drain and the substrate is grounded.

A programmed cell (“0”) has a positive threshold voltage and an erased cell (“1”) has a

22

negative threshold voltage. Therefore, if the selected cell is a “1” (erased cell), the

memory cell transistor is in depletion mode and current flows as shown in FIGURE 2.17

(B). On the other hand, if the selected cell is a “0” (programmed cell) no current flows

because the memory cell is in the enhancement mode as shown in FIGURE 2.17 (A).

Due to large arrays of flash cells, the resulting signal, for the read operation, has a much

lower voltage swing. To compensate the swing, sense amplifier will amplify a signal

coming off the bit lines during read sequence. A sense amplifier that is connected to the

bit line detects the state of the cell. Thus, a read operation is performed on the NAND

flash array to read the state of cell i.e. whether it is erased or programmed.

FIGURE 2.15 FIGURE 2.16

Reading of a NAND Flash Array [9] Schematic of Selected NAND Cell

for Read [9]

23

(A) (B)

FIGURE 2.17 (A) Reading “0” Programmed Cell

(B) Reading “1” Erased Cell

2.2 NAND Flash Memory Chip Fabrication Process

Device fabrication processes are used to create chips, the integrated circuits that

are present in everyday electrical and electronic systems. It is a multiple-step sequence of

photographic and chemical processing during which electronic circuits are gradually

created on a wafer made of its doped silicon.

The wafer is made out of extremely pure silicon grown into mono-crystalline

cylindrical ingots up to 12" (300 mm) in diameter using the Czochralski process [23].

These ingots are then sliced into wafers about 0.75mm thick and polished to obtain a very

regular and flat surface. Once the wafers are prepared, they undergo a series of process

steps to produce the desired semiconductor integrated circuit; i.e., NAND flash memory.

The NAND flash memory fabrication process is grouped into four areas.

24

• Wafer Fabrication

o Front end processing

o Back end processing

• Wafer Probe or Test

• Assembly Cycle

• Package Test

In this section, the fabrication process (which is compromised of both front end and

backend processing) of NAND flash memories is explained in detail. Flash memory

testing is discussed in the next section.

"Front End Processing" refers to the formation of the transistors directly on the

silicon. "Back End Processing" creates metal interconnecting wires, isolated by insulating

dielectrics. First, the front end processing of NAND flash memory chip is discussed in

this section. Crystalline or contaminate defects kill the operation of an IC, so it is

desirable that the silicon be ultra-pure. The best possible quality of silicon is created by

growing a pure layer of silicon on the raw wafer via an epitaxial growth process.

FIGURE 2.18 illustrates the epi-layer formed. This layer is very thin approximately 3

percent or less of the wafer thickness. The active circuits are thus fabricated in this epi-

layer.

25

FIGURE 2.18 Epitaxy

Source: http://www.infras.com/Tutorial

The construction of NAND flash cells on wafers involves several steps. The first

step involves heating of the epi-wafer to grow an oxide layer, specifically silicon dioxide.

The lithography process is then used to transfer a pattern from a photomask (reticle) to

the surface of a substrate as illustrated in FIGURE 2.19. The photoresist is spun and

baked to make it harder. The reticle is exposed step-by step over the wafer and the resist

is developed to create the pattern on the wafer.

FIGURE 2.19 Photolithography


26

The wafer with patterned photoresist is then put into an oxide etch process to

remove the oxide where there is no pattern as illustrated in FIGURE 2.20. Either a “wet”

etch or a "dry" etch is used for this purpose. The photoresist is then removed or stripped.

The stripping of photoresist must be entirely complete as in FIGURE 2.20 (B), otherwise

it would cause surface contamination.

(A) (B) FIGURE 2.20 (A) Etch (B) Strip


The next step in the fabrication of NAND flash memory is ion implantation.

During implantation, the dopant molecules are implanted vertically into the surface of the

silicon by a high-energy ion beam as illustrated in FIGURE 2.21. These regions are now

doped with negative ions, creating n-type source and drain regions of the transistor in a p-

type silicon base. A layer of oxide is then deposited and an opening is made in the oxide

to build the gate region using the oxidation and photolithography process as shown in

FIGURE 2.22. A thin layer of tunnel oxide is then deposited on the surface of wafer

27

using chemical vapor deposition. Then a floating gate made of polysilicon is deposited by

a Physical Vapor Deposition (PVD) process as shown in FIGURE 2.22.

FIGURE 2.21 FIGURE 2.22

Diffusion & Implantation Deposition of Oxide Layer


Another layer of oxide is deposited on top of the floating gate. The polyisilicon,

used as the floating gate is deposited on top for gate voltage control. FIGURE 2.23 shows

the schematic cross section of single NAND flash memory cell with source, drain and

gate contacts respectively.

FIGURE 2.23 NAND Flash Memory Cell

Source: http://www.freescale.com/files/microcontrollers/doc/app_note/AN1837.pdf

28

After the NAND flash cells are created, they must be interconnected to form the

desired electrical circuit. This "Back End Processing" involves creation of metal

interconnecting wires, isolated by insulating dielectrics. Reticles and photolithography

are used in back end processing for formation of contact areas. The contact areas in the

silicon dioxide are unmasked to etch all the way down to silicon and polysilicon areas of

the transistor's source, drain and gate regions. These holes, called "vias", are essentially

chemically "drilled" holes which expose the contacts to the three-terminals of the

transistor. A layer of aluminum is deposited on the surface and down into the via holes.

Excess aluminum is etched away during another photolithography process, leaving the

desired interconnect pattern. Another layer of dielectric isolation oxide is deposited to

insulate the first layer of aluminum from the next layer of another NAND flash cell.

CMP (Chemical Mechanical Planarization), an abrasive process, is used for

polishing the surface of the wafer flat. Chemical slurries and a circular (sanding) action

are used to polish and smooth the surface of the wafer. The smoothed surfaces are then

ready for additional process steps and additional layers. Another set of via holes are

etched in the dielectric isolation oxide to enable access down to the layer below. Contact

plugs of tungsten are deposited into the vias to reach down and make contact to lower

layers. The layers establish the interconnection between various NAND flash cells to

form a NAND flash memory. The next layer of aluminum is deposited, patterned and

etched. Typically there are about 2-3 layers of metal. This process is repeated for as many

interconnect layers as are required for the NAND flash memory chip design.

29

After fabricating the NAND flash cells; i.e., NMOS transistors with floating

gates, they are interconnected as per the NAND flash memory structure to form a NAND

flash memory chip. The fabrication process is then followed by a wafer testing process

discussed in the next section. When the finished wafer comes out of the fabrication

process, it is ready for the wafer test, assembly and packaging processes to finally

produce a set of good, usable integrated circuits. The flow chart in FIGURE 2.24 outlines

the salient steps involved in the memory chip manufacturing process.

FIGURE 2.24 Chip Manufacturing Process


30

2.3 NAND Flash Memory Testing

NAND flash memory is tested at the fabrication phase before the wafer is sent to

die packaging and this is defined as wafer probe or test. After packaging the die is tested,

defined as package test. Wafer probe is performed after wafer fabrication during which

the electrical parameters of the integrated circuits are extracted, and the circuits are tested

for functionality. The wafer probe is performed after the fabrication so that yield data can

be assessed quickly and fed back to the fabrication group, in order to correct and optimize

the fabrication processes. After IC packaging, a packaged chip will be tested again with

the process similar to that of wafer probe. Removal of defective die at wafer probe saves

the cost of packaging faulty devices. Therefore, wafer probing is performed after

fabrication of the finished wafer and before package test as shown in FIGURE 2.25. The

packaged die is tested again under stressed conditions after package burn-in. A detailed

discussion of the package tests on the NAND flash parts is presented in Section 2.3.2.

Then the packaged die is finally checked for its functionality at final test as shown in

FIGURE 2.25. The good products are then shipped to the customers.

FIGURE 2.25 NAND Flash Memory Testing

Source: http://www.chipscalereview.com/archives/ES/issues/0103/f3_01.php

31

Thus, wafer probing after fabrication accelerates the detection of any defects from

fabrication and provides a faster feedback to the fabrication engineers. The tests done

after the chip is packaged ensure that the parts are good before they are shipped to the

customers. Wafer probe and package tests result in the elimination of the defects thus

improving the yield of the die.

2.3.1 Wafer Probe/Test on NAND Flash Parts

The NAND flash fabrication process consists of many complicated steps that

form functional die on the wafer. Unexpected variations at any of these steps can affect

the electrical characteristics of the memory cells. Therefore, the wafer probing step is

performed after the fabrication process to determine the failures. Wafer probing is a

complex procedure. Wafer probe employs the use of a probe station combined with

complicated electrical test equipment along with software tools to store information about

the parts tested. At wafer probe, a large volume of parts are initially tested for basic

operations and functionality. The memory chips that fail at wafer probe are not packaged.

Wafer probing is performed before a wafer is sent to die packaging. All individual

integrated circuits that are present on the wafer are tested for functional defects by

applying special test patterns to them. A test pattern is a sequence of bits (‘0’ or ‘1’)

provided as input to the circuit to check its functionality. The wafer testing is performed

with a piece of test equipment called a prober, and the process in general is referred to as

a wafer probe or test.

32

The three basic tools used to perform wafer probe are illustrated in FIGURE 2.26,

and are called wafer prober, test head and test mainframe. First, the wafer prober takes

wafers from their carriers, loads them onto a flat chuck, and then aligns and positions

them precisely under a set of fine contacts on a probe card. Secondly, in test head set-up,

each input-output or power pad on the die is contacted by a fine electrical probe. This is

done by a probe card, which translates the small individual die pad features into

connections to the tester. A probe card, shown in FIGURE 2.27 holds a number of tiny

needles with specific spacings designed to make contact with bond pads so that the die

can be tested while still in wafer form. Thirdly, the functional tester or automatic test

equipment (ATE) as shown in FIGURE 2.28 is connected to the probe system using

special interfacing hardware. ATE is a test mainframe, which is capable of exercising the

die on the wafer under software control. It also provides inputs for testing the

functionality of die and identifies the failed die on wafer. In this thesis, the failure data

for samples of 2Gb NAND flash die was collected from agilent ATE. Agilent testers are

effectively used in the semiconductor industry for wafer testing and offer lower test cost

per bit when compared to other testers in the market. Thus, the information from ATE in

wafer probe is normally used for the failure analysis.

33

FIGURE 2.26 Wafer Probe Set-Up


FIGURE 2.27 Probe Card FIGURE 2.28 Fully Automated Wafer

Probing System

Source: http://www.chipscalereview.com/archives/ES/issues

The wafer electrical tests are not as extensive as that of the packaged parts.

However, the wafer probing checks for the functional and critical electrical parameters. If

a device does not meet the data sheet specifications, it is identified by the tester and the

device is rejected. The tester/probe card combination may be able to contact and test

34

more than one die at a time on the wafer. This parallel test capability enhances the

productivity of wafer testing.

The main objective of wafer probe is to look for the defects that occurred during

manufacturing. The tests performed on NAND flash parts at wafer probe are as listed

below:

• Functional testing determines whether the device is able to perform its basic

operations.

• Parametric testing usually consists of applying a constant voltage at a node and

measuring the current response (force-voltage-measure-current) at that node, or

applying a constant current at a node and measuring the voltage response (force-

current-measure-voltage). Parametric testing, thus checks if the device exhibits the

correct voltage, current, or power characteristics, regardless of whether the unit is

functional or not.

When a die passes all the tests at wafer probe, its position on the wafer is stored in

database for use during IC packaging. If a particular NAND flash memory part fails one

of the tests, wafer probe categorizes it as a specific failure. For example, the parts are

tested for column shorts at wafer probe. When any two columns in a NAND array are

shorted, it is defined as a column short. Yield enhancement engineers group or categorize

all the parts which fail to this test. Wafer probe provides large amounts of defect

information and process related issues to fabrication engineers, product engineers, and

design engineers. This assists in process and design improvement. A die that passes some

35

but not all test patterns can still be used as a product with limited functionality and can be

shipped to the required customers. All good die, those that pass the functional and

parametric tests at wafer probe, are then sent to assembly for packaging.

2.3.1.1 Redundancy/Repair Strategy in Wafer Probe

Redundancy/Repair has been widely used for enhancing the yield and reliability

of memory chips [18]. Redundancy is the duplication of elements to provide an

alternative incase of failures. Memory Repair is performed after the wafers are tested at

wafer probe. Redundant memory is the extra or spare memory built in the chip which can

be used incase of failures. If a fault occurs in the main memory, it is switched to the

redundant memory [21]. The blocks or columns of a memory array that fail certain tests

at probe can thus be replaced with the redundant blocks/columns built into the chip. This

improves the yield of the die. The redundancy/repair strategy used in this thesis work for

2Gb NAND flash parts is discussed in this section.

A NAND flash memory is designed with redundant rows and columns (spares)

which can logically replace rows or columns which may contain defective memory cells,

as illustrated in FIGURE 2.29. If a particular bit fails, the entire row or column

containing that cell is to be replaced. If a NAND flash chip does not pass some test

patterns at probe, it is repaired with the available internal spare resources. The redundant

solution provides the information about the redundant column used for repair and the

column to be replaced. Repair is done merely by programming in the redundant solution.

36

The probe engineers at wafer probe repair as many die as possible by analyzing all

failures and replacing failing elements with redundant elements.

The yield of die increases with memory repair than without repair as the failure

rate is decreased. This is illustrated in FIGURE 2.29 (B) where percentage of yield of die

increases with repair. Design engineers make sure that there are not many redundant

columns in a die, as it will increase the die size which shall have an impact on yield.

Probe tests and redundancy repairs are performed at the wafer level in order to fail non-

functioning die before they are sent to assembly, thereby reducing packaging and final

test costs.

(A) (B)

FIGURE 2.29 (A) Memory Repair for NAND Flash Memory Devices

(B) Increase of Yield with Memory Repair


2.3.1.2 Overview of Defect Failure Analysis at Wafer Probe Failure analysis (FA) plays a vital role in the development and manufacture of

integrated circuits (ICs) [19]. Failure analysis at probe is useful for determining the

37

causes for the failure of a semiconductor device and enables corrective and preventive

measures in the future. The steps followed for failure analysis are unique. Analysis

proceeds with each subsequent step depending on the outcome of the previous step. The

analysis is completed once enough information is obtained to draw a conclusion about

the cause of the failure.

Wafer probe is a test procedure where various tests are conducted on NAND flash

parts. The failures are analyzed after the wafers are tested. Then, the information about

the block/column repaired and redundant block/column used for the repair are provided.

As part of this thesis work, repair data for different tests at wafer probe were collected in

order to observe and analyze any abnormalities from the expected trend/pattern. A pattern

or a trend is a graphical representation of the sample repair or failure data.

Various trends can be represented from the repair data. For example, from the

repair data we can plot a trend of each of the columns or blocks in a sample of NAND

flash parts determine the count of fails. Suppose the trend shows a particular

column/block to fail a larger number of times as compared to the other columns/blocks.

This would constitute an abnormal trend. Another abnormal trend could be a set of

columns in the middle of a NAND flash array that failed more than other columns. It is

necessary to find out the cause for such abnormal trends in order to eliminate such fails in

future production. The analysis of the repair data is thus provided to the fabrication

department, product engineering, and design department for assistance in process and

design improvements, which will improve the yield.

38

2.3.2 Package Test on NAND Flash Parts

Package test checks the chips for functionality just before leaving the factory.

Package test is performed after the die is packaged. The information generated at package

test is used to monitor yields and performance of a product. In the assembly process,

individual die are separated from the wafer and packaged. The die is then passed through

the package test to screen out infant mortalities and perform functional pattern tests at

ambient, cold, and hot temperatures. The chips are tested to ensure that they were not

damaged during packaging and that the die-to-pin interconnect operation was performed

correctly. At package test more extensive tests are performed than at wafer probe. At

wafer probe, only the critical electrical parameters and basic operations are tested. In

package testing, the devices are tested for data sheet specifications and electrical

parameters under stressed conditions at different temperatures. This is done to improve

the quality of die. The tools employed for packaged test are discussed in this section.

The three tools used to perform the package test operation are illustrated in

FIGURE 2.30, and are called package handler, test head and test mainframe. First, the

package handler takes packaged die from their carriers and sets the environmental

temperature as specified. Secondly, each pin on the chip's package must be contacted by

inserting it into a socket on a custom designed PC board known as Design Under Test

(DUT). This DUT is the test head set up as illustrated in FIGURE 2.30. Thirdly, the

functional tester, or automatic test equipment (ATE), is used as a Test Main Frame which

is capable of functionally exercising all of the chip's designed features under software

control as illustrated in FIGURE 2.30. Any failure to meet the published specification is

39

identified by the tester and the device is marked as a reject. The tester/handler

combination is able to contact and test more than one part at a time in parallel for

increased productivity.

FIGURE 2.30 Package Test Set-Up


Chips are tested at more than one temperature before being shipped, to make sure

it functions properly. Thus, testing helps insure the quality, performance, and integrity of

parts so that the customers receive a product that meets published device specifications.

2.3.2.1 Package Tests in Electrical Flash Test Flow

Package tests ensure that the customer’s requirements are met and the die

performs as per the data sheet specifications. The packaged die are tested in two

environmental conditions, i.e.; hot sort and cold final.

40

Hot Sort Testing

In hot sort testing, parametric and functional tests are conducted at high temperatures

ranging from 70oC to 90oC on production testers. This is done to verify if the parts

function over a range of temperatures as specified in the datasheet.

• Parametric tests are performed to detect opens, shorts, input / output leakage and to

determine whether input / output high and low levels and standby / operating currents

are within specified limits.

• Functional tests check for noise margin, programming and erase times, and

verification of AC parameters. Some of the AC parameters, for which the parts are

verified are rise time/ fall time, setup time, hold time, and write cycle timings.

At hot sort, the packaged die are tested at extended temperatures. This makes hot sort

testing one of the most important tests at package. Some of the functional tests that are

performed on packaged NAND flash parts in hot sort conditions were focused on for the

project. More parts fail for certain functional tests. Typically the operating power supply

of a NAND flash chip is 3.3V. Vcc is the power supplied to the whole part externally, not

for any specific cell. The data sheet specifies a Vcc range to the customers, across which

the part is good. So, the part is tested at Vcc range corners i.e. low Vcc and high Vcc to

catch the worst case problems. High corner Vcc applied to the NAND parts is normally

about 3.7V and low corner Vcc is about 2.6V. Five functional tests at hot sort were

chosen for this thesis in order to have enough failure data for analysis. They are as

discussed below:

41

� Test I: Speed Timing Write Test (High corner Vcc)

This test checks whether a test pattern is written into an array of flash memory with

high corner Vcc applied to the NAND flash parts within data sheet timings. In the data

sheet specific program time is specified, within which the memory array has to be

programmed. The test pattern that checks for the flash write operation has an alternating

pattern of 1’s and 0’s. The data in the first logical address location has 1’s and the next

logical address location has 0's. This is called a logical checker board test pattern. For

example, if each logical address stores 4 bits of information then the logical checkerboard

test pattern would be as shown in FIGURE 2.31.

FIGURE 2.31 Logical Checkerboard Test Pattern

for Speed Timing Write Test

This test is used to check whether a particular test pattern is written into the cells of a

NAND flash array after it is programmed. This is done by reading back the data and

comparing it with the input values. The chip which takes lesser time to program the flash

array with a particular test pattern has greater performance. The test pattern must be

written onto the flash array of NAND flash part in typically about 500-750us as

mentioned in the data sheet. This is called as datasheet programming time. Speed Timing

write Test also checks whether the flash cells are programmed within the timings

42

specified in the data sheet. Thus, it is important to check whether the flash array is

programmed with a pattern similar to that of input test pattern and within the time

specified to improve the performance and yield of the NAND flash part.

� Test II: Speed Timing Write Test (Low Corner Vcc )

This test checks if a flash memory array is programmed with a different test pattern

i.e. physical checkerboard test pattern when compared to logical checkerboard pattern, as

illustrated in FIGURE 2.32 with low corner Vcc applied to the NAND flash parts. The

test pattern has alternating 1’s and 0’s stored in flash cells. This is called as physical

checkerboard test pattern. The blocks of flash memory array are programmed with a

different test pattern as compared to the test pattern used for Speed Timing Write Test

(High corner Vcc) to ensure that it can be programmed to various test patterns within the

timings specified in the data sheet.

FIGURE 2.32 Physical Checkerboard Test Pattern


When the bits are read back, each bit in the array should be in the state opposite to

that of all adjacent bits (both horizontally and vertically); i.e., the first physical bit line in

an array is a ‘1’ and the adjacent bit line is a ‘0’ and so forth. Thus, the reason for the

43

Speed Timing Write Test is to check whether the flash cells are programmed correctly

within the timings for the NAND flash parts at low corner Vcc.

� Test III: Speed Timing Read Test

The Speed Timing Read Test programs the flash memory array with a logical

checkerboard test pattern with low corner Vcc applied to the NAND flash parts. The

blocks of the flash memory array are programmed with a test pattern and read by

applying the necessary voltage combination to the flash cells. The tests checks if the

blocks of flash memory array are read correctly within the specified datasheet timings

which is typically about 20-25us. Here the time taken for reading the blocks of array is

checked whereas in Test I and Test II, time taken to program the flash cells is tested.

� Test IV: Speed Timing Write Test (with different logical checkerboard test pattern)

The blocks of the flash memory array is programmed to a different logical

checkerboard pattern when compared to the pattern used for Test I, with high corner Vcc

applied to the NAND flash parts. The test pattern used has the data in the first logical

address has 0’s and the next logical address location has 1's as shown in FIGURE 2.33.

This pattern is called logical checkerboard ‘0’ test pattern as the first logical address

location starts with ‘0’. The test checks for the logical checkerboard ‘0’ test pattern to be

written into an array within the data sheet specifications.

44

FIGURE 2.33 Logical Checkerboard ‘0’ Test Pattern


� Test V: Read1 Test

This package test runs checks to read the blocks of flash memory array after an erase

operation to verify that the flash cells are in an erased state with low corner Vcc applied

to the NAND flash parts. When the cells are in an erased state they should read ‘1’.

Hence, if the data stored in the flash cells is ‘1’, the NAND flash part passes the Read1

Test.

The failure data was extracted for these five tests for analysis in the thesis. The

sample size of the flash parts that fail to these five tests ranges from 10,000 – 20,000

individual die. If there are more number of parts with fails then it is meaningful to extract

the data related to them and determine the reason for their failure. The five tests

mentioned thus, provided sufficient data for failure analysis. This was the criterion for

choosing these five tests. There are many more tests conducted on NAND flash memory

in the package test phase, but we focused on these five tests and a few test patterns for

failure analysis.

45

Cold Final Testing

In cold final testing parametric and functional tests are also conducted similar to hot

sort testing. However, the tests are run under different temperature conditions, ranging

from 0 to -40oC on production testers. This is done to verify if the parts function over a

range of temperatures as specified in the datasheet. The failure information about the

parts that failed under cold conditions is feedback to the fabrication group and design

engineers for decreasing the fail.

2.3.2.2 Overview of Defect Failure Analysis at Package Test

Failure analysis is used to provide specialized information that contributes

towards the determination of the failure mechanisms operating in a sample. Application

of failure analysis ensures improved designs, results in higher yields, and shortens the

development cycle since the sources of failure that necessitate redesign and

manufacturing changes are identified early [20]. Individual analytical tests are performed

to complete the failure analysis process. In this process, non-destructive analysis must be

conducted first, prior to any destructive ones.

Non-destructive failure analysis at package test involves the extraction of whole

block failure data of NAND flash parts. Packaged die from assembly are tested for their

functionality at cold and hot temperatures. As discussed previously, the NAND flash

memory array is divided into blocks where each block is 1Mb of array space. Failed

blocks are blocks those contain one or more invalid bits. When the die fails to function

properly, block information on the die is extracted for easy analysis. This information

46

helps to focus only on a particular block of the die responsible for the failure, instead of

all the blocks in the die. From the failure information obtained, the reasons for the failure

can be normally determined. Possible reasons for failure may be due to die scratches, die

cracking, wire to wire shorting, wire to die shorting, or wire breaking.

In this project, failure analysis of the block data for each NAND flash part at

package test was studied. Samples of failed block data for different tests at package test

were collected to investigate any abnormal trends. In the trends, if higher failure rate of

the parts is observed, the cause for it has to be determined than the parts with lower

failure rate as it shall effect the yield.

2.3.2 Introduction to the Wafer Map Tool Used for Failure Analysis

Wafer Map Tool is a standard software tool used for failure analysis in the

semiconductor industry. Wafer maps are widely used by the semiconductor industry for

process monitoring and yield enhancement [22]. A wafer map is a report generated by the

wafer map software tool that shows each individual unit, or die, on the surface of a

silicon wafer, as illustrated in FIGURE 2.34. Various tests are performed on the wafers at

wafer probe. Wafer Map Tool displays the wafer map using color-coded die to indicate

the test results. This helps the test engineers to visually identify the faults and locate the

failed die on the wafer. The location of the die on the wafer is displayed using X/Y

coordinates relative to a reference die. The reference die is selected anywhere on the

wafer. It is also possible to zoom in and out on the wafer map to view more information

about a particular die. Wafer Maps helps to look at individual wafers for specific failures

47

and can significantly improve the operational efficiencies of the wafer manufacturing

process. They provide fast feedback to the fabrication process engineers to make

adjustments to the process to improve overall yield.

FIGURE 2.34 Wafer Maps

Source: http://www.hologenix.com/YP.pdf

2.4 Summary

In this chapter, we presented the theoretical background, concepts, and

applications of NAND flash memory. The NAND flash memory cell structure and its

operations were outlined. NAND flash memory chip array organization was also

discussed. NAND flash chip fabrication processes and the tests performed on the devices

at the wafer level and packaged die level were discussed. An overview of the failure

analysis at wafer test and package test was described. Overall, this chapter provides the

foundation and theory of the concepts and terminology required for a better

understanding of the failure analysis methodologies undertaken in the next chapters.

CHAPTER 3

FAILURE ANALYSIS OF WAFER PROBE AND PACKAGE TEST

Failure analysis plays a vital role in the development and manufacturing of

integrated circuits [19]. It is important to keep a detailed record of failure rate at every

stage of the chip manufacturing process. When the memory devices encounter an

increase in the failure rate, the causes for it have to be determined as soon as possible so

that production efficiency is not affected. Any similar future defects may be eliminated or

rectified with alternative solutions. Failure analysis is performed at wafer probe to

provide a feedback to the fabrication process engineers. It’s cheaper for the industry to

identify the defects at the earliest at wafer level so that they can be rectified early in the

production cycle. However, the failures which are not caught at wafer probe shall be seen

in package test because the parts are tested rigorously. This chapter provides in-sight into

the failure analysis conducted at the wafer level and package level to identify defective

parts, enabling quality and yield improvement of memory devices.

3.1 Analysis at Wafer Probe

A NAND flash chip at wafer probe undergoes a series of electrical tests. Wafer probe

analyzes the failures at each of these tests to detect the blocks and columns of NAND

flash parts to be repaired. The failed blocks/columns are replaced by the redundant

blocks/columns. There are extra columns and blocks built into the chip to provide repair

solution information. This information provides the column/block being repaired and the

49

redundant column/block used for repair. This repair solution information is tracked to

observe if there are more number of repairs which have an impact on the yield. For

example, we can ascertain from this information if certain blocks/columns are being

repaired the most or if a set of blocks/columns on one side of the array fail more than the

other side, etc. The repair information is plotted and the trends are observed for

abnormality.

Failure analysis in this project was performed based on the repair solution

information of a sample of 2Gb NAND flash parts. Column and Block repair analysis

was performed on a 2Gb NAND flash part at wafer probe. The main objective was to

observe any abnormal trends in the data. The following parametric tests were considered

and repair data was extracted.

• Test to screen out grossly non-functioning bits

• Test for shorts that would lead to invalid data

The tests mentioned above were considered for the analysis at wafer probe since the

NAND flash parts have tendency to fail for these tests. Hence, there will be sufficient

repair data for a sample of 2Gb NAND flash parts for analysis.

50

3.1.1 Procedure for the Extraction of Wafer Probe Repair Data

The wafer probe repair data extraction process requires understanding of the

concepts of probing and terminology of the semiconductor industry. The wafer probe

repair data; i.e., block and column repair data used for the analysis, are extracted using

web based tools and PERL scripts. A lot of time was spent extracting the necessary repair

data from a large volume of test data using the PERL scripts. The following series of

steps are involved in the repair data extraction used for failure analysis

1. Extraction of lots (A lot is a set of 25 wafers) that ran in wafer probe a few days

back from the database using specific commands in UNIX.

2. Generation of Die ID’s for each lot. Each wafer has about 700-800 die with

specific ID’s associated with them to keep track of the information. About 20,000

die ID’s are generated.

3. Repair solutions are obtained for each of the die. PERL scripts are developed to

extract the necessary repair data for specific tests from large amounts of wafer

probe data.

4. Specific parametric tests at hot sort are focused in wafer probe phase. These tests

include the test to detect shorts and test to screen out non-functioning bits. The

tests yielding more repair solutions are used for failure analysis in order to

produce enough column repair data.

5. The block/column repair data is plotted to investigate the count of parts with a

particular block/column repair in a sample of 2Gb NAND flash die. For example,

in a sample of 20,000 die, a particular block 100 is repaired in 25 die. Here “25”

51

represents count of parts where the 100th block is repaired in a sample of 20,000

NAND flash die.

The generated trends from the repair data and an analysis of the block/column

failures are presented and discussed in the next sections.

3.1.2 Observation of the Trends/Patterns for Repair Data

Repair analysis allows us to observe the trends in the NAND flash repair data

and determine the reasons for any unexpected variations from the expected patterns. The

block/column repair data generated for a sample of 20,000 individual die were plotted in

Excel with the block/column number on the X-axis and the number of die which had a

particular block/column repaired, or the number of times a particular block/column was

repaired, on the Y-axis. The results are presented below.

Column Repair Analysis

A 2Gb NAND flash chip has typically 65536 rows and 33792 columns of flash

cells arranged in an array. Columns are global bit lines, so the same column is repaired in

all 2048 blocks. The parts are tested for column shorts in wafer probe and information

about the failed columns is stored for repairing. The column repair data was extracted for

a sample of 20,000 die, which were tested for column shorts in wafer probe. The column

repair data for few columns is tabulated in Table 3.1. In the table, the data for every four

columns i.e. 33750, 33754, 33758 and so on is shown. This is because one column repair

consists of 4 physical columns being replaced. The column repair data from 33750 –

52

33790 columns is presented, since it was observed that they are repaired a larger number

of times when compared to other columns. The complete repair data of all the columns

can be presented upon request as it is a large amount of data. The column repair data is

normalized to the largest value, because the defect density is confidential at Micron

Technology Inc.

Sample Size – 20,000 NAND Flash Parts

Column# #Parts having a particular column

repaired (Normalized Values) 33750 0.345521

33754 0.413163 33758 0.391225 33762 0.447898 33766 0.458867

33770 0.453382 33774 0.453382 33778 0.493601

33782 0.431444 33786 0.334552 33790 1

Table 3.1 Column Repair Data at Wafer Probe for 2Gb NAND Flash Parts

A graph was plotted with the extracted column repair data tabulated in

Appendix-A for 20,000 NAND flash parts at wafer probe using Excel. The resulting plot

is as shown in FIGURE 3.1. Information about number of parts having a particular

column repaired is known by plotting the column number on the x-axis and the count of

parts for each of the columns repaired in a sample of 20,000 NAND flash die on the y-

axis. It was observed from the generated trend in FIGURE 3.1, that for a sample of

53

20,000 NAND flash parts, the last few columns of an array have a higher repair rate than

the other columns. A similar trend was observed for the other test at wafer probe which

screens out non-functioning bits. The next section discusses the possible reasons for the

observed trend.

0

0.2

0.4

0.6

0.8

1

1.2

0 5000 10000 15000 20000 25000 30000 35000 40000

Column# (0-33792)

No

rmalized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Co

lum

n R

ep

air

ed

FIGURE 3.1 Plot of Column Repair Data after Wafer Probe

for 2Gb NAND Flash Parts

Block Repair Analysis

A 2Gb NAND flash memory is typically divided into 2048 blocks. Functional

and parametric tests are conducted on the parts at wafer probe and information about the

failed blocks is stored for repairing. The block repair data was extracted for a sample of

54

20,000 die, which were tested for shorts in wafer probe. The procedure for the extraction

of block repair data at wafer probe is similar to that of the column repair analysis of

section 3.1.1. The block repair data for few blocks is tabulated in Table 3.2. In the table,

the repair data for blocks 0-10 is presented, since it was observed that they were repaired

more number of times when compared to other blocks. The complete repair data of all the

blocks 0-2047 can be presented upon request as it is a large amount of data. The block

repair data is normalized to the largest value as the defect density is confidential at

Micron Technology Inc.

Block# #Parts having a particular column repaired (Normalized Values)

0 1 1 0.941385 2 0.724954 3 0.728242

4 0.689165 5 0.64476 6 0.619893 7 0.543517 8 0.548845 9 0.507993

10 0.403197

Table 3.2 Block Repair Data after Wafer Probe for 2Gb NAND Flash Parts

A graph is plotted with extracted block repair data, tabulated in Appendix-B, for

20,000 NAND flash parts at wafer probe using Excel. The resulting plot is as shown in

FIGURE 3.2. Information about the number of parts having a particular block repaired is

known by plotting the block number on the x-axis and count of parts for each of the

55

blocks repaired on the y-axis. It was observed from the generated trend in FIGURE 3.2

that there is a decreasing pattern for the number of times a particular block is repaired. It

is also observed from FIGURE 3.2 that Block-0 and Block-1 are being repaired the most.

A similar pattern was generated for other test in wafer probe which screens out non-

functioning bits. The following section discusses some possible reasons for the

observed trends.

0

0.2

0.4

0.6

0.8

1

1.2

0 500 1000 1500 2000 2500

Block# (0-2047)

No

rma

lize

d C

ou

nt

of

Pa

rts

wit

h a

Pa

rtic

ula

r B

loc

k R

ep

air

ed

FIGURE 3.2 Plot of Block Repair Data after Wafer Probe

for 2Gb NAND Flash Parts

56

3.1.3 Explanation for the Cause of the Generated Patterns

Column Repair Analysis

It was observed from the column repair analysis at wafer probe that last few

columns towards the end of the array were repaired more when compared to the other

columns. The column defects found were mainly due to the process variations such as

metal width, etch time, implant variation, critical dimension variation, photo exposure,

and chamber defects. Detailed explanations of some possible process induced reasons

behind the failures of a particular column are explained below.

• Critical Dimension Variation:

The critical dimensions of metal lines are thinner towards the edges of the die.

This is because the chip is designed and fabricated in such a way that metal lines

become dense and thinner towards the edges. This increases the resistance of the

metal lines which decreases the charge flowing through them. This makes the bits

slow to program and results in the subsequent failure of that particular column.

This is one of the reasons behind the failure of the last column. This is a well

known issue in fabrication but the failure rate is so small that there is no yield loss

of die.

• Periphery Fails:

The periphery is all of the circuitry that surrounds the array. All of the logic,

latches, pumps, driver, and decoder are part of the periphery. If an entire column

fails, it could be a problem in the periphery. For example, voltage pump is

connected in the external circuitry to supply voltage to the parts. If the voltage

57

pump is not able to provide the necessary voltage to the flash cells for performing

the operations they fail.

• Metal Widths:

Metal lines could be shorted together during manufacturing of the part, causing

columns to fail. The reason for this, may be contamination blocking the etch,

photoresist or deposition. These are the process variations. FIGURE 3.3 illustrates

such a failure of columns due to process variations.

FIGURE 3.3 Column Fails due to Process Variations

Early in the life of a new process, the column repair trend will have a higher

failure rate towards the end of the flash array due to the process variations. But as the

process matures and steps are optimized, edge defects are reduced and the curve flattens.

Block Repair Analysis

In the block repair trend generated at wafer probe in section 3.1.2, it was

observed that block-0 and block-1 were repaired the most. Block–0 and block-1 are given

priority over the other blocks for repair because it is one of the customer’s requirements

that block-0 and block-1 of the NAND flash part must be good. So, the probe engineers

58

repair the block-0 & block-1 more when compared to other blocks. This is to ensure that

customer’s specifications are satisfied.

We can also see in the trend in FIGURE 3.2 that the block repairs are more

towards both the edges of NAND flash array. Redundant blocks are the extra blocks built

in the chip which can be used to replace the failed blocks. Typically there are about 10-12

block repairs per die. First, the redundant blocks are used for repairing failed block-0 and

block-1. Then other failed blocks of the die are repaired. During the sampling period, the

repair algorithm starts repairing the bad blocks starting from block-0 and then continues

down sequentially. So, the die is not left with enough redundant blocks towards the end

for repair. Therefore, the blocks are repaired less towards the end. Thus, the block repair

data analysis at wafer probe for a sample of 20,000 NAND flash die resulted in an

expected pattern with more failures in both the ends of the flash array and is shown in

FIGURE 3.2. An abnormal pattern was not observed for column repair analysis and block

repair analysis at wafer probe. So, the failure analysis for the NAND flash memory at

package test was done to look for abnormal patterns in order to search for the reasons

behind the failure patterns.

3.2 Analysis at Package Test

The packaged parts from assembly are passed through a test flow which is an

electrical process that tests every part for parametric (operating currents, opens, shorts &

input/output leakage), speed, and functional performance to device specification. In wafer

probe, repair analysis is done whereas at package test failure analysis is the focused. This

59

is because by the time the product reaches package test it will be too late for repair.

Analysis of the failed blocks at package test is done for the same 2Gb NAND flash parts

since part of this thesis work is to look for any abnormal patterns and find the possible

causes/explanation for these patterns. The more parts with failing blocks, the more data

there is to analyze. Based on this criterion, the tests in electrical flash test flow were

chosen for failure analysis and are listed below:

• Test I: Speed Timing Write Test ( High Corner Vcc)

• Test II: Speed Timing Write Test (Low Corner Vcc)

• Test III: Speed Timing Read Test

• Test IV: Speed Timing Write Test (logical checkerboard ‘0’ test pattern)

• Test V: Read1 Test

The block failure data for each of these tests were extracted for failure analysis, the

procedure for the block failure data extraction is described in the next section.

3.2.1 Procedure for the Extraction of Package Test Failure Data

The block failure data extraction involves coding in PERL. A clear

understanding of the format of stored package test data in the semiconductor industry is

necessary to perform this failure data extraction. The package test failure data used for

the analysis was extracted using web based tools and PERL scripts. The following series

of steps are involved in the block failure data extraction

60

1. Extraction of lots that ran in package test a few days back from the database using

specific commands in UNIX.

2. Generation of Die ID’s for each lot. About 20,000 die ID’s are generated. Among

them, the parts that have at least one block failing at a particular test are extracted

using a PERL script. Parts generated for each lot and the tests conducted on them

are given as input to this script. The number of parts that fail after this particular

test is conducted is obtained as output. This sample of failed parts is used to

obtain the block failure data as illustrated in step 3. The Scripts developed are not

presented as they are proprietary to Micron Technology Inc.

3. The blocks which fail for specific tests for each of the failed parts are extracted

from the sample generated in step 2. PERL scripts are developed to extract the

block failure data for specific tests from large amounts of package test data. The

scripts used for the generation of block failure data are not presented as they are

confidential to Micron Technology Inc.

4. Specific tests conducted at package test such as Speed Timing Write Test and

Speed Timing Read Test are chosen. This is because they have more repairs and

have sufficient failure data for analysis.

5. The block failure data is plotted for selected tests after packaging to investigate

the count of parts with a particular block fail in a sample of 2Gb NAND flash die.

The block failure data at package test is thus extracted using the steps

mentioned above for a sample of 2Gb NAND flash parts. The block failure data for

61

Speed Timing Read Test and Speed Timing Write Test at package test are extracted

and plotted to look for abnormal patterns. The generated trends from block failure

data at package test and an analysis of block failures are presented and discussed in

the next sections.

3.2.2 Observation of the Failure Trends/Patterns for Different Package Tests

In wafer probe, the trends generated from the column repair and block repair data

were as expected. So, we focused on generating the failure trends for package test. The

main purpose of analyzing the failure trends for different package tests is to look for any

abnormal patterns, and to try to relate the patterns back to the design or the process to

determine the causes. The trends observed for the various test runs are presented below:

� Test I: Speed Timing Write Test (High Corner Vcc)

Speed Timing Write Test is conducted on the 2Gb NAND flash memory with

high corner Vcc applied to the flash chip, which is typically about 3.7V. This test checks

if all the blocks of NAND flash array are programmed with the logical checkerboard test

pattern. If the test pattern is not written correctly onto the blocks of NAND flash array,

they fail. The block failure data was extracted after the Speed Timing Write Test (High

Corner Vcc) was conducted, using the procedure followed in section 3.2.1. It was found

that 12,000 NAND flash parts failed after this particular test. The block failure data was

extracted from 12,000 NAND flash parts. The failure data gives the information about the

normalized count of parts that have a particular block fail. The count of parts that fail to a

62

block is normalized to the largest value, because the information is confidential to Micron

Technology Inc. The count of the parts having a particular block fail is plotted for all the

blocks in the NAND flash array to observe the failure pattern. The resulting block failure

pattern for the Speed Timing Write test is shown in FIGURE 3.4. Here x-axis represents

blocks of the 2Gb NAND flash array; i.e., 0- 2047 blocks, and the y-axis represents the

number of parts having a particular block fail. It was thus observed from the trend

generated that there is an increase in the block failure rate towards both the edges of the

flash array. The explanation for the cause of generated pattern is presented in section

3.2.3.

SAMPLE SIZE: 12,000 NAND Flash Parts

63

0

0.2

0.4

0.6

0.8

1

1.2

0 500 1000 1500 2000

Block# (0-2047)

Count of Parts w

ith a

Partic

ula

r Blo

ck F

ail

FIGURE 3.4 Plot of Block Fails after Speed Timing Write Test

(High Corner Vcc)

� Test II: Speed Timing Write Test (Low Corner Vcc)

Speed Timing Write Test is conducted on 2Gb NAND flash memory with low

corner Vcc applied to the flash chip, which is typically about 2.6V. The blocks of the

NAND flash array are programmed with a logical checkerboard test pattern in this test,

and then the blocks are tested to determine the correct test pattern is written. The block

failure data was extracted after the Speed Timing Write Test (Low Corner Vcc) was

conducted, using the procedure followed in section 3.2.1. It was found that 32,000

NAND flash parts failed after this particular test. The block failure data was extracted

from these 32,000 NAND flash parts. This gives the information about the normalized

count of parts that have a particular block fail. The count of parts that fail in a block after

conducting the Speed Timing Write Test is normalized to the largest value because the

64

information is confidential to Micron Technology, Inc. A graph is plotted from the block

failure data tabulated in Appendix D which is shown in FIGURE 3.5. In the plot, the x-

axis represents the block numbers; i.e., 0-2047 of a 2Gb NAND flash array and y-axis

represents the normalized count of flash parts with a particular block fail. The generated

trend thus has higher block fails towards one end of the flash array when compared the

other. The explanation for the cause of generated pattern is presented in section 3.2.3.


0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 500 1000 1500 2000

Block# (0-2047)

Norm

alized C

ount of P

art

s w

ith a

Part

icula

r B

lock F

ail

FIGURE 3.5 Plot of Block fails after Speed Timing Write Test

(Low Corner Vcc)

• Test III: Speed Timing Read Test

65

Speed Timing Read Test is used to check if the blocks of the 2Gb NAND flash

memory array are able to read the test pattern within data sheet timings. If the blocks of

the flash array are not able to read the values within the time specified in the data sheet,

they fail this particular test. The block failure data for 2Gb NAND flash memory was

generated using the procedure followed in section 3.2.1. The count of NAND flash parts

that failed after this test was conducted was 14,000. The block failure data was extracted

from these 14,000 NAND flash parts. A graph is plotted to investigate the count of flash

parts that fail in each of the blocks; i.e., 0-2047. The plot is generated from the values

failure data, with block numbers on the x-axis and the count of parts that fail to a

particular block on the y-axis. A normalized count of the parts is presented because the

data is confidential to Micron Technology, Inc. Thus, from the generated trend as shown

in FIGURE 3.6 it can be seen that there is higher failure rate at the edges than the middle

of the flash array. The explanation for the cause of generated pattern is presented in

section 3.2.3.

66

SAMPLE SIZE: 14,000 NAND Flash Parts N

orm

alized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

Block# (0-2047)

FIGURE 3.6 Plot of Block Fails after

Speed Timing Read Test

� Test IV: Speed Timing Write Test (with logical ‘0’ checkerboard test pattern)

Speed Timing Write Test is conducted on the 2Gb NAND flash parts which

checks whether a logical ‘0’ test pattern is written correctly onto the flash array. This

logical ‘0’ test pattern is different from the physical checkerboard pattern and logical

checkerboard test pattern. The blocks of flash array are programmed to a logical ‘0’

checkerboard test pattern to check whether the pattern is written and within the datasheet

specified timings. The series of steps discussed in section 3.2.1 are followed for the

extraction of block failure data on the 2Gb NAND flash memory. 9,000 NAND flash

67

parts failed after this particular test. The block failure data was extracted from these 9,000

NAND flash parts. This failure data gives the information about the normalized count of

parts that have a particular block fail. The count of parts that fail in a block after

conducting the Speed Timing Write Test is normalized to the largest value because the

information is confidential to Micron Technology Inc. A graph is plotted from the block

failure data which is as shown in FIGURE 3.7. In this plot, the x-axis represents the block

numbers; i.e., 0-2047 of the 2Gb NAND flash memory and the y-axis represents the

normalized count of flash parts with a particular block fail. Thus, the generated trend has

higher block fails at both the edges of the flash array. The explanation for the cause of

generated pattern is presented in section 3.2.3.

68

SAMPLE SIZE: 9,000 NAND Flash Parts N

orm

ali

zed

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

0

0.2

0.4

0.6

0.8

1

1.2

0 500 1000 1500 2000

Block# (0-2047)

FIGURE 3.7 Plot of Block Fails after Speed Timing Write Test

(with logical ‘0’ checkerboard test pattern)

� Test V: Read1 Test

Read1 Test is conducted on the blocks of the NAND flash array with low corner Vcc

applied to the parts after an erase operation was performed to verify that all the blocks are

in an erased state. The blocks in the NAND flash array should be ‘1’ when they are read

after an erase operation. If the blocks of the array do not have value ‘1’ after the Read1

Test is conducted, they fail this test. The block failure data was extracted after Read1

Test was conducted, using the series of steps mentioned in section 3.2.1. It was found that

3,000 NAND flash parts failed after this particular test. The block failure data was

extracted from 3,000 NAND flash parts and is tabulated in Appendix A. This table gives

the information about the normalized count of parts that have a particular block fail. The

69

count of parts that fail to a block is normalized to the largest value because the

information is confidential to Micron Technology Inc. The normalized count of the parts

having a particular block fail is plotted for all the blocks in the NAND flash array to

observe the failure pattern. The resulting block failure pattern after Read1 Test is shown

in FIGURE 3.8. Here, the x-axis represents the blocks of the 2Gb NAND flash array;

i.e., 0- 2047 blocks, and the y-axis represents the number of parts having a particular

block fail. The plot in FIGURE 3.8 shows that the number of blocks that failed at this

particular package test had an abrupt increase in the middle of the array and towards the

ends. There was a higher failure rate for the blocks in between 0-15, 976-1071 and 2032-

2047.


No

rmalized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

0.6

0.7

0.8

0.9

1

1.1

0 500 1000 1500 2000 Block# (0-2047)

FIGURE 3.8 Plot of Block Fails after Read1 Test

70

The block failure analysis was done for five package tests for the 2Gb NAND

flash memory. The plots generated from the block failure data gave us the information

about the number of parts that have a particular block fail. It was observed that Speed

Timing Write Tests and Speed Timing Read Test resulted in the trends that had increase

in block failure rate towards both the edges of the NAND flash array. However, the

blocks that underwent the Read1 Test were found to have a trend which is different when

compared to other four package tests conducted on the flash parts. The blocks 0-15, 976-

1071, and 2031-2047 had larger number of failed blocks after the Read1 Test than the

failed blocks after Speed Timing Write Tests and Speed Timing Read Test. Read1 Test

resulted in higher block failure rate towards the middle and edges of the array as

compared to other blocks in the array. The reason for this increase in block failure rate

after the Read1 Test was conducted must be determined. The following section discusses

the cause for the generated trends after the package tests are conducted on the flash parts.

3.2.3 Explanation for the Cause of the Generated Patterns

It was observed from the trends presented in the previous section that Speed

Timing Write Test (High Corner Vcc), Speed Timing Write Test (Low Corner Vcc),

Speed Timing Write Test (with logical checkerboard ‘0’ test pattern) and Speed Timing

Read Test resulted in an increase of failed blocks on both the edges as compared to the

middle of the NAND flash array. Typically, the critical dimensions of the parts towards

the edge of the array are smaller because the array boundaries of the chip are denser,

causing developing or etching differences near the edges of the array. Smaller critical

71

dimensions increase the resistance of the flash cells toward the edges of array. The

increase in the resistance of the flash cells implies a higher voltage is needed to turn on

the transistors. Thus, smaller critical dimensions results in an increase in the threshold

voltage of flash cells. Because of this increase in threshold voltage, the control voltage

applied to the flash cells is not sufficient to program the flash array. This causes the flash

cells towards the edge of the array to be programmed slowly. When the blocks towards

the edges of the array are tested, they tend to fail more than the other blocks of the array.

Thus, when Speed Timing Write Test (High Corner Vcc), Speed Timing Write Test (Low

Corner Vcc), Speed Timing Write Test (Logical checkerboard ‘0’ test pattern) and Speed

Timing Read Test are conducted on the NAND flash parts, the blocks towards the both

the edges of the array fail. Thus, the patterns generated for these tests were as expected.

However, after Read1 Test it was seen that there was an increase in the block failure rate

towards the edges of the array and in the middle of the array from blocks 976-1071.

Block failure analysis of 2Gb NAND flash parts for the Read1 test resulted in an

unexpected pattern, specifically the increase in block failure rate in the middle of the

array. At this stage in the research the exact reason for this increase in the failure rate of

blocks 976-1071 was not known.

72

3.2.4 Variation of Trend for the Failure Data of Read1 Test

The block failure trend at Read1 Test deviates from the trends generated at other

package tests. The tests are conducted in the package test process to catch the block fails

before the parts are shipped to the customers. There would be higher block fails on both

edges of the array because the flash cells are programmed slowly and hence the cells are

not programmed correctly. This would be an expected pattern after the tests are

conducted on the NAND flash parts in Package Test. Therefore, the Speed Timing Write

Tests and Speed Timing Read Test generated expected trends as shown in FIGURE 3.9.

But, the Read1 Test resulted in an increase in block failure rate in middle of the array

along with the edges of the flash array. This is an unexpected trend. FIGURE 3.10, shows

the unexpected trend that resulted in the higher block failure rate from blocks 0-15, 976-

1071, and 2031-2047. The block failure trend at Read1 Test is unexpected as there was

an increase in the failed blocks in the middle of the array. The plots in FIGURE 3.9 and

FIGURE 3.10 show the expected and unexpected trends at Read1 Test for 2Gb NAND

flash parts respectively.

Systematic approaches must to be made to determine the exact cause for the

higher failure rate of blocks 0-15, 976-1071, and 2032-2047. We discuss in the next

chapter the methodologies followed to determine the cause for the unexpected pattern

generation of block failure after Read1 Test.

73

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 500 1000 1500 2000

Block# (0-2047)

Norm

alized C

ount of P

art

s w

ith a

Part

icula

r B

lock F

ail

FIGURE 3.9 Plot of Expected Trend after Read1 Test

No

rmalized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

0.6

0.7

0.8

0.9

1

1.1

0 500 1000 1500 2000

Block# (0-2047)

FIGURE 3.10 Plot of Unexpected Trend after Read1 Test

74

3.3 Summary

In this chapter, we presented the failure analysis performed at wafer probe and

package test. The trends generated at wafer probe and package test were observed. The

trends generated for the tests at wafer probe were as expected and the reasons for the

generation of the failure trends were explained clearly. In package test, five tests for a

sample of 2Gb NAND flash parts were considered for analysis. The plots generated from

the block failure data gives information about the number of parts which have a particular

block fail. The trends generated for four tests were similar. However, an abnormal trend

was observed for Read1 Test. We discuss in next chapter, the methodologies followed to

determine the reason for the increase in the block failure rate after Read1 Test.

CHAPTER 4

METHODOLOGIES FOR THE DETECTION OF

HIGH BLOCK FAILURE RATES AFTER READ1 TEST

As discussed in the previous chapter, the 2Gb NAND flash parts that were tested

at Read1 Test, exhibited a pattern that deviated from other package tests. It was presented

in Chapter 3 that Speed Timing Write Test (High Corner Vcc), Speed Timing Write Test

(Low Corner Vcc), Speed Timing Write Test (with logical checkerboard ‘0’ test pattern)

and Speed Timing Read Test resulted in an increase of failed blocks on both the edges

when compared to the middle of the NAND flash array. However, the Read1 Test had a

higher failure rate for blocks in the middle of the array i.e. 976-1071 along with the

blocks towards the edges of array i.e. 0-15 and 2032-2047 as shown in FIGURE 3.8. The

increased failure rate decreases the yield of a die. This will have a direct impact on the

quality of the final product and the efficiency of production. Hence it is pivotal for the

semiconductor industry to diagnose the parts with failed blocks and resolve such

problems.

This research employs a systematic approach to this problem that will attempt to

analyze all possible parameters that are responsible for failure of the parts. It will reduce

the uncertainty window and help in getting to the crux of the problem. In the thesis work,

three different methodologies were investigated to determine the reason for the increase

in the block failure rate at Read1 Test. The three methodologies followed are Extraction

of History on the Parts with High Failure Rate, Use of Wafer Map Tool to Determine the

Causes for the Increase in the Block Failure Rates and Package Tests Performed on Parts

76

with Higher Failure Rate. In this section, we provide a detailed discussion on the

sequence of different approaches we made to determine the possible causes for the higher

block failure rate in a sample of NAND flash parts.

4.1 First Approach – Extraction of History on the Parts with High Failure Rate

The seemingly obvious and best approach for determining the increase in block

failure rate would be to gather all the information about the failed blocks. The failure data

at fabrication, wafer probe, and package phases may possibly lead to some particular

parameters responsible for increase in block fails in a sample of NAND flash parts.

Device failures are traced using the part information stored during wafer probe, assembly,

and package test. The historical information about the parts with higher failure rate is

stored at every stage of die manufacturing. This historical information is extracted to

scrutinize any major failures and determine the causes for the failure.

The information extracted on the NAND flash parts with failed blocks is

discussed below. The failed parts were first grouped based on attributes. Attributes are

the parameters which uniquely identify the part. The following is a list of some of the

many attributes available that are important to this discussion.

• Country of assembly: Determines the location of the plant where the parts were

built. Categories of country of assembly are US and China. Categories are

different parts of an attribute.

77

• Product Grade: Classifies the quality of the part based on the following unique

levels of quality classifications. The categories of product grade are as listed

below.

o Level 1 : Cleanest die (Die which meet all the standard data sheet

specifications)

o Level 2 : Die with a lower quality (Die which partially meet the data sheet

specifications)

o Level 3 : Die with poor quality (The die that does not meet data sheet

specifications with respect to speed tests or stress tests, but is functionally

operational; i.e., passes parametric tests and margin tests.)

• Machine Model: The designated make and model number of the machine which

electrically tested the failed parts.

• Machine ID: The unique identification number of the machine which tested the

failed parts.

• Operator ID: The ID of the operator who conducted the tests.

The failed parts were grouped based on the attributes listed above using PERL scripts.

A large amount of information is stored in the database about the manufactured parts. A

lot of time was spent in extracting the necessary data from a large volume of data. The

scripts that were developed earlier in the company would only give the information about

attributes associated with a particular part. But for the thesis work, PERL scripts were

written to group all the failed parts with the same attribute. The particular scripts written

78

are not presented in this thesis as it is confidential information at Micron

Technology Inc.

The failed parts were grouped based on the test attributes and plotted to determine the

percentage of parts failed, due to a particular attribute. In other words the main purpose

was to determine whether the higher percentage of particular block fails was due to a

particular attribute. For example, consider the machine ID test attribute. It may be

possible that a particular machine is not functioning properly and the parts were

manufactured using that machine. So, by grouping the failed parts based on test

attributes we shall come to know if a particular machine, operator or country of assembly

is responsible for increase in the block fails. From the data extracted it was observed that

each category of the attribute contributed equally towards the block failure. There was no

such category in any of the attributes that resulted in a higher block failure rate when

compared to others. There were an equal percentage of failed blocks for each of the

categories of an attribute. It was thus observed that no particular attribute was

responsible for the higher failure rate for blocks 0-15, 976-1071, and 2032-2047.

Although this methodology could not be used to determine the cause for the increase in

block fails after Read1 Test, it did provide a good starting point.

79

4.2 Second Approach - Use of Wafer Map Tool to Determine the Causes for the Increase in Block Failure Rates

Since the analysis of external parameters described in the previous section did not

provide a solution to the problem, an in-depth analysis was needed. Before proceeding

with any further analysis it is necessary to know the location on the wafer of the parts

with higher block failure rate. This may lead to the reasons behind the higher failure rate.

Wafer Map Tool was used for this purpose. Wafer Map Tool is a complex software tool

which plays a useful role in failure analysis by visually presenting large amounts of die

information onto a wafer map. Wafer Map Tool allows us to collect, edit, analyze, and

visualize measured physical parameters on semiconductor wafers. Details about the

Wafer Map Tool were described in Chapter 2.

The usage of Wafer Map Tool for this project requires a clear understanding of its

operation for effective use in failure analysis. The fabrication group stores the

information about the location of the part/die on the wafer in a database during

manufacturing. The information stored provides die ID, Wafer ID, and location of die (X-

location and Y-location). When the die ID is provided to the Wafer Map Tool, it looks in

the database for the wafer ID on which the die was manufactured and then for the

location of die. It then shows the location of part on the wafer map. Wafer Map Tool can

thus be used to determine the location of parts on the wafer by viewing the wafer map

generated.

Wafer Map Tool was employed to map the location of the NAND flash parts

with failed blocks after Read1 Test to a wafer map. A lot of time was spent putting a

large volume of block failure data; i.e., sample of 3,000 failed NAND flash parts, onto

80

the wafer map. It was important to identify the part from which the failed block occurred

and that the die ID of failed block was stored correctly. This stored information was then

presented as input to the Wafer Map Tool. The Wafer Map Tool then presents the exact

location of the NAND flash parts with failed blocks on the wafer based on the die ID.

The actual wafer map obtained could not be presented as the information of die density

on the wafer is confidential to Micron Technology Inc. However, the wafer map

schematic layout shown in FIGURE 4.1 is similar to the actual wafer map obtained. This

figure presents the location of parts with block fails after Read1 Test was conducted on

the 2Gb NAND flash parts. The blue color in the wafer map represents the maximum

parts where blocks 0-15, 976-1071, and 2031-2047 failed. The red color indicates the

minimum parts where blocks 0-15, 976-1071, and 2031-2047 failed. The dark green, light

green and yellow colors in the wafer map indicate the location of parts whose count is

between maximum parts and minimum parts for which blocks 0-15, 976-1071, and 2031-

2047 fail. Thus, wafer map generated in FIGURE 4.1 using Wafer Map Tool shows the

location of NAND flash parts for which blocks 0-15, 976-1071, and 2031-2047 fail.

81

ACTUAL SAMPLE SIZE USED – 3,000 NAND Flash Parts

FIGURE 4.1 Wafer Map of NAND Flash Parts after Read1 Test

Note: Blue – Location of Parts having maximum number of block fails

Red – Location of Parts having minimum number of block fails

The main objective of analyzing block failure data on NAND flash parts using a

Wafer Map Tool was to obtain information about the parts corresponding to failed blocks

on the wafer. This determines to know the concentration of parts with higher block

failure rate on any particular area of the wafer. Based on these results, a detailed analysis

can be performed which may lead to design or manufacturing related issues. From the

above wafer map in FIGURE 4.1, it can be observed that the parts with failed blocks

were not concentrated in a particular region of the wafer. This approach to evaluate the

reasons for the higher failure rate was also not conclusive as the location of parts that fail

at read1 package test were randomly distributed on the wafer. The NAND flash parts

with higher block fails were not concentrated on the wafer map. So, further analysis is

82

not useful in determining the cause for higher block fails on NAND flash parts after

Read1 test.

4.3 Third Approach – Package Tests Performed on the Parts with Higher Failure Rate

Since the previous approaches did not provide any conclusive evidence, a third

approach was used to understand the higher failure rate on blocks 0-15, 976-1071, and

2032-2047 after Read1 Test. In this methodology, the focus was on the tests conducted

on the failed blocks at Package Test. At Package Test, the parts being shipped to the

customers undergo a series of tests that check functional and electrical parameters for the

last time. The tests are conducted on the NAND flash parts in a particular order, called

the standard test flow. However, the test flow can be varied to improve the yield by

including extra tests. When the parts are not tested under the standard test flow, i.e., when

an extra test is added, they may have a higher failure rate as compared to the parts tested

in the standard test flow. One possible reason could be that the addition of an extra test

might have affected the threshold voltages of the flash cells in such a way that they tend

to fail in the succeeding tests. Hence, variation in threshold voltage may cause incorrect

programming, erasing, or reading the flash cells and they fail after tests are conducted.

Thus, there is a need to investigate the tests performed on the parts with a higher failure

rate, and study the threshold voltage distribution of the NAND flash parts before and

after Read1 Test. This will ensure that flash cells have the necessary threshold voltage to

perform the program, erase, and read operations properly.

83

The information on the Package Tests performed on the NAND flash parts with

failed blocks from 0-15, 976-1071, and 2032-2047 is to be extracted to ensure that there

was no extra test added to the standard test flow. Then, the study of the threshold voltage

distribution of the NAND flash parts before and after Read1 Test may possibly lead to

the determination of the reason for the higher block failures. The next chapter illustrates

in detail how the study of the threshold voltage distribution of the NAND flash parts for

tests conducted before and after Read1 Test was helpful in determining the reason for the

higher block failure rate.

4.4 Summary

In this chapter, three different methodologies were employed to determine the

reasons for the higher block failure rate in a sample of NAND flash parts at Read1 Test.

The first method involved the extraction of historical information about the parts, to

identify if any particular parameters or attributes were correlated to the increase in block

failure. This process could not determine the cause, because all the attributes contributed

equally towards the block failure. The second method made use of the Wafer Map Tool

to determine the exact location of the NAND flash parts with higher block failures which

could help determine the exact reason for the block failure. But this method was also not

conclusive, because the parts with failed blocks at read1 package test were randomly

distributed. The third method that was employed, we focused on the tests conducted on

the NAND flash parts with higher block fails in the package test phase. The next chapter

discusses and analyzes to show how this particular approach was helpful in detection of

84

reasons for the higher block failure rate in a sample of NAND flash parts at read1

package test.

CHAPTER 5

DETECTION OF HIGHER BLOCK FAILURE RATE

AFTER READ1 TEST

As illustrated in the previous chapter, different methodologies were used to detect

the reasons for the higher block failure rate in a sample of NAND flash parts at Read1

Test. The first two approaches were not helpful in finding out the exact reasons for the

failure. The third approach presented more possibilities to determine the reason for

increase in block failure rate. This approach requires information on the tests conducted

at the package test phase on the blocks of NAND flash parts with higher failure rate. This

is to determine if there was a deviation from the standard test flow by addition of an extra

test. Then, the threshold voltage distributions of NAND parts before and after Read1 Test

are to be studied, to make sure that parts have necessary threshold voltage to perform

write, erase and read operations. If the NAND flash parts do not have required threshold

voltage to write, erase or read, they fail after the tests at package test phase. Therefore,

the study of voltage distributions after the tests at package test phase may possibly lead

us in determining the exact reasons for the higher block failure rate at Read1 Test. The

standard test flow employed for NAND flash parts is described in the Section 5.1 as

mentioned.

86

5.1 Standard Test Flow Employed for NAND Flash Parts

The parts at Package Test undergo a series of tests, called a test flow. The parts are

tested in blocks of arrays and are marked as failed when so detected. The other tests in

test flow skip the failed parts. The test flow can be modified at anytime to increase the

yield. The standard test flow employed for NAND flash parts to check for operational

modes is as listed below:

• Block Erase

• Block Read

• Block Program

• Block Read

Detailed descriptions of the operational modes of NAND flash parts were given in

Chapter 2. The threshold voltage combinations applied to the flash cells define the mode

of operation. All the blocks of the flash parts are first tested for the erase operation at the

package test phase. The NAND flash cells (bits) of the block are erased and then read

using Block Read Test to check if they were erased properly. A flash cell which is erased

correctly should be read as 1. Then the flash cells are tested for the program operation.

Program operation is tested by programming/writing all the blocks with a test pattern and

then reading them to determine whether all the flash cells are written with the same

pattern as programmed. The blocks of the NAND flash parts can be programmed with

different test patterns for intensive testing at Package Test. The parts are thus first tested

87

for their erase and program operation using Block Read Test in a standard test flow.

Different tests are employed to check for write, erase and read operation of NAND flash

parts. For example, different test can be conducted for program operation using various

test patterns such as logical checker board pattern or physical checker board pattern.

The standard test flow can be modified at anytime to increase the yield. During this

process new tests may be inserted or excluded. The next section discusses the

observations of modified test flow on the blocks with higher failure rate in the sample of

NAND flash parts at the package test phase.

5.2 Observation of Deviation from Standard Test Flow

It was observed from the block failure data after Read1 Test in Chapter 3, that

there was an increase in block failure rate for blocks 0-15, 976-1071 and 2032-2047. The

exact reason for this higher block failure in the NAND flash parts needs to be determined.

We focused on the third methodology discussed in Chapter 4 i.e., to verify if an extra test

was added in the standard test flow to make sure that the threshold voltage of the flash

cells were not altered. If the parts do not have required threshold voltage they fail after

the Package Test. So, the third approach shall possibly help us in determining the reason

for higher failure rate of blocks 0-15, 976-1071 and 2032-2047 in a sample of 2Gb

NAND flash parts.

It is thus necessary to know the information of tests conducted on the NAND

flash parts at package test phase to make sure that there was no extra test added in the

standard test flow. For this, the information about the series of tests conducted on failed

88

blocks of 2Gb NAND flash parts at package test was extracted. The extraction first

involves grabbing the die ID’s of the parts with higher block fails. The die ID’s are then

given as input to a PERL program to determine if the parts were tested in the standard

test flow. Existing programs at Micron Technology Inc., outputs only the tests which

were done on the parts without the sequence in which the tests are conducted on NAND

flash parts. The PERL script developed for this thesis checks for the sequence in which

the tests are conducted and outputs the tests inserted in the standard flow other than the

tests in the standard test flow. The written PERL script is not presented as it is

confidential to Micron Technology Inc. It was observed from the output information

generated from the PERL script that there was a deviation from standard test flow by

addition of extra test in standard test flow. The following section discusses and analyzes

to show how the addition of extra test in standard test flow altered the threshold voltage

of NAND flash parts after the tests at package test phase.

5.2.1 Addition of Programming Time Test on NAND Flash Parts

It was observed that there was an additional test conducted only on blocks 0-15,

976-1071, 2032-2047 of the 2Gb NAND flash parts using the PERL scripts mentioned in

section 5.2. This particular test modified the standard test flow on NAND flash parts.

This additional test was found to be the Programming Time (tprog) Test. Product

engineers try varying the parameters, such as the input supply voltage, temperature at

which the test is conducted, and the test patterns to be applied to the NAND flash parts to

investigate results after test. They analyze the results and try to find out the best possible

89

way to improve the quality of NAND flash parts. In the process of this, the engineers

collect data to keep track of time taken by the part to program. Programming Time Test

was inserted in the standard test flow after an erase operation. This is because if tprog is

conducted on a fully erased block, we would be able to get the correct time/pulses

required to program a block. Otherwise, if tprog is conducted on an already programmed

block, it would take less time or pulses to program it again and the programming time

shall decrease. This was the reason for the addition of Programming Time Test in the

standard test flow.

For proprietary reasons, the specific details of how the tprog test is conducted are

not presented here. In general the tprog test is used to assess the length of time the part

took to program a page of the array. Initially, the Vcc levels that range from 2.65 – 3.6V

are set. A five-cycle command is then issued to the part where two cycles are for

instruction and three cycles are for page address within the block. Then, the test pattern is

chosen for programming the part. The programming time is the time measured from

when the status pin goes low (busy) till until it goes high (ready). Thus, the programming

time is the time taken by the part to program a particular test pattern onto the page of

array for a NAND flash part.

It was detected that the blocks with higher failure rates were tested for

programming time before Read1 Test. Thus, we speculated that insertion of the tprog test

may be the reason for the higher block failure rate. It was discussed in Chapter 2 that the

threshold voltage distribution of the flash cells varies for each of its operations. If the

threshold voltage of each of the flash cells is not sufficient to perform write, erase and

90

read operations then the flash cells fail after the test is conducted on the parts. Read1 Test

fails the blocks if it does not read ‘1’ in the flash cells. This test is performed after an

erase operation. The value stored in the flash cells after they are erased should be ‘1’. In

the thesis it was observed that there were failed blocks after the Read1 Test as the blocks

were not erased properly. This is because if the blocks would have been erased properly

they would read ‘1’ and shall not fail after Read1 Test. The possible reason for not being

erased properly could be that the flash cells in the blocks did not have the required

threshold voltage to perform the erase operation. Thus, there is a need to ensure that the

addition of the Programming Time Test has not altered the threshold voltage of the flash

cells. The mechanism by which the addition of the tprog test resulted in an increase in

block fails at Read1 Test is discussed in detail in the next section. The observed threshold

voltage distribution of all the blocks for the 2Gb NAND flash parts before and after

Read1 Test is conducted is presented in the next section.

5.2.2 Variation in Threshold Voltage Distribution of NAND Flash Parts

As discussed in the previous section, it was detected that tprog was conducted on

the NAND flash parts just before Read1 Test. The tprog was inserted after erase

operation and Read1 Test which might have caused the fails after Read1 Test. This

Programming Time Test was speculated to be responsible for the alteration of threshold

voltages of the parts after Read1 Test. Thus there is a need to observe the threshold

voltage distribution after each of the tests conducted before and after the Read1 Test. The

threshold voltage distribution of flash cells in all the blocks was observed after the tests

91

listed below. The Programming Time Test and Read1 Test are embedded in the test flow

as shown below.

1) Erase all blocks

2) Programming Time Test on blocks 0-15, 976-1071 and 2032-2047

3) Erase all blocks

4) Read1 Test

In the test flow that was conducted, all the blocks of the parts were first erased.

This results in a decrease in the threshold voltage of the flash cells in each of the blocks.

FIGURE 5.1 represents the threshold voltage distribution of flash cells in the blocks after

an erase operation is performed. In the threshold voltage distribution curves presented in

this thesis, the x-axis represents the blocks and the y-axis represents the threshold

voltage, which ranges from 2V to -2V. The threshold voltage distributions presented are

just for illustration purposes and they are not the actual measured values. The product

engineers at Micron Technology, Inc. have previously recorded the threshold voltage

values of the flash cells after the tests are conducted in test flow. With their guidance the

threshold voltage distributions of the NAND flash cells were sketched. In the FIGURE

5.1, all the NAND flash cells in the blocks have a negative threshold voltage after they

are erased as illustrated in section 2.1.3.2.

The blocks 0-15, 976-1071 and 2032-2047 were then programmed to measure the

programming time. The ideal situation would be to test all pages in all blocks from 0 to

2047, so that the entire array will be covered. However, due to test time and cost

92

constraints, certain pages on those blocks are chosen. The end of the array; i.e., blocks 0-

15 and 2032-2047, as well as the middle of the array; i.e., blocks 976-1071, are checked

on the 2Gb parts because these blocks of the array have a high probability of failure as

per the previous results noted by Product Engineers at Micron Technology Inc.

After they are tested for programming time, the blocks are called programmed

blocks. The threshold voltage distribution of the flash cells in blocks after Programming

Time Test is illustrated in FIGURE 5.2. The threshold voltage of the programmed blocks

increases to a positive value as the write operation is performed on the blocks of the

NAND flash array. So, it can be seen that the threshold voltage increases for the flash

cells in programmed blocks 0-15, 976-1071, and 2032-2047. But, the threshold voltage of

the non-programmed blocks does not change as no operation is performed on them.

93

FIGURE 5.1 Threshold Voltage FIGURE 5.2 Threshold Voltage

Distribution after Erase Operation Distribution after Programming

Time Test

The Programming Time Test is followed by a block erase, where all the blocks are

erased. The threshold voltage distribution of the flash cells in blocks after Block Erase is

presented in FIGURE 5.3. When an erase operation is performed on the programmed

blocks the threshold voltage of the flash cells decreases to a negative value. Hence, the

threshold voltage of flash cells in the programmed blocks decreases from positive value

to negative value as shown in FIGURE 5.3. However, it was observed that the block

erase operation caused the programmed blocks to decrease to a different threshold level

distribution as compared to that of non-programmed blocks.

94

There was an increase in the threshold voltage level after the tprog test for

programmed blocks. The programmed blocks thus need more erase pulses to yield a

threshold voltage distribution similar to the non-programmed blocks. More pulses could

be applied to make the threshold voltage levels of flash cells in programmed and non-

programmed blocks same. But, that would not meet the specifications mentioned in the

data sheet to the customers. The customers are guaranteed that the erase operation is

performed within the time specified in the datasheet. Moreover, the non-programmed

blocks were already in the erase state as the tprog test was not conducted on them. So,

when the blocks are erased again after tprog, the threshold voltage of the flash cells in the

non-programmed blocks would decrease more when compared to that of flash cells in

programmed blocks. Hence, the threshold voltage of flash cells in programmed blocks 0-

15, 976-1071, and 2032-2047 is not the same as that of non-programmed blocks for a

sample of 2Gb NAND flash parts.

95

FIGURE 5.3 Threshold Voltage Distribution after Block Erase

The Read1 Test follows Block Erase, which checks if the flash cells in the blocks

are read as ‘1’ after block erase. An erased cell in a block stores ‘1’. We present in

FIGURE 5.4 the threshold voltage distribution after Read1 Test. The threshold voltage

distribution of the flash cells after Read1 Test (FIGURE 5.4) is same as that of threshold

voltage distribution after Block Erase (FIGURE 5.3). However, FIGURE 5.4 shows the

erase verify level and the flash cells that fail after Read1 Test. It was observed that after

Read1 Test the programmed blocks failed more as compared to the non-programmed

blocks. The blocks above the erase verify level would not have required threshold voltage

to perform the erase operation correctly and they fail. In FIGURE 5.4, the threshold

voltage of the flash cells in programmed blocks exceeded the erase verify level. So, the

96

blocks were not erased properly and the flash cells were not read as ‘1’ when Read1 Test

was conducted.

FIGURE 5.4 Threshold Voltage Distribution after Read1 Test

Read1 Test is included in the package test flow to check for the cells to be erased

properly after an erase operation. The voltage applied to the parts for Read1 Test was set

accordingly to suit the primely erased cells and not regular erase. However, due to the

inclusion of tprog, a few blocks were in the programmed state and the others were in the

erased state. So, the programmed blocks did not have erase margin similar to that of the

non-programmed blocks, which caused them to fail after Read1 Test. Therefore, the

addition of the Programming Time Test resulted in a difference in the threshold voltage

97

distribution of programmed and non-programmed blocks. This was the primary reason

for the higher block failure rate of the NAND flash parts at Read1 Test.

5.3 Mechanism for the Increase in Block Failure Rate after Read1 Test

Failure analysis resulted in the conclusion that the increase in block failure rate

for the NAND flash parts after Read1 Test was due to the insertion of a Programming

Time Test in the standard test flow. This test was conducted on blocks 0-15, 976-1071,

and 2032-2047 and was embedded in the test flow just before the Read1 Test. The

Programming Time Test is followed by erasing all the blocks of the NAND flash parts.

Then after Read1 Test, blocks were checked to see if they were erased properly. The

blocks 0-15, 976-1071, and 2032-2047 failed after the Read1 Test. This was because the

threshold voltage of the flash cells was not sufficient to perform the erase operation.

When the tprog was conducted, there was an increase in threshold voltage for the

programmed blocks. After the tprog test, the programmed blocks required more pulses to

produce an erase margin similar to that of non-programmed blocks. Thus, the threshold

voltage was not sufficient to perform the erase operation correctly on programmed

blocks. This resulted in a higher failure rate to the programmed blocks as compared to the

non-programmed blocks. If tprog had been run on all the blocks, this would result in an

increase in failure rate for all the blocks, not just the blocks 0-15, 976-1071, and 2032-

2047. However, due to the test time constraints, only a few blocks at both the edges and

middle of the NAND flash array are chosen. Thus, the addition of the Programming Time

Test just before Read1 Test resulted in a higher failure rate of the NAND flash parts.

98

From the discussion it can be concluded that the Programming Time Test should

not be conducted on the parts just before Read1 Test. This shall alter the threshold

voltage required to perform the operations correctly. The Programming Time Test was

thus inserted after the Read1 Test was conducted. The block failure trend was observed

for NAND flash parts after Read1 Test, as shown in FIGURE 5.5. The graph is plotted

using the block failure rate after Read1 Test tabulated in Appendix B. The values

tabulated in Appendix B are the values extracted when the tprog is moved. It can be seen

that the block failure rate decreased for all the blocks in the NAND flash array after the

Programming Time test was inserted after Read1 Test as compared to the FIGURE 3.10.

We present FIGURE 3.10 again in this chapter to compare the results when the tprog was

inserted just before the Read1 Test and then when tprog was moved after Read1 Test.

No

rmalized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

0.6

0.7

0.8

0.9

1

1.1

0 500 1000 1500 2000

FIGURE 5.5 Plot of Block Fails after Read1 Test with Programming

Time Test moved in Standard Test Flow

99

No

rmalized

Co

un

t o

f P

art

s w

ith

a

Part

icu

lar

Blo

ck F

ail

0.6

0.7

0.8

0.9

1

1.1

0 500 1000 1500 2000

Block# (0-2047)

FIGURE 3.10 Plot of Unexpected Trend after Read1 Test

It was found that the Programming Time Test has to be conducted after Read1

Test at package test to decrease the failure rate. This is useful to the product engineers at

Micron Technology, Inc. in improving the yield. The scripts developed in the process of

determination of the higher failure rate after Read1 test could be used by the engineers

for future failure analysis.

5.4 Summary

In this chapter, the reason for the higher block failure rate after Read1 Test for a

sample of 2Gb NAND flash parts was determined. The increase was due to a deviation

from the standard test flow conducted on the parts at Package Test. It was determined

that the Programming Time Test was responsible for the failures. We described in this

100

chapter in detail how the insertion of the Programming Time Test just before Read1 Test,

resulted in a variation in the threshold voltage distribution of the NAND flash parts. It

was thus concluded that the addition of the Programming Time Test before the Read1

Test was the primary reason for the higher block failure rate. So, the Programming Time

Test was inserted after Read1 Test is performed in the standard test flow at Package Test.

This results in a decrease in the failure rate of the NAND flash parts.

CHAPTER 6

THEORETICAL CALCULATIONS FOR PROGRAMMING

AND ERASING A NAND FLASH CELL

This chapter focuses on the theoretical calculations involving programming and

erasing operations of a NAND flash cell. In section 6.1, the count of electrons on the

floating gate of a single 2Gb NAND flash cell during program operation is calculated.

Tunnel current density of a NAND flash cell is determined in section 6.3 assuming the

standard parameters of a 0.12µm NAND flash technology. From tunneling current, the

minimum number of electrons that must be injected into the floating gate to “Program” a

single cell to the “0” state is computed in section 6.2. Towards the end of the chapter in

section 6.4, a method of calculating the minimum energy required to erase a flash cell is

qualitatively explained.

6.1 Calculation of charge stored on the Floating Gate of a NAND Flash Cell

Floating gate NAND - non volatile memory operation is based on the capacitive

coupling between the Floating Gate (FG) and all other electrodes. By applying an

external voltage to the control gate (CG) it is possible to control the FG potential in order

to capture the electrons during cell writing or emit them during cell erasing. FIGURE 1

shows the schematic cross section of a single NAND flash cell with intrinsic

capacitances. The upper gate in FIGURE l is the control gate (CG) and the lower gate,

completely isolated within the gate oxide, is the floating gate (FG). CFG, CFD, CFS, and

CFsub are the capacitances between the floating gate and the control gate, drain, source,

102

and substrate regions, respectively. For programming a NAND cell, the source and

substrate are both grounded and potentials VGS and VDS are applied to the control gate

and the drain, respectively.

FIGURE 6.1. Schematic Cross Section of Single NAND Flash Cell

with Intrinsic Capacitances [30]

During programming operation, in order to initiate Fowler-Nordheim tunneling,

high voltage is required on the control gate with respect to the substrate for program

times in the µs range. This is called programming voltage/control gate voltage (Vpp or

VGS). Typically, Vpp is 15-20V to have an appreciable tunnel current in a NAND flash.

This ensures the collection of electrons on the floating gate and causes an increase in the

threshold voltage of the programmed cell. Thus for programming, i.e., putting electrons

103

into the floating gate of a NAND flash cell, a minimum programming voltage of 15V is

required. With this voltage, the minimum number of electrons injected into the floating

gate during program operation can be calculated. The Fowler–Nordheim electron

tunneling mechanism is a quantum-mechanical mechanism, induced by an electric field,

where electrons tunnel through a reduced barrier width. Applying a strong electric field

(in the range of 8–10 MV/cm) across a thin oxide, it is possible to force a large electron

tunneling current through it without destroying its dielectric properties.

The parameters of the 2Gb NAND flash manufactured at micron are typically as

follows [31, 32]:

Floating gate (W) = 30nm;

Control gate W= 70nm;

Oxide thickness= tox= 7.5nm;

ONO thickness = 15.5nm;

CFD=0.06 ×10-16 F;

CFS=0.04 ×10-16 F;

CFsub=0.624 ×10-16 F;

CFG=1.2 ×10-16 F;

Tunneling oxide capacitance (Ctunox ) = 5.3 ×10-17 F

104

For programming a 2Gb NAND cell the voltages applied are: VDS=0V, VGS=15V. These

voltages are required for the electrons to be injected onto the floating gate from the

inversion channel by Fowler-Nordheim tunneling. The potential of the floating gate VFG,

due to capacitive coupling during programming mode, is given by [29]:

V FG = FSubFSFDFG

DSFDGSFG

CCCC

VCVC

+++

+ ** ----- (6.1)

The floating gate is completely isolated by surrounding layers of oxide and acts as

a capacitor with charge retention capability. The floating gate voltage is less than the

control gate voltage because of the influence of internal capacitances. During

programming operation of a NAND cell as the source and substrate are grounded, we

have considered in equation 6.1, the effects of source, drain and control gate capacitances

on the floating gate. From equation 6.1, the sum of capacitances between the floating

gate and the control gate, drain, source, and substrate regions is termed as the total

capacitance (CT) on the floating gate. CT is given by following equation [29]:

CT = FSubFSFDFG CCCC +++ ----- (6.2)

Substituting CT from above equation 6.2 in equation 6.1, the floating gate voltage during

programming a flash cell is given by [29]

105

V FG = T

DSFDGSFG

C

VCVC ** + ----- (6.3)

= )( DS

FG

FDGS

T

FGV

C

CV

C

C+ ----- (6.4)

The parameter values of the 2Gb NAND flash cell are substituted to equation 6.2 to

calculate the total capacitance value, and the result is:

CT = FSubFSFDFG CCCC +++

= (1.2 + 0.06 + 0.04 + 0.624) × 10-16 F

= 1.92 ×10-16 F

The value of the floating gate voltage can be found by substituting the parameter values

of the 2Gb NAND flash cell in equation 6.4 yielding:

VFG = )( DS

FG

FDGS

T

FGV

C

CV

C

C+

= )0102.1

1006.015(

1092.1

102.116

16

16

16

××

×+

×

×−

−

−

−

= 1592.1

2.1×

= 9.375V

106

Thus, when a voltage of 15V is applied on the control gate (VGS), the floating gate

voltage of the NAND cell is found to be 9.375V. This is the voltage necessary to inject

the electrons onto the floating gate during program operation using the Fowler Nordheim

mechanism. A detailed explanation of Fowler Nordheim tunneling in NAND flash cells is

given in section 6.2.

The charge stored on either side of the floating gate in terms of the floating gate potential

calculated above, is given by [29]:

QFG = Ctunox × (VFG – VDS ) ----- (6.5)

= 5.3 × 10-17 × (9.375 – 0)

= 5.3 × 10-17 × 9.375

= 4.97 ×10-16 C

1 Coulomb of charge requires 6.2 ×1018 electrons, so 4.97 ×10-16 C of charge on the

floating gate implies 4.97 ×10-16×6.2 ×1018 = 3080 electrons.

No. of electrons on the floating gate during programming of a NAND cell

= 4.97 ×10-16×6.2 ×1018= 3080 electrons

The value determined above for 120nm gate length is in accordance with the results from

the plot of number of electrons and gate length as shown in FIGURE 6.2 [38]. It is

107

expected that less than 100 electrons will be stored for 30nm design rule cell [38]. For

120nm, the number of electrons on the floating gate will typically range from 1000 –

10,000 from FIGURE 6.2. It was found from equation 6.5 that for a 2Gb NAND flash

cell 4.97 ×10-16 C of charge is stored on the floating gate and the number electrons stored

on the floating gate is 3080 electrons.

FIGURE 6.2 Number of stored electrons in a NAND Flash cell [38]

6.2 Mechanism of Electron Injection into the Floating Gate of a NAND Flash Cell

The charge storage on either side of the floating gate during programming of a

NAND flash cell is determined from calculations in section 6.1. In this section,

mechanism of electron injection into the floating gate using Fowler Nordheim tunneling

is discussed. In NAND flash memory devices, data is represented by a certain amount of

108

electrical charge on the floating gate, and the charge is injected through a tunnel junction

by using the Fowler-Nordheim (FN) tunneling process. The junction between the floating

gate and silicon substrate of a NAND flash cell is the tunnel junction. In order to charge

the floating gate, a control pulse is applied to the control gate of a NAND flash cell so

that a strong electric field appears across the tunnel junction. When the pulse is applied to

the control gate, the tunneling current charges the floating gate. In program operation the

floating gate is charged negatively with electrons tunneling from the drain through the

thin oxide. After the pulse on the control gate is terminated, the charge injected into the

floating gate slowly diffuses into the silicon substrate and changes the floating gate

potential. This decreases the threshold voltage of the cell as it requires less gate voltage to

be applied to turn on the flash cell.

Charge injection characteristics can be analyzed based on the equivalent circuit as

shown in FIGURE 6.3 below. The floating gate potential is denoted by VFG and VGS is

the voltage applied to the control gate. The charge injection mechanism can be

qualitatively described by considering the way VFG responds to the control pulses. When

the positive pulse, Vpp (programming voltage) is applied to the terminal as shown in

FIGURE 6.2, it raises the tunnel junction voltage Vtun (|Vsub – VFG|) by γ*Vpp [36], where

γ is the coupling capacitance ratio CFG/Ci. Ci is the sum of the tunnel junction capacitance

Ctunox, capacitance between the floating gate and substrate CFSub, and the coupling

capacitance CFG between the floating gate and the control gate. The tunneling current Itun,

flows and charges the floating gate. As VFG rises, the tunnel junction voltage (Vtun = |Vsub

– VFG|) decreases from γ*Vpp to a certain voltage defined as tunneling threshold voltage

109

(Vtt). Accordingly, Itun rapidly decreases to zero, and charge is no longer injected. The

charge injection is thus self limiting within a short period of time. The amount of the

charge injected can be roughly estimated by the change in floating gate voltage (from

γ*Vpp to Vtt) during the pulse application [36].

FIGURE 6.3 Equivalent Circuit of a NAND Flash Cell

The amount of charge injected into floating gate (Qinj) is given by, [34]

Qinj = Capacitance of the floating gate × Floating gate voltage for charge injection

= Ci × ( γ*Vpp - Vtt ) ----- (6.6)

where Vtt is tunneling threshold voltage. It is defined as the voltage of the control gate

relative to the ground that would induce F-N tunneling when the body region is

grounded.

The charge injected for one pulse is given by,

Qinj = ∫T I * dt = Itun * T ----- (6.7)

where T is the pulse period applied to the control gate.

110

6.3 Calculation of Tunneling Current (Itun) using Fowler Nordheim Tunneling Mechanism

Charge injected into the floating gate of a NAND flash cell can be found using

equation 6.7. From equation 6.7, the tunneling current (Itun) can be calculated by the

Fowler Nordheim tunneling mechanism. Programming and erasing of a flash cell is done

by using the FN tunneling process. During programming of a flash cell, a relatively large

voltage is applied to the control gate as shown in FIGURE 6.4. The interpoly dielectric

(IPD) that separates the floating gate from the control gate in FIGURE 6.3 is formed by a

triple layer of oxide–nitride–oxide (ONO). The applied control voltage creates the

electric field which changes the potential barrier. The change in barrier reduces the width

of the channel allowing the electrons in the substrate to tunnel through the thin gate oxide

(typically less than 12 nm) and eventually be collected in the n+ poly-Si floating gate.

FIGURE 6.4 Programming a NAND Flash Cell

During erasing a NAND flash cell, control gate is grounded and 15V is applied to

the substrate as shown in FIGURE 6.5. The electric field generated causes the electrons

111

to tunnel away from the floating gate, making the flash cell more positive and turning on

the NAND flash cell.

FIGURE 6.5 Erasing a NAND Flash Cell

The tunneling current density through the tunnel oxide is approximated by the well-

known Fowler-Nordheim equation and is given by [28]:

)exp()( 2

tun

tuntunE

EJβ

α−

±= ----- (6.8)

where Jtun is the current density in A/cm2, Etun is the electric field in the oxide in V/cm,

and α and β and are constants. The thin-oxide field Etun is given by [28]

ox

tun

tunt

VE = ----- (6.9)

112

where Vtun is the voltage drop across the thin tunnel oxide (|Vsub – VFG|) and tox is oxide

thickness.

The tunneling current (Itun) due to Fowler-Nordheim tunneling in terms of tunneling

voltage from equation 6.8 and 6.9, can be written as [36]

=tunI Jtun * Atun

tun

FGsub

ox

ox

FGsub AVV

t

t

VV∗

−

×−−±= )exp(

)(2

2 βα ----- (6.10)

where Atun is the area of the tunnel oxide (length of the tunnel oxide multiplied by tunnel

oxide thickness), α and β are constants and are given by

box

Si

m

mq

φπα

h2

3

16= ----- (6.11)

box

Si

m

m

φ

11054.1 6−×= (A/V2),

2/3

2/1)2(

3

4b

ox

q

mφβ

h= ----- (6.12)

2/32/17 )(1083.6 b

Si

ox

m

mφ×= (V/cm),

where q is the electronic charge, mSi and mox are the effective electron mass in Si and

SiO2, respectively, h is the Planck constant, h is the reduced Planck’s constant, and φb is

113

the oxide barrier height. Electrons in a Floating Gate should acquire an Energy equivalent

to barrier potential of SiO2 and Silicon P-Substrate. It is equal to φb = 3.2 eV.

The values of α and β can be calculated from a Fowler-Nordheim (F-N) plot.

From equation 6.8, a plot of log (J/E2) Vs 1/E is called a FN plot because it is a linear

curve. This plot gives the value of the slope constant β, from which the (mox /mSi)1/2φb

3/2

product can be obtained. Then, with a known effective mass, φb can be calculated, or with

a known φb, the effective mass can be calculated. α and β values can be determined from

typical measured tunneling current characteristics for electrons being injected onto

(forward) or removed (reverse) from the floating gate as a function of the voltage

difference between the floating gate and the silicon substrate [33]. The voltages required

to produce an appreciable tunnel current in the forward and reverse directions for a

NAND flash cell are typically 12V and 15V, respectively [37]. A typical measured

tunneling I-V curve is as shown in FIGURE 6.6 [32, 34]. The x-axis represents the

voltage applied on the control gate (Vpp) and the y-axis represents the tunneling current

(Itun).

To better characterize the tunneling performance, the measured data are plotted on

Fowler-Nordhiem plots (log [Itun / Vtun2] vs. [1/Vtun]) [32, 34]. Based on the I-V

measurements, a Fowler-Nordheim plot in forward and reverse directions is plotted as

shown in FIGURE 6.7 [32, 34]. From the forward Fowler-Nordheim plot in FIGURE 6.7,

α and β were extracted as 1.25 x 10-6 A/V2 and 2.67 x l08 V/cm, respectively. In the

reverse direction, α and β were 1.88 x 10-6 A/V2 and 2.55 x l08 V/cm respectively, for tox

in the range 100-150 Ǻ. The above mentioned tunneling characteristics obtained from the

114

research paper [32] are in accordance with 2Gb NAND flash cells of Micron. The

parameters and the voltages applied on the control gate for tunneling are similar. The

comparison of parameters of 2 Gb NAND flash cell from Micron and 0.12µm design rule

NAND flash cell from the research paper [32] are shown in Table 6.1. The parameters of

2Gb NAND flash cell of Micron and from the research paper are identical. In a 0.12µm

design rule cell, gate length = gate space = floating gate height = channel width = 120nm.

From Table 6.1 it is found that minimum programming voltage applied to the control gate

in Micron and Research paper is15V. So, the values α and β determined from FN plot and

tunneling I-V characteristics of Research Paper can be used for the calculation of

tunneling current for a 2Gb NAND flash cell.

Parameters of 2Gb NAND flash cell

(Micron)

Parameters of NAND Flash Cell

(Research Paper [32])

Design Rule Cell = 0.12µm Design Rule Cell = 0.12µm

Vpp = 15V Vpp = 15V

Oxide thickness= tox= 7.5nm Oxide thickness= tox= 7.5nm

ONO thickness = 15.5nm ONO thickness = 15.5nm

Ctunox = 5.3 ×10-17 F Ctunox = 5.3 ×10-17 F

Table 6.1 Comparison of 2Gb NAND Flash Cell Parameters

from Micron and Research Paper

115

FIGURE 6.6 Measured I-V Characteristics of NAND Flash Cell [32, 34]

116

FIGURE 6.7 Fowler-Nordheim plot of the FIGURE 6.3

(a) Forward direction (b) Reverse direction [32, 34]

117

Substituting the values of α and β into equation 6.10, the tunneling current (Itun) can be

calculated.

Itun tun

FGsub

ox

ox

FGsub AVV

t

t

VV∗

−

×−−±= )exp(

)(2

2 βα

)5.7120(*)0375.9

105.71067.2exp(

)5.7(

)0375.9(1025.1

78

2

2

6nmnm

nm×

−

×××−−××±=

−−

= 9.3 × 10 -13 A

From Itun, the charge injected into the floating gate of a NAND flash cell (Qinj) can be

calculated using the equation 6.7. The value of pulse period (T) to program a typical 2Gb

micron device is 300µs as per the 2Gb specification sheet in Appendix C [40]. Qinj is

determined as follows:

Qinj = Itun * T

= 9.3 × 10 -13 × 300µs

= 2.79 × 10 -16 C

1 Coulomb is amount of electrical charge in 6.2 ×1018 electrons. So, electrons injected

into the floating gate (Ninj) is given by

Ninj = Qinj * ×6.2 ×1018

= 2.79 ×10-16×6.2 ×1018 = 1730 electrons

118

It is observed from section 6.1 that the number of electrons stored on the floating gate

is 3080 electrons. This is calculated from charge stored on either side of the floating gate

when 9.375V is applied to the FG of the flash cell. Charge on either side of the floating

gate drains away when no voltage is applied. When we apply a large DC voltage of about

15V to the control gate, electrons are trapped in the FG according to Fowler Nordheim

tunneling. When no voltage is applied these electrons are retained in the floating gate.

The number of trapped electrons (Ninj) was 1730 electrons as per the calculations in this

section 6.4. The number of electrons injected (Ninj) during programming of a NAND

flash cell is also in accordance with the plot in FIGURE 6.2 [38].

6.4 Calculation of Required Energy to Program and Erase a NAND Flash Cell

A NAND flash cell is erased with pulses. Erase requires just 1 pulse of 300µs width,

20V peak with ~200µs charge-up and discharge time. Time between the pulses is 4.7µs.

So if the block does not verify after this 1 pulse then it fails. Energy of the carriers must

be sufficient to surmount the barrier to electrons. By considering the number of electrons

injected into the floating gate per pulse, total energy required can be calculated. This

section provides the qualitative way to calculate the minimum energy required for erasing

a flash cell.

We erase by raising the silicon p-substrate to 20V. The selected WL is tied to

ground. The electrons must have an energy close to or higher than that of the oxide

barrier (3.15eV) to be injected into the floating gate. A very small percentage of electrons

in the channel have such high energy, so the current injected into the floating gate is very

119

small, resulting in slow programming. High voltages are required to produce these hot

electrons, so it is difficult to scale the program/erase voltages with each technology node.

During the erase operation of a flash cell, the electric field generated causes the

electrons to tunnel away from the floating gate, making it more positive and turning on

the transistor. This decreases the threshold voltage of the cell as it requires less gate

voltage to turn on the flash cell. The energy band structure of the floating gate memory

during erasing by FN tunneling is as shown in FIGURE 6.8. Ec and Ev are the conduction

and valence bands respectively and Eg is the energy band gap (1.1 eV for silicon).

FIGURE 6.8 Energy Band Diagram of a Floating Gate Memory

during Erasing by FN Tunneling [10].

120

Erasing a flash cell by FN tunneling removes the charge from the floating gate

and the erased cell stores logic ‘1’. The energy required to erase a flash cell is the

minimum tunneling voltage (Vtun) required to erase a cell multiplied by the charge on the

floating gate and is given by:

Energy required to erase a flash cell = |Vtun| ERASE × Qinj ----- (6.13)

For computing the energy required to erase a NAND flash cell Vtun should be calculated.

Vtun can be expressed for an electrically neutral floating gate for programming a NAND

flash cell in terms of simple coupling ratios, and is given by [28]:

----- (6.14)

where Kw represents the fraction of applied voltage across the tunnel oxide during

programming of the flash cell and is given by the ratio between CFG and the total

capacitance (CFG+CFsub+Ctunox). During the write operation of a NAND flash cell, a high

voltage is applied to the control gate (Vpp) and the substrate and drain are grounded.

Hence in equation.6.14, the control gate voltage is considered. The voltage applied to the

floating gate is dependant on the capacitance between the floating gate and control gate

(CFG). The voltage to be applied to the floating gate for programming a NAND flash cell

can be found using Kw , which is given by [28]:

|Vtun|WRITE = Vpp * Kw

121

Kw = tunoxFsubFG

FG

CCC

C

++ [28]

= 161053.01610624.016102.1

16102.1

−×+−×+−×

−×

= 0.5

During the erase operation of a NAND flash cell, the control gate is grounded (VCG=0).

A voltage of 15V is applied to the silicon substrate and drain is grounded (VDS= -15V).

The drain voltage (VDS) is considered for determining the tunnel oxide voltage

(|Vtun|ERASE). The voltage drop across the tunnel oxide during erasing a flash cell is given

by [28]:

----- (6.15)

where Ke represents the fraction of applied voltage across the tunnel oxide during erasing

a flash cell and is given by the ratio between (CFG+CFsub) and the total capacitance

(CFG+CFsub+Ctunox). The tunneling voltage for erasing a NAND flash cell can be found

using Ke , which is given by [28]:

Ke = tunoxFsubFG

FsubFG

CCC

CC

++

+ [28]

|Vtun|ERASE = VDS * Ke

122

= 1 - tunoxFsubFG

tunox

CCC

C

++

= 1 -161053.01610624.016102.1

161053.0

−×+−×+−×

−×

= 1-0.225 = 0.77

The coupling ratios, Kw and Ke, denote the fraction of the applied voltage that appears

across the tunnel oxide. Note that the above equations are applicable only when the

charge on the floating gate is zero. During a WRITE operation buildup of negative stored

charge on the floating gate will reduce the tunnel-oxide voltage according to equation

6.16 as shown below [28].

|Vtun|WRITE = Vpp * Kw + tunoxFsubFG

inj

CCC

Q

++ ----- (6.16)

=15*0.5 + 161053.01610624.016102.1

103.9 17

−×+−×+−×

× −

≈ 7.5 V

In the ERASE operation, the initial negative stored charge on the floating gate will

increase the tunnel-oxide voltage according to the equation 6.17 as shown below [28]

123

|Vtun|ERASE = VDS * Ke - tunoxFsubFG

inj

CCC

Q

++ ----- (6.17)

= -15*0.77 - 161053.01610624.016102.1

20103.9

−×+−×+−×

−×

≈ -12 V

From equations 6.16 and 6.17 the minimum tunneling voltage required during program

and erase operations are calculated. Substituting the value of |Vtun|ERASE from equation

6.17 and Qinj from equation 6.8 in equation 6.13, the minimum energy to erase a flash cell

can be calculated.

Energy required to erase a flash cell = |Vtun|ERASE × Qinj

= 12 × 2.79 × 10-16

= 3.35×10-15 J = 3.35 fJ

Energy required to program a flash cell = |Vtun|WRITE × Qinj

= 7.5 × 2.79 × 10-16

= 2.1×10-15 J = 2.1 fJ

The energy required to erase and program a flash cell are determined as 3.35fJ and 2.1fJ.

The energy values calculated above for a single NAND flash cell (single bit) compare

well with the results obtained by 4Gb NAND flash memory [39]. It was found that for a

Micron 512MB (4Gb) flash memory, the energy required per byte to write/erase was of

the order 0.034µJ [39]. A byte is 8bits. So, the energy to write a single bit is 4.25 nJ

124

(0.034µJ/8bits). The values obtained for erasing and programming a single 2Gb NAND

flash cell are less than 4Gb Micron NAND flash memory and are reasonable.

CHAPTER 7

SUMMARY AND CONCLUSIONS

The objective of this research project was to analyze the failure data of NAND

flash parts at wafer probe and package test for the detection of anomalous failure rates

and to determine the reasons for the failures. In the process of failure analysis, trends in

the plotted failure data were investigated to identify abnormalities. The repair analysis at

wafer probe revealed in the trends that were as expected. Failure data was extracted for

various tests conducted on a sample of NAND flash parts at the package test phase. An

abnormal trend was observed after Read1 Test. This abnormal pattern showed higher

failure rates for blocks 0-15, 976-1071 and 2032-2047 for a sample of 2Gb NAND flash

parts. The main goal of this thesis was the determination of the reason for the unexpected

failure rate variation after Read1 Test. The increase in failure rate needed to be

determined in order to reduce the affect on production efficiency.

Three different methodologies were employed to determine the causes for the

increase in block failure rate. The first method involved the extraction of historical

information about the parts, to identify whether any particular parameters or attributes

were correlated to the increase in block failure. This process could not determine the

cause, because all the attributes contributed equally towards the block failure. The second

method made use of the Wafer Map Tool to determine the location of the NAND flash

parts with higher block failures on a wafer map, which could help determine the exact

reason for the block failure. But this method was also inconclusive, because the parts

with failed blocks at Read1 package test were randomly distributed. The third method

126

focused on the tests conducted on the NAND flash parts at the package test phase, before

and after Read1 test. This approach resulted in the determination of the exact cause for

the increase in higher failure rate.

When the tests conducted on the NAND flash parts at package test were extracted,

it was observed that the test procedure deviated from the standard electrical test flow.

There was a Programming Time Test inserted in the standard test flow just before Read1

Test. This particular test resulted in a variation in the threshold voltage distribution for

the blocks of NAND flash parts. The Programming Time Test increased the threshold

voltage of the flash cells in the programmed blocks 0-15, 976-1071 and 2032-2047.

These programmed blocks were subsequently erased and Read1 Test was performed.

After Read1 Test, the programmed blocks had a different threshold voltage distribution

than that of the non-programmed blocks. The non-programmed blocks had a slightly

different threshold voltage distribution than programmed blocks since the tprog was

inserted between erases for blocks 0-15, 976-1071 and 2032-2047. Hence, most of the

programmed blocks exceeded the erase verify level, which resulted in more frequent

failures of these blocks. Thus, it was determined that this was the primary reason for the

higher failure rates of blocks 0-15, 976-1071 and 2032-2047 after Read1 Test. It was

concluded that the Programming Time Test should be conducted on the parts after Read1

Test in the standard test flow in order to eliminate slow program blocks at the earliest

possible time, thus decreasing the failure rate.

127

This thesis provided insight into the failure analysis conducted at Wafer probe and

Package test. Failed parts were identified at each stage of manufacturing the chip, and the

reasons for their failure were also found. The main contributions to this project are

• The PERL scripts and software programs developed for the failure data extraction

at Wafer Probe and Package Test shall be useful to engineers in generation of

similar data with more ease.

• The systematic approaches made for the determination of the higher failure rates

shall be helpful to Micron Technology Inc. in future failure analysis of similar

kind of failures.

In future research, modern techniques should be employed to eliminate defects at

Wafer Probe before the die is packaged, which will increase production efficiency. The

Wafer Map Software Tool has to be developed with all compatible input data formats.

This reduces the time spent for data extraction, which is used for analysis. Better

approaches and tools may be employed in the future for the determination of failures at

Wafer Probe and Package Test, thus improving the yield of flash memory devices.

APPENDICES

APPENDIX A

Block Failure Data after Read1 Test In the table presented below “X” represents block number (0-2047) and “Y” represents the normalized count of parts with particular block fail.

X Y X Y X Y X Y

0 1 41 0.833333 81 0.841954 121 0.821839

1 0.922414 42 0.824713 82 0.818966 122 0.818966

2 0.902299 43 0.833333 83 0.824713 123 0.816092

3 0.905172 44 0.833333 84 0.83046 124 0.818966

4 0.902299 45 0.83046 85 0.833333 125 0.816092

5 0.902299 46 0.821839 86 0.821839 126 0.818966

6 0.896552 47 0.818966 87 0.836207 127 0.816092

7 0.908046 48 0.824713 88 0.833333 128 0.827586

8 0.893678 49 0.833333 89 0.83908 129 0.810345

9 0.890805 50 0.836207 90 0.816092 130 0.818966

10 0.887931 51 0.827586 91 0.83046 131 0.813218

11 0.890805 52 0.83908 92 0.821839 132 0.818966

12 0.87931 53 0.83908 93 0.83046 133 0.813218

13 0.896552 54 0.816092 94 0.813218 134 0.821839

14 0.87931 55 0.83046 95 0.818966 135 0.824713

15 0.893678 56 0.841954 96 0.818966 136 0.821839

16 0.847701 57 0.844828 97 0.821839 137 0.824713

17 0.833333 58 0.827586 98 0.827586 138 0.813218

18 0.83908 59 0.824713 99 0.824713 139 0.810345

19 0.836207 60 0.83908 100 0.821839 140 0.821839

20 0.853448 61 0.841954 101 0.83046 141 0.807471

21 0.847701 62 0.816092 102 0.813218 142 0.807471

22 0.836207 63 0.833333 103 0.836207 143 0.824713

23 0.83908 64 0.827586 104 0.821839 144 0.804598

24 0.841954 65 0.836207 105 0.83908 145 0.813218

25 0.836207 66 0.824713 106 0.807471 146 0.810345

26 0.816092 67 0.824713 107 0.821839 147 0.801724

27 0.844828 68 0.83908 108 0.824713 148 0.824713

28 0.83046 69 0.83046 109 0.818966 149 0.813218

29 0.844828 70 0.827586 110 0.813218 150 0.807471

30 0.824713 71 0.821839 111 0.821839 151 0.816092

31 0.833333 72 0.841954 112 0.824713 152 0.83046

32 0.841954 73 0.83908 113 0.83046 153 0.816092

33 0.83908 74 0.827586 114 0.821839 154 0.824713

34 0.836207 75 0.821839 115 0.818966 155 0.804598

35 0.824713 76 0.827586 116 0.821839 156 0.818966

36 0.841954 77 0.83046 117 0.821839 157 0.824713

37 0.824713 78 0.818966 118 0.816092 158 0.816092

38 0.824713 79 0.824713 119 0.810345 159 0.818966

129

39 0.824713 80 0.83046 120 0.841954 160 0.818966

40 0.83908

161 0.821839 201 0.821839 241 0.810345 281 0.827586

162 0.810345 202 0.795977 242 0.795977 282 0.821839

163 0.821839 203 0.821839 243 0.810345 283 0.804598

164 0.833333 204 0.813218 244 0.813218 284 0.824713

165 0.827586 205 0.818966 245 0.816092 285 0.83908

166 0.816092 206 0.810345 246 0.810345 286 0.810345

167 0.810345 207 0.813218 247 0.807471 287 0.810345

168 0.821839 208 0.816092 248 0.810345 288 0.818966

169 0.821839 209 0.821839 249 0.816092 289 0.810345

170 0.810345 210 0.810345 250 0.798851 290 0.807471

171 0.801724 211 0.804598 251 0.816092 291 0.816092

172 0.824713 212 0.810345 252 0.807471 292 0.824713

173 0.833333 213 0.824713 253 0.813218 293 0.821839

174 0.821839 214 0.807471 254 0.801724 294 0.813218

175 0.818966 215 0.813218 255 0.807471 295 0.807471

176 0.827586 216 0.827586 256 0.83046 296 0.833333

177 0.807471 217 0.824713 257 0.818966 297 0.816092

178 0.813218 218 0.807471 258 0.804598 298 0.810345

179 0.818966 219 0.807471 259 0.813218 299 0.818966

180 0.827586 220 0.804598 260 0.816092 300 0.83046

181 0.827586 221 0.836207 261 0.83046 301 0.816092

182 0.810345 222 0.793103 262 0.807471 302 0.816092

183 0.813218 223 0.807471 263 0.813218 303 0.804598

184 0.827586 224 0.813218 264 0.813218 304 0.83046

185 0.824713 225 0.810345 265 0.816092 305 0.818966

186 0.813218 226 0.813218 266 0.801724 306 0.818966

187 0.807471 227 0.810345 267 0.813218 307 0.795977

188 0.824713 228 0.821839 268 0.810345 308 0.810345

189 0.813218 229 0.821839 269 0.807471 309 0.813218

190 0.807471 230 0.801724 270 0.816092 310 0.804598

191 0.801724 231 0.813218 271 0.804598 311 0.813218

192 0.818966 232 0.816092 272 0.813218 312 0.83046

193 0.824713 233 0.813218 273 0.816092 313 0.824713

194 0.813218 234 0.810345 274 0.813218 314 0.801724

195 0.804598 235 0.810345 275 0.804598 315 0.798851

196 0.83046 236 0.813218 276 0.83046 316 0.801724

197 0.821839 237 0.83046 277 0.810345 317 0.816092

198 0.801724 238 0.798851 278 0.810345 318 0.810345

199 0.801724 239 0.824713 279 0.818966 319 0.818966

200 0.824713 240 0.818966 280 0.824713 320 0.816092

130

321 0.827586 361 0.824713 401 0.824713 441 0.821839

322 0.798851 362 0.818966 402 0.801724 442 0.816092

323 0.816092 363 0.816092 403 0.813218 443 0.798851

324 0.816092 364 0.827586 404 0.833333 444 0.824713

325 0.818966 365 0.816092 405 0.83908 445 0.816092

326 0.804598 366 0.807471 406 0.821839 446 0.804598

327 0.818966 367 0.818966 407 0.813218 447 0.804598

328 0.833333 368 0.824713 408 0.818966 448 0.816092

329 0.821839 369 0.816092 409 0.818966 449 0.83908

330 0.816092 370 0.804598 410 0.810345 450 0.810345

331 0.813218 371 0.818966 411 0.818966 451 0.813218

332 0.816092 372 0.821839 412 0.821839 452 0.816092

333 0.827586 373 0.821839 413 0.833333 453 0.824713

334 0.801724 374 0.813218 414 0.801724 454 0.816092

335 0.813218 375 0.816092 415 0.818966 455 0.816092

336 0.821839 376 0.816092 416 0.824713 456 0.816092

337 0.818966 377 0.813218 417 0.821839 457 0.827586

338 0.810345 378 0.818966 418 0.818966 458 0.824713

339 0.810345 379 0.816092 419 0.810345 459 0.813218

340 0.813218 380 0.813218 420 0.821839 460 0.813218

341 0.821839 381 0.83046 421 0.821839 461 0.816092

342 0.804598 382 0.821839 422 0.816092 462 0.813218

343 0.824713 383 0.813218 423 0.824713 463 0.816092

344 0.827586 384 0.824713 424 0.824713 464 0.83046

345 0.824713 385 0.827586 425 0.821839 465 0.818966

346 0.821839 386 0.807471 426 0.813218 466 0.816092

347 0.801724 387 0.813218 427 0.816092 467 0.813218

348 0.813218 388 0.813218 428 0.816092 468 0.816092

349 0.824713 389 0.810345 429 0.836207 469 0.824713

350 0.804598 390 0.813218 430 0.807471 470 0.813218

351 0.807471 391 0.813218 431 0.821839 471 0.821839

352 0.821839 392 0.821839 432 0.818966 472 0.836207

353 0.824713 393 0.821839 433 0.813218 473 0.810345

354 0.807471 394 0.807471 434 0.801724 474 0.816092

355 0.818966 395 0.804598 435 0.821839 475 0.804598

356 0.818966 396 0.816092 436 0.821839 476 0.816092

357 0.824713 397 0.807471 437 0.836207 477 0.824713

358 0.810345 398 0.807471 438 0.813218 478 0.804598

359 0.807471 399 0.824713 439 0.813218 479 0.824713

360 0.824713 400 0.827586 440 0.824713 480 0.821839

131

481 0.83908 521 0.827586 561 0.824713 601 0.827586

482 0.818966 522 0.816092 562 0.818966 602 0.810345

483 0.824713 523 0.813218 563 0.818966 603 0.818966

484 0.827586 524 0.821839 564 0.818966 604 0.83046

485 0.821839 525 0.821839 565 0.821839 605 0.818966

486 0.824713 526 0.813218 566 0.807471 606 0.798851

487 0.810345 527 0.816092 567 0.810345 607 0.824713

488 0.836207 528 0.824713 568 0.824713 608 0.824713

489 0.83908 529 0.821839 569 0.821839 609 0.827586

490 0.798851 530 0.818966 570 0.813218 610 0.818966

491 0.810345 531 0.824713 571 0.818966 611 0.810345

492 0.813218 532 0.813218 572 0.821839 612 0.827586

493 0.833333 533 0.818966 573 0.83046 613 0.833333

494 0.813218 534 0.810345 574 0.824713 614 0.818966

495 0.807471 535 0.83046 575 0.818966 615 0.821839

496 0.824713 536 0.827586 576 0.83046 616 0.827586

497 0.827586 537 0.827586 577 0.821839 617 0.818966

498 0.807471 538 0.816092 578 0.816092 618 0.810345

499 0.801724 539 0.816092 579 0.824713 619 0.824713

500 0.821839 540 0.824713 580 0.827586 620 0.818966

501 0.818966 541 0.818966 581 0.821839 621 0.824713

502 0.810345 542 0.807471 582 0.813218 622 0.801724

503 0.818966 543 0.821839 583 0.827586 623 0.816092

504 0.824713 544 0.821839 584 0.827586 624 0.83046

505 0.821839 545 0.833333 585 0.833333 625 0.821839

506 0.801724 546 0.807471 586 0.816092 626 0.816092

507 0.810345 547 0.824713 587 0.818966 627 0.818966

508 0.827586 548 0.816092 588 0.833333 628 0.83046

509 0.807471 549 0.821839 589 0.83046 629 0.824713

510 0.807471 550 0.821839 590 0.804598 630 0.798851

511 0.816092 551 0.818966 591 0.804598 631 0.818966

512 0.824713 552 0.818966 592 0.821839 632 0.816092

513 0.83908 553 0.816092 593 0.818966 633 0.821839

514 0.813218 554 0.816092 594 0.821839 634 0.807471

515 0.824713 555 0.813218 595 0.813218 635 0.813218

516 0.827586 556 0.824713 596 0.810345 636 0.821839

517 0.816092 557 0.827586 597 0.83046 637 0.83046

518 0.807471 558 0.821839 598 0.816092 638 0.801724

519 0.813218 559 0.824713 599 0.813218 639 0.810345

520 0.821839 560 0.818966 600 0.83046 640 0.818966

132

641 0.821839 681 0.821839 721 0.821839 761 0.824713

642 0.801724 682 0.807471 722 0.816092 762 0.810345

643 0.807471 683 0.836207 723 0.821839 763 0.821839

644 0.83046 684 0.827586 724 0.816092 764 0.827586

645 0.827586 685 0.824713 725 0.824713 765 0.821839

646 0.801724 686 0.807471 726 0.824713 766 0.807471

647 0.810345 687 0.824713 727 0.824713 767 0.821839

648 0.813218 688 0.827586 728 0.816092 768 0.821839

649 0.818966 689 0.824713 729 0.821839 769 0.818966

650 0.807471 690 0.813218 730 0.804598 770 0.810345

651 0.807471 691 0.804598 731 0.818966 771 0.818966

652 0.818966 692 0.818966 732 0.818966 772 0.83046

653 0.821839 693 0.827586 733 0.821839 773 0.816092

654 0.810345 694 0.810345 734 0.813218 774 0.804598

655 0.818966 695 0.821839 735 0.818966 775 0.813218

656 0.827586 696 0.827586 736 0.818966 776 0.824713

657 0.827586 697 0.83046 737 0.824713 777 0.83046

658 0.810345 698 0.810345 738 0.818966 778 0.813218

659 0.804598 699 0.804598 739 0.827586 779 0.813218

660 0.83046 700 0.810345 740 0.827586 780 0.83908

661 0.833333 701 0.821839 741 0.821839 781 0.813218

662 0.807471 702 0.804598 742 0.816092 782 0.821839

663 0.807471 703 0.816092 743 0.810345 783 0.818966

664 0.821839 704 0.821839 744 0.83046 784 0.83046

665 0.836207 705 0.824713 745 0.818966 785 0.83046

666 0.818966 706 0.818966 746 0.804598 786 0.816092

667 0.816092 707 0.818966 747 0.818966 787 0.83046

668 0.813218 708 0.83046 748 0.836207 788 0.83908

669 0.824713 709 0.827586 749 0.827586 789 0.827586

670 0.818966 710 0.810345 750 0.813218 790 0.816092

671 0.836207 711 0.816092 751 0.816092 791 0.810345

672 0.824713 712 0.841954 752 0.824713 792 0.827586

673 0.827586 713 0.816092 753 0.818966 793 0.816092

674 0.821839 714 0.824713 754 0.807471 794 0.821839

675 0.807471 715 0.824713 755 0.827586 795 0.83046

676 0.810345 716 0.827586 756 0.83908 796 0.83046

677 0.827586 717 0.824713 757 0.816092 797 0.821839

678 0.813218 718 0.816092 758 0.810345 798 0.801724

679 0.810345 719 0.821839 759 0.816092 799 0.818966

680 0.83046 720 0.816092 760 0.821839 800 0.821839

133

801 0.833333 841 0.824713 881 0.83908 921 0.833333

802 0.821839 842 0.818966 882 0.816092 922 0.821839

803 0.821839 843 0.810345 883 0.818966 923 0.810345

804 0.827586 844 0.824713 884 0.827586 924 0.824713

805 0.818966 845 0.821839 885 0.827586 925 0.827586

806 0.818966 846 0.813218 886 0.807471 926 0.821839

807 0.813218 847 0.824713 887 0.83046 927 0.821839

808 0.833333 848 0.824713 888 0.824713 928 0.83046

809 0.824713 849 0.818966 889 0.83046 929 0.83908

810 0.821839 850 0.79023 890 0.821839 930 0.804598

811 0.816092 851 0.821839 891 0.818966 931 0.810345

812 0.827586 852 0.83046 892 0.818966 932 0.833333

813 0.813218 853 0.827586 893 0.844828 933 0.827586

814 0.821839 854 0.818966 894 0.810345 934 0.813218

815 0.816092 855 0.813218 895 0.818966 935 0.818966

816 0.833333 856 0.827586 896 0.833333 936 0.827586

817 0.83046 857 0.824713 897 0.827586 937 0.818966

818 0.813218 858 0.818966 898 0.821839 938 0.818966

819 0.818966 859 0.818966 899 0.827586 939 0.813218

820 0.83046 860 0.824713 900 0.83046 940 0.827586

821 0.827586 861 0.807471 901 0.83046 941 0.824713

822 0.813218 862 0.813218 902 0.821839 942 0.818966

823 0.804598 863 0.810345 903 0.83046 943 0.827586

824 0.827586 864 0.821839 904 0.83046 944 0.833333

825 0.816092 865 0.836207 905 0.836207 945 0.824713

826 0.816092 866 0.821839 906 0.818966 946 0.821839

827 0.813218 867 0.813218 907 0.813218 947 0.821839

828 0.824713 868 0.827586 908 0.827586 948 0.83908

829 0.827586 869 0.83046 909 0.841954 949 0.818966

830 0.810345 870 0.807471 910 0.824713 950 0.824713

831 0.824713 871 0.824713 911 0.818966 951 0.827586

832 0.824713 872 0.827586 912 0.821839 952 0.824713

833 0.83046 873 0.833333 913 0.841954 953 0.833333

834 0.818966 874 0.807471 914 0.818966 954 0.818966

835 0.818966 875 0.813218 915 0.827586 955 0.827586

836 0.827586 876 0.827586 916 0.824713 956 0.824713

837 0.824713 877 0.821839 917 0.827586 957 0.818966

838 0.824713 878 0.813218 918 0.804598 958 0.824713

839 0.810345 879 0.804598 919 0.813218 959 0.813218

840 0.827586 880 0.816092 920 0.810345 960 0.827586

134

961 0.827586 1001 0.873563 1041 0.873563 1081 0.83908

962 0.818966 1002 0.87069 1042 0.873563 1082 0.813218

963 0.816092 1003 0.876437 1043 0.853448 1083 0.824713

964 0.833333 1004 0.882184 1044 0.87931 1084 0.821839

965 0.821839 1005 0.867816 1045 0.87931 1085 0.813218

966 0.833333 1006 0.859195 1046 0.876437 1086 0.818966

967 0.821839 1007 0.867816 1047 0.873563 1087 0.818966

968 0.83046 1008 0.87931 1048 0.882184 1088 0.836207

969 0.827586 1009 0.87931 1049 0.882184 1089 0.827586

970 0.83046 1010 0.867816 1050 0.873563 1090 0.821839

971 0.807471 1011 0.873563 1051 0.87069 1091 0.816092

972 0.827586 1012 0.856322 1052 0.87931 1092 0.827586

973 0.824713 1013 0.887931 1053 0.862069 1093 0.83046

974 0.818966 1014 0.864943 1054 0.864943 1094 0.824713

975 0.818966 1015 0.87069 1055 0.887931 1095 0.821839

976 0.87069 1016 0.87931 1056 0.87069 1096 0.827586

977 0.873563 1017 0.867816 1057 0.882184 1097 0.833333

978 0.87069 1018 0.864943 1058 0.867816 1098 0.807471

979 0.867816 1019 0.873563 1059 0.864943 1099 0.827586

980 0.876437 1020 0.876437 1060 0.87931 1100 0.816092

981 0.867816 1021 0.87069 1061 0.882184 1101 0.833333

982 0.867816 1022 0.867816 1062 0.873563 1102 0.816092

983 0.864943 1023 0.862069 1063 0.87069 1103 0.816092

984 0.882184 1024 0.864943 1064 0.873563 1104 0.816092

985 0.885057 1025 0.87069 1065 0.87069 1105 0.833333

986 0.882184 1026 0.873563 1066 0.87069 1106 0.813218

987 0.867816 1027 0.859195 1067 0.87069 1107 0.827586

988 0.867816 1028 0.876437 1068 0.867816 1108 0.833333

989 0.87069 1029 0.87069 1069 0.876437 1109 0.836207

990 0.87069 1030 0.856322 1070 0.847701 1110 0.816092

991 0.864943 1031 0.882184 1071 0.876437 1111 0.827586

992 0.887931 1032 0.864943 1072 0.833333 1112 0.836207

993 0.876437 1033 0.867816 1073 0.83908 1113 0.824713

994 0.859195 1034 0.864943 1074 0.821839 1114 0.818966

995 0.867816 1035 0.867816 1075 0.816092 1115 0.824713

996 0.87069 1036 0.873563 1076 0.824713 1116 0.821839

997 0.87931 1037 0.882184 1077 0.836207 1117 0.836207

998 0.867816 1038 0.876437 1078 0.810345 1118 0.821839

999 0.87069 1039 0.867816 1079 0.816092 1119 0.827586

1000 0.873563 1040 0.873563 1080 0.827586 1120 0.824713

135

1121 0.821839 1161 0.818966 1201 0.827586 1241 0.836207

1122 0.816092 1162 0.818966 1202 0.813218 1242 0.813218

1123 0.818966 1163 0.824713 1203 0.821839 1243 0.833333

1124 0.836207 1164 0.83046 1204 0.827586 1244 0.83908

1125 0.833333 1165 0.83046 1205 0.836207 1245 0.833333

1126 0.810345 1166 0.821839 1206 0.818966 1246 0.810345

1127 0.818966 1167 0.824713 1207 0.824713 1247 0.824713

1128 0.827586 1168 0.827586 1208 0.833333 1248 0.821839

1129 0.824713 1169 0.836207 1209 0.833333 1249 0.821839

1130 0.807471 1170 0.818966 1210 0.813218 1250 0.827586

1131 0.821839 1171 0.821839 1211 0.816092 1251 0.827586

1132 0.83046 1172 0.83908 1212 0.821839 1252 0.841954

1133 0.841954 1173 0.833333 1213 0.833333 1253 0.856322

1134 0.813218 1174 0.836207 1214 0.827586 1254 0.827586

1135 0.83046 1175 0.827586 1215 0.833333 1255 0.810345

1136 0.844828 1176 0.827586 1216 0.83046 1256 0.824713

1137 0.824713 1177 0.833333 1217 0.827586 1257 0.827586

1138 0.824713 1178 0.821839 1218 0.804598 1258 0.816092

1139 0.821839 1179 0.827586 1219 0.827586 1259 0.821839

1140 0.83046 1180 0.844828 1220 0.83046 1260 0.821839

1141 0.836207 1181 0.844828 1221 0.833333 1261 0.821839

1142 0.821839 1182 0.818966 1222 0.813218 1262 0.827586

1143 0.821839 1183 0.816092 1223 0.818966 1263 0.813218

1144 0.833333 1184 0.83908 1224 0.833333 1264 0.821839

1145 0.83908 1185 0.824713 1225 0.824713 1265 0.83046

1146 0.804598 1186 0.821839 1226 0.816092 1266 0.833333

1147 0.824713 1187 0.821839 1227 0.818966 1267 0.818966

1148 0.836207 1188 0.833333 1228 0.818966 1268 0.833333

1149 0.83908 1189 0.813218 1229 0.841954 1269 0.83046

1150 0.824713 1190 0.807471 1230 0.810345 1270 0.810345

1151 0.818966 1191 0.827586 1231 0.816092 1271 0.824713

1152 0.824713 1192 0.841954 1232 0.824713 1272 0.83908

1153 0.821839 1193 0.827586 1233 0.821839 1273 0.821839

1154 0.818966 1194 0.813218 1234 0.807471 1274 0.827586

1155 0.824713 1195 0.818966 1235 0.83046 1275 0.816092

1156 0.83046 1196 0.821839 1236 0.83046 1276 0.836207

1157 0.836207 1197 0.83908 1237 0.83046 1277 0.816092

1158 0.824713 1198 0.818966 1238 0.821839 1278 0.818966

1159 0.821839 1199 0.807471 1239 0.836207 1279 0.821839

1160 0.821839 1200 0.836207 1240 0.816092 1280 0.833333

136

1281 0.827586 1321 0.824713 1361 0.818966 1401 0.818966

1282 0.804598 1322 0.818966 1362 0.816092 1402 0.824713

1283 0.827586 1323 0.824713 1363 0.821839 1403 0.807471

1284 0.833333 1324 0.827586 1364 0.827586 1404 0.824713

1285 0.833333 1325 0.824713 1365 0.833333 1405 0.818966

1286 0.813218 1326 0.813218 1366 0.816092 1406 0.804598

1287 0.824713 1327 0.810345 1367 0.807471 1407 0.810345

1288 0.841954 1328 0.827586 1368 0.833333 1408 0.83908

1289 0.824713 1329 0.841954 1369 0.836207 1409 0.827586

1290 0.816092 1330 0.821839 1370 0.816092 1410 0.813218

1291 0.83046 1331 0.83046 1371 0.816092 1411 0.818966

1292 0.833333 1332 0.83046 1372 0.821839 1412 0.836207

1293 0.810345 1333 0.821839 1373 0.824713 1413 0.833333

1294 0.813218 1334 0.821839 1374 0.821839 1414 0.821839

1295 0.810345 1335 0.824713 1375 0.807471 1415 0.816092

1296 0.818966 1336 0.836207 1376 0.836207 1416 0.824713

1297 0.83046 1337 0.818966 1377 0.83046 1417 0.824713

1298 0.818966 1338 0.821839 1378 0.818966 1418 0.804598

1299 0.836207 1339 0.836207 1379 0.827586 1419 0.810345

1300 0.83046 1340 0.821839 1380 0.833333 1420 0.841954

1301 0.816092 1341 0.824713 1381 0.827586 1421 0.821839

1302 0.821839 1342 0.827586 1382 0.821839 1422 0.813218

1303 0.813218 1343 0.821839 1383 0.827586 1423 0.821839

1304 0.83046 1344 0.827586 1384 0.824713 1424 0.818966

1305 0.836207 1345 0.83046 1385 0.821839 1425 0.827586

1306 0.816092 1346 0.818966 1386 0.821839 1426 0.821839

1307 0.798851 1347 0.818966 1387 0.816092 1427 0.804598

1308 0.833333 1348 0.818966 1388 0.821839 1428 0.824713

1309 0.827586 1349 0.83046 1389 0.844828 1429 0.821839

1310 0.816092 1350 0.824713 1390 0.818966 1430 0.83046

1311 0.821839 1351 0.824713 1391 0.816092 1431 0.818966

1312 0.83046 1352 0.836207 1392 0.824713 1432 0.833333

1313 0.824713 1353 0.827586 1393 0.836207 1433 0.836207

1314 0.833333 1354 0.807471 1394 0.821839 1434 0.816092

1315 0.818966 1355 0.818966 1395 0.821839 1435 0.816092

1316 0.833333 1356 0.83046 1396 0.83908 1436 0.833333

1317 0.853448 1357 0.818966 1397 0.83908 1437 0.818966

1318 0.818966 1358 0.807471 1398 0.833333 1438 0.818966

1319 0.824713 1359 0.810345 1399 0.824713 1439 0.813218

1320 0.824713 1360 0.824713 1400 0.833333 1440 0.824713

137

1441 0.841954 1481 0.844828 1521 0.836207 1561 0.83046

1442 0.813218 1482 0.827586 1522 0.810345 1562 0.836207

1443 0.827586 1483 0.83908 1523 0.827586 1563 0.83046

1444 0.83046 1484 0.824713 1524 0.83046 1564 0.833333

1445 0.813218 1485 0.83046 1525 0.824713 1565 0.824713

1446 0.816092 1486 0.810345 1526 0.818966 1566 0.816092

1447 0.818966 1487 0.816092 1527 0.824713 1567 0.810345

1448 0.836207 1488 0.833333 1528 0.83046 1568 0.827586

1449 0.83908 1489 0.821839 1529 0.827586 1569 0.827586

1450 0.821839 1490 0.818966 1530 0.821839 1570 0.821839

1451 0.827586 1491 0.813218 1531 0.813218 1571 0.821839

1452 0.83908 1492 0.833333 1532 0.824713 1572 0.821839

1453 0.836207 1493 0.816092 1533 0.83046 1573 0.821839

1454 0.824713 1494 0.810345 1534 0.801724 1574 0.821839

1455 0.824713 1495 0.816092 1535 0.816092 1575 0.827586

1456 0.824713 1496 0.833333 1536 0.816092 1576 0.833333

1457 0.83046 1497 0.821839 1537 0.827586 1577 0.833333

1458 0.83046 1498 0.798851 1538 0.821839 1578 0.804598

1459 0.816092 1499 0.821839 1539 0.824713 1579 0.818966

1460 0.821839 1500 0.836207 1540 0.833333 1580 0.83046

1461 0.83046 1501 0.810345 1541 0.836207 1581 0.821839

1462 0.816092 1502 0.824713 1542 0.813218 1582 0.813218

1463 0.813218 1503 0.824713 1543 0.821839 1583 0.810345

1464 0.821839 1504 0.827586 1544 0.83046 1584 0.827586

1465 0.824713 1505 0.833333 1545 0.827586 1585 0.824713

1466 0.818966 1506 0.821839 1546 0.818966 1586 0.816092

1467 0.827586 1507 0.818966 1547 0.818966 1587 0.824713

1468 0.827586 1508 0.827586 1548 0.827586 1588 0.824713

1469 0.821839 1509 0.83046 1549 0.836207 1589 0.827586

1470 0.818966 1510 0.818966 1550 0.804598 1590 0.821839

1471 0.804598 1511 0.810345 1551 0.83046 1591 0.833333

1472 0.836207 1512 0.833333 1552 0.83046 1592 0.83046

1473 0.83046 1513 0.83046 1553 0.821839 1593 0.83908

1474 0.824713 1514 0.818966 1554 0.824713 1594 0.818966

1475 0.816092 1515 0.818966 1555 0.798851 1595 0.827586

1476 0.833333 1516 0.813218 1556 0.856322 1596 0.833333

1477 0.83046 1517 0.821839 1557 0.827586 1597 0.833333

1478 0.833333 1518 0.813218 1558 0.807471 1598 0.83046

1479 0.83046 1519 0.827586 1559 0.821839 1599 0.818966

1480 0.83046 1520 0.836207 1560 0.827586 1600 0.841954

138

1601 0.827586 1641 0.827586 1681 0.821839 1721 0.83046

1602 0.816092 1642 0.818966 1682 0.818966 1722 0.818966

1603 0.813218 1643 0.816092 1683 0.821839 1723 0.813218

1604 0.83046 1644 0.83046 1684 0.821839 1724 0.827586

1605 0.816092 1645 0.821839 1685 0.836207 1725 0.833333

1606 0.821839 1646 0.827586 1686 0.818966 1726 0.813218

1607 0.818966 1647 0.833333 1687 0.821839 1727 0.813218

1608 0.824713 1648 0.824713 1688 0.836207 1728 0.810345

1609 0.821839 1649 0.83046 1689 0.83046 1729 0.83046

1610 0.816092 1650 0.810345 1690 0.824713 1730 0.824713

1611 0.827586 1651 0.816092 1691 0.804598 1731 0.813218

1612 0.824713 1652 0.836207 1692 0.824713 1732 0.816092

1613 0.83046 1653 0.824713 1693 0.83908 1733 0.821839

1614 0.816092 1654 0.813218 1694 0.807471 1734 0.804598

1615 0.810345 1655 0.816092 1695 0.824713 1735 0.816092

1616 0.824713 1656 0.824713 1696 0.83046 1736 0.836207

1617 0.833333 1657 0.83908 1697 0.833333 1737 0.827586

1618 0.818966 1658 0.813218 1698 0.818966 1738 0.810345

1619 0.827586 1659 0.821839 1699 0.818966 1739 0.818966

1620 0.824713 1660 0.83046 1700 0.827586 1740 0.816092

1621 0.824713 1661 0.821839 1701 0.818966 1741 0.816092

1622 0.818966 1662 0.807471 1702 0.807471 1742 0.821839

1623 0.821839 1663 0.836207 1703 0.818966 1743 0.818966

1624 0.824713 1664 0.827586 1704 0.847701 1744 0.827586

1625 0.83046 1665 0.824713 1705 0.827586 1745 0.813218

1626 0.810345 1666 0.816092 1706 0.818966 1746 0.816092

1627 0.83908 1667 0.827586 1707 0.816092 1747 0.807471

1628 0.818966 1668 0.818966 1708 0.824713 1748 0.836207

1629 0.821839 1669 0.833333 1709 0.816092 1749 0.821839

1630 0.827586 1670 0.821839 1710 0.795977 1750 0.816092

1631 0.816092 1671 0.827586 1711 0.813218 1751 0.813218

1632 0.833333 1672 0.83046 1712 0.833333 1752 0.83046

1633 0.827586 1673 0.83046 1713 0.836207 1753 0.818966

1634 0.810345 1674 0.807471 1714 0.818966 1754 0.818966

1635 0.821839 1675 0.804598 1715 0.824713 1755 0.813218

1636 0.83908 1676 0.824713 1716 0.83046 1756 0.821839

1637 0.821839 1677 0.836207 1717 0.827586 1757 0.821839

1638 0.816092 1678 0.818966 1718 0.821839 1758 0.818966

1639 0.824713 1679 0.821839 1719 0.821839 1759 0.813218

1640 0.833333 1680 0.824713 1720 0.836207 1760 0.818966

139

1761 0.818966 1801 0.827586 1841 0.824713 1881 0.824713

1762 0.824713 1802 0.816092 1842 0.818966 1882 0.821839

1763 0.83046 1803 0.818966 1843 0.821839 1883 0.810345

1764 0.833333 1804 0.833333 1844 0.818966 1884 0.824713

1765 0.816092 1805 0.827586 1845 0.827586 1885 0.833333

1766 0.827586 1806 0.821839 1846 0.821839 1886 0.804598

1767 0.807471 1807 0.821839 1847 0.818966 1887 0.827586

1768 0.824713 1808 0.818966 1848 0.824713 1888 0.824713

1769 0.836207 1809 0.833333 1849 0.824713 1889 0.818966

1770 0.804598 1810 0.816092 1850 0.801724 1890 0.801724

1771 0.816092 1811 0.810345 1851 0.810345 1891 0.818966

1772 0.824713 1812 0.821839 1852 0.818966 1892 0.827586

1773 0.824713 1813 0.818966 1853 0.821839 1893 0.816092

1774 0.816092 1814 0.816092 1854 0.816092 1894 0.816092

1775 0.824713 1815 0.801724 1855 0.818966 1895 0.824713

1776 0.833333 1816 0.821839 1856 0.827586 1896 0.821839

1777 0.810345 1817 0.810345 1857 0.821839 1897 0.833333

1778 0.816092 1818 0.827586 1858 0.810345 1898 0.813218

1779 0.827586 1819 0.818966 1859 0.813218 1899 0.827586

1780 0.818966 1820 0.833333 1860 0.818966 1900 0.818966

1781 0.827586 1821 0.824713 1861 0.83046 1901 0.824713

1782 0.818966 1822 0.824713 1862 0.807471 1902 0.813218

1783 0.827586 1823 0.818966 1863 0.818966 1903 0.813218

1784 0.818966 1824 0.833333 1864 0.818966 1904 0.821839

1785 0.813218 1825 0.824713 1865 0.827586 1905 0.818966

1786 0.824713 1826 0.813218 1866 0.821839 1906 0.818966

1787 0.813218 1827 0.818966 1867 0.816092 1907 0.813218

1788 0.818966 1828 0.83046 1868 0.827586 1908 0.821839

1789 0.833333 1829 0.824713 1869 0.824713 1909 0.818966

1790 0.807471 1830 0.804598 1870 0.807471 1910 0.807471

1791 0.810345 1831 0.833333 1871 0.818966 1911 0.824713

1792 0.833333 1832 0.824713 1872 0.847701 1912 0.833333

1793 0.83046 1833 0.824713 1873 0.813218 1913 0.836207

1794 0.810345 1834 0.813218 1874 0.807471 1914 0.816092

1795 0.813218 1835 0.813218 1875 0.813218 1915 0.813218

1796 0.816092 1836 0.821839 1876 0.827586 1916 0.833333

1797 0.827586 1837 0.836207 1877 0.816092 1917 0.827586

1798 0.810345 1838 0.807471 1878 0.821839 1918 0.818966

1799 0.816092 1839 0.818966 1879 0.807471 1919 0.827586

1800 0.824713 1840 0.813218 1880 0.824713 1920 0.807471

140

1921 0.824713 1961 0.813218 2001 0.824713 2041 0.876437

1922 0.810345 1962 0.801724 2002 0.821839 2042 0.859195

1923 0.824713 1963 0.818966 2003 0.827586 2043 0.864943

1924 0.824713 1964 0.807471 2004 0.83046 2044 0.87069

1925 0.821839 1965 0.833333 2005 0.83046 2045 0.867816

1926 0.824713 1966 0.804598 2006 0.816092 2046 0.856322

1927 0.824713 1967 0.818966 2007 0.816092 2047 0.887931

1928 0.83046 1968 0.824713 2008 0.818966

1929 0.833333 1969 0.827586 2009 0.824713

1930 0.795977 1970 0.821839 2010 0.821839

1931 0.798851 1971 0.824713 2011 0.83046

1932 0.824713 1972 0.833333 2012 0.83908

1933 0.827586 1973 0.821839 2013 0.833333

1934 0.795977 1974 0.810345 2014 0.83046

1935 0.810345 1975 0.821839 2015 0.827586

1936 0.818966 1976 0.813218 2016 0.818966

1937 0.83046 1977 0.827586 2017 0.833333

1938 0.821839 1978 0.818966 2018 0.816092

1939 0.821839 1979 0.83046 2019 0.816092

1940 0.827586 1980 0.824713 2020 0.816092

1941 0.827586 1981 0.824713 2021 0.841954

1942 0.804598 1982 0.807471 2022 0.821839

1943 0.807471 1983 0.818966 2023 0.827586

1944 0.816092 1984 0.813218 2024 0.827586

1945 0.833333 1985 0.824713 2025 0.83046

1946 0.827586 1986 0.816092 2026 0.821839

1947 0.824713 1987 0.813218 2027 0.827586

1948 0.827586 1988 0.810345 2028 0.824713

1949 0.824713 1989 0.833333 2029 0.83908

1950 0.816092 1990 0.813218 2030 0.804598

1951 0.813218 1991 0.804598 2031 0.824713

1952 0.827586 1992 0.83046 2032 0.87069

1953 0.827586 1993 0.821839 2033 0.876437

1954 0.816092 1994 0.810345 2034 0.864943

1955 0.804598 1995 0.833333 2035 0.876437

1956 0.821839 1996 0.813218 2036 0.873563

1957 0.827586 1997 0.821839 2037 0.873563

1958 0.816092 1998 0.801724 2038 0.876437

1959 0.818966 1999 0.818966 2039 0.873563

1960 0.836207 2000 0.824713 2040 0.867816

141

APPENDIX B

Block Failure Data after Read1 Test with Programming Time Test moved in Standard

Test Flow In the table presented below “X” represents block number (0-2047) and “Y” represents the normalized count of parts with particular block fail.

X Y X Y X Y X Y

0 0.886207 41 0.833333 81 0.841954 121 0.821839

1 0.873678 42 0.824713 82 0.818966 122 0.818966

2 0.847701 43 0.833333 83 0.824713 123 0.816092

3 0.833333 44 0.833333 84 0.83046 124 0.818966

4 0.83908 45 0.83046 85 0.833333 125 0.816092

5 0.856207 46 0.821839 86 0.821839 126 0.818966

6 0.853448 47 0.818966 87 0.836207 127 0.816092

7 0.857701 48 0.824713 88 0.833333 128 0.827586

8 0.866207 49 0.833333 89 0.83908 129 0.810345

9 0.83908 50 0.836207 90 0.816092 130 0.818966

10 0.841954 51 0.827586 91 0.83046 131 0.813218

11 0.836207 52 0.83908 92 0.821839 132 0.818966

12 0.816092 53 0.83908 93 0.83046 133 0.813218

13 0.844828 54 0.816092 94 0.813218 134 0.821839

14 0.844828 55 0.83046 95 0.818966 135 0.824713

15 0.893678 56 0.841954 96 0.818966 136 0.821839

16 0.847701 57 0.844828 97 0.821839 137 0.824713

17 0.833333 58 0.827586 98 0.827586 138 0.813218

18 0.83908 59 0.824713 99 0.824713 139 0.810345

19 0.836207 60 0.83908 100 0.821839 140 0.821839

20 0.853448 61 0.841954 101 0.83046 141 0.807471

21 0.847701 62 0.816092 102 0.813218 142 0.807471

22 0.836207 63 0.833333 103 0.836207 143 0.824713

23 0.83908 64 0.827586 104 0.821839 144 0.804598

24 0.841954 65 0.836207 105 0.83908 145 0.813218

25 0.836207 66 0.824713 106 0.807471 146 0.810345

26 0.816092 67 0.824713 107 0.821839 147 0.801724

27 0.844828 68 0.83908 108 0.824713 148 0.824713

28 0.83046 69 0.83046 109 0.818966 149 0.813218

29 0.844828 70 0.827586 110 0.813218 150 0.807471

30 0.824713 71 0.821839 111 0.821839 151 0.816092

31 0.833333 72 0.841954 112 0.824713 152 0.83046

32 0.841954 73 0.83908 113 0.83046 153 0.816092

33 0.83908 74 0.827586 114 0.821839 154 0.824713

34 0.836207 75 0.821839 115 0.818966 155 0.804598

35 0.824713 76 0.827586 116 0.821839 156 0.818966

36 0.841954 77 0.83046 117 0.821839 157 0.824713

37 0.824713 78 0.818966 118 0.816092 158 0.816092

38 0.824713 79 0.824713 119 0.810345 159 0.818966

39 0.824713 80 0.83046 120 0.841954 160 0.818966

142

40 0.83908

X Y X Y X Y X Y

161 0.821839 201 0.821839 241 0.810345 281 0.827586

162 0.810345 202 0.795977 242 0.795977 282 0.821839

163 0.821839 203 0.821839 243 0.810345 283 0.804598

164 0.833333 204 0.813218 244 0.813218 284 0.824713

165 0.827586 205 0.818966 245 0.816092 285 0.83908

166 0.816092 206 0.810345 246 0.810345 286 0.810345

167 0.810345 207 0.813218 247 0.807471 287 0.810345

168 0.821839 208 0.816092 248 0.810345 288 0.818966

169 0.821839 209 0.821839 249 0.816092 289 0.810345

170 0.810345 210 0.810345 250 0.798851 290 0.807471

171 0.801724 211 0.804598 251 0.816092 291 0.816092

172 0.824713 212 0.810345 252 0.807471 292 0.824713

173 0.833333 213 0.824713 253 0.813218 293 0.821839

174 0.821839 214 0.807471 254 0.801724 294 0.813218

175 0.818966 215 0.813218 255 0.807471 295 0.807471

176 0.827586 216 0.827586 256 0.83046 296 0.833333

177 0.807471 217 0.824713 257 0.818966 297 0.816092

178 0.813218 218 0.807471 258 0.804598 298 0.810345

179 0.818966 219 0.807471 259 0.813218 299 0.818966

180 0.827586 220 0.804598 260 0.816092 300 0.83046

181 0.827586 221 0.836207 261 0.83046 301 0.816092

182 0.810345 222 0.793103 262 0.807471 302 0.816092

183 0.813218 223 0.807471 263 0.813218 303 0.804598

184 0.827586 224 0.813218 264 0.813218 304 0.83046

185 0.824713 225 0.810345 265 0.816092 305 0.818966

186 0.813218 226 0.813218 266 0.801724 306 0.818966

187 0.807471 227 0.810345 267 0.813218 307 0.795977

188 0.824713 228 0.821839 268 0.810345 308 0.810345

189 0.813218 229 0.821839 269 0.807471 309 0.813218

190 0.807471 230 0.801724 270 0.816092 310 0.804598

191 0.801724 231 0.813218 271 0.804598 311 0.813218

192 0.818966 232 0.816092 272 0.813218 312 0.83046

193 0.824713 233 0.813218 273 0.816092 313 0.824713

194 0.813218 234 0.810345 274 0.813218 314 0.801724

195 0.804598 235 0.810345 275 0.804598 315 0.798851

196 0.83046 236 0.813218 276 0.83046 316 0.801724

197 0.821839 237 0.83046 277 0.810345 317 0.816092

198 0.801724 238 0.798851 278 0.810345 318 0.810345

199 0.801724 239 0.824713 279 0.818966 319 0.818966

200 0.824713 240 0.818966 280 0.824713 320 0.816092

143

X Y X Y X Y X Y

321 0.827586 361 0.824713 401 0.824713 441 0.821839

322 0.798851 362 0.818966 402 0.801724 442 0.816092

323 0.816092 363 0.816092 403 0.813218 443 0.798851

324 0.816092 364 0.827586 404 0.833333 444 0.824713

325 0.818966 365 0.816092 405 0.83908 445 0.816092

326 0.804598 366 0.807471 406 0.821839 446 0.804598

327 0.818966 367 0.818966 407 0.813218 447 0.804598

328 0.833333 368 0.824713 408 0.818966 448 0.816092

329 0.821839 369 0.816092 409 0.818966 449 0.83908

330 0.816092 370 0.804598 410 0.810345 450 0.810345

331 0.813218 371 0.818966 411 0.818966 451 0.813218

332 0.816092 372 0.821839 412 0.821839 452 0.816092

333 0.827586 373 0.821839 413 0.833333 453 0.824713

334 0.801724 374 0.813218 414 0.801724 454 0.816092

335 0.813218 375 0.816092 415 0.818966 455 0.816092

336 0.821839 376 0.816092 416 0.824713 456 0.816092

337 0.818966 377 0.813218 417 0.821839 457 0.827586

338 0.810345 378 0.818966 418 0.818966 458 0.824713

339 0.810345 379 0.816092 419 0.810345 459 0.813218

340 0.813218 380 0.813218 420 0.821839 460 0.813218

341 0.821839 381 0.83046 421 0.821839 461 0.816092

342 0.804598 382 0.821839 422 0.816092 462 0.813218

343 0.824713 383 0.813218 423 0.824713 463 0.816092

344 0.827586 384 0.824713 424 0.824713 464 0.83046

345 0.824713 385 0.827586 425 0.821839 465 0.818966

346 0.821839 386 0.807471 426 0.813218 466 0.816092

347 0.801724 387 0.813218 427 0.816092 467 0.813218

348 0.813218 388 0.813218 428 0.816092 468 0.816092

349 0.824713 389 0.810345 429 0.836207 469 0.824713

350 0.804598 390 0.813218 430 0.807471 470 0.813218

351 0.807471 391 0.813218 431 0.821839 471 0.821839

352 0.821839 392 0.821839 432 0.818966 472 0.836207

353 0.824713 393 0.821839 433 0.813218 473 0.810345

354 0.807471 394 0.807471 434 0.801724 474 0.816092

355 0.818966 395 0.804598 435 0.821839 475 0.804598

356 0.818966 396 0.816092 436 0.821839 476 0.816092

357 0.824713 397 0.807471 437 0.836207 477 0.824713

358 0.810345 398 0.807471 438 0.813218 478 0.804598

359 0.807471 399 0.824713 439 0.813218 479 0.824713

360 0.824713 400 0.827586 440 0.824713 480 0.821839

144

X Y X Y X Y X Y

481 0.83908 521 0.827586 561 0.824713 601 0.827586

482 0.818966 522 0.816092 562 0.818966 602 0.810345

483 0.824713 523 0.813218 563 0.818966 603 0.818966

484 0.827586 524 0.821839 564 0.818966 604 0.83046

485 0.821839 525 0.821839 565 0.821839 605 0.818966

486 0.824713 526 0.813218 566 0.807471 606 0.798851

487 0.810345 527 0.816092 567 0.810345 607 0.824713

488 0.836207 528 0.824713 568 0.824713 608 0.824713

489 0.83908 529 0.821839 569 0.821839 609 0.827586

490 0.798851 530 0.818966 570 0.813218 610 0.818966

491 0.810345 531 0.824713 571 0.818966 611 0.810345

492 0.813218 532 0.813218 572 0.821839 612 0.827586

493 0.833333 533 0.818966 573 0.83046 613 0.833333

494 0.813218 534 0.810345 574 0.824713 614 0.818966

495 0.807471 535 0.83046 575 0.818966 615 0.821839

496 0.824713 536 0.827586 576 0.83046 616 0.827586

497 0.827586 537 0.827586 577 0.821839 617 0.818966

498 0.807471 538 0.816092 578 0.816092 618 0.810345

499 0.801724 539 0.816092 579 0.824713 619 0.824713

500 0.821839 540 0.824713 580 0.827586 620 0.818966

501 0.818966 541 0.818966 581 0.821839 621 0.824713

502 0.810345 542 0.807471 582 0.813218 622 0.801724

503 0.818966 543 0.821839 583 0.827586 623 0.816092

504 0.824713 544 0.821839 584 0.827586 624 0.83046

505 0.821839 545 0.833333 585 0.833333 625 0.821839

506 0.801724 546 0.807471 586 0.816092 626 0.816092

507 0.810345 547 0.824713 587 0.818966 627 0.818966

508 0.827586 548 0.816092 588 0.833333 628 0.83046

509 0.807471 549 0.821839 589 0.83046 629 0.824713

510 0.807471 550 0.821839 590 0.804598 630 0.798851

511 0.816092 551 0.818966 591 0.804598 631 0.818966

512 0.824713 552 0.818966 592 0.821839 632 0.816092

513 0.83908 553 0.816092 593 0.818966 633 0.821839

514 0.813218 554 0.816092 594 0.821839 634 0.807471

515 0.824713 555 0.813218 595 0.813218 635 0.813218

516 0.827586 556 0.824713 596 0.810345 636 0.821839

517 0.816092 557 0.827586 597 0.83046 637 0.83046

518 0.807471 558 0.821839 598 0.816092 638 0.801724

519 0.813218 559 0.824713 599 0.813218 639 0.810345

520 0.821839 560 0.818966 600 0.83046 640 0.818966

145

X Y X Y X Y X Y

641 0.821839 681 0.821839 721 0.821839 761 0.824713

642 0.801724 682 0.807471 722 0.816092 762 0.810345

643 0.807471 683 0.836207 723 0.821839 763 0.821839

644 0.83046 684 0.827586 724 0.816092 764 0.827586

645 0.827586 685 0.824713 725 0.824713 765 0.821839

646 0.801724 686 0.807471 726 0.824713 766 0.807471

647 0.810345 687 0.824713 727 0.824713 767 0.821839

648 0.813218 688 0.827586 728 0.816092 768 0.821839

649 0.818966 689 0.824713 729 0.821839 769 0.818966

650 0.807471 690 0.813218 730 0.804598 770 0.810345

651 0.807471 691 0.804598 731 0.818966 771 0.818966

652 0.818966 692 0.818966 732 0.818966 772 0.83046

653 0.821839 693 0.827586 733 0.821839 773 0.816092

654 0.810345 694 0.810345 734 0.813218 774 0.804598

655 0.818966 695 0.821839 735 0.818966 775 0.813218

656 0.827586 696 0.827586 736 0.818966 776 0.824713

657 0.827586 697 0.83046 737 0.824713 777 0.83046

658 0.810345 698 0.810345 738 0.818966 778 0.813218

659 0.804598 699 0.804598 739 0.827586 779 0.813218

660 0.83046 700 0.810345 740 0.827586 780 0.83908

661 0.833333 701 0.821839 741 0.821839 781 0.813218

662 0.807471 702 0.804598 742 0.816092 782 0.821839

663 0.807471 703 0.816092 743 0.810345 783 0.818966

664 0.821839 704 0.821839 744 0.83046 784 0.83046

665 0.836207 705 0.824713 745 0.818966 785 0.83046

666 0.818966 706 0.818966 746 0.804598 786 0.816092

667 0.816092 707 0.818966 747 0.818966 787 0.83046

668 0.813218 708 0.83046 748 0.836207 788 0.83908

669 0.824713 709 0.827586 749 0.827586 789 0.827586

670 0.818966 710 0.810345 750 0.813218 790 0.816092

671 0.836207 711 0.816092 751 0.816092 791 0.810345

672 0.824713 712 0.841954 752 0.824713 792 0.827586

673 0.827586 713 0.816092 753 0.818966 793 0.816092

674 0.821839 714 0.824713 754 0.807471 794 0.821839

675 0.807471 715 0.824713 755 0.827586 795 0.83046

676 0.810345 716 0.827586 756 0.83908 796 0.83046

677 0.827586 717 0.824713 757 0.816092 797 0.821839

678 0.813218 718 0.816092 758 0.810345 798 0.801724

679 0.810345 719 0.821839 759 0.816092 799 0.818966

680 0.83046 720 0.816092 760 0.821839 800 0.821839

146

X Y X Y X Y X Y

801 0.833333 841 0.824713 881 0.83908 921 0.833333

802 0.821839 842 0.818966 882 0.816092 922 0.821839

803 0.821839 843 0.810345 883 0.818966 923 0.810345

804 0.827586 844 0.824713 884 0.827586 924 0.824713

805 0.818966 845 0.821839 885 0.827586 925 0.827586

806 0.818966 846 0.813218 886 0.807471 926 0.821839

807 0.813218 847 0.824713 887 0.83046 927 0.821839

808 0.833333 848 0.824713 888 0.824713 928 0.83046

809 0.824713 849 0.818966 889 0.83046 929 0.83908

810 0.821839 850 0.79023 890 0.821839 930 0.804598

811 0.816092 851 0.821839 891 0.818966 931 0.810345

812 0.827586 852 0.83046 892 0.818966 932 0.833333

813 0.813218 853 0.827586 893 0.844828 933 0.827586

814 0.821839 854 0.818966 894 0.810345 934 0.813218

815 0.816092 855 0.813218 895 0.818966 935 0.818966

816 0.833333 856 0.827586 896 0.833333 936 0.827586

817 0.83046 857 0.824713 897 0.827586 937 0.818966

818 0.813218 858 0.818966 898 0.821839 938 0.818966

819 0.818966 859 0.818966 899 0.827586 939 0.813218

820 0.83046 860 0.824713 900 0.83046 940 0.827586

821 0.827586 861 0.807471 901 0.83046 941 0.824713

822 0.813218 862 0.813218 902 0.821839 942 0.818966

823 0.804598 863 0.810345 903 0.83046 943 0.827586

824 0.827586 864 0.821839 904 0.83046 944 0.833333

825 0.816092 865 0.846207 905 0.836207 945 0.824713

826 0.816092 866 0.821839 906 0.818966 946 0.821839

827 0.813218 867 0.813218 907 0.813218 947 0.821839

828 0.824713 868 0.827586 908 0.827586 948 0.83908

829 0.827586 869 0.83046 909 0.841954 949 0.818966

830 0.810345 870 0.807471 910 0.824713 950 0.824713

831 0.824713 871 0.824713 911 0.818966 951 0.827586

832 0.824713 872 0.827586 912 0.821839 952 0.824713

833 0.83046 873 0.833333 913 0.841954 953 0.833333

834 0.818966 874 0.807471 914 0.818966 954 0.818966

835 0.818966 875 0.813218 915 0.827586 955 0.827586

836 0.827586 876 0.827586 916 0.824713 956 0.824713

837 0.824713 877 0.821839 917 0.827586 957 0.818966

838 0.824713 878 0.813218 918 0.804598 958 0.824713

839 0.810345 879 0.804598 919 0.813218 959 0.813218

840 0.827586 880 0.816092 920 0.810345 960 0.827586

147

X Y X Y X Y X Y

961 0.827586 1001 0.827586 1041 0.821839 1081 0.83908

962 0.818966 1002 0.816092 1042 0.83046 1082 0.813218

963 0.816092 1003 0.843333 1043 0.836207 1083 0.824713

964 0.833333 1004 0.816092 1044 0.821839 1084 0.821839

965 0.821839 1005 0.816092 1045 0.821839 1085 0.813218

966 0.833333 1006 0.816092 1046 0.833333 1086 0.818966

967 0.821839 1007 0.833333 1047 0.83908 1087 0.818966

968 0.83046 1008 0.813218 1048 0.804598 1088 0.836207

969 0.827586 1009 0.827586 1049 0.824713 1089 0.827586

970 0.83046 1010 0.833333 1050 0.836207 1090 0.821839

971 0.807471 1011 0.836207 1051 0.83908 1091 0.816092

972 0.827586 1012 0.816092 1052 0.824713 1092 0.827586

973 0.824713 1013 0.827586 1053 0.818966 1093 0.83046

974 0.818966 1014 0.836207 1054 0.824713 1094 0.824713

975 0.818966 1015 0.824713 1055 0.821839 1095 0.821839

976 0.81069 1016 0.818966 1056 0.818966 1096 0.827586

977 0.816092 1017 0.824713 1057 0.824713 1097 0.833333

978 0.824713 1018 0.821839 1058 0.83046 1098 0.807471

979 0.836207 1019 0.836207 1059 0.836207 1099 0.827586

980 0.810345 1020 0.821839 1060 0.824713 1100 0.816092

981 0.816092 1021 0.827586 1061 0.851839 1101 0.833333

982 0.827586 1022 0.824713 1062 0.821839 1102 0.816092

983 0.83908 1023 0.821839 1063 0.818966 1103 0.816092

984 0.813218 1024 0.816092 1064 0.818966 1104 0.816092

985 0.824713 1025 0.818966 1065 0.824713 1105 0.833333

986 0.821839 1026 0.836207 1066 0.83046 1106 0.813218

987 0.813218 1027 0.833333 1067 0.83046 1107 0.827586

988 0.818966 1028 0.810345 1068 0.821839 1108 0.833333

989 0.818966 1029 0.818966 1069 0.824713 1109 0.836207

990 0.836207 1030 0.827586 1070 0.827586 1110 0.816092

991 0.827586 1031 0.824713 1071 0.836207 1111 0.827586

992 0.821839 1032 0.807471 1072 0.818966 1112 0.836207

993 0.816092 1033 0.821839 1073 0.821839 1113 0.824713

994 0.827586 1034 0.83046 1074 0.824713 1114 0.818966

995 0.83046 1035 0.841954 1075 0.816092 1115 0.824713

996 0.824713 1036 0.813218 1076 0.824713 1116 0.821839

997 0.821839 1037 0.83046 1077 0.836207 1117 0.836207

998 0.827586 1038 0.844828 1078 0.810345 1118 0.821839

999 0.833333 1039 0.824713 1079 0.816092 1119 0.827586

1000 0.807471 1040 0.824713 1080 0.827586 1120 0.824713

148

X Y X Y X Y X Y

1121 0.821839 1161 0.818966 1201 0.827586 1241 0.836207

1122 0.816092 1162 0.818966 1202 0.813218 1242 0.813218

1123 0.818966 1163 0.824713 1203 0.821839 1243 0.833333

1124 0.836207 1164 0.83046 1204 0.827586 1244 0.83908

1125 0.833333 1165 0.83046 1205 0.836207 1245 0.833333

1126 0.810345 1166 0.821839 1206 0.818966 1246 0.810345

1127 0.818966 1167 0.824713 1207 0.824713 1247 0.824713

1128 0.827586 1168 0.827586 1208 0.833333 1248 0.821839

1129 0.824713 1169 0.836207 1209 0.833333 1249 0.821839

1130 0.807471 1170 0.818966 1210 0.813218 1250 0.827586

1131 0.821839 1171 0.821839 1211 0.816092 1251 0.827586

1132 0.83046 1172 0.83908 1212 0.821839 1252 0.841954

1133 0.841954 1173 0.833333 1213 0.833333 1253 0.856322

1134 0.813218 1174 0.836207 1214 0.827586 1254 0.827586

1135 0.83046 1175 0.827586 1215 0.833333 1255 0.810345

1136 0.844828 1176 0.827586 1216 0.83046 1256 0.824713

1137 0.824713 1177 0.833333 1217 0.827586 1257 0.827586

1138 0.824713 1178 0.821839 1218 0.804598 1258 0.816092

1139 0.821839 1179 0.827586 1219 0.827586 1259 0.821839

1140 0.83046 1180 0.844828 1220 0.83046 1260 0.821839

1141 0.836207 1181 0.844828 1221 0.833333 1261 0.821839

1142 0.821839 1182 0.818966 1222 0.813218 1262 0.827586

1143 0.821839 1183 0.816092 1223 0.818966 1263 0.813218

1144 0.833333 1184 0.83908 1224 0.833333 1264 0.821839

1145 0.83908 1185 0.824713 1225 0.824713 1265 0.83046

1146 0.804598 1186 0.821839 1226 0.816092 1266 0.833333

1147 0.824713 1187 0.821839 1227 0.818966 1267 0.818966

1148 0.836207 1188 0.833333 1228 0.818966 1268 0.833333

1149 0.83908 1189 0.813218 1229 0.841954 1269 0.83046

1150 0.824713 1190 0.807471 1230 0.810345 1270 0.810345

1151 0.818966 1191 0.827586 1231 0.816092 1271 0.824713

1152 0.824713 1192 0.841954 1232 0.824713 1272 0.83908

1153 0.821839 1193 0.827586 1233 0.821839 1273 0.821839

1154 0.818966 1194 0.813218 1234 0.807471 1274 0.827586

1155 0.824713 1195 0.818966 1235 0.83046 1275 0.816092

1156 0.83046 1196 0.821839 1236 0.83046 1276 0.836207

1157 0.836207 1197 0.83908 1237 0.83046 1277 0.816092

1158 0.824713 1198 0.818966 1238 0.821839 1278 0.818966

1159 0.821839 1199 0.807471 1239 0.836207 1279 0.821839

1160 0.821839 1200 0.836207 1240 0.816092 1280 0.833333

149

X Y X Y X Y X Y

1281 0.827586 1321 0.824713 1361 0.818966 1401 0.818966

1282 0.804598 1322 0.818966 1362 0.816092 1402 0.824713

1283 0.827586 1323 0.824713 1363 0.821839 1403 0.807471

1284 0.833333 1324 0.827586 1364 0.827586 1404 0.824713

1285 0.833333 1325 0.824713 1365 0.833333 1405 0.818966

1286 0.813218 1326 0.813218 1366 0.816092 1406 0.804598

1287 0.824713 1327 0.810345 1367 0.807471 1407 0.810345

1288 0.841954 1328 0.827586 1368 0.833333 1408 0.83908

1289 0.824713 1329 0.841954 1369 0.836207 1409 0.827586

1290 0.816092 1330 0.821839 1370 0.816092 1410 0.813218

1291 0.83046 1331 0.83046 1371 0.816092 1411 0.818966

1292 0.833333 1332 0.83046 1372 0.821839 1412 0.836207

1293 0.810345 1333 0.821839 1373 0.824713 1413 0.833333

1294 0.813218 1334 0.821839 1374 0.821839 1414 0.821839

1295 0.810345 1335 0.824713 1375 0.807471 1415 0.816092

1296 0.818966 1336 0.836207 1376 0.836207 1416 0.824713

1297 0.83046 1337 0.818966 1377 0.83046 1417 0.824713

1298 0.818966 1338 0.821839 1378 0.818966 1418 0.804598

1299 0.836207 1339 0.836207 1379 0.827586 1419 0.810345

1300 0.83046 1340 0.821839 1380 0.833333 1420 0.841954

1301 0.816092 1341 0.824713 1381 0.827586 1421 0.821839

1302 0.821839 1342 0.827586 1382 0.821839 1422 0.813218

1303 0.813218 1343 0.821839 1383 0.827586 1423 0.821839

1304 0.83046 1344 0.827586 1384 0.824713 1424 0.818966

1305 0.836207 1345 0.83046 1385 0.821839 1425 0.827586

1306 0.816092 1346 0.818966 1386 0.821839 1426 0.821839

1307 0.798851 1347 0.818966 1387 0.816092 1427 0.804598

1308 0.833333 1348 0.818966 1388 0.821839 1428 0.824713

1309 0.827586 1349 0.83046 1389 0.844828 1429 0.821839

1310 0.816092 1350 0.824713 1390 0.818966 1430 0.83046

1311 0.821839 1351 0.824713 1391 0.816092 1431 0.818966

1312 0.83046 1352 0.836207 1392 0.824713 1432 0.833333

1313 0.824713 1353 0.827586 1393 0.836207 1433 0.836207

1314 0.833333 1354 0.807471 1394 0.821839 1434 0.816092

1315 0.818966 1355 0.818966 1395 0.821839 1435 0.816092

1316 0.833333 1356 0.83046 1396 0.83908 1436 0.833333

1317 0.853448 1357 0.818966 1397 0.83908 1437 0.818966

1318 0.818966 1358 0.807471 1398 0.833333 1438 0.818966

1319 0.824713 1359 0.810345 1399 0.824713 1439 0.813218

1320 0.824713 1360 0.824713 1400 0.833333 1440 0.824713

150

X Y X Y X Y X Y

1441 0.841954 1481 0.844828 1521 0.836207 1561 0.83046

1442 0.813218 1482 0.827586 1522 0.810345 1562 0.836207

1443 0.827586 1483 0.83908 1523 0.827586 1563 0.83046

1444 0.83046 1484 0.824713 1524 0.83046 1564 0.833333

1445 0.813218 1485 0.83046 1525 0.824713 1565 0.824713

1446 0.816092 1486 0.810345 1526 0.818966 1566 0.816092

1447 0.818966 1487 0.816092 1527 0.824713 1567 0.810345

1448 0.836207 1488 0.833333 1528 0.83046 1568 0.827586

1449 0.83908 1489 0.821839 1529 0.827586 1569 0.827586

1450 0.821839 1490 0.818966 1530 0.821839 1570 0.821839

1451 0.827586 1491 0.813218 1531 0.813218 1571 0.821839

1452 0.83908 1492 0.833333 1532 0.824713 1572 0.821839

1453 0.836207 1493 0.816092 1533 0.83046 1573 0.821839

1454 0.824713 1494 0.810345 1534 0.801724 1574 0.821839

1455 0.824713 1495 0.816092 1535 0.816092 1575 0.827586

1456 0.824713 1496 0.833333 1536 0.816092 1576 0.833333

1457 0.83046 1497 0.821839 1537 0.827586 1577 0.833333

1458 0.83046 1498 0.798851 1538 0.821839 1578 0.804598

1459 0.816092 1499 0.821839 1539 0.824713 1579 0.818966

1460 0.821839 1500 0.836207 1540 0.833333 1580 0.83046

1461 0.83046 1501 0.810345 1541 0.836207 1581 0.821839

1462 0.816092 1502 0.824713 1542 0.813218 1582 0.813218

1463 0.813218 1503 0.824713 1543 0.821839 1583 0.810345

1464 0.821839 1504 0.827586 1544 0.83046 1584 0.827586

1465 0.824713 1505 0.833333 1545 0.827586 1585 0.824713

1466 0.818966 1506 0.821839 1546 0.818966 1586 0.816092

1467 0.827586 1507 0.818966 1547 0.818966 1587 0.824713

1468 0.827586 1508 0.827586 1548 0.827586 1588 0.824713

1469 0.821839 1509 0.83046 1549 0.836207 1589 0.827586

1470 0.818966 1510 0.818966 1550 0.804598 1590 0.821839

1471 0.804598 1511 0.810345 1551 0.83046 1591 0.833333

1472 0.836207 1512 0.833333 1552 0.83046 1592 0.83046

1473 0.83046 1513 0.83046 1553 0.821839 1593 0.83908

1474 0.824713 1514 0.818966 1554 0.824713 1594 0.818966

1475 0.816092 1515 0.818966 1555 0.798851 1595 0.827586

1476 0.833333 1516 0.813218 1556 0.856322 1596 0.833333

1477 0.83046 1517 0.821839 1557 0.827586 1597 0.833333

1478 0.833333 1518 0.813218 1558 0.807471 1598 0.83046

1479 0.83046 1519 0.827586 1559 0.821839 1599 0.818966

1480 0.83046 1520 0.836207 1560 0.827586 1600 0.841954

151

X Y X Y X Y X Y

1601 0.827586 1641 0.827586 1681 0.821839 1721 0.83046

1602 0.816092 1642 0.818966 1682 0.818966 1722 0.818966

1603 0.813218 1643 0.816092 1683 0.821839 1723 0.813218

1604 0.83046 1644 0.83046 1684 0.821839 1724 0.827586

1605 0.816092 1645 0.821839 1685 0.836207 1725 0.833333

1606 0.821839 1646 0.827586 1686 0.818966 1726 0.813218

1607 0.818966 1647 0.833333 1687 0.821839 1727 0.813218

1608 0.824713 1648 0.824713 1688 0.836207 1728 0.810345

1609 0.821839 1649 0.83046 1689 0.83046 1729 0.83046

1610 0.816092 1650 0.810345 1690 0.824713 1730 0.824713

1611 0.827586 1651 0.816092 1691 0.804598 1731 0.813218

1612 0.824713 1652 0.836207 1692 0.824713 1732 0.816092

1613 0.83046 1653 0.824713 1693 0.83908 1733 0.821839

1614 0.816092 1654 0.813218 1694 0.807471 1734 0.804598

1615 0.810345 1655 0.816092 1695 0.824713 1735 0.816092

1616 0.824713 1656 0.824713 1696 0.83046 1736 0.836207

1617 0.833333 1657 0.83908 1697 0.833333 1737 0.827586

1618 0.818966 1658 0.813218 1698 0.818966 1738 0.810345

1619 0.827586 1659 0.821839 1699 0.818966 1739 0.818966

1620 0.824713 1660 0.83046 1700 0.827586 1740 0.816092

1621 0.824713 1661 0.821839 1701 0.818966 1741 0.816092

1622 0.818966 1662 0.807471 1702 0.807471 1742 0.821839

1623 0.821839 1663 0.836207 1703 0.818966 1743 0.818966

1624 0.824713 1664 0.827586 1704 0.847701 1744 0.827586

1625 0.83046 1665 0.824713 1705 0.827586 1745 0.813218

1626 0.810345 1666 0.816092 1706 0.818966 1746 0.816092

1627 0.83908 1667 0.827586 1707 0.816092 1747 0.807471

1628 0.818966 1668 0.818966 1708 0.824713 1748 0.836207

1629 0.821839 1669 0.833333 1709 0.816092 1749 0.821839

1630 0.827586 1670 0.821839 1710 0.795977 1750 0.816092

1631 0.816092 1671 0.827586 1711 0.813218 1751 0.813218

1632 0.833333 1672 0.83046 1712 0.833333 1752 0.83046

1633 0.827586 1673 0.83046 1713 0.836207 1753 0.818966

1634 0.810345 1674 0.807471 1714 0.818966 1754 0.818966

1635 0.821839 1675 0.804598 1715 0.824713 1755 0.813218

1636 0.83908 1676 0.824713 1716 0.83046 1756 0.821839

1637 0.821839 1677 0.836207 1717 0.827586 1757 0.821839

1638 0.816092 1678 0.818966 1718 0.821839 1758 0.818966

1639 0.824713 1679 0.821839 1719 0.821839 1759 0.813218

1640 0.833333 1680 0.824713 1720 0.836207 1760 0.818966

152

X Y X Y X Y X Y

1761 0.818966 1801 0.827586 1841 0.824713 1881 0.824713

1762 0.824713 1802 0.816092 1842 0.818966 1882 0.821839

1763 0.83046 1803 0.818966 1843 0.821839 1883 0.810345

1764 0.833333 1804 0.833333 1844 0.818966 1884 0.824713

1765 0.816092 1805 0.827586 1845 0.827586 1885 0.833333

1766 0.827586 1806 0.821839 1846 0.821839 1886 0.804598

1767 0.807471 1807 0.821839 1847 0.818966 1887 0.827586

1768 0.824713 1808 0.818966 1848 0.824713 1888 0.824713

1769 0.836207 1809 0.833333 1849 0.824713 1889 0.818966

1770 0.804598 1810 0.816092 1850 0.801724 1890 0.801724

1771 0.816092 1811 0.810345 1851 0.810345 1891 0.818966

1772 0.824713 1812 0.821839 1852 0.818966 1892 0.827586

1773 0.824713 1813 0.818966 1853 0.821839 1893 0.816092

1774 0.816092 1814 0.816092 1854 0.816092 1894 0.816092

1775 0.824713 1815 0.801724 1855 0.818966 1895 0.824713

1776 0.833333 1816 0.821839 1856 0.827586 1896 0.821839

1777 0.810345 1817 0.810345 1857 0.821839 1897 0.833333

1778 0.816092 1818 0.827586 1858 0.810345 1898 0.813218

1779 0.827586 1819 0.818966 1859 0.813218 1899 0.827586

1780 0.818966 1820 0.833333 1860 0.818966 1900 0.818966

1781 0.827586 1821 0.824713 1861 0.83046 1901 0.824713

1782 0.818966 1822 0.824713 1862 0.807471 1902 0.813218

1783 0.827586 1823 0.818966 1863 0.818966 1903 0.813218

1784 0.818966 1824 0.833333 1864 0.818966 1904 0.821839

1785 0.813218 1825 0.824713 1865 0.827586 1905 0.818966

1786 0.824713 1826 0.813218 1866 0.821839 1906 0.818966

1787 0.813218 1827 0.818966 1867 0.816092 1907 0.813218

1788 0.818966 1828 0.83046 1868 0.827586 1908 0.821839

1789 0.833333 1829 0.824713 1869 0.824713 1909 0.818966

1790 0.807471 1830 0.804598 1870 0.807471 1910 0.807471

1791 0.810345 1831 0.833333 1871 0.818966 1911 0.824713

1792 0.833333 1832 0.824713 1872 0.847701 1912 0.833333

1793 0.83046 1833 0.824713 1873 0.813218 1913 0.836207

1794 0.810345 1834 0.813218 1874 0.807471 1914 0.816092

1795 0.813218 1835 0.813218 1875 0.813218 1915 0.813218

1796 0.816092 1836 0.821839 1876 0.827586 1916 0.833333

1797 0.827586 1837 0.836207 1877 0.816092 1917 0.827586

1798 0.810345 1838 0.807471 1878 0.821839 1918 0.818966

1799 0.816092 1839 0.818966 1879 0.807471 1919 0.827586

1800 0.824713 1840 0.813218 1880 0.824713 1920 0.807471

153

X Y X Y X Y X Y

1921 0.824713 1961 0.813218 2001 0.824713 2041 0.876437

1922 0.810345 1962 0.801724 2002 0.821839 2042 0.859195

1923 0.824713 1963 0.818966 2003 0.827586 2043 0.864943

1924 0.824713 1964 0.807471 2004 0.83046 2044 0.87069

1925 0.821839 1965 0.833333 2005 0.83046 2045 0.867816

1926 0.824713 1966 0.804598 2006 0.816092 2046 0.856322

1927 0.824713 1967 0.818966 2007 0.816092 2047 0.887931

1928 0.83046 1968 0.824713 2008 0.818966

1929 0.833333 1969 0.827586 2009 0.824713

1930 0.795977 1970 0.821839 2010 0.821839

1931 0.798851 1971 0.824713 2011 0.83046

1932 0.824713 1972 0.833333 2012 0.83908

1933 0.827586 1973 0.821839 2013 0.833333

1934 0.795977 1974 0.810345 2014 0.83046

1935 0.810345 1975 0.821839 2015 0.827586

1936 0.818966 1976 0.813218 2016 0.818966

1937 0.83046 1977 0.827586 2017 0.833333

1938 0.821839 1978 0.818966 2018 0.816092

1939 0.821839 1979 0.83046 2019 0.816092

1940 0.827586 1980 0.824713 2020 0.816092

1941 0.827586 1981 0.824713 2021 0.841954

1942 0.804598 1982 0.807471 2022 0.821839

1943 0.807471 1983 0.818966 2023 0.827586

1944 0.816092 1984 0.813218 2024 0.827586

1945 0.833333 1985 0.824713 2025 0.83046

1946 0.827586 1986 0.816092 2026 0.821839

1947 0.824713 1987 0.813218 2027 0.827586

1948 0.827586 1988 0.810345 2028 0.824713

1949 0.824713 1989 0.833333 2029 0.83908

1950 0.816092 1990 0.813218 2030 0.804598

1951 0.813218 1991 0.804598 2031 0.824713

1952 0.827586 1992 0.83046 2032 0.87069

1953 0.827586 1993 0.821839 2033 0.876437

1954 0.816092 1994 0.810345 2034 0.864943

1955 0.804598 1995 0.833333 2035 0.876437

1956 0.821839 1996 0.813218 2036 0.873563

1957 0.827586 1997 0.821839 2037 0.873563

1958 0.816092 1998 0.801724 2038 0.876437

1959 0.818966 1999 0.818966 2039 0.873563

1960 0.836207 2000 0.824713 2040 0.867816

154

APPENDIX C

2Gb NAND Flash Memory Data Sheet

155

REFERENCES

[1] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, “Introduction to Flash memory”, Proceedings of the IEEE, V.91, No.4, pp. 489 – 502, Apr. 2003.

[2] M. Assar, S. Nemazie, P. Estakhri, “Flash Memory Mass Storage Architecture”,

United States Patent Number: 5,388,083, 1995. [3] B. Dipert, M. Levy, Designing with Flash Memory, Anna books, 1993. [4] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash Memory Cells – An Overview,”

Proceedings of the IEEE, V.35, No.8, pp. 1248-1271, Aug. 1997. [5] Liu. Vei-Han Chan, D.K.Y, “An enhanced erase mechanism during channel

Fowler- Nordheim tunneling in flash EPROM memory devices”, Electron

Device Letters, IEEE, V.20, No. 3, pp. 140 – 142, Mar. 1999

[6] G. Crisenza, C. Clementi, G. Ghidini, M. Tosi, “Floating gate memories”, Qual.

Reliab. Eng. Int., V.8, pp. 177–187, 1992. [7] D.C. Kim et al., "A 2Gbit NAND Flash Technology with 0.044um2 Cell Size using

90nm Flash Technology", IEDM Tech. Dig., 2002. [8] W. D. Brown, J. E. Brewer, “Nonvolatile Semiconductor Memory Technology: A

Comprehensive Guide to Understanding and Using Nvsm Devices”, IEEE Press, pp. 189-255, Oct 1997.

[9] K. Takeuchi, S. Satoh, K. Imamiya, K. Sakui, “A Source-Line Programming Scheme

for Low-Voltage Operation NAND Flash Memories”, IEEE Journal of Solid-State

Circuits, V.35, No. 5, pp. 1-5, May 2000. [10] Webfeet Inc., “Semiconductor industry outlook,” presented at the Non-Volatile

Memory Conference, Santa Clara, CA, 2002. [11] M. Momodomi, Y. Itoh, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T.Tanaka,

S. Aritome, T. Endoh, K. Ohuchi, F. Masuoka, “An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell”, IEEE Journal of Solid-State Circuits, V. 24, No.5, pp. 1-3, Oct. 1989.

[12] Micron Technology Inc., “2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory”,

Data sheet, pp.14, Dec 2005.

156

[13] T. Trexler, “Flash memory complexity”, IEEE Instrumentation & Measurement

Magazine, V.8, No. 1, pp. 22–26, Mar. 2005. [14] Y. C. Dawn, J. C. Yeh; C. Wen Wu, C. C. Wang, Y. C. Lin C. H. Chen, “Flash

Memory Die Sort by a Sample Classification Method”, 14th

Asian Test

Symposium Proceedings, V. 18-21, pp. 182-187, Dec. 2005. [15] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S.Tanaka, “A new Flash E2PROM

cell using triple polysilicon technology”, IEDM Tech. Dig., pp. 464–467, 1984. [16] F. Masuoka, M. Momodomi, Y. Iwata, R. Shirota, “New ultra high density EPROM

and flash EEPROM with NAND structured cell”, IEEE Tech. Dig. IEDM, pp. 552–555, 1987.

[17] S. Ledford, “Non-Volatile Memory Technology Overview”, Non-Volatile Memory

Technology Center, Austin, Texas, 2004. [18] C. L. Su, Y. T. Yeh, C. W. Wu “An integrated ECC and redundancy repair scheme

for memory reliability enhancement” 20th IEEE International Symposium, pp.81-89, Oct. 2005.

[19] D. P. Vallett, “Failure analysis requirements for nanoelectronics”, Proceedings of

the 2nd IEEE-NANO Conference, pp. 89-92, Aug. 2002. [20] J. M. Soden, R. E. Anderson, “IC failure analysis: techniques and tools for

quality reliability improvement”, Proceedings of the IEEE, V.81, No.5, pp. 703-715, May 1993.

[21] J. Hirase, “Yield increase of VLSI after redundancy-repairing”, Proceedings of 10

th

Asian Test Symposium, pp. 353-358, Nov. 2001. [22] Y. A. Lin, “Parametric wafer map visualization”, Computer Graphics and

Applications, IEEE, V.19, No.4, pp. 14-17, July-Aug. 1999. [23] L. S.Roy, A. Wiesnoski, R. Zorich, Advanced SemiconductorFabrication Handbook,

Integrated Circuit Engineering Corp., Scottsdale, Ariz., 1998. http://www.ice-corp.com.

[24] http://www.ewh.ieee.org/r6/central_coast/Hsu2001.html [25] P. Photopoulos, A.G. Nassiopoulou, “Room-and low-temperature voltage

tunable electroluminescence from a single layer of silicon quantum dots in between two thin SiO2 layers”, Applied Physics Letter 77, 1816–1818, 2000.

157

[26] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2”, Journal of Applied Physics, vol. 40, pp. 278, 1969. [27] M. Itsumi, “Positive and negative charging of thermally grown SiO2 induced by

Fowler-Nordheim Emission”, Journal of Applied Physics, vol. 52. pp. 3491-3497, 1981.

[28] Avinoam Kolodny, Sidney T.K.Nieh, Boaz Eitan, “Analysis and Modeling of

Floating-Gate EEPROM Cells”, IEEE Transactions on Electronic Devices, Vol. 33, No. 6, June 1986.

[29] Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits”, Tata

McGRAW HILL, Third Edition. [30] Samuel Tuan Wang, “On the I-V Characteristics of Floating-Gate MOS

Transistors”, IEEE Transactions on Electronic Devices, Vol. ED-26, No.9, September 1979.

[31] J. D. Choi, S. S. Cho, Y. S. Yim, J. D. Lee, H. S. Kim, K.J. Joo, S. H. Hur, H.S. Im, J.Kim, J. W. Lee, K. I. Seo, M. S. Kang, K. H. Kim, J. L. Nam, K. C. Park, and M.Y. Lee, “Highly manufacturable 1 Gb NAND flash using 0.12 µm process technology”, IEDM Tech. Dig., pp. 25–28, 2001.

[32] Jae-Duk Lee, Sung-Hoi Hur; Jung-Dal Choi, “Effects of floating-gate interference on NAND flash memory cell operation”, IEEE Electron Device Letters, Volume 23, Issue 5, pp. 264 – 266, May 2002. [33] P. Prince, Semiconductor Memories, England, Addison Wisley, 1992. [34] W.N.Gao, W.M.Snelgrove, “Floating Gate MOS Device as an Analog Trimming Element”, Journal of Custom IC’s, June 15, 1998. [35] http://aplawrence.com/Makwana/nonvolmem.html [36] Osamu Fujita, Yoshihito Amemiya, “A Floating-Gate Analog Memory Device for Neural Networks”, IEEE Transaction on Electronic Devices, Vol. 40, N0. 11, November 1993 [37] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash Memory Cells – An Overview”, Proceedings of the IEEE, V.35, No.8, pp. 1248-1271, Aug. 1997. [38] YunSeung Shin, “Non-volatile Memory Technologies for Beyond 2010”, Symposium on VLSI Circuits Digest of Technical Papers, 2005.

158

[39] Gaurav Mathur, Peter Desnoyers, Deepak Ganesan, Prashant Shenoy, “UltraLow Power Data Storage for Sensor Networks”, Information Processing in Sensor

Networks, 2006. [40] Micron Technology Inc., www.micron.com/products/nand/, 2Gb, 4Gb, 8Gb: x8, x16

NAND Flash Memory Features MT29F2G08AACWP, MT29F4G08BACWP, MT29F8G08FACWP, 2005.

Date post:	14-Feb-2022
Category:	Documents
Upload:	others
View:	5 times
Download:	0 times

WAFER PROBE AND PACKAGE TEST FAILURE ANALYSIS

Documents