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WCM 2008, June 3-4, Boston

Source/Drain Junction Partition in MOS Snapback Modeling for

ESD Simulation

Yuanzhong (Paul) Zhou,

Jean-Jacques Hajjar

Analog Devices Inc.Wilmington, MA, USA

Y. Zhou, J.J. Hajjar 2WCM 2008, June 1-4, Boston

� Motivation

� Compact Modeling for ESD Application

� On-Chip ESD Protection Scheme

� Brief Review on Compact ESD Modeling for Snapback

� Macro Model using Advanced MOS and BJT Models

� Enhanced Model with Junction Partition

� Discrepancies in Existing Model

� Macro Model with Junction Partition

� Simulation using New Model

� Conclusion

Outline

Y. Zhou, J.J. Hajjar 3WCM 2008, June 1-4, Boston

� Why SPICE-type ESD simulation?

� ESD Protection Cell Design Aid

� ESD Performance Prediction Prior to Silicon

� ESD Failure/Weakness Analysis

� Prominent Modeling Challenges:

� Devices operate beyond process rated current/voltage

� ESD-capable Compact Model

� Practical SPICE Model

Motivation

Y. Zhou, J.J. Hajjar 4WCM 2008, June 1-4, Boston

During ESD events, ESD protection

– shunts high current discharges away from the core circuitry – clamps pad voltage to a safe level

On-Chip ESD Protection Schemes

IN OUT

VDD

VSS

CORE CIRCUIT

ES

D

ES

D

ES

D

ES

DE

SD

Y. Zhou, J.J. Hajjar 5WCM 2008, June 1-4, Boston

Snapback in ESD DevicesSnapback in ESD DevicesSnapback in ESD DevicesSnapback in ESD Devices

� Operating I-V Regions of MOS Devices

1) Linear Region

2) Saturation Region

3) Avalanche Region

4) Snapback Region

5) Failure Region

� Vt1 represents the “snapback effect”trigger voltage

� Devices (MOS) operating in “snapback” mode carries more current per unit width

VDRAIN →

ID

RA

IN

→

DEVICE

REGION-1

0

REGION-2

REGION-3

REGION-4

GATE BIAS

Vt1

REGION-5

FAILS

Y. Zhou, J.J. Hajjar 6WCM 2008, June 1-4, Boston

Snapback Effect in MOS is due to turning on of the Parasitic BJT, triggered by the substrate current (ISUB).

Snapback in MOS DevicesSnapback in MOS DevicesSnapback in MOS DevicesSnapback in MOS Devices (cont.)(cont.)(cont.)(cont.)

N+N+P+

POLY

VS

VG

VD

PSUB

STI STISTI

ISUB

N+N+P+

POLY

VS

VG

VD

PSUB

STI STISTI

RSUB

LNPN

IC

ISD

ISUB

Y. Zhou, J.J. Hajjar 7WCM 2008, June 1-4, Boston

� Voltage drop across Base/Emitter junction of

parasitic NPN

� Substrate current as function of VDS, VGS and VBS

� Due to impact ionization in Drain/Body depletion layer

� Multiplication factor is different before and after snapback

� Displacement current (dV/dt) through Drain/Body junction

� Gate induced drain leakage (GIDL)

� The base transit time of the parasitic NPN

� Snapback models must have:� Main MOS

� Parasitic BJT

� Substrate Resistor

� Avalanche Current Source

Critical Effects in Snapback Modeling

Y. Zhou, J.J. Hajjar 8WCM 2008, June 1-4, Boston

� Snapback MOS models are extension of standard models

� The explicit current source is a function of VGS and VDS

� The implementation includes C code or behavioral languages

● Verilog-A models have low simulation speed and may cause serious convergence problems

● C-code has limited accessibility and needs extra simulator support

� Complexity results from the explicit current source

General Approaches of Snapback Models

G

DS

B

RdRs

Rsub

Igen

Ic

Ids

Id=Ids+Ic+Igen

Isub

Ib

Y. Zhou, J.J. Hajjar 9WCM 2008, June 1-4, Boston

Macro Model for MOS SnapbackMacro Model for MOS SnapbackMacro Model for MOS SnapbackMacro Model for MOS Snapback

� New approach eliminates the current source. [1]

� Model Consists of Standard Components only.

� Intrinsically includes all major effects outlined.

[1] Zhou et al, ISQED 2005

G

BSIM4Mextram

Ib

Bi

Isub_total

Rsub

Isub+Igidl

Id=Id'+Ic

Ic

Ids

Id'

S

D

B

Y. Zhou, J.J. Hajjar 10WCM 2008, June 1-4, Boston

� Current sources for avalanche and GIDL are intrinsically built into MOS and BJT models.

� Decoupled multiplication factors for BJT and MOS are included in IAVL and ISUB respectively.

� The dV/dt effect is modeled by C/B junction capacitance of BJT.

� The transit time of the BJT is included in the BJT model.

IGEN = IAVL + ISUB + IGIDL

Key Effects in the Macro ModelKey Effects in the Macro ModelKey Effects in the Macro ModelKey Effects in the Macro ModelSummary

Y. Zhou, J.J. Hajjar 11WCM 2008, June 1-4, Boston

� Fail to accurately model the impedance for

negative VDS

� Different capacitance values for Base/Collector

junction from CV measurement and transmission

line pulse (TLP) measurement data

� Different current gain (beta) of the BJT from DC

measurement and TLP data

Discrepancies in Existing ModelsDiscrepancies in Existing ModelsDiscrepancies in Existing ModelsDiscrepancies in Existing Models

Y. Zhou, J.J. Hajjar 12WCM 2008, June 1-4, Boston

Enhanced Model by Junction PartitionModel by Junction PartitionModel by Junction PartitionModel by Junction Partition

� Add S/B D/B Junction Diodes to Macro Model

� Substrate current becomes

� D/B Junction Capacitance

� Total base terminal currentwhen the BJT in forward Gummel configuration

1IdioIavlIgidlIsubIgen +++=

2IdiobIIb +′=

1DBJTDB CJCJCC +=

G

BSIM4Mextram

Ib

Bi

Isub_total

Rsub

Isub+Igidl

Id=Id'+Ic

Ic

Ids

Id'

S

D

B

D2 (S/B diode)

D1 (D/B diode)

Ib

Y. Zhou, J.J. Hajjar 13WCM 2008, June 1-4, Boston

Model Extraction Flow

� Extract the MOS and BJT models for DC and AC

operation using standard practice

� Obtain substrate resistance RSUB, BJT parameters

CJC and BF from snapback characteristics

� Determine diode parameters from IV curve for

VDS<0 and total junction capacitance.

Y. Zhou, J.J. Hajjar 14WCM 2008, June 1-4, Boston

Simulation Results vs. TLP Measurement-- A ggNMOS device

Y. Zhou, J.J. Hajjar 15WCM 2008, June 1-4, Boston

Simulation Results vs. TLP Measurement--Snapback curves of a ggNMOS device for different rise times

CJCBJT /CDB ≅ 0.9

Y. Zhou, J.J. Hajjar 16WCM 2008, June 1-4, Boston

SPICE Simulation Results-- Base current in forward Gummel plot for the parasitic BJT

ISBJT /(ISBJT + ISDIO) ≅ 0.6

Y. Zhou, J.J. Hajjar 17WCM 2008, June 1-4, Boston

� Junction partition in MOS snapback model has been discussed using a new macro model approach

� Enhanced compact model retains the advantages in the original approach

� Uses industry standard models

� Simple implementation

� High simulation speed

� Wide accessibility

� Fewer convergence issues

� New model offers significant improvement

� Valid for both positive and negative VDS stresses

� Consistent total drain capacitance

� Accurate base current for the parasitic BJT

ConclusionConclusionConclusionConclusion