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Weikang Qian

Room 430, University of Michigan-Shanghai Jiao Tong University Joint Institute

Shanghai Jiao Tong University

800 Dong Chuan Road, Shanghai, China 200240

Phone: +86-021-34206765-4301

Email: qianwk@sjtu.edu.cn

Web: http://umji.sjtu.edu.cn/~wkqian/

Employment: Tenured Associate Professor 09/2019-Present

Tenure-Track Associate Professor 02/2018-08/2019

Tenure-Track Assistant Professor 09/2011-01/2018

University of Michigan-Shanghai Jiao Tong University Joint Institute,

Shanghai Jiao Tong University, Shanghai, China

Education: Ph.D., Electrical Engineering 07/2011

Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities

Advisor: Marc Riedel

Dissertation Title: Digital yet Deliberately Random: Synthesizing Logical Computation on

Stochastic Bit Streams

Bachelor of Engineering, Automation 07/2006

Department of Automation, Tsinghua University, Beijing, China

Awards & Honors: Advisor of the First-Place Undergraduate Winner of ACM Student Research

Competition (SRC) Grand Finals

2019

Advisor of the First-Place Undergraduate Winner of ACM Student Research

Competition (SRC) at International Conference on Computer-Aided Design

(ICCAD)

2018

UM-SJTU Joint Institute Research Excellence Award 2018

Nomination for Best Student Paper Award,

International Workshop on Logic and Synthesis (IWLS)

2016

Mong Man-Wei International Exchange Award 2015

Doctoral Dissertation Fellowship, University of Minnesota 2010

Nomination for William J. McCalla Best Paper Award,

International Conference on Computer-Aided Design (ICCAD)

2009

Best Poster Award,

Center on Functional Engineered Nano Architectonics (FENA)

2009

First-Rank Scholarship for Academic Excellent Students, Tsinghua University 2005

First-Rank Scholarship for Academic Excellent Students, Tsinghua University 2004

First-Rank Scholarship for Academic Excellent Students, Tsinghua University 2003

Research Interests: Electronic Design Automation (Logic Synthesis, Physical Design, High-level Synthesis, etc.)

Circuit Design and Synthesis for Novel Computing Paradigms (Stochastic Computing,

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Approximate Computing, Neuromorphic Computing, etc.)

Circuit Design and Synthesis for Emerging Technologies (Carbon-Nanotube Field Effect

Transistors, Memristors, Single-Electron Transistors, etc.)

Circuit Design and Synthesis for Specific Applications (Artificial Intelligence, Digital Signal

Processing, Communication, etc.)

Teaching: VE451 Digital Signal Processing and Analysis Fall 2011

VE280 Programming and Elementary Data Structures Summer 2012-2019

VE281 Data Structures and Algorithms Fall 2012-2018

VE527 Computer-Aided Design of Integrated Circuits Summer 2015-2017,

Fall 2013, 2017-2018

Industrial

Experience:

Research Intern 05/2008-09/2008

IBM T. J. Watson Research Center, Yorktown Heights, NY

Professional

Activities:

Membership in Professional Organizations

Member, IEEE

Member, ACM

Member, ACM Special Interest Group on Design Automation (SIGDA)

Conference and Workshop Chair and Organizer

China Semiconductor Technology International Conference (CSTIC) Symposium IX on

Design and Automation of Circuits and Systems, 2019-2020, Co-chair

Workshop on Stochastic Computing for Neuromorphic Architectures, 2020, Co-organizer

Conference and Workshop Technical Program Committee Member

Great Lakes Symposium on VLSI (GLSVLSI), 2020

International Conference on VLSI Design (VLSID), 2020

International Conference on Computer-Aided Design (ICCAD), 2017-2019

Asia and South Pacific Design Automation Conference (ASPDAC), 2019

China Semiconductor Technology International Conference (CSTIC), 2013-2019

International Workshop on Logic and Synthesis (IWLS), 2013-2019

Design Automation Conference (DAC) Ph.D. Forum, 2015-2017

Journal Special Issue Guest Editor

Integration, the VLSI Journal’s special issue on 2019 IEEE China Semiconductor

Technology International Conference (CSTIC) Symposium on Design and Automation of

Circuits and Systems, 2019

Microelectronics Journal’s special issue on “Approximate computing: Co-design of

circuits, architectures, and algorithms”, 2018

Conference and Workshop Special Session Organizer

International Workshop on Signal Processing Systems (SiPS)’s special session on

emerging computing paradigms for signal processing and smart learning, 2019

Conference and Workshop Session Chair

Design, Automation, and Test in Europe Conference (DATE), 2019

Asia and South Pacific Design Automation Conference (ASPDAC), 2017

International Workshop on Logic and Synthesis (IWLS), 2016

Great Lakes Symposium on VLSI (GLSVLSI), 2015-2016

International Symposium on Design Technologies for Internet of Things, 2015

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International Workshop on Emerging Technologies of Synthesis and Optimization, 2014

China Semiconductor Technology International Conference (CSTIC), 2013-2019

International Workshop on Emerging Circuits and Systems, 2012

Paper Refereeing

IEEE Transactions on Computers

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Circuits and Systems I

IEEE Transactions on Circuits and Systems II

IEEE Transactions on Circuits and Systems for Video Technology

IEEE Transactions on Emerging Topics in Computing

IEEE Transactions on Information Theory

IEEE Transactions on Multimedia

IEEE Transactions on Nanotechnology

IEEE Transactions on Neural Networks and Learning Systems

IEEE Transactions on VLSI

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

IEEE Embedded System Letters

ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Embedded Computing Systems

ACM Journal on Emerging Technologies in Computing Systems

Microelectronics Journal

Microelectronics Reliability Journal

Integration, the VLSI Journal

International Journal of Approximate Reasoning

Journal of Computer Science and Technology

Journal of Signal Processing Systems

IET Computers and Digital Techniques

Design Automation Conference (DAC)

Design, Automation, and Test in Europe (DATE)

International Conference on Computer-Aided Design (ICCAD)

Asia and South Pacific Design Automation Conference (ASPDAC)

International Conference on Computer Design (ICCD)

Great Lakes Symposium on VLSI (GLSVLSI)

International Symposium on Circuits and Systems (ISCAS)

China Semiconductor Technology International Conference (CSTIC)

International Symposium on Nanoscale Architectures (NANOARCH)

International Symposium on Physical Design (ISPD)

International Workshop on Logic and Synthesis (IWLS)

International Workshop on Signal Processing Systems (SiPS)

International Symposium on Multiple-Valued Logic (ISMVL)

International Symposium on Integrated Circuits (ISIC)

International Conference on ASIC (ASICON)

International Conference on VLSI Design (VLSID)

Other Services

Judge for ACM Student Research Competition at 2014 International Conference on

Computer-Aided Design (ICCAD)

Panelist of the special session on MOOC at 2014 International Conference on Field-

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Programmable Technology (ICFPT)

Judge for Ph.D. forum at 2016 Design Automation Conference (DAC)

Publications: Book Chapters

(*/^ indicates the

supervised graduate/

undergraduate

students.)

B1. Marc Riedel and Weikang Qian, “Synthesis of polynomial functions”, in Stochastic

Computing: Techniques and Applications, Warren Gross and Vincent Gaudet editors,

Springer Publishing, 2019.

B2. Xuesong Peng* and Weikang Qian, “A branch-and-bound-based minterm

assignment algorithm for synthesizing stochastic circuit”, in Advanced Logic

Synthesis, Andre Reis and Rolf Drechsler editors, Springer Publishing, 2018.

B3. Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “Synthesizing

combinational logic to generate probabilities: theories and algorithms,” in Advanced

Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and

Kanupriya Gulati editors, Springer Publishing, 2011.

Peer-Reviewed Journal Articles

J1. Yi Wu* and Weikang Qian, “ALFANS: Multi-level approximate logic synthesis

framework by approximate node simplification,” to appear in IEEE Transactions on

Computer-Aided Design of Integrated Circuits and Systems, 2019.

J2. Sanbao Su*, Chen Zou^, Weijiang Kong^, Jie Han, and Weikang Qian, “A novel

heuristic search method for two-level approximate logic synthesis,” to appear in IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.

J3. Zhijing Li^, Zhao Chen^, Yili Zhang^, Zixin Huang^, and Weikang Qian,

“Simultaneous area and latency optimization for stochastic circuits by D flip-flop

insertion,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 38, no. 7, pp. 1251-1264, 2019.

J4. Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao,

Weikang Qian, and Li Jiang, “Energy-efficient nonvolatile SRAM design based on

resistive switching multi-level cell,” in IEEE Transactions on Circuits and Systems II:

Express Briefs, vol. 66, no. 5, pp. 753-757, 2019.

J5. Junjun Hu*, Zhijing Li^, Meng Yang*, Zixin Huang^, and Weikang Qian, “A high-

accuracy approximate adder with correct sign calculation,” in Integration, the VLSI

Journal, vol. 65, pp. 370-388, 2019.

J6. Yi Wu*+, You Li^+, Xiangxuan Ge^+, Yuan Gao^, and Weikang Qian, “An efficient

method for calculating the error statistics of block-based approximate adders,” in

IEEE Transactions on Computers, vol. 68, no. 1, pp. 21-38, 2019. (+These authors

contributed equally.)

J7. Xuesong Peng* and Weikang Qian, “Stochastic circuit synthesis by cube

assignment,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 37, no. 12, pp. 3109-3122, 2018.

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J8. Armin Alaghi, Weikang Qian, and John Hayes, “The promise and challenge of

stochastic computing,” in IEEE Transactions on Computer-Aided Design of

Integrated Circuits and Systems, vol. 37, no. 8, pp. 1515-1531, 2018. (Keynote

Paper)

J9. Chen Wang*, Yanan Sun, Shiyan Hu, Li Jiang, and Weikang Qian, “Variation-aware

global placement for improving timing-yield of carbon-nanotube field effect transistor

circuit,” in ACM Transactions on Design Automation of Electronic Systems, vol. 23,

no. 4, pp. 44:1-44:27, 2018.

J10. Yanbo Wang, Weikang Qian, and Bo Yuan, “A graphical model of smoking-induced

global instability in lung cancer,” in IEEE/ACM Transactions on Computational

Biology and Bioinformatics, vol. 15, no. 1, pp. 1-14, 2018.

J11. M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, and Marc

D. Riedel, “A reconfigurable architecture with sequential logic-based stochastic

computing,” in ACM Journal on Emerging Technologies in Computing Systems, vol.

13, no. 4, pp. 57:1-57:28, 2017.

J12. Yu Wang^, Weikang Qian, Shuchang Zhang, Xiaoyao Liang, and Bo Yuan, “A

learning algorithm for Bayesian networks and its efficient implementation on GPUs,”

in IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 1, pp. 17-30,

2016.

J13. Weikang Qian, Marc D. Riedel, and Ivo Rosenberg, “Synthesizing cubes to satisfy a

given intersection pattern,” in Journal of Discrete Applied Mathematics, vol. 193, pp.

11-38, 2015.

J14. Peng Li, David J. Lilja, Weikang Qian, Marc D. Riedel, and Kia Bazargan, “Logical

computation on stochastic bit streams with linear finite state machines,” in IEEE

Transactions on Computers, vol. 63, no. 6, pp. 1474-1486, 2014.

J15. Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, and Marc. D. Riedel,

“Computation on stochastic bit streams: digital image processing case studies,” in

IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, vol. 22, no. 3, pp.

449-462, 2014.

J16. Weikang Qian, Marc D. Riedel, Hongchao Zhou, and Jehoshua Bruck,

“Transforming probabilities with combinational logic,” in IEEE Transactions on

Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 9, pp. 1279-

1292, 2011.

J17. Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “An

architecture for fault-tolerant computation with stochastic logic,” in IEEE

Transactions on Computers, vol. 60, no. 1, pp. 93-105, 2011.

J18. Weikang Qian, Marc D. Riedel, and Ivo Rosenberg, “Uniform approximation and

Bernstein polynomials with coefficients in the unit interval,” in European Journal of

Combinatorics, vol. 32, no. 3, pp. 448-463, 2011.

J19. Weikang Qian, John Backes, and Marc D. Riedel, “The synthesis of stochastic

circuits for nanoscale computation,” in International Journal of Nanotechnology and

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Molecular Computation, vol. 1, no. 4, pp. 39-57, 2010.

Peer-Reviewed Conference Papers

C1. Kuncai Zhong* and Weikang Qian, “Accuracy analysis for stochastic circuits with

D-flip flop insertion,” to appear in Proceedings of the 2020 Design, Automation, and

Test in Europe Conference (DATE), Grenoble, France, 2020.

C2. Chang Ma*, Yanan Sun, Weikang Qian, Ziqi Meng*, Rui Yang, and Li Jiang, “Go

unary: a novel synapse coding and mapping scheme for reliable ReRAM-based

neuromorphic computing,” to appear in Proceedings of the 2020 Design, Automation,

and Test in Europe Conference (DATE), Grenoble, France, 2020.

C3. Yawen Zhang*, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang

Qian, and Ru Huang, “When sorting network meets parallel bitstreams: A fault-

tolerant parallel ternary neural network (TNN) accelerator based on stochastic

computing,” to appear in Proceedings of the 2020 Design, Automation, and Test in

Europe Conference (DATE), Grenoble, France, 2020.

C4. Chuliang Guo, Li Zhang, Xian Zhou, Weikang Qian, and Cheng Zhuo, “A

reconfigurable approximate multiplier for quantized CNN applications,” to appear in

Proceedings of the 2020 Asia and South Pacific Design Automation Conference

(ASPDAC), Beijing, China, 2020.

C5. Lun Zhang*, Weikang Qian, and Haibao Chen, “Area-efficient parallel stochastic

computing with shared weighted binary generator,” in Proceedings of the 13th

International Conference on ASIC (ASICON), Chongqing, China, 2019.

C6. Menghui Xu, Weikang Qian, Zaichen Zhang, Xiaohu You, and Chuan Zhang, “A

data structure-based approximate belief propagation decoder for polar codes,” in

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems

(SiPS), Nanjing, China, 2019 (Invited Paper).

C7. Weikang Qian+, Runsheng Wang+, Yuan Wang, Marc Riedel, and Ru Huang, “A

survey of computation-driven data encoding,” in Proceedings of the 2019 IEEE

International Workshop on Signal Processing Systems (SiPS), Nanjing, China, 2019

(Invited Paper). (+These authors contributed equally.)

C8. Chang Meng*, Paul Weng, Sanbao Su*, and Weikang Qian, “Advanced ordering

search for multi-level approximate logic synthesis,” in Proceedings of the 2019

International Workshop on Logic and Synthesis (IWLS), Lausanne, Switzerland,

2019, pp. 89-96.

C9. Kuncai Zhong*, Meng Yang*, and Weikang Qian, “Optimizing stochastic

computing-based FIR filters,” in Proceedings of the 2018 International Conference

on Digital Signal Processing (DSP), Shanghai, China, 2018, pp. 1-5 (Invited Paper).

C10. Zhuangzhuang Zhou^, Yue Yao^, Shuyang Huang^, Sanbao Su*, Chang Meng*, and

Weikang Qian, “DALS: Delay-driven approximate logic synthesis,” in Proceedings

of the 2018 IEEE/ACM International Conference on Computer-Aided Design

(ICCAD), San Diego, CA, USA, 2018, pp. 86:1-86:7.

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C11. Bingzhe Li, Meng Yang*, Soheil Mohajer, Weikang Qian, and David J. Lilja, “Tier-

code: An XOR-based RAID-6 code with improved write and degraded-mode read

performance,” in Proceedings of the 13th IEEE International Conference on

Networking, Architecture, and Storage, Chongqing, China, 2018, pp. 1-10.

C12. Meng Yang*, Bingzhe Li, David J. Lilja, Bo Yuan, and Weikang Qian, “Towards

theoretical cost limit of stochastic number generators for stochastic computing,” in

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI

(ISVLSI), Hong Kong, 2018, pp. 154-159 (Invited Paper).

C13. Sanbao Su*, Yi Wu*, and Weikang Qian, “Efficient batch statistical error estimation

for iterative multi-level approximate logic synthesis,” in Proceedings of the 2018

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2018,

pp. 54:1-54:6.

C14. Menghui Xu, Shusen Jing, Jun Lin, Weikang Qian, Zaichen Zhang, Xiaohu You, and

Chuan Zhang, “Approximate belief propagation decoder for polar codes,” in

Proceedings of the 2018 IEEE International Conference on Acoustics, Speech and

Signal Processing (ICASSP), Calgary, AB, Canada, 2018, pp. 1169-1173.

C15. Meng Yang*, John Hayes, Deliang Fan, and Weikang Qian, “Design of accurate

stochastic number generators with noisy emerging devices for stochastic computing,”

in Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided

Design (ICCAD), Irvine, CA, USA, 2017, pp. 638-644.

C16. Yue Yao^, Shuyang Huang^, Chen Wang*, Yi Wu*, and Weikang Qian,

“Approximate disjoint bi-decomposition and its application to approximate logic

synthesis,” in Proceedings of the 35th IEEE International Conference on Computer

Design (ICCD), Boston, MA, USA, 2017, pp. 517-524.

C17. Meng Yang* and Weikang Qian, “Design of reliable stochastic number generators

using emerging devices for stochastic computing,” in Proceedings of the 2017

International Workshop on Logic and Synthesis (IWLS), Austin, TX, USA, 2017, pp.

52-59.

C18. Yi Wu*, Chuyu Shen*, Yi Jia^, and Weikang Qian, “Approximate logic synthesis

for FPGA by wire removal and local function change”, in Proceedings of the 2017

Asia and South Pacific Design Automation Conference (ASPDAC), Chiba, Japan,

2017, pp. 163-169.

C19. Xuesong Peng* and Weikang Qian, “A branch-and-bound-based minterm

assignment algorithm for synthesizing stochastic circuit”, in Proceedings of the 2016

International Workshop on Logic and Synthesis (IWLS), Austin, TX, USA, 2016, pp.

155-162 (Nominated for Best Student Paper Award).

C20. Yi Wu* and Weikang Qian, “An efficient method for multi-level approximate logic

synthesis under error rate constraint”, in Proceedings of the 2016 ACM/IEEE Design

Automation Conference (DAC), Austin, TX, USA, 2016, pp. 128:1-128:6.

C21. Rui Zhou^ and Weikang Qian, “A general sign bit error correction scheme for

approximate adders”, in Proceedings of the 2016 Great Lakes Symposium on VLSI

(GLSVLSI), Boston, MA, USA, 2016, pp. 221-226.

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C22. Chuyu Shen*, Zili Lin*, Ping Fan, Xianglong Meng, and Weikang Qian,

“Parallelizing FPGA technology mapping through partitioning”, in Proceedings of the

2016 International Symposium on Field-Programmable Custom Computing Machines

(FCCM), Washington D.C., USA, 2016, pp. 164-167.

C23. Lezhong Huang^, Guanhui Chen^, Peng Li, and Weikang Qian, “Accelerating

stochastic computation for binary classification applications,” in Proceeding of the

2016 IEEE International Conference on Acoustics, Speech and Signal Processing

(ICASSP), Shanghai, China, 2016, pp. 6530-6534 (Invited Paper).

C24. Chen Zou^, Weikang Qian, and Jie Han, “DPALS: A dynamic programming-based

algorithm for two-level approximate logic synthesis,” in Proceedings of the 11th

International Conference on ASIC (ASICON), Chengdu, China, 2015, pp. 1-4.

C25. Chen Wang*, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, and

Weikang Qian, “Timing-driven placement for carbon nanotube circuits,” in

Proceedings of the 2015 IEEE International System-on-Chip Conference (SOCC),

Beijing, China, 2015, pp. 362-367 (Invited Paper).

C26. Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, and Li Jiang “On

microarchitectural modeling for CNFET-based circuits,” in Proceedings of the 2015

IEEE International System-on-Chip Conference (SOCC), Beijing, China, 2015,

pp. 356-361 (Invited Paper).

C27. Yi Wu*, Chen Wang*, and Weikang Qian, “Minimizing error of stochastic

computation through linear transformation,” in Proceedings of the 2015 Great Lakes

Symposium on VLSI (GLSVLSI), Pittsburgh, PA, USA, 2015, pp. 349-354 (Invited

Paper).

C28. Junjun Hu* and Weikang Qian, “A new approximate adder with low relative error

and correct sign calculation,” in Proceedings of the 2015 Design, Automation, and

Test in Europe Conference (DATE), Grenoble, France, 2015, pp. 1449-1454.

C29. Zheng Zhao* and Weikang Qian, “A general design of stochastic circuit and its

synthesis,” in Proceedings of the 2015 Design, Automation, and Test in Europe

Conference (DATE), Grenoble, France, 2015, pp. 1467-1472.

C30. Yili Ding^, Yi Wu*, and Weikang Qian, “Generating multiple correlated

probabilities for MUX-based stochastic computing architecture,” in Proceedings of

the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD),

San Jose, CA, USA, 2014, pp. 519-526.

C31. Zheng Zhao*, Chian-Wei Liu, Chun-Yao Wang, and Weikang Qian, “BDD-based

synthesis of reconfigurable single-electron transistor arrays,” in Proceedings of the

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San

Jose, CA, USA, 2014, pp. 47-54.

C32. Daran Cai^, Ang Wang^, Ge Song^, and Weikang Qian, “An ultra-fast parallel

architecture using sequential circuits computing on random bits,” in Proceedings of

the 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing,

China, 2013, pp. 2215-2218.

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C33. Chen Wang* and Weikang Qian, “Optimizing multi-level combinational circuits for

generating random bits,” in Proceedings of the 18th Asia and South Pacific Design

Automation Conference (ASPDAC), Yokohama, Japan, 2013, pp. 139-144.

C34. Weikang Qian, Chen Wang*, Peng Li, David J. Lilja, Kia Bazargan, and Marc D.

Riedel, “An efficient implementation of numerical integration using logical

computation on stochastic bit streams,” in Proceedings of the 2012 IEEE/ACM

International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA,

2012, pp. 156-162 (Invited Paper).

C35. Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, and Marc D. Riedel, “The

synthesis of complex arithmetic computation on stochastic bit streams using

sequential logic,” in Proceedings of the 2012 IEEE/ACM International Conference on

Computer-Aided Design (ICCAD), San Jose, CA, USA, 2012, pp. 480-487.

C36. Peng Li, Weikang Qian, and David J. Lilja, “A stochastic reconfigurable architecture

for fault-tolerant computation with sequential logic,” in Proceedings of the 30th IEEE

International Conference on Computer Design (ICCD), Montreal, QC, Canada, 2012,

pp. 303-308.

C37. Peng Li, Weikang Qian, David Lilja, Kia Bazargan, and Marc Riedel, “Case studies

of logical computation on stochastic bit streams,” in Proceedings of the 22nd

International Workshop on Power and Timing Modeling, Optimization and

Simulation (PATMOS), Newcastle upon Tyne, UK, 2012, pp. 235-244. (Invited

Paper).

C38. Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “The

synthesis of linear finite state machine-based stochastic computational elements,” in

Proceedings of the 17th Asia and South Pacific Design Automation Conference

(ASPDAC), Sydney, Australia, 2012, pp. 757-762.

C39. Weikang Qian and Marc D. Riedel, “Two-level logic synthesis for probabilistic

computation,” in Proceedings of the 19th International Workshop on Logic and

Synthesis (IWLS), Irvine, CA, USA, 2010, pp. 95-102.

C40. Weikang Qian and Marc D. Riedel, “Synthesizing cubes to satisfy a given

intersection pattern,” in Proceedings of the 19th International Workshop on Logic and

Synthesis (IWLS), Irvine, CA, USA, 2010, pp. 217-224.

C41. Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “The synthesis of

combinational logic to generate probabilities,” in Proceedings of the 2009 IEEE/ACM

International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA,

2009, pp. 367-374 (Nominated for Best Paper Award).

C42. Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, “A

reconfigurable stochastic architecture for highly reliable computing,” in Proceedings

of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, USA,

2009, pp. 315-320.

C43. Weikang Qian and Marc D. Riedel, “The synthesis of robust polynomial arithmetic

with stochastic logic,” in Proceedings of the 45th ACM/IEEE Design Automation

Page 10 of 13

Conference (DAC), Anaheim, CA, USA, 2008, pp. 648-653.

C44. Weikang Qian and Marc D. Riedel, “The synthesis of stochastic logic to perform

multivariate polynomial arithmetic,” in Proceedings of the 17th International

Workshop on Logic and Synthesis (IWLS), Lake Tahoe, CA, USA, 2008, pp. 79-86.

Invited Talks: T1. “Sequential optimization based on signal equivalence merging and its validation,”

IBM CMOS Forum, 08/27/2008.

T2. “The synthesis of combinational logic for probabilistic computation,” Department of

Electrical Engineering, California Institute of Technology, USA, 11/06/2009.

Host: Prof. Jehoshua Bruck.

T3. “Digital yet deliberately random: synthesizing logical computation on stochastic bit

streams,” Department of Electrical Engineering, University of Southern California,

USA, 02/28/2011, Host: Prof. Sandeep Gupta.

T4. “Digital yet deliberately random: synthesizing logical computation on stochastic bit

streams,” Department of Electrical Engineering, University of California, Riverside,

USA, 03/02/2011, Host: Prof. Sheldon Tan.

T5. “Digital yet deliberately random: synthesizing logical computation on stochastic bit

streams,” Department of Electrical and Computer Engineering, Missouri University

of Science and Technology, USA, 03/18/2011, Host: Prof. Yiyu Shi.

T6. “Digital yet deliberately random: synthesizing logical computation on stochastic bit

streams,” University of Michigan-Shanghai Jiao Tong University Joint Institute,

China, 03/31/2011, Host: Prof. Olivier Bauchau.

T7. “Digital yet deliberately random: synthesizing logical computation on stochastic bit

streams,” Cadence Design Systems, Inc., 04/19/2011, Host: Dr. Inki Hong.

T8. “Synthesizing logical computation on stochastic bit streams,” Center for Energy-

Efficient Computing and Applications, Peking University, China, 01/06/2012,

Host: Prof. Guojie Luo.

T9. “Digital computation on stochastic bit streams: a pseudo-analog approach,”

International Workshop on Emerging Circuits and Systems, Shanghai, China,

08/09/2012.

T10. “The synthesis of digital computation on stochastic bit streams,” China

Semiconductor Technology International Conference (CSTIC), Shanghai, China,

03/18/2013.

T11. “The synthesis of digital computation on stochastic bit streams,” Fudan University,

China, 06/28/2013. Host: Prof. Lingli Wang.

T12. “Digital computation on stochastic bit streams,” ShanghaiTech University, China,

10/16/2013. Host: Prof. Pingqiang Zhou.

Page 11 of 13

T13. “Accelerating digital computation on stochastic bit streams,” China Semiconductor

Technology International Conference (CSTIC), Shanghai, China, 03/16/2014.

T14. “Digital design and synthesis for emerging computing paradigm and device

technology,” Cadence Design Systems, Inc., Shanghai, China, 11/26/2014. Host: Mr.

Haobin Li.

T15. “BDD-based synthesis of reconfigurable single-electron transistor arrays,”

International Workshop on Emerging Technologies of Synthesis and Optimization

(IWETSO), Shanghai, China, 12/13/2014.

T16. “BDD-based synthesis of reconfigurable single-electron transistor arrays,” China

Semiconductor Technology International Conference (CSTIC), Shanghai, China,

03/16/2015.

T17. “Digital design and synthesis for emerging computing paradigm and device

technology,” Synopsys, Inc., Shanghai, China, 03/18/2015. Host: Dr. Jove Pan.

T18. “Approximate computing and approximate logic synthesis”, Synopsys, Inc.,

Shanghai, China, 11/05/2015. Host: Dr. Jove Pan.

T19. “Approximate computing: think wrong, achieve great”, Shanghai Jiao Tong

University-Microsoft Research Asia Joint Lab Workshop, Wuzhen, China,

06/04/2016.

T20. “Approximate computing: a novel energy-efficient design methodology for error-

tolerant applications”, Advanced Computer Architecture Conference, Weihai, China,

08/22/2016.

T21. “Design and synthesis of approximate computing circuits,” Zhejiang University,

China, 12/22/2016. Host: Prof. Chen Zhuo.

T22. “Design and synthesis of approximate computing circuits,” ShanghaiTech University,

China, 12/27/2016. Host: Prof. Pingqiang Zhou.

T23. “Design and synthesis of approximate computing circuits,” Meji University, Japan,

01/19/2017. Host: Prof. Tsutomu Sasao.

T24. “Logic synthesis for approximate computing,” China Semiconductor Technology

International Conference (CSTIC), Shanghai, China, 03/12/2017.

T25. “Logic synthesis for approximate computing,” Ningbo University, China,

07/29/2017. Host: Prof. Zhufei Chu.

T26. “Design and synthesis of approximate computing circuits,” Southeast University,

China, 08/30/2017. Host: Prof. Chuan Zhang.

T27. “Design and synthesis of approximate computing circuits,” Fudan University, China,

09/04/2017. Host: Prof. Xuan Zeng.

T28. “Design and synthesis of approximate computing circuits,” University of Michigan,

Ann Arbor, U.S.A., 11/09/2017. Host: Prof. John Hayes.

Page 12 of 13

T29. “Design and synthesis of approximate computing circuits,” University of Notre

Dame, U.S.A., 11/10/2017. Host: Prof. Yiyu Shi.

T30. “Design and synthesis of approximate computing circuits,” Peking University, China,

12/21/2017. Host: Prof. Guojie Luo.

T31. “The promise and challenge of stochastic computing,” Peking University, China,

12/21/2017. Host: Prof. Runsheng Wang.

T32. “Design and synthesis of approximate computing circuits,” Institute of Computing

Technology, Chinese Academy of Sciences, China, 12/22/2017. Host: Prof. Yinhe

Han.

T33. “Optimizing stochastic number generators for stochastic computing,” China

Semiconductor Technology International Conference (CSTIC), Shanghai, China,

03/12/2018.

T34. “Efficient batch statistical error estimation for iterative multi-level approximate logic

synthesis,” ChinaDA Conference, Beijing, China, 06/09/2018.

T35. “Design and synthesis of approximate computing circuits,” Chinese University of

Hong Kong, Hong Kong, 07/11/2018. Host: Prof. Qiang Xu.

T36. “DALS: Delay-driven approximate logic synthesis,” China Test Conference, Harbin,

China, 08/15/2018.

T37. “Design and synthesis for emerging computing paradigms,” Peking University,

China, 10/09/2018. Host: Prof. Runsheng Wang.

T38. “Logic synthesis for approximate computing,” Asian Test Symposium (ATS), Hefei,

China, 10/17/2018.

T39. “Logic synthesis for approximate computing,” IEEE CEDA Shanghai Chapter

Meeting, Shanghai, China, 11/25/2018.

T40. “Optimizing stochastic number generators for stochastic computing,” ChinaDA

Conference, Shanghai, China, 01/13/2019.

T41. “Approximate logic synthesis for area and delay optimization,” 2019 Design,

Automation, and Test in Europe Conference (DATE) Friday Workshop, Florence,

Italy, 03/29/2019.

T42. “A survey of computation-driven data encoding,” 2019 IEEE International Workshop

on Signal Processing Systems (SiPS), Nanjing, China, 10/22/2019.

Student Advising: Doctoral Students

Page 13 of 13

Yi Wu (2012 – 2017)

Chen Wang (2014 – )

Kuncai Zhong (2018 – )

Weihua Xiao (2019 – )

Master Students

Chen Wang (2011 – 2014)

Junjun Hu (2012 – 2015)

Zheng Zhao (2012 – 2015)

Chuyu Shen (2013 – 2016)

Zili Lin (2014 – 2017)

Xuesong Peng (2014 – 2017)

Sanbao Su (2016 – 2019)

Meng Yang (2016 – 2019)

Chang Meng (2018 – )

Ziqi Meng (2019 – )