What is Vlsi

7/30/2019 What is Vlsi

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Vlsi Technology

Digital systems are highly complex at their most detailed level. Theymay consist of millions of elements i.e., transistors or logic gates. For manydecades, logic schematics served as thengua franca of logic design, but not any

more. Today, hardware complexity has grown to such a degree that a schematicwith logic gates is almost useless as it shows only a web of connectivity and notfunctionality of design. Since the 1970s, computer engineers, electrical engineersand electronics engineers have moved toward Hardware description language(HDLs).

Digital circuit has rapidly evolved over the last twenty five years .Theearliest digital circuits were designed with vaccum tubes and transistors.

Integrated circuits were then invented where logic gates were placed on a singlechip. The first IC chip were small scale integration (SSI) chips where the gatecount is small. When technology became sophisticated ,designers were able toplace circuits with hundreds of gates on a chip. These chips were called MSIchips with advent ofLSI, designers could put thousands of gates on a single chip.At this point, design process is getting complicated and designers felt the need toautomate these processes.

With the advent of VLSI technology, designers could design single chipwith more than hundred thousand gates. Because of the complexity of thesecircuits computer aided techniques became critical for verification and fordesigning these digital circuits.

One way to lead with increasing complexity of electronic systems and theincreasing time to market is to design at high levels of abstraction. Traditional

paper and pencil and capture and simulate methods have largely given way to thedescribed unsynthesized approach.


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For these reasons, hardware description languages have played animportant role in describe and synthesis design methodology. They are used forspecification, simulation and synthesis of an electronic system. This helps to

reduce the complexity in designing and products are made to be available inmarket quickly.

The components of a digital system can be classified as being specificto an application or as being standard circuits. Standard components are takenfrom a set that has been used in other systems. MSI components are standardcircuits and their use results in a significant reduction in the total cost as

compared to the cost of using SSI Circuits. In contrasts, specific components areparticular to the system being implemented and are not commonly found amongthe standard components.

The implementation of specific circuits with LSI chips can be done bymeans of IC that can be programmed to provide the required logic.

EMERGENCE OF HARDWARE DESCRIPTION LANGUAGE

As designs got larger and complex, logic simulation assumed animportant role in design process. For a long time, programming languagessuch as fortran, pascal & c were been used to describe the computerprograms that were been used to describe the computer programs thatwere sequential in nature. Similarly in digital design field, designers felt the

need for a standard language to describe digital circuits. Thus HDL iscame in to exitance. HDLs allowed the designers to model the concurrencyof processes found in hardware elements. HDLs such as VERILOG HDL &VHDL( Very high speed integrated circuit hardware descriptionlanguage). became popular.


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Doubles


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DESIGN FLOW

X=(ABCD+A+D+A(B+C))

Y=(A(B+C)+AC+D+A(BC+D))

Packaging and testing

Fabrication

Circuit design

Physical design

Logic design

Functional design

system specification


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POPULARITY OF VERILOG HDL

Verilog hdl has evolved as a standard hardware descriptionallanguage.Verilog offers many useful features for hadware design.

Verilog is a general purpose hardware descriptionlanguage that is easy to learn and to use.It has thusbecome user friendly.

Verilog allows different levels of abstraction to be mixedin the same model.Thus a designer can design a

hardware model in terms of switches,gates,RTL orbehavioural codes.

Verilog is one language for simulation and design.Mostpopular logic synthesis tools support verilog HDL.Thismakes it the language of choice of designers .

TYPICAL DESIGN FLOW

Typical design flow for designing VLSI circuitsis shown in the tool flow diagram.

This design flow is typically used by designerswho use HDLs.In any design,specification are first.Specification describethe functionality,interface and overall architecture of the digital circuit to bedesigned.At this point,architects need not think about how they willimplement their circuit.

A behavioural description is then created toanalyse the design in terms of functionality,performances and other highlevel issues.

The behavioural description is manuallyconverted to an RTL (Register Transfer Level) description in an HDL.Thedesigner has to describe the data flow that will implement the desireddigital circuit.From this point onward the design process is done with

assistance ofCAD tools.


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Logic synthesis tools convert the RTLdescription to a gate level netlist.A gate level netlist is a description of thecircuit in terms of gates and connections between them.

The gate level netlist is input to an automaticplace and route tool, which creates a layout.

The layout is verified and then fabricated on achip.Thus most digital design activity is concentrated on manuallyoptimizing the RTL description of the circuit.After the RTL description isfrozen,CAD tools are available to assist the designer in further

proceeese.Designing at RTL level has shrunk design cycle times fromyears to a few months.

TYPICAL DESIGN FLOW OF VLSI

BEHAVIORAL DESCRIPTION

RTL DESCRIPTION HDL

FUNCTIONAL VERIFICATION

AND TESTING

LOGIC SYNTHESIS

GATE LEVEL NETLIST

LOGICAL VERIFICATION

AND TESTING

DESIGN SPECIFICATION


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OVERVIEW OF DIGITAL DESIGN WITH VERILOG HDL

1.HELLO VERILOG HDL:

From a modest beginning of early 1985 atGATEWAY DESIGN SYSTEM CORPORATION,now a part ofCADENCEDESIGN SYSTEMS,the verilog hardware descriptional language hasbecome an industry standard in digital circuit designing.Verilog came in tobeing as a language that was the first to support mixed levels of design

representationsComprising switches,gates,register transfer level and higher levels ofabstractions.

We have three types of levels

1.GATE LEVEL it might describe the logical gates and flip flops in adigital systems.

2.SWITCH LEVEL an HDL might describe the layout of the

wires,resistors & transistors on INTEGRATED CIRCUIT (IC) chip.

3.REGISTER TRANSFER LEVEL is an even higher level describes theregisters and transfers of vectors of information between registers.

FLOOR PLANNINGAUTOMATIC PLACE&ROUTE

PHYSICAL LAYOUT

LAYOUT VERIFICATION

IMPLEMENTATION


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2. MODELLING LEVELS IN VERILOG:

Verilog is both structural and behaviouralintervals of each module can be divided in to four levels depending onthe needs of the design.

MODELLING TECHNIQUES

BEHAVIOURAL MODELLING

.

DATA FLOW MODELLING

GATE LEVEL MODELLING

SWITCH LEVEL MODELLING

BEHAVIOURAL MODELLING:

This is the highest level of abstraction providedby verilog.A module can be implemented interms of the desired designalgorithm without concern for hardware implementation details.We coverassignments for all kinds,control constructs,time and event controls, tasks

and functions.

DATA FLOW MODELLING:

At this module is designed specifying the dataflow.Designers should be aware of how data flows between hardwareregisters and how data is processed in the designs.Data flow description ofa circuit is more concise than a gate level description.

GATE LEVEL MODELLING:


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The module is implemented interms of logicgates and interconnections between the gates.Design at this level is similarto describing a design interms of a gate level logic diagram.

SWITCH LEVEL:

This is the lowest level of abstraction providedby verilog.A module can be implemented interms of switches,storage nodeand the interconnections between them.Verilog allows the designers to mixand match all four levels of abstraction in a design.In a digital designcommunity,the term RTL is frequently used for a verilog description that

uses a combination of two behavioural and data flow constructs and isacceptable to logic synthesis tools.If a design contains fourmodules,verilog allows each of the modules to be written at a different levelof abstraction,the more flexible and technology dependent and inflexible.Asmall modification can cause a significant number of changes in thedesign.

Before we discuss the details of veriloglanguage,we must first understand basic hierarchial modeling concepts indigital design.The designer must use a good design methodology to doefficientVerilog HDL based design.

Now we discuss the typical designmethodological and illustrate how these concepts are translated to verilog.

3. DESIGN METHODOLGY:

There are two basic types of digital design

methodologies.

1.Top down methodology2.Bottom up methodology

In Top down design method ,we define the toplevel block and identify the sub blocks necessary to build the top levelblock. We further subdivide the cells that cannot be further divided.The topdown methodology is shown .

In Bottom up methodology,we first identify thebuilding blocks that are available to us.We build bigger cells using thesebuilding blocks.These cells are then used for higher level blocks until we


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build the top level block in the design.The bottom up design methodologyis shown.

Consider an example of designing a ripple carry

counter.In top down design method,we first have to specify the functionalityof the ripple carry counter which is the top level block.Then we implementthe counter with T flipflop.We build the T flipflop from the D flipflop. Webuild the T flipflop from the D flipflop and additional inverter gates.

Thus we break bigger blocks in to smaller subblocks until we decide that we cannot break up the blocks any further.Abottom up method flows in the opposite direction.We combine smallbuilding blocks and build bigger blocks.

TOP DOWN DESIGN

MACRO CELLS MACRO CELLS

LEAF LEAF LEAF LEAFCELL CELL CELL CELL

BOTTOM UP DESIGN

MACRO CELLS MACRO CELLS

LEAF LEAF LEAF LEAFCELL CELL CELL CELL

USE OF VERIWELL:Veriwell is a comprehensive implementaion of

verilog HDL originally developed by WELLSPRING SOLUTIONS ,Inc.Veriwell supports the verilog language as specified by the OVIlanguagepreference manual veriwell was first introduced in December1992 andwas written to be compatible with both the OVIstandard with cadenceverilog-xl.

USE OF VERILOG HDL:The verilog language provides the digital

designer with a means of describing a digital system a wide range of levels


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of abstraction and at the same time,provides access to computer aideddesign tools to aid in the design process at these levels.

Verilog allows hardware designers to express

their design with behavioural constructs deterring the details ofimplementation to a later stage of design in the design .An abstactrepresentation helps the designer explore architectural alternatives throughsimulations and to detect using bottle necks before detailed design begins.

Though the behavioural level of verilog is a highlevel description of a digital system,it is still a precise notation.Computer-aided-design tools I,e., programs,exist which will compile programs in theverilog notation to the level of circuits consisting of logic gates and

flipflops.One could then go to the lab and wire up the logical circuits andhave a functioning system.And other tools can compile programs inverilog notation to a description of the integrated circuit masks forveryscale integration circuit(VLSI). Therefore,with the proper automatedtools,one can create a VLSI description of a design in verilog and send theVLSI description via electronic mail to asilicon foundry in california andreceive the integrated chip in a few weeks by way of snail mail.Verilog alsoallows the designer to specific designs at the logical gate level using gateconstructs and the transistor level using switch constructs.

Our goal in the course is not ot create VLSIchips but to use verilog to precisely describe the functionality of any digitalsystem.For example,a computer .However,a VLSI chip designed by way ofverilogs behavioural constructs will be rather slow and be wastefull ofchiparea.The lower levels in verilog allow engineers to optimize the logicalcircuits and VLSI layouts to maximize speed and minimize area bof theVLSIChip.

TRENDS IN HDL:The speed and complexity of digital circuits has

increased rapidly.Designers have responded by designing at higher levelof abstraction.

The most popular trend currently is to design inHDL at an RTL level,because logic synthesis tools can create gate-levelnetlists from RTL level designs.Behavioural synthesis has recentlyemerged.As these tools improve,designers will be able to design directlyinterms of algorithms and the behaviour of the circuit and then use CADtools to do translation and optimization in each phase of the design.Behaviour modeling will be used more and more as behavioural synthesismatures.Until then,RTL design will remain very popular.


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A trend that is emerging for system level designis a mixed bottom-up methodology where the designers use either existingverilog HDL modules,basic buildings, or vendor-supplied core blocks to

quickly bring up their system simulation.This is to done to reducedevelopment costs and compress design schedules.For example ,considera system that has a cpu.graphics chip,i/o chip and a system bus.The cpudesigners would build the next generation cpu themselves at an RTLlevel.But they would use behavioural models for the graphics chip and thei/o chip and would buy a vendor-supplied model for the systembus.Thus,the system-level simulationFor the cpu could be up and running very quickly and along before the RTL

description for the graphics chip and the i/o chip are completed.

CONSTRUCTS& CONVENTIONS IN VERILOG

We are now to discuss the constructs andconventions in verilog.These conventions provide the necessaryframework for verilog hdl .The basic lexical conventions used by verilog hdlare very similar to the C language.

Verilog is a case sensitive language.Allkeywords are written in the lowercase.

BASIC CONCEPTS:

Comments

Comments can be inserted in the code forreadability and documentation.There are two ways to write comments.Aone line line comment starts with //.Verilog skips from that point to theend of that line.A multiple line comment starts with /* and ends with */.

Example

// This is a one line comment.// *This is a mutiple line comment*/

Operators


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Operators are of three types:-

(1) Unary

(2) Binary(3) Ternary

Unary operators precede the operand.

Example

A=~b;//~is a unary operator.

Binary operators appear between two operands.

Example

A=b&&c;// is a binary operator.

Ternary operators are two separate operators that separate two operands.

Example

A=b?c:d;//?: is a ternary operator.

Number specification

There are two types of number specification inverilog they are

Sized

Unsized

Sized numbers are represented as

is written only in decimal and specifies the number of bits inthe number.Legal base formats are decimal (d), hexadecimal (h),binary(b) and octal (o).


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Example

4b1001 - This is a 4 bit binary number.

12habc - This is a 12 bit hexadecimal number.

16d255 - This is a 16 bit decimal number.

Unsized numbers are numbers that are specified a base formatspecification and are decimal numbers by default.Numbers that are writtenwithout a size specification have a default number of bits that is machinespecific.

X or Z Values

Verilog has two symbols for unknown and highimpedence values.There values are very important for modeling realcircuits.An unknown value is denoted by x.A high impedence value isdenoted by z.

Example

1bx - This is one bit unknown number.8hz - This is a eight bit high impedence number.

IDENTIFIERS AND KEYWORDS

Keywords are identifiers reserved to define thelanguage constructs.Keywords are written in lower case.

Identifiers are made up of alpha numericcharacters, the underscore(_) and the dollar sign ($) and are casesensitive .Identifier start with an alphabet or an underscore and cannotstart with a number or$.

Example


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Reg a;//reg is a keyword, a is an identifier.

Input clk;/*input is a keyword,clk is an identifier.*/

DATA TYPES IN VERILOG

Verilog supports four values and eight strengthsto model the functionality of real hardware.There 4 levels are:

0 Logic zero False condition

1 Logic one True conditionX Unknown value -Z High -

In addition to logic values,strengths levels areoften used to resolve conflicts between drivers of different strength indigital circuits.Value levels 0 or 1 can have strength levels as listedbelow:supply strong pull large weak medium small high impedence.

NETS

Nets represent connection between hardwareelements.Just as in real circuits,nets have continuously driven on them bythe outputs of the devices that they are connected to.

Example

Wire a;

In the above figure,net a is connected to theoutput of AND gate.Nets are primarily declared with keyword wire.Netsare one bit value by default unless they are declared explicitly as vectors.

REGISTER


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Registers represent data storageelements.Registers retain value until another value is placed on to them.Register data types declared by keywords reg.

Example

Reg a,b;

VECTORS

Nets are register data types can be declared as

vectors .Vectors have multiple bit widths.

Example

Wire[7:0]a,b;

Reg[3:0]a,b;

INTEGERS

It is a general data types used for manipulatingquantities.Integers are declared by the keyword integer. Example:integer counter; /* general purpose variable used as counter */ initialcounter = 1;// one is stored in counter.

REALS

Real number constants and real data types aredeclared with keyword real.When a real value is assigned to an integerthe real number is rounded off to the nearest integer.

Example

Real a; initial a=4.23

TIME


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Verilog simulation is done with respect tosimulation time.A special time register data types is used in verilog to storesimulation.The keyword is time.The system function $time is invoked to

get the current simulation time.

Example

Time t; //define a time variable t.

Initial

T=$time; // save the current simulation time.

PARAMETER

Verilog allows constants to be defined in themodule by the keyword parameter.Parameters cannot be used asvariables.

Example

Parameter a=5; //defines a constant

SYSTEM TASKS

Verilog provides standard system tasks to docertain routine operations.All system tasks appear in the form

$.Operations such as displaying on the screen, monitoringvalues of nets,stopping and finishing are done by system tasks.

Displaying information

$display is a main system task for displayingvalues of variables or strings or expressions.

Example

$display(p1,p2,.pn);


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where p1,p2,..pn are variables or expressions.

Monitoring information

Verilog provides a mechanism to monitor asignal when its value changes.This facility is provided by $monitor task.

Example

$monitor(p1,p2,..pn);where p1,p2,pn can be variables or quoted strings.

$monitor continuously monitors the values ofthe variables or signals specified in the parameter list and displays allparameters in the list whenever the value of any one variable or signalchangesHence $monitor needs to be invoked only once.

Stopping and finishing in a simulation

1. The task $stop is provided to stop during a simulation.

Example

$stop

The $stop tasks puts the simulation in aninteractive mode.The designer can then debug a design from interactivemode. The $stop task is used whenever the designer wants to suspend a

simulation and examine the values of simulation in the design.

2.The task $finish terminates the simulation.

Example

$finish;

COMPILER DIRECTIVES


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Compiler directives are provided in verilog.Allcompiler directives are defined by using the constuct.We dealwith the two most useful compiler directives.

1. define2. include

The define is used to define text macros inverilog .The verilog compiler substitutes the text of the macro where ever itencounters a.

The include directive allows you to includeentire contents of a verilog source file in another verilog file during

compilation.

Two other directives are available they are

ifdef

timescaleare frequently used.

COMPONENTS OF VERILOG

MODULE

Verilog provides the concepts of a module.A module is the

basic building block in verilog.A module can have an element or acollection of low level design blocks.Typically,elements are grouped in tomodules to provide common functionality that is used at many places in thehigher level block through its port interface (inputs or ouputs), but hides theinternal implementation.This allows the designer to modify moduleinternals without affecting the rest of the design.

A module definition always begins with the keywordmodule.The module name,port list declarations and optional parameters

must first come in a module definition.The syntax of module with modulename and module terminal list is shown below:

Module();


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.

.

.endmodule.

The five components of within a moduledeclaration,data flow statements,instantiation of lower levelmodules,behaviour blocks and tasks or functions.An endmodule mustalways come in module definition.

COMPONENTS OF SIMULATION

Once a design block is completed,it must betested.The functionality of the design blocks can be tested by applyingstimulus and checking results.We call such a block the stimulus block.Thestimulus block is also commonly called a testbench.

Ports

Ports provide the interface by which the modulecan communicate with its environment.For example, the input or outputpins of an IC chip are its ports.

The environment can interavt with its moduleonly through its ports.The internals of the module are not visible to theenvironment.This provides a power flexibility to the designer.The internalsof a module can be changed without affecting the environment as long asthe interface is not modified.Ports are also reffered to as terminals.Ports

can be declared as input port or output port or bi-directional port based onthe direction of the direction of the port signal.

The respective keywords are:

Keyword Type of portInput Input portOutput Output port

Inout Bi-directional port

GATE LEVEL INSTRUCTIONS


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In gate level description,the circuit is describedin terms of gates like and,nand,or,xor,nor etc.Hardware design at this level

is intuitive to the other user with the basic knowledge of digital logicdesign.Since it is possible to see a one to one correspondence betweenthe logic circuit diagram and the verilog description.

Gate types

All logic circuits can be designed using basicgates.Verilog supports basic logic gates as predefined primitives.There aretwo classes of basic gates:

1. and/or gate2. buf/not gate

and/or gates have one scalar output and multiple scalar inputs.The firstterminal in the list of gate terminal is an output and the other terminals areinputs.The and/or gates available in verilog are:

and or xornand nor xnor

Example

And a1(z,x,y);Where x,y are inputs and z is the output of the and gate a1.

Buf/not gates have one or more scalar outputs and only one scalarinput.The last terminal in the portlist is the input.Two basic buf/not gateprimitives are provided in verilog namely buf gate and not gate.

DATA FLOW INSTRUCTIONS

In a complex design where the number of gatesare very large,design at a high level of abstraction is necessary.Data flowmodeling provides a provides a powerful way for this purpose.Verilogallows a circuit to be in terms of data flow between registers rather than


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between individual gates.Data flow modeling describes a design interms ofexpressions of primitive gates.

Assignment statement

Assignment statement is used to drive a valueon to a net.Assignment statement starts with a keyword assign.

Example

Assign Assign out =i1 & i2;Assign {carry,sum} =a+b;

Expressions

Expressions are constructs that combineoperators and operands to produce a result.

Example

A & bA + b

Operands

Operands can be any of the data types definedpreviously.They can be constants,integers,real,numbers,nets,registers ortime.

Example

C = a-b; // a and b are operands

Operators

Operators act on the operands to producedesired results.Verilog provides various types of operators.Operators can


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be arithmetic,logical,relational,equality,bitwise, reduction,shift,concatenation or conditional.Some of these operators are similar to theoperators used in C language.Each operator type is denoted by a

symbol.Let us discuss each of the operator types in detail:

Arithmetic operators

Arithmetic operators can be unary andbinary.Binary arithmetic operators are:

* Multiply/ Divide+ Add- Subtract

% modulus

Examples

A*b -This operator multiplies a and b.A%b-This operator gives the remainder.The operators + and also work as unary operators.They are

used to specify the positive or negative sign of the operand.

Logical operators

Logical operators available in verilog are:

Logical and (&&)Logical or (||)Logical not (!)

The operators && and || are binary operators,while logical not is an unary operator.Logical operators always evaluate toa one bit value either 0,1 or x.


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Examples

A && b // Evaluates logical and of a,b

A || b // Evaluates logical or of a,b

Relational operators

Verilog provides 4 relational operators given by:

If relational operators are used in anexpression,the expression returns a logical value of one,if it is true andzero if it is false.

Examples

A Greater than

< Lesser than>= Greater than or equal to


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A==b /* compares logically a and b returns 1If true and 0 if false */

Bitwise operatorsBitwise operators available in verilog are:

~ Negation& And

| Or^ xor^~ xnor

Bitwise operators perform a bit by bit operationon two operands.

Examples

~x //negation of xx^y // bitwise xor of x and y

Reduction operators

Reduction operators are nand (-&), and(&),or(|),nor(~|),xor(^) and xnor(~^,^~).

Reduction operators take only one operand.

They perform a bitwise operation on a single vector operand and yield aone bit result.The difference is that bitwise operations are on bits from twodifferent operands,whereas reduction operations are on the bits of thesame operand. They work bit by bit from right to left.

Shift operators

Shift operators are right shift (>>) and left shift(


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Y = x>>1; /* shift right 1 bit,0 filled inMSB operation. */

Concatenation operator

The concatenation operator ({,}) provides amechanism to append multiple operands.The operands must besized.Unsized operands are not allowed because the size of each operandmust be known for computation of the size of the result.Operands can bescalar nets or registers,vector nets or registers,bit select or sized

constants.

Example

Y={b,c};// appends b and c to result y

Conditional operator

The conditional operator (?:) takes threeoperands.

Usage

Conditional expr ? true expr: false expr;

The conditional expression is first evaluated.Ifthe result is true,then the true expression is evaluated.If the result is

false,then the false expression is evaluated.

Example

Assign out = control ? in1 : in0;

If the expression is true in1 is assigned to outand if the expression is false in0 is assigned to out.


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Operator type Operator symbol Operationperformed

Number ofoperands

Arithmetic */+-%

MutiplyDivideAddSubtractModulus

TwoTwoTwoTwoTwo

Logical !&&||

Logical negationLogical andLogical or

OneTwoTwo

Relational >=

>


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Verilog provides designers the ability todescribe the design functionality in an algorithmic manner.In otherwords,the designer describes the behaviour of the circuit.Thus behavioral

modeling represents the circuit at a very high level of abstraction.Design atthis level resembles C programming more than than it resembles digitalcircuit designing.

Structured procedures

There are two structured procedure statementsin verilog .

Always

Initial

These statements are the two most basicstatements in behavioural modeling.All other behaviour statements canappear only inside these structured statements.

initial statement

all statement inside an initial statementconstitute an initial block.An initial block starts at time zero,executes onceduring a simulation and then does not execute again.Multiple behaviouralstatements must be grouped typically using the keywords begin and end.The initial block is typically used for initialization,monitoring waveforms andother processes that must be executed only once during the entiresimulation time.

Example

The following module illustrates the use of initial statement.

Module stimulus;Begin

#5 a= 1b1;#5 b=1b0;endendmodule


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In the above module,a will be assigned a valueof 1 at time 5 and b will be assigned value of 0 at time 10.

always statement

All statements inside an always statementconstitute an always block.The always statement starts at zero time andexecutes the statements in the block continuously in a digital circuit.

Example

A clock generator module that toggles the clock signal every halfcycle is shown.In real circuits,the clock generator is active from time zeroto the time as long as the circuit is powered on.

module clock;reg clk;initialclk=1'b0;always

#10 clk=~clk;initial

#100 $finish;endmodule

In the above module,the always statement

starts at time zero and executes the statement clk=~clk for every 10 timeunits.

The simulation must be halted inside an initialstatement by the use of $finish or $stop statements.

Timing control

Various behavioural timing control constructs

are available in verilog.Timing controls provide a way to specify,thesimulation time at which procedural statements will execute.

There are three methods of timing control:


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1. Delay based timing control.2. Event based timing control.

3. Level sensitive timing control.

Delay based timing control

This can be specified by a number,identifier ora mintypmax expression.There are three types of delay control.They are:

1. Regular delay control

2. Intra-assignment delay control3. Zero delay control

Regular delay control

It is used when a non zero delay is specified tothe left of a procedural assignment.

Example

InitialBeginX=0; //no delay control#10 y=1; /* delay control with the nuber delay execution of y=1 by 10units*/end

Intra-assignment delay control

Instead of specifying delay control to the left ofthe assignment,it is possible a delay to the right of the assignmentoperator.

Zero delay control

It is a method that the statement is executed,last after all other statements in that simulation time are executed.


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Event based timing control

An event is the change in the value of a register

or a net.There are four types of event based timing control namely,Regularevent,Named event,Event OR control and Level sensitive timing control.

Event OR timing control

Sometimes atransition of any one of multiplesignals or events can trigger the execution of the statement or the block ofstatements.This is expressed as an OR of events or signals.The list of

events or signals expressed as an OR is also known as a sensitivitylist.The keyword or is used to specify multiple triggers.

Example

always@(reset or clk or d); /* wait for reset or clk or d to change */beginif(reset) //if reset is high,set q to zeroq=1b0;else if(clk) // if clk is high,set q to dq=d;end

Level sensitive timing control

Verilog provides level sensitive timing control

that is the ability to wait for a certain condition to be true before astatement is executed.

Conditional statement

Conditional statements are used for makingdecisions.These conditions decide whether or not a statement should beexecuted.Keywords if and else are used.

Case statement

The keywords case,endcase and default areused in the case statement.
mailto:always@(resetmailto:always@(reset


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Example

//Execute statements based on timer ic 8253-control signalreg [1:0] timer ic 8253;..case (timer ic 8253)2d0: y=x+z;2d1: y=x-z;2d2:y=x*z;

default: $display(invalid signal);endcase

For loop

The keyword for is used to specify thisloop. The for loop contains three parts.

1. initial condition.2. a check to see if the terminating cognition is true.3. a procedural assignment to change the value of the control

variable.

Example

Integer count;Initial

For (count =0;count


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sum

Behavioral synthesis

Register level- 20% technology dependent

Logic synthesis

Gate level -- 100% technology dependent

-

Data[0]

Data[15]

Data[0]

0]Data[15]

Summ

MEM

Clock

Clearaddress

Clear

sum


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Important ConsiderationsYou need your network identification card (NIC) ID for licensing the

Quartus II software. Your NIC number is a 12-digit hexadecimal number thatidentifies the Windows NT workstation that serves Quartus II licenses. Networked(or floating node) licensing requires an NIC number or server host ID. When

obtaining a license file for network licensing, you should use the NIC number fromthe PC that will issue the Quartus II licenses to distributed users over a network.You can find the NIC number for your card by typing ipconfig /all at a commandprompt. Your NIC number is the number on the physical address line, without thedashes.

Installing the Quartus II SoftwareYou need administrative privileges to install the software.

Refer to Installing the Quartus II Software in the Quartus II Installation &Licensing Manual for PCs, which is included on the CD-ROM (in DOC Folder),for the software installation instructions. After the software finishes installing, youmust request and install a license to enable it.

Setting Up LicensingBefore using the Quartus II software, you must request a license file from the

Altera web site at www.altera.com/licensing and install it on your PC. When yourequest a license file, Altera e-mails you a license.dat file that enables thesoftware. To obtain a license, perform the following steps:

1. Log on to the Altera web site at www.altera.com/licensing.2. Click Quartus II Web Edition Software.3. Follow the on-line instructions to request your license. A license file will be

E-mailed to you.4. To install your license, refer to Specifying the License File in the Quartus

II Installation & Licensing Manual for PCs, included on the CD-ROM (inDOC Folder).


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A field programmable gate array (FPGA) is a semiconductor device containing

programmable logic components and programmable interconnects. The programmable

logic components can be programmed to duplicate the functionality of basic logic gates

such as AND, OR, XOR, NOT or more complex combinational functions such asdecoders or simple math functions. In most FPGAs, these programmable logic

components (or logic blocks, in FPGA parlance) also include memory elements, which

may be simple flip-flops or more complete blocks of memories.

Features in common with FPGAs:

Large number of gates available. CPLDs typically have the equivalent of thousands to

tens of thousands of logic gates, allowing implementation of moderately complicated dataprocessing devices. PALs typically have a few hundred gate equivalents at most, while

FPGAs typically range from tens of thousands to several million.

CPLD stands forComplex Programmable Logic Device. It is a programmablelogic device with complexity between that of FPGAs and PALs, and architecturalfeatures from both. The building block of a CPLD is the macro cell, whichcontains logic implementing disjunctive normal form expressions and morespecialized logic operations

Complex Programmable Logic Devices (CPLD) utilize a matrix of "Sum-of-Products" logic function with a global interconnection


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