“What Will You Invent With The Latest Converter Innovations?”

Gil EngelSenior Staff Design Engineer

Analog Devices High Speed Converter Group

January 29, 2014

Introduction• There is a rapid expansion of consumer demand for data services of all

types.• Cable service providers

– Work to improve video quality from analog to digital to high definition.– Include internet service at higher and higher data rates.

• Wireless service providers– Move from analog to digital cellular to support more voice services.– Upgrading networks from 3G to LTE and beyond.

• Backhaul service providers– Must upgrade systems to support increased traffic bandwidth– Move to optical.

January 29, 2014 2

Introduction• There is a rapid expansion of consumer demand for data services of all

types.• Cable service providers

– Work to improve video quality from analog to digital to high definition.– Include internet service at higher and higher data rates.

• Wireless service providers– Move from analog to digital cellular to support more voice services.– Upgrading networks from 3G to LTE and beyond.

• Backhaul service providers– Must upgrade systems to support increased traffic bandwidth– Move to optical.

• Customers still expect data services at a nominal cost regardless of amount of data transferred!

January 29, 2014 3

Outline

I. Driving Applications for Mixed SignalII. Next Generation Converter CapabilitiesIII. ADC & DAC InnovationsIV. New Architectural OpportunitiesV. Conclusions

January 29, 2014 4

Outline

I. Driving Applications for Mixed Signal

January 29, 2014 5

ADC Timeline: Driving Application

January 29, 2014 6

1980 85 90 2010050095

Driving Applications

Mil/Aero

Instrumentation

Consumer Computer

Telecom Broadband

Networked Multimedia

The Driving Applications

January 29, 2014 7

Automotive Applications

January 29, 2014 8

Advanced TV: Analog Content Will Double in Three Years

January 29, 2014 9

Converters: Doorway Between Analog & Digital

January 29, 2014 10

Light

Sound

RF

Pressure & Flow

Speed

Proximity

ADC Digital SignalProcessingTemp

Amp DAC

SharedMemory

…SPII2C I2CSPI

SPI

Power Management

Amp

Digital Domain Analog Domain

Control / MCU

Motion

Analog Domain

-120

-100

-80

-60

-40

-20

0

0 37.5

Converter Performance = Capacity

January 29, 2014 11

2nd3rd

SNR THDSFDRNSD d

B

Frequency (MHz)

BW

Outline

I. Driving Applications for Mixed SignalII. Next Generation Converter Capabilities

January 29, 2014 12

Applications (Speed vs. Accuracy)

January 29, 2014 13

Bits of Resolution (also dynamic range, SNDR)

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

64 640 6,400 64,000 640,000 6,400,000

8 10 12 14 16 18 206 22 24

1,000 10,000 100,000 1,000,000 10M100Precision in Parts per Unit

100kHz

10kHz

1kHz

1GHz

100MHz

10MHz

1MHz

Sp

ee

d /

Ba

nd

wid

th

10GHz

Process Control PLC/DCS

DVD Audio CT

UltrasoundFlat Panel

SONET

Distance/ Level

Industrial Automation

DVD VideoDVC

Cable TV

Defense/Aero Comms

Bio Instruments

MRI

Precision Optics

Weigh Scale

Water Analysis

Digital X-Ray

Building Automation

Precision Measurement

Digital CameraAuto Radar

Radar

Digital Oscilloscope

Monitor & Control

Spectrum Analyzer

DSL

Motor Control

High-Performance Frontier

Low-Performance PatientMonitoring

Wireless Infrastructure

Applications (Speed vs. Accuracy)

January 29, 2014 14

Bits of Resolution (also dynamic range, SNDR)

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

64 640 6,400 64,000 640,000 6,400,000

8 10 12 14 16 18 206 22 24

1,000 10,000 100,000 1,000,000 10M100Precision in Parts per Unit

100kHz

10kHz

1kHz

1GHz

100MHz

10MHz

1MHz

Sp

ee

d /

Ba

nd

wid

th

10GHz

Process Control PLC/DCS

DVD Audio CT

UltrasoundFlat Panel

SONET

Distance/ Level

Industrial Automation

DVD VideoDVC

Cable TV

Defense/Aero Comms

Bio Instruments

MRI

Precision Optics

Weigh Scale

Water Analysis

Digital X-Ray

Building Automation

Precision Measurement

Digital CameraAuto Radar

Radar

Digital Oscilloscope

Monitor & Control

Spectrum Analyzer

DSL

Motor Control

High-Performance Frontier

Low-Performance PatientMonitoring

Wireless Infrastructure

High Speed

Precision

Raw performance dimensions for HS ADCs/DACs

January 29, 2014 15

Trade-off Trade-off

Trade-off

Performance Metrics – f70, FOM, BW, SNDR

• SFDR – Spurious Free Dynamic Range• f70 – Frequency at which SFDR falls below 70dBc.• FOM – Efficiency of conversion

Simply put: higher score to the converter consuming lower power for a given SNDR and given bandwidth.

R. Schreier’s figure of merit:

• BW – Bandwidth synthesized or received.• SNDR – Signal to Noise plus Distortion Ratio

January 29, 2014 16

Digital-to-Analog Converter Trends

January 29, 2014 17

199419961998200020022004200620082010201220141

10

100

1000

10000

5

5050

120220

500340

Next Gen

Year

f70[

MH

z]

Analog-to-Digital Converter Trends

January 29, 2014 18

Analog-to-Digital Converter Trends

January 29, 2014 19

PrecisionHigh Speed

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

10 20 30 40 50 60 70 80 90 100 110 120

SNDR [dB]

BW

[H

z]

FlashFoldingPipelineSAROversamplingIdeal Sampler with 1psrms Jitter

Performance Survey (ISSCC 1997-2007)(courtesy of Dr. Boris Murmann, Stanford)

January 29, 2014 20

Outline

I. Driving Applications for Mixed SignalII. Next Generation Converter CapabilitiesIII. ADC & DAC Innovations

January 29, 2014 21

DAC - Code Dependent Output Impedance

January 29, 2014 22

xIIN

OP 12

20

With digital input x:

11 x

xIIN

ON 12

20

Ref. Lin, et al., ISSCC, 2009

DAC - Code Dependent Output Impedance(cont.)

January 29, 2014 23

It can be shown:

Biased on cascode minimizes “Zon-Zoff” improving HD3.

)1(2

2 0

x

ZZ

NOP

ONONLOPOPLONOPOUT IZRIZRVVV

)1(2

2 0

x

ZZ

NON

....

)()2(

1

2

22 3

00

2

0 xfZfZ

RxIRV

NLN

LOUT

)()2(

1

4

2

00

2

3 fZfZ

RHD

NL

Ref. Lin, et al., ISSCC, 2009

DAC – Timing Error Dependent Distortion

January 29, 2014 24

Process mismatch will result inclock-to-out mismatch (σt).

Every segment will have a different timing error resulting in data dependent timing errors.

Ref. Doris, et al., Proc. ISCS, 2003Y. Tang, et al., JSSC, 2011

DAC – Timing Error Dependent Distortion(cont.)

January 29, 2014 25

Each segment has a random timing error and may also have a systematic error.

The timing error is integrated among the bits toggling within a period.

SamplePeriod

Data-dependentσt timing error

Timing error limits performance for high frequency applications. Timing Error Compensation demonstrated recently.

Ref. Doris, et al., Proc. ISCS, 2003Y. Tang, et al., JSSC, 2011

DAC – Quad-switch current steering:Minimizes data-dependent settling errors

January 29, 2014 26

By introducing a second pair of switches transitions occur even when data is not changing.

Ref. - Schafferer, ISSCC 2004 G. Engel, ISSCC 2012

LTE Carrier centered at 2.9GHz @3.2GSPS

January 29, 2014 27

>66dBc

ACLR >66dBc for 18MHz BW output at 2.9GHz

Ref. - G. Engel, ISSCC 2012

Time-interleaved ADCs: the basic idea

January 29, 2014 28

• Sample Vin with M identical converters in a round-robin (cyclic) fashion

• The sample rate of each converter is only fs/M

• Power and area grow linearly with M

Time-interleaved ADCs: the reality

January 29, 2014 29

M=4 in this example

Discrete versus Continuous Time DS

January 29, 2014 30

• Discrete time DS samples the input directly– Input structure same as Nyquist rate pipeline ADC, switched cap– Loop filter is discrete time, H(z)– switched cap poles and zeros

• Continuous time DS samples after the loop filter– Input structure is passive– Loop filter is continuous time, LF(f) “real” poles and zeros, generally need tuning

• Either loop filter can be lowpass or bandpass

LOOP FILTERQUANTIZER

+-

DA

C

ADC

MODULATOR

DECIMATIONFILTER

Pushes the switches “back”

Ref. H. Shibata, et al., ISSCC, 2012G. Manganaro, “Advanced Data Converters”

Continuous Time DS

January 29, 2014 31

• Multiple possibilities of digitization– Low pass– Band pass– Quadrature, Complex…

Measured spectra from: H.Shibata, “A DC-to-1GHz Tunable RF ΔΣ ADC Achieving DR = 74dB and BW = 150MHz at f0 = 450MHz Using 550mW”, ISSCC 2012

Low pass

Band pass

Ref. H. Shibata, et al., ISSCC, 2012

Outline

I. Driving Applications for Mixed SignalII. Next Generation Converter CapabilitiesIII. ADC & DAC InnovationsIV. New Architectural Opportunities

January 29, 2014 32

Cell Sites

Mobile Backhaul

RadioControllerSite

Pre-Aggr.Site Aggr.

SiteMetro

NetworkAggr.Site

Wireless Infrastructure Microwave Radio Links and Topologies

January 29, 2014 33

Transmit Architectures Low/High IF Sampling with Image Rejection

January 29, 2014 34

• Familiar Heterodyne Architecture – Quadrature Balance Errors need to be managed– Offset and gain corrected in DAC– Phase corrected in DUC

LPF

Channel Select Filter

DAC

DSP

DSP

DSP Cluster

Network Interface

Clock Distribution

LPF DAC

DUC& PAPR

TuningControl

900

+ωRF

LO Feedthrough

Unsuppressed Sideband

Gain, Phase & offset errors

PA pre-distortion observation path

DSPBPF ADC

Antenna

Power Amplifier

BPF

Band Select Filter

Power Detect and Gain Control

ωRF +ωDAC/4-ωDAC/4

PTARGET

Move Converter Closer to Antennae

January 29, 2014 35

• Familiar Heterodyne Architecture – Quadrature Balance Errors need to be managed– Offset and gain corrected in DAC– Phase corrected in DUC

LPF

Channel Select Filter

DAC

DSP

DSP

DSP Cluster

Network Interface

Clock Distribution

LPF DAC

DUC& PAPR

TuningControl

900

Gain, Phase & offset errors

PA pre-distortion observation path

DSPBPF ADC

Antenna

Power Amplifier

BPF

Band Select Filter

Power Detect and Gain Control

Transmit ArchitecturesDirect RF Synthesis

January 29, 2014 36

• Potential for Direct to RF Synthesis– Eliminate Quadrature balance errors.– No gain or offset errors between converters.– No phase error.

Multi-Band: 1800MHz + 2100MHz + 2600MHz

January 29, 2014 37

• Fdac = 2457.6MHz• 4C WCDMA: PAR = 11.7dB, (no additional backoff)• FSC = 28mA

Transmit ArchitecturesMulti-Band Direct RF Synthesis

January 29, 2014 38

• Transmit multiple bands from a single converter

Heterodyne Receive Architectures

January 29, 2014 39

BPF

Clock Distribution

DSPBPF ADC

DSP

DSP

DSP Cluster

Network Interface

Antenna

• Conventional Heterodyne Receiver Architecture – Need frequency planning for MxN Mixer spurious– Different circuit & network optimization for different bands

Move Converter Closer to Antennae

January 29, 2014 40

BPF

Clock Distribution

DSPBPF ADC

DSP

DSP

DSP Cluster

Network Interface

Antenna

• Conventional Heterodyne Receiver Architecture – Need frequency planning for MxN Mixer spurious– Different circuit & network optimization for different bands

Receive ArchitecturesDirect RF Conversion

January 29, 2014 41

LPF

Clock Distribution

DSPRFADC

DSP

DSP

DSP Cluster

Network Interface

Antenna

• Potential to Directly to Convert from Antennae– Single LPF for full band.– Tremendous dynamic range requirement.

As the converter moves, performance requirements increase

The Dynamic Range Problem:Analog, Digital and the Converter

January 29, 2014 42

• Signal processing is the extraction of the desired signal from the “noise.”

• Moving to digital processing requires much better converter performance

Conclusions

January 29, 2014 43

Enables Innovative Technology

Innovative Technology

Enabled by Innovative Technology

Advanced High-Performance Converters

The Cloud

Conclusions

• Market shifts drive converter technology• New converter technologies enable innovative technology

– Communication Architectures– Defense/Aerospace Technology– Integrated functionality

• Next generation instrumentation and measurement equipment enables development of next generation converters

• WHAT WILL YOU INVENT WITH THE LATEST CONVERTER INNOVATIONS!

January 29, 2014 44

References1. DATA-OVER-CABLE SERVICE INTERFACE SPECIFICATIONS, DOWNSTREAM RF INTERFACE

SPECIFICATION, ISSUE 12, CM-SP-DRFI-I12-111117, CABLE TELEVISION LABORATORIES, INC., 17 NOVEMBER 2011.

2. “3GPP TS 45.005 RADIO TRANSMISSION AND RECEPTION (RELEASE 10)”, v10.4.0, MARCH 2012.3. B. RAZAVI, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN”, IEEE PRESS, PISCATAWAY, NJ,

1995.4. RUDY J. VAN DE PLASSCHE, “CMOS INTEGRATED ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG

CONVERTERS 2ND ED.”, KLUWER, DORDRECHT, THE NETHERLANDS, 2003.5. G. MANGANARO, “ADVANCED DATA CONVERTERS”, CAMBRIDGE UNIVERSITY PRESS, 2011.6. A. RODRIGUEZ-VAZQUEZ, F. MEDEIRO, & E. JANSSENS, “CMOS TELECOM DATA CONVERTERS”,

KLUWER ACADEMIC PUBLISHERS, 2003.7. C.-H. LIN, “A 12-BIT 2.9 GS/S DAC WITH IM3< -60DBC BEYOND 1GHZ IN 65NM CMOS”, IEEE JSSC,

DECEMBER 2009.8. S. LUSCHAS AND H.-S. LEE, “OUTPUT IMPEDANCE REQUIREMENTS FOR DACS”, IEEE

INTERNATIONAL SYMPOSIUM OF CIRCUITS AND SYSTEMS”, VOL. 1, 2003, PP. 861-864.9. G. ENGEL, “THE POWER SPECTRAL DENSITY OF PHASE NOISE AND JITTER: THEORY, DATA

ANALYSIS, AND EXPERIMENTAL RESULTS”, ANALOG DEVICES, AN-1067.10. P. SMITH, “LITTLE KNOWN CHARACTERISTICS OF PHASE NOISE”, ANALOG DEVICES, AN-741.11. K. DORIS, “MISMATCH-BASED TIMING ERRORS IN CURRENT STEERING DACS”, IEEE

PROCEEDINGS OF ISCAS, 2003.12. G. ENGEL, “A 14B 3/6GHZ CURRENT-STEERING RF DAC IN 0.18UM CMOS WITH 66DB ACLR AT

2.9GHZ”, IEEE ISSCC, 2012.January 29, 2014 45

References13. K. POULTON, “A 7.2-GSA/S, 14-BIT OR 12-GSA/S, 12-BIT DAC IN A 165-GHZ FT BICMOS

PROCESS”, VLSI SYMPOSIUM, 2011.14. Y. TANG, “A 14 BIT 200MS/S DAC WITH SFDR >78DBC, IM3 <-83DBC AND NSD <-163DBM/HZ

ACROSS THE WHOLE NYQUIST BAND ENABLED BY DYNAMIC MISMATCH MAPPING”, IEEE JSSC JUNE 2011.

15. H. Shibata, “A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW”, ISSCC 2012.

January 29, 2014 46

January 29, 2014 47