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Wideband, High GainVOLTAGE LIMITING AMPLIFIER
OPA699
SBOS261D – NOVEMBER 2002 – REVISED DECEMBER 2008
www.ti.com
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
Copyright © 2002-2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
FEATURES● HIGH LINEARITY NEAR LIMITING
● FAST RECOVERY FROM OVERDRIVE: 1ns
● LIMITING VOLTAGE ACCURACY: ±10mV● –3dB BANDWIDTH (G = +6): 260MHz
● GAIN BANDWIDTH PRODUCT: 1000MHz
● STABLE FOR G ≥ +4V/V● SLEW RATE: 1400V/µs● ±5V AND +5V SUPPLY OPERATION● LOW GAIN VERSION: OPA698
APPLICATIONS● TRANSIMPEDANCE WITH FAST
OVERDRIVE RECOVERY
● FAST LIMITING ADC INPUT DRIVER
● LOW PROP DELAY COMPARATOR
● NONLINEAR ANALOG SIGNALPROCESSING
● DIFFERENCE AMPLIFIER
● IF LIMITING AMPLIFIER
● OPA689 UPGRADE
DESCRIPTIONThe OPA699 is a wideband, voltage-feedback op amp thatoffers bipolar output voltage limiting, and is stable for gains≥ +4. Two buffered limiting voltages take control of the outputwhen it attempts to drive beyond these limits. This newoutput limiting architecture holds the limiter offset error to±10mV. The op amp operates linearly to within 20mV of thelimits.
The combination of narrow nonlinear range and low limitingoffset allows the limiting voltages to be set within 100mV ofthe desired linear output range. A fast 1ns recovery fromlimiting ensures that overdrive signals will be transparent to
the signal channel. Implementing the limiting function at theoutput, as opposed to the input, gives the specified limitingaccuracy for any gain, and allows the OPA699 to be used inall standard op amp applications.
Nonlinear analog signal processing circuits will benefit fromthe OPA699 sharp transition from linear operation to outputlimiting. The quick recovery time supports high-speed applica-tions.
The OPA699 is available in an industry-standard pinout in anSO-8 package. For lower gain applications requiring outputlimiting with fast recovery, consider the OPA698.
OPA699
OPA699
VIN
RG374Ω
RF750Ω
CF4pF
CS18pF
VOUT
VOUT = –2VIN
VH
+5V
–5V
VL
Low Gain, Improved SFDR Amplifier with Output Limiting
OPA6992SBOS261Dwww.ti.com
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
OPA699 SO-8 D –40°C to +85°C OPA699ID OPA699ID Rails, 100" " " " " OPA699IDR Tape and Reel, 2500
Supply Voltage ................................................................................. ±6.5VInternal Power Dissipation ........................... See Thermal CharacteristicsInput Voltage Range ............................................................................ ±VSDifferential Input Voltage ..................................................................... ±VSLimiter Voltage Range ........................................................... ±(VS – 0.7V)Storage Temperature Range: D ..................................... –65°C to +125°CLead Temperature (SO-8, soldering, 3s) ...................................... +260°CJunction Temperature .................................................................... +150°CESD Resistance: HBM .................................................................... 2000V
MM ........................................................................ 200VCDM ................................................................... 1000V
NOTE: (1) Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may degradedevice reliability.
PIN CONFIGURATION
Top View SO
ABSOLUTE MAXIMUM RATINGS(1)
PACKAGE/ORDERING INFORMATION(1)
SINGLES DUALS DESCRIPTION
Output Limiting OPA698 Unity Gain Stable, Wideband
Voltage Feedback OPA690 OPA2690 High Slew, Unity Gain Stable
RELATED PRODUCTS
ELECTROSTATICDISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-ments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage.
ESD damage can range from subtle performance degradationto complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametricchanges could cause the device not to meet its publishedspecifications.
1
2
3
4
8
7
6
5
NC
Inverting Input
Noninverting Input
–VS
VH
+VS
Output
VL
NC = No Connection
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI websiteat www.ti.com.
OPA699 3SBOS261D www.ti.com
OPA699ID
0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)
AC PERFORMANCE (see Figure 1)Small Signal Bandwidth (VO < 0.5VPP) G = +6 260 220 215 210 MHz min B
G = +12 86 MHz typ CG = –6 269 MHz typ C
Gain Bandwidth Product (G ≥ +20) VO < 0.5VPP, G = +6 1000 820 800 750 MHz min BGain Peaking VO < 0.5VPP, G = +4 7.5 dB typ C0.1dB Gain Flatness Bandwidth VO < 0.5VPP 30 MHz typ CLarge-Signal Bandwidth VO = 4VPP 290 190 180 170 MHz min BStep Response
Slew Rate 4V Step 1400 1300 1200 1100 V/µs min BRise-and-Fall Time 0.5V Step 1.6 1.65 1.8 2 ns max BSettling Time: 0.05% 2V Step 8 ns typ C
Spurious-Free Dynamic Range, Even f = 5MHz, VO = 2VPP 67 64 62 60 dB min BOdd f = 5MHz, VO = 2VPP 87 85 84 80 dB min B
Differential Gain NTSC, PAL, RL = 500Ω 0.012 % typ CDifferential Phase NTSC, PAL, RL = 500Ω 0.008 ° typ CInput Noise Density
Voltage Noise f ≥ 1MHz 4.1 4.6 5.2 5.5 nV/√Hz max BCurrent Noise f ≥ 1MHz 2.0 2.5 2.7 2.9 pA/√Hz max B
DC PERFORMANCE (VCM = 0V)Open-Loop Voltage Gain (AOL) VO = ±0.5V 66 58 56 55 dB min AInput Offset Voltage ±1.5 ±5.0 ±6 ±7 mV max A
Average Drift — ±15 ±20 µV/°C max BInput Bias Current(4) +3 ±10 ±11 ±12 µA max A
Average Drift — ±15 ±20 nA/°C max BInput Offset Current ±0.3 ±2 ±2.5 ±3 µA max A
Average Drift — ±10 ±10 nA/°C max B
INPUTCommon-Mode Rejection Ratio Input Referred, VCM = ±0.5V 61 55 54 52 dB min ACommon-Mode Input Range(5) ±3.3 ±3.2 ±3.2 ±3.1 V min AInput Impedance
Differential-Mode 0.32 || 1 MΩ || pF typ CCommon-Mode 3.5 || 1 MΩ || pF typ C
OUTPUT VH = –VL = 4.3VOutput Voltage Range RL ≥ 500Ω ±4.1 ±3.9 ±3.9 ±3.8 V min ACurrent Output, Sourcing +120 +90 +85 +80 mA min A
Sinking –120 –90 –85 –80 mA min AClosed-Loop Output Impedance G = +4, f < 100kHz 0.8 Ω typ C
POWER SUPPLYOperating Voltage, Specified ±5 V typ C
Maximum — ±6 ±6 ±6 V max AQuiescent Current, Maximum VS = ±5V 15.5 15.9 16.3 16.6 mA max A
Minimum VS = ±5V 15.5 15.2 14.9 14.6 mA min APower-Supply Rejection Ratio +VS = 4.5V to 5.5V
+PSRR (Input Referred) 75 68 67 66 dB min A
TYP MIN/MAX OVER TEMPERATURE
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambienttemperature + 23°C at high temperature limit Test Level A specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperaturetested specifications.
(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value for information only.
(4) Current is considered positive out-of-node.(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.(6) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 12.(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
ELECTRICAL CHARACTERISTICS: VS = ±5VBoldface limits are tested at +25°C.G = +6, RF = 750Ω, RL = 500Ω, and VH = –VL = 2V, (see Figure 1 for AC performance only), unless otherwise noted.
OPA6994SBOS261Dwww.ti.com
OPA699ID
0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)
OUTPUT VOLTAGE LIMITERS Pins 5 and 8Output Voltage Limited Range ±3.8 typ CDefault Limit Voltage, Upper Limiter Pins Open +3.5 +3.3 +3.2 +3.1 V min A
Lower –3.5 –3.3 –3.2 –3.1 V max AMinimum Limiter Separation (VH – VL) 400 400 400 400 mV min BMaximum Limit Voltage — ±4.3 ±4.3 ±4.3 V max BLimiter Input Bias Current Magnitude(6) VO = 0
Maximum 50 60 62 64 µA max AMinimum 50 40 38 36 µA min AAverage Drift — 30 35 nA/°C max B
Limiter Input Impedance 3.4 || 1 MΩ || pF typ CLimiter Feedthrough(7) f = 5MHz –60 dB typ CDC Performance in Limit Mode VIN = ±0.7V
Limiter Offset Voltage (VO – VH) or (VO – VL) ±10 ±30 ±35 ±40 mV max AOp Amp Input Bias Current Shift(4) Linear ↔ Limited Operation 3 µA typ C
AC Performance in Limit ModeLimiter Small-Signal Bandwidth VIN = ±0.7V, VO < 0.02VPP 600 MHz typ CLimiter Slew Rate(8) 125 V/µs typ C
Limited Step ResponseOvershoot VIN = 0V to ±0.7V Step 250 mV typ CRecovery Time VIN = ±0.7V to 0V Step 1 1.9 2 2.1 ns max B
Linearity Guardband(9) f = 5MHz, VO = 2VPP 30 mV typ C
THERMAL CHARACTERISTICSTemperature Range Specification, I –40 to +85 °C typ CThermal Resistance Junction-to-Ambient
D SO-8 125 °C/W typ C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambienttemperature +23°C at high temperature limit Test Level A specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperaturetested specifications.
(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value for information only.
(4) Current is considered positive out-of-node.(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.(6) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 12.(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.(8) VH slew rate conditions are: VIN = +0.7V, G = +6, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar.(9) Linearity Guardband is defined for an output sinusoid (f = 1MHz, VO = 2VPP) centered between the limiter levels (VH and VL). It is the difference
between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.)Boldface limits are tested at +25°C.G = +6, RF = 750Ω, RL = 500Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted.
TYP MIN/MAX OVER TEMPERATURE
OPA699 5SBOS261D www.ti.com
AC PERFORMANCE (see Figure 2)Small Signal Bandwidth (VO < 0.5VPP) G = +6 234 200 190 180 MHz min B
G = +12 83 MHz typ CG = –6 242 MHz typ C
Gain Bandwidth Product (G ≥ +20) VO < 0.5VPP 880 700 650 600 MHz min BGain Peaking VO < 0.5VPP, G = +4 8 dB typ C0.1dB Gain Flatness Bandwidth VO < 0.5VPP, G = +6 30 MHz typ CLarge-Signal Bandwidth VO = 2VPP 250 200 190 180 MHz min BStep Response
Slew Rate 2V Step 1050 850 800 700 V/µs min BRise-and-Fall Time 0.5V Step 1.75 1.8 1.9 2.1 ns max BSettling Time: 0.05% 2V Step 8 ns typ C
Spurious-Free Dynamic Range, Even f = 5MHz, VO = 2VPP 64 61 60 58 dB min BOdd f = 5MHz, VO = 2VPP 70 69 67 65 dB min B
Input NoiseVoltage Noise Density f ≥ 1MHz 4.2 4.6 5.2 5.6 nV/√Hz max BCurrent Noise Density f ≥ 1MHz 2.1 2.6 2.8 3.0 pA/√Hz max B
DC PERFORMANCEOpen-Loop Voltage Gain (AOL) VO = VCM ± 0.5V 66 56 54 53 dB min AInput Offset Voltage ±2 ±6 ±7 ±8 mV max A
Average Drift — ±14 ±14 µV/°C max BInput Bias Current(4) +3 ±10 ±11 ±12 µA max A
Average Drift — ±25 ±25 nA/°C max BInput Offset Current ±0.4 ±2 ±2.5 ±3 µA max A
Average Drift — ±15 ±15 nA/°C max B
INPUTCommon-Mode Rejection Ratio Input Referred, VCM ±0.5V 58 54 53 52 dB min ACommon-Mode Input Range(5) VCM ±0.8 VCM ±0.7 VCM ±0.7 VCM ±0.6 V min AInput Impedance MΩ || pF typ C
Differential-Mode 0.32 || 1Common-Mode 3.5 || 1 MΩ || pF typ C
OUTPUT VH = VCM + 1.8V, VL = VCM – 1.8VOutput Voltage Range RL ≥ 500Ω VCM ±1.6 VCM ±1.4 VCM ±1.4 VCM ±1.3 V min ACurrent Output, Sourcing +70 +60 +55 +50 mA min A
Sinking –70 –60 –55 –50 mA min AClosed-Loop Output Impedance G = +4, f < 100kHz 0.2 Ω typ C
POWER SUPPLYOperating Voltage, Specified 5 V typ C
Maximum — +12 +12 +12 V max AQuiescent Current, Maximum VS = +5V 14.3 14.9 15.1 15.3 mA max A
Minimum VS = +5V 14.3 13.6 13.4 13.2 mA min APower-Supply Rejection Ratio VS = 4.5V to 5.5V
+PSRR (Input Referred) 70 dB typ C
OPA699ID
0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)
ELECTRICAL CHARACTERISTICS: VS = +5VBoldface limits are tested at +25°C.G = +6, RF = 750Ω, RL = 500Ω tied to VCM = +2.5V, VL = VCM –1.2V, and VH = VCM +1.2V, (see Figure 2 for AC performance only), unless otherwise noted.
TYP MIN/MAX OVER TEMPERATURE
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambienttemperature +23°C at high temperature limit Test Level A specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperaturetested specifications.
(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value for information only.
(4) Current is considered positive out of node.(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.(6) IVH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 12.(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.(8) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = VCM –1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar.(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM ±1VPP) centered between the limiter levels (VH and VL). It is the
difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
OPA6996SBOS261Dwww.ti.com
OUTPUT VOLTAGE LIMITERSMaximum Limited Voltage +3.9 V typ CMinimum Limited Voltage +1.1 V typ CDefault Limiter Voltage Limiter Pins Open VCM ±1.1 VCM ±0.9 VCM ±0.8 VCM ±0.7 V min BMinimum Limiter Separation (VH – VL) 400 400 400 400 mV min BMaximum Limit Voltage — VCM ±1.8 VCM ±1.8 VCM ±1.8 V max BLimiter Input Bias Current Magnitude(6) VO = 2.5V –15 µA typ CLimiter Input Impedance 3.4 || 1 MΩ || pF typ CLimiter Isolation(7) f = 5MHz –60 dB typ CDC Performance in Limit Mode VIN = VCM ±0.4V
Limiter Voltage Accuracy (VO – VH) or (VO – VL) ±15 ±30 ±35 ±40 mV max AOp Amp Bias Current Shift(4) Linear ↔ Limited Operation 5 µA typ C
AC Performance in Limit ModeLimiter Small-Signal Bandwidth VIN = ±0.4V, VO < 0.02VPP 450 MHz typ CLimiter Slew Rate(8) 100 V/µs typ C
Limited Step ResponseOvershoot VIN = VCM to VCM ±0.4V Step 55 mV typ CRecovery Time VIN = VCM ±0.4V to VCM Step 3 ns typ C
Linearity Guardband(9) f = 5MHz, VO = 2VPP 30 mV typ C
THERMAL CHARACTERISTICSTemperature Range Specification, I –40 to +85 °C typ CThermal Resistance Junction-to-Ambient
D SO-8 125 °C/W typ C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambienttemperature +23°C at high temperature limit Test Level A specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperaturetested specifications.
(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value for information only.
(4) Current is considered positive out of node.(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.(6) IVH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 12.(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.(8) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = VCM –1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar.(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM ±1VPP) centered between the limiter levels (VH and VL). It is the
difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.)Boldface limits are tested at +25°C.G = +6, RF = 750Ω, RL = 500Ω tied to VCM = +2.5V, VL = VCM –1.2V, and VH = VCM +1.2V, (see Figure 2 for AC performance only), unless otherwise noted.
OPA699ID
0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)
TYP MIN/MAX OVER TEMPERATURE
OPA699 7SBOS261D www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5VTA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
9
6
3
0
−3
−6
−9
−12
−15
NONINVERTING SMALL-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Nor
mal
ized
Gai
n (d
B)
1M 10M 100M 1G
VO = 0.5VPP
G = +12
G = +20
See Figure 1
G = +4
G = +6
6
3
0
−3
−6
−9
−12
−15
−18
INVERTING SMALL-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Nor
mal
ized
Gai
n (d
B)
1M 10M 100M 1G
VO = 0.5VPP
G = −12
G = −4
G = −6
See Figure 3
18
15
12
9
6
3
NONINVERTING LARGE-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Gai
n (d
B)
1M 10M 100M 1G
G = +6
VO = 7VPP
VO = 4VPP
VO = 1VPP
VO = 2VPP
See Figure 1
18
15
12
9
6
3
INVERTING LARGE-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Gai
n (d
B)
1M 10M 100M 1G
G = −6
VO = 7VPP
VO = 4VPP
VO = 1VPP
VO = 2VPP
See Figure 3
VH—LIMITER SMALL-SIGNALFREQUENCY RESPONSE
Lim
iter
Gai
n (d
B)
Frequency (Hz)
1M 10M 100M 1G
3
0
–3
–6
–9
VO = 0.02VPP
OPA699
750Ω
125Ω
0.02VPP + 2.0VDC
150Ω
VO
VH
VL
Open
0.7VDC
VL—LIMITER SMALL-SIGNALFREQUENCY RESPONSE
Lim
iter
Gai
n (d
B)
Frequency (Hz)
1M 10M 100M 1G
3
0
–3
–6
–9
OPA699
750Ω
125Ω
0.02VPP + 2.0VDC
150Ω
VO
VH
Open
VL
0.7VDC
VO = 0.02VPP
OPA6998SBOS261Dwww.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
SMALL-SIGNAL PULSE RESPONSE
VO
UT (
V)
Time (5ns/div)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VO = 0.5VPP
See Figure 1
LARGE-SIGNAL PULSE RESPONSE
VO
UT (
V)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
VO = 4VPPVH = –VL = 2.5V
See Figure 1
VH—LIMITED PULSE RESPONSE
Inpu
t and
Out
put V
olta
ge (
V)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
G = +6VH = +2VVIN = 0 → 0.7V
VOUT
VIN
VL—LIMITED PULSE RESPONSEIn
put a
nd O
utpu
t Vol
tage
(V
)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
−2.5
VIN
VOUT
G = +6VH = –2VVIN = 0 → 0.7V
LIMITED OUTPUT RESPONSE
Inpu
t and
Out
put V
olta
ge (
V)
Time (200ns/div)
2.5
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
−2.5
G = +6VH = 2VVL = −2V
VOUT
VIN
DETAIL OF LIMITED OUTPUT RESPONSE
Out
put V
olta
ge (
V)
Time (50ns/div)
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
VOUT
OPA699 9SBOS261D www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
HARMONIC DISTORTIONvs LOAD RESISTANCE
Har
mon
ic D
isto
rtio
n (d
Bc)
Load Resistance (Ω)100 1k
–55
–60
–65
–70
–75
–80
–85
–90
VO = 2VPPf = 5MHz
3rd-Harmonic
See Figure 1
2nd-Harmonic
5MHz HARMONIC DISTORTIONvs SUPPLY VOLTAGE
Har
mon
ic D
isto
rtio
n (d
Bc)
± Supply Voltage (V)2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
–60
–65
–70
–75
–80
–85
–90
VO = 2VPPRL = 500Ω
3rd-Harmonic
2nd-Harmonic
See Figure 1
HARMONIC DISTORTION vs FREQUENCY
Har
mon
ic D
isto
rtio
n (d
Bc)
Frequency (MHz)
0.5 1 10 20
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
3rd-Harmonic
See Figure 1
2nd-Harmonic
VO = 2VPPRL = 500Ω
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Har
mon
ic D
isto
rtio
n (d
Bc)
Output Voltage (VPP)
0.5 1.0 1.5 2.0 2.5 3.5 4.0 4.5 5.03.0 5.5 6.0 6.5 7.0 7.5 8.0
–50
–55
–60
–65
–70
–75
–80
–85
–90
3rd-Harmonic
See Figure 1
2nd-Harmonic
RL = 500ΩVH = –VL = VOPP /2 + 0.5Vf = 5MHz
HARMONIC DISTORTION vs NONINVERTING GAIN
Har
mon
ic D
isto
rtio
n (d
Bc)
Gain (V/V)
4 8 12 16 20
–55
–60
–65
–70
–75
–80
–85
–90
–95
VO = 2VPPRL = 500Ωf = 5MHz
3rd-Harmonic
2nd-Harmonic
HARMONIC DISTORTION vs INVERTING GAIN
Har
mon
ic D
isto
rtio
n (d
Bc)
Gain (V/V)
−4 −8 −12 −16 −20
−55
−60
−65
−70
−75
−80
−85
−90
VO = 2VPPRL = 500Ωf = 5MHz
3rd-Harmonic
2nd-Harmonic
OPA69910SBOS261Dwww.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
Har
mon
ic D
isto
rtio
n (d
Bc)
± Limit Voltage (V)0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
−40
−50
−60
−70
−80
−90
3rd-Harmonic
2nd-Harmonic
VO = 0VDC ± 1VPf = 5MHzRL = 500Ω
2-TONE, 3RD-ORDER INTERMODULATIONINTERCEPT
Inte
rcep
t Poi
nt (
+dB
m)
Frequency (MHz)
0 10 20 30 40 50
G = +6V/V38
36
34
32
30
28
26
24
22
20
OPA699
750Ω150Ω
500Ω
PO
VH
Open
OpenVL
PI
140
120
100
80
60
40
20
0
RECOMMENDED RS vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100 1000
Res
ista
nce
(Ω)
FREQUENCY RESPONSE vs CAPACITIVE LOADG
ain
to C
apac
itive
Loa
d (d
B)
Frequency (Hz)
1M 10M 100M 1G
18
15
12
9
6
3
0
VO = 0.5VPPG = +6
CL = 1000pF
CL = 100pF
CL = Open
CL = 10pF
OPA699
750Ω
RS
150Ω
CL1kΩ(1)
Note: (1) 1kΩ(1) is optional.
VIN
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100 1k 10k 100k 1M 10M
Vol
tage
Noi
se D
ensi
ty (
nV/√
Hz)
Cur
rent
Noi
se D
ensi
ty (
pA/√
Hz)
Voltage Noise (4.1nV/√Hz)
Current Noise (2pA/√Hz)
OPEN-LOOP GAIN AND PHASE
Ope
n-Lo
op G
ain
(dB
)
Frequency (Hz)
10k 100k 100M10M1M 1G
70
60
50
40
30
20
10
0
–10
Ope
n-Lo
op P
hase
(°)
0
–30
–60
–90
–120
–150
–180
–210
–240
VO = 0.5VPP
Phase
Gain
OPA699 11SBOS261D www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
VOLTAGE RANGES vs TEMPERATURE±V
olta
ge R
ange
s (V
)
Ambient Temperature (°C)−50 −25 7550250 100
5.0
4.5
4.0
3.5
3.0
Output Voltage Range
VH = –VL = 4.3V
Common-Mode Input Range
LIMITED VOLTAGE RANGE vs TEMPERATURE
Vol
tage
(V
)
Ambient Temperature (°C)−50 −25 7550250 100
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
VH
VL
VH and VL left openInternal Default Limited Voltage
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Lim
iter
Inpu
t Bia
s C
urre
nt (
µA)
Limiter Headroom (V)
0 1.00.5 4.0 4.53.53.02.52.01.5 5.0
100
75
50
25
0
–25
–50
–75
–100
Maximum Over Temperature
Minimum Over Temperature
Limiter Headroom = +VS – VH= VL – (–VS)
Current = IVH or –IVL
SUPPLY AND OUTPUT CURRENTSvs TEMPERATURE
Sup
ply
Cur
rent
(m
A)
Ambient Temperature (°C)–50 –25 0 755025 100
20
18
16
14
12
10
Out
put C
urre
nts
(mA
)
100
98
96
94
92
90
Output Current, Sourcing
Supply Current
Output Current, Sinking
COMMON-MODE REJECTION RATIO ANDPOWER-SUPPLY REJECTION vs FREQUENCY
CM
RR
and
PS
RR
(dB
)
Frequency (Hz)
10k 100k 10M1M 100M
80
70
60
50
40
30
20
10
0
–PSRR
+PSRR
CMRR
TYPICAL DRIFT OVER TEMPERATURE
Inpu
t Bia
s C
urre
nt (
µA)
Ambient Temperature (°C)−50 −25 7550250 100
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
Inpu
t Offs
et V
olta
ge (
mA
)In
put O
ffset
Cur
rent
(µA
)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Input Bias Current (IB)
Input Offset Voltage (VOS)
Input Offset Current (IOS)
OPA69912SBOS261Dwww.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
LIMITER FEEDTHROUGH
Fee
dthr
ough
(dB
)
Frequency (MHz)
1 10 100
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
OPA699
750Ω
125Ω
0.02VPP + 2VDC
150Ω
VO
VH
VLOpen
CLOSED-LOOP OUTPUT IMPEDANCE
Out
put I
mpe
danc
e (Ω
)
Frequency (Hz)
1M 100M10M 1G
100
10
1
0.1
0.01
G = +4VO = 0.5VPP
CMRR and PSRR(±) vs TEMPERATURE
CM
RR
and
PS
RR
(dB
)
Ambient Temperature (°C)−50 −25
PSRR+
PSRR–
CMRR
7550250 100
100
90
80
70
60
50
OUTPUT VOLTAGE AND CURRENT LIMITATIONSO
utpu
t Vol
tage
(V
)
Output Current (mA)
–400 –300 –200 –100 0 200100 300 400
5
4
3
2
1
0
–1
–2
–3
–4
–5
1W InternalPower Limit
1W InternalPower Limit
RL = 25Ω
VH = –VL = 4.3V
RL = 50Ω
RL = 100Ω
OPA699 13SBOS261D www.ti.com
TYPICAL CHARACTERISTICS: VS = +5VTA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted.
9
6
3
0
–3
–6
–9
–12
–15
NONINVERTING SMALL-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Nor
mal
ized
Gai
n (d
B)
1M 10M 100M 1G
VO = 0.5VPP
G = +12
See Figure 2
G = +20
G = +4
G = +6
6
3
0
–3
–6
–9
–12
–15
INVERTING SMALL-SIGNALFREQUENCY RESPONSE
Frequency (Hz)
Nor
mal
ized
Gai
n (d
B)
1M 10M 100M 1G
VO = 0.5VPP
G = –6
G = –12
G = –4
See Figure 3
18
15
12
9
6
3
0
LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
0.1 10M 100M 1G
Gai
n (d
B)
VLIM = VH = −VL
VO = 3VPP,VLIM = VCM ± 2.0V
VO = 1VPP,VLIM = VCM
± 1.2V
VO = 2VPP,VLIM = VCM
± 1.5V
See Figure 2
SMALL-SIGNAL PULSE RESPONSE
VO
UT (
V)
Time (5ns/div)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
G = +6
See Figure 2
LARGE-SIGNAL PULSE RESPONSE
VO
UT (
V)
Time (5ns/div)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
G = +6
See Figure 2
VH and VL—LIMITED PULSE RESPONSE
Inpu
t and
Out
put V
olta
ge (
V)
Time (20ns/div)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
VIN
VOUT
OPA69914SBOS261Dwww.ti.com
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
Har
mon
ic D
isto
rtio
n (d
Bc)
Load Resistance (Ω)100 1k
–50
–55
–60
–65
–70
–75
–80
VO = 2VPPf = 5MHz
2nd-Harmonic
3rd-Harmonic
See Figure 2
HARMONIC DISTORTION vs FREQUENCY
Har
mon
ic D
isto
rtio
n (d
Bc)
Frequency (MHz)
0.5 1 10 20
–50
–55
–60
–65
–70
–75
–80
–85
–90
3rd-Harmonic
2nd-Harmonic
VO = 2VPPRL = 500Ω
See Figure 2
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Har
mon
ic D
isto
rtio
n (d
Bc)
Output Voltage Swing (VPP)
0.5 1.0 2.01.5 2.5
–60
–65
–70
–75
–80
–85
2nd-Harmonic
See Figure 2
3rd-Harmonic
RL = 500Ω to VS/2f = 5MHzVH = VCM + VOPP/2 + 0.5VVL = VCM + VOPP/2 + 0.5V
2-TONE, 3RD-ORDERINTERMODULATION INTERCEPT
Inte
rcep
t Poi
nt (
+dB
M)
Frequency (MHz)
0 10 403020 50
38
36
34
32
30
28
26
24
22
20
OPA699
750Ω150Ω
500Ω
PO
VH
Open
OpenVL
PI
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
Har
mon
ic D
isto
rtio
n (d
Bc)
Limit Voltages - 2.5V0.9 1.0 1.1 1.6 1.71.4 1.51.2 1.3 1.8
–40
–45
–50
–55
–60
–65
–70
–75
–80
VO = VCM ±1VPf = 5MHzRL = 500Ω
3rd-Harmonic
2nd-Harmonic
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Lim
iter
Inpu
t Bia
s C
urre
nt (
µA)
Limiter Headroom (V)
0 0.5 2.01.51.0 2.5
100
75
50
25
0
–25
–50
–75
–100
Maximum Over Temperature
MinimumOver Temperature
Limiter Headroom = +VS – VH= VL – (–VS)
Current = IVH or –IVL
OPA699 15SBOS261D www.ti.com
TYPICAL APPLICATIONSWIDEBAND VOLTAGE LIMITING OPERATION
The OPA699 is a gain voltage of +4V/V, voltage-feedbackamplifier that combines features of a wideband, high slewrate amplifier with output voltage limiters. Its output canswing up to 1V from each rail and can deliver up to 120mA.These capabilities make it an ideal interface to drive an ADCwhile adding overdrive protection for the ADC inputs.
Figure 1 shows the DC-coupled, gain of +6V/V, dual power-supply circuit configuration used as the basis of the ±5VElectrical Characteristics and Typical Characteristics. Fortest purposes, the input impedance is set to 50Ω with aresistor to ground and the output is set to 500Ω. Voltageswings reported in the specifications are taken directly at theinput and output pins. For the circuit of Figure 1, the totaloutput load will be 500Ω || 900Ω = 321Ω. The voltage limitingpins are set to ±2V through a voltage divider network be-tween the +VS and ground for VH, and between–VS and ground for VL. These limiter voltages are adequatelybypassed with a 0.1µF ceramic capacitor to ground. Thelimiter voltages (VH and VL) and the respective bias currents(IVH and IVL) have the polarities shown. One additionalcomponent is included in Figure 1. An additional resistor(100Ω) is included in series with the noninverting input.Combined with the 25Ω DC source resistance looking backtowards the signal generator, this gives an input bias current-canceling resistance that matches the 125Ω source resis-tance seen at the inverting input (see the DC accuracy andoffset control section). The power-supply bypass for each
supply consists of two capacitors: one electrolytic 2.2µF andone ceramic 0.1µF. The power-supply bypass capacitors areshown explicitly in Figures 1 and 2, but will be assumed in theother figures. An additional 0.01µF power-supply decouplingcapacitor (not shown here) can be included between thetwo power-supply pins. In practical PC board layouts, thisoptional, added capacitor will typically improve the 2ndharmonic distortion performance by 3dB to 6dB.
SINGLE-SUPPLY, NONINVERTING AMPLIFIER
Figure 2 shows an AC-coupled, noninverting gain amplifierfor single +5V supply operation. This circuit was used for ACcharacterization of the OPA699, with a 50Ω source (which itmatches) and a 500Ω load. The mid-point reference on thenoninverting input is set by two 1.5kΩ resistors. This gives aninput bias current-canceling resistance that matches the750Ω DC source resistance seen at the inverting input (seethe DC accuracy and offset control section). The power-supply bypass for the supply consists of two capacitors: oneelectrolytic 2.2µF and one ceramic 0.1µF. The power-supplybypass capacitors are shown explicitly in Figures 1 and 2, butwill be assumed in the other figures. The limiter voltages (VHand VL) and the respective bias currents (IVH and IVL) havethe polarities shown. These limiter voltages are adequatelybypassed with a 0.1µF ceramic capacitor to ground. Noticethat the single-supply circuit can use three resistors to set VHand VL, where the dual-supply circuit usually uses four toreference the limit voltages to ground. While this circuitshows +5V operation, the same circuit may be used forsingle supplies up to +12V.
OPA69949.9Ω 6
IVH
VO
VIN
IVL
–VS = –5V
3
2
4
7
8
5
RF750Ω
RG150Ω
500Ω
0.1µF
0.1µF0.1µF
100Ω
3.01kΩ 1.91kΩ
3.01kΩ 1.91kΩ
0.1µFVH = +2V
VL = –2V
+2.2µF
+2.2µF
+VS = +5V
OPA69953.6Ω 6
IVH
VH = 3.7V
VO
VL = 1.3V
VIN
IVL
1.5kΩ
3
2
4
7
8
5
1.5kΩ
523Ω
976Ω
523Ω
RG150Ω
RF750Ω
500Ω
0.1µF
0.1µF
0.1µF
+2.2µF
0.1µF
VS = +5V
0.1µF
0.1µF
FIGURE 1. DC-Coupled, Dual-Supply Amplifier. FIGURE 2. AC-Coupled, Single-Supply Amplifier.
OPA69916SBOS261Dwww.ti.com
WIDEBAND INVERTING OPERATION
Operating the OPA699 as an inverting amplifier has severalbenefits and is particularly useful when a matched 50Ωsource and input impedance are required. Figure 3 showsthe inverting gain of –4V/V circuit used as the basis of theinverting mode typical characteristics.
LOW-GAIN COMPENSATION FOR IMPROVED SFDR
Where a low gain is desired, and inverting operation isacceptable, a new external compensation technique can beused to retain the full slew rate and noise benefits of theOPA699, while giving increased loop gain and the associ-ated distortion improvements offered by a non-unity-gainstable op amp. This technique shapes the loop gain for goodstability, while giving an easily controlled 2nd-order low-passfrequency response. To set the compensation capacitors (CSand CF), consider the half-circuit of Figure 5, where the 50Ωsource is used.
Considering only the noise gain for the circuit of Figure 5, thelow-frequency noise gain (NG1) is set by the resistor ratio,while the high-frequency noise gain (NG2) is set by thecapacitor ratio. The capacitor values set both the transitionfrequencies and the high-frequency noise gain. If the high-frequency noise gain, determined by NG2 = 1 + CS/CF, is setto a value greater than the recommended minimum stablegain for the op amp, and the noise gain pole (set by 1/RFCF)is placed correctly, a very well controlled 2nd-order low-passfrequency response results.
In the inverting case, only the feedback resistor appears aspart of the total output load in parallel with the actual load. Fora 500Ω load used in the typical characteristics, this gives atotal load of 329Ω in this inverting configuration. The gainresistor is set to get the desired gain (in this case, 187Ω fora gain of –4) while an additional input resistor (RM) can beused to set the total input impedance equal to the source, ifdesired. In this case, RM = 68.1Ω in parallel with the 187Ωgain setting resistor gives a matched input impedance of50Ω. This matching is only needed when the input needs tobe matched to a source impedance, as in the characteriza-tion testing done using the circuit of Figure 3.
For bias current-cancellation matching, the noninverting inputrequires a 169Ω resistor to ground. The calculation for thisresistor includes a DC-coupled 50Ω source impedance alongwith RG and RM. Although this resistor will provide cancella-tion for the bias current, it must be well-decoupled (0.1µF inFigure 3) to filter the noise contribution of the resistor and theinput current noise.
As the required RG resistor approaches 50Ω at higher gains,the bandwidth for the circuit in Figure 3 will far exceed thebandwidth at that same gain magnitude for the noninvertingcircuit of Figure 1. This occurs due to the lower noise gain forthe circuit of Figure 3 when the 50Ω source impedance isincluded in the analysis. For instance, at a signal gain of –15(RG = 50Ω, RM = open, RF = 750Ω) the noise gain for thecircuit of Figure 3 will be 1 + 750Ω/(50Ω + 50Ω) = 8.5 due tothe addition of the 50Ω source in the noise gain equation.This approach gives considerably higher bandwidth than thenoninverting gain of +15. Using the 1GHz gain bandwidthproduct for the OPA699, an inverting gain of –15 from a 50Ωsource to a 50Ω RG will give 140MHz bandwidth, whereasthe noninverting gain of +8 will give 55MHz, as shown in themeasured results of Figure 4.
OPA699
–5V
VI
–2V
+5V +2V
RM68.1Ω
RF750Ω
RG187Ω
500Ω
0.1µF RT169Ω
VH
VL
VO
50Ω Source
1M 10M 100M 1GFrequency (Hz)
Gai
n (d
B)
24
21
18
15
12
9
G = +15
G = –15
RF402Ω
CS13pF
OPA699
+5V
–5V
VO
VI
CF2.8pF
200Ω
RG402Ω
VH
VL
FIGURE 3. Inverting G = –4 Specifications and Test Circuit.
FIGURE 4. G = +15 and –15 Frequency Response.
FIGURE 5. Broadband, Low-Inverting Gain ExternalCompensation.
OPA699 17SBOS261D www.ti.com
To choose the values for both CS and CF, two parameters andonly three equations need to be solved. The first parameter isthe target high-frequency noise gain (NG2), which should begreater than the minimum stable gain for the OPA699. Here,a target of NG2 = 26 is used. The second parameter is thedesired low-frequency signal gain, which also sets the low-frequency noise gain (NG1). To simplify this discussion, we willtarget a maximally flat 2nd-order low-pass Butterworth fre-quency response (Q = 0.707). The signal gain shown in Figure5 sets the low-frequency noise gain to NG1 = 1 + RF/RG (= 2in this example). Then, using only these two gains and thegain bandwidth product for the OPA699 (1000MHz), the keyfrequency in the compensation is set by Equation1.
ZGBP
NG
NGNG
NGNGO
= −
− −
1
21
2
1
21 1 2 (1)
Physically, this ZO (22.3MHz for the values shown above) isset by 1/(2πRF(CF + CS)) and is the frequency at which therising portion of the noise gain would intersect the unity gainif projected back to a 0dB gain. The actual zero in the noisegain occurs at NG1 • ZO and the pole in the noise gain occursat NG2 • ZO. That pole is physically set by 1/(RFCF). SinceGBP is expressed in Hz, multiply ZO by 2π and use to get CFby solving Equation 2.
CR Z NG
pFFF O
= =( )12
32π
(2)
Finally, since CS and CF set the high-frequency noise gain,determine CS using Equation 3 (solving for CS by usingNG2 = 6):
C NG CS F= −( )2 1 (3)which gives CS = 15pF.
Both of these calculated values have been reduced slightlyin Figure 5 to account for parasitics. The resulting closed-loop bandwidth is approximately equal to Equation 4.
f Z GBPdB O–3 ≅ • (4)
For the values shown in Figure 5, f–3dB is approximately149MHz. This is less than that predicted by simply dividingthe Gain Bandwidth Product (GBP) product by NG1. Thecompensation network controls the bandwidth to a lowervalue, while providing the full slew rate at the output and animproved distortion performance due to increased loop gainat frequencies below NG1 • ZO.
LOW DISTORTION, LIMITED OUTPUT,ADC INPUT DRIVER
Figure 6 shows a simple ADC driver that operates on a singlesupply, and gives excellent distortion performance. The limitvoltages track the input range of the converter, completelyprotecting against input overdrive. Note that the limitingvoltages have been set 100mV above/below the correspond-ing reference voltage from the converter. This circuit alsoimplements an improved distortion for an inverting gain of–2 using external compensation.
OPA699
VS = +5V
4
2
3 7
5
86
VS = +5V
+3.5V
+1.5V
REFB
REFT
IN
VIN
0.1µF
100pF
VH = +3.6V
VL = +1.4V 0.1µF
0.1µF
18pF
1000pF
4pF
750Ω
24.9Ω
374Ω
562Ω
102Ω
1.4kΩ
1.4kΩ102Ω
562Ω
ADS82210-Bit
40MSPS
10-BitData
VS = +5V
INT/EXT
RSEL +VS
GND
FIGURE 6. Single Supply, Limiting ADC Input Driver.
OPA69918SBOS261Dwww.ti.com
LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER
Figure 7 shows a differential ADC driver that takes advan-tage of the OPA699 limiters to protect the input of the ADC.Two OPA699s are used. The first one is an inverting configu-ration at a gain of –2. The second one is in a noninvertingconfiguration at a gain of +2. Refer to the section, Low GainCompensation for Improved SFDR, for a discussion of stabil-ity issues of the OPA699 operating at a gain less than 4.Each amplifier is swinging 2VPP providing a 4VPP differentialsignal to drive the input of the ADC. Limiters have been set100mV away from the magnitude of each amplifier maximumsignal to provide input protection for the ADC while maintain-ing an acceptable distortion level.
PRECISION HALF WAVE RECTIFIER
Figure 8 shows a half wave rectifier with outstanding preci-sion and speed. VH (pin 8) will default to a 3.5 typically if leftopen, while the negative limit is set to ground.
The gain for the circuit in Figure 8 is set at +6. Figure 9 showsinput and output for ±0.5V 100MHz input.
VERY HIGH-SPEED SCHMITT TRIGGER
Figure 10 shows a very high-speed Schmitt Trigger. Theoutput levels are precisely defined, and the switching time isexceptional. The output voltage swings between VH and VL.
OPA699
+5V
–5V
VIN = 200mVPP
1kΩ 24.9Ω
1kΩ
1kΩ
0.01µF 10pF
10pF
0.01µF24.9Ω
100Ω
100ΩOPA699
+5V
–5V900Ω
+1.1V
–1.1V
IN
VCM
ADC
IN
+1.1V4VPP
–1.1V
100Ω
OPA699 6 VO
VO = Open
–VS = –5V
+VS = +5V
VIN2
3
4
7
8
5
750Ω150Ω
75Ω
50ΩSource
Time (5ns/div)
Output
Input
Inpu
t and
Out
put V
olta
ge (
V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
OPA699
R2402Ω
R1200Ω
R3200Ω
VREF
VOUT
VH
VL
+2V
–2V
VIN
FIGURE 8. Precision Half-Wave Rectifier.
FIGURE 9. 100MHz Sinewave Rectified.
FIGURE 10. Very High-Speed Schmitt Trigger.
FIGURE 7. Single to Differential AC-Coupled, High Gain Output Limited ADC Driver.
OPA699 19SBOS261D www.ti.com
The circuit operates as follows. When the input voltage isless than VHL then the output is limiting at VH. When the inputis greater than VHH, then the output is limiting at VL, with VHLand VHH defined as the following:
VR R R
RV
R R RR
VHL HH REF OUT,|| || || ||
= ×
+ ×
1 2 3
1
1 2 3
2
Due to the inverting function realized by the Schmitt Trigger,VHL corresponds to VOUT = VH, and VHH corresponds toVOUT = VL.
Figure 11 shows the Schmitt Trigger operating with VREF =+5V. This gives us VHH = 2.4V and VHL = 1.6V. The propa-gation delay for the OPA699 in a Schmitt Trigger configura-tion is 4ns from high-to-low, and 4ns from low-to-high.
OPERATING SUGGESTIONSTHEORY OF OPERATION
The OPA699 is a voltage-feedback, gain of +4V/V stable opamp. The output voltage is limited to a range set by thevoltage on the limiter pins (5 and 8). When the input tries tooverdrive the output, the limiters take control of the outputbuffer. This action from the limiters avoids saturating any partof the signal path, giving quick overdrive recovery andexcellent limiter accuracy at any signal gain. The limitershave a very sharp transition from the linear region of opera-tion to output limiting. This transition allows the limiter volt-ages to be set very near (< 100mV) the desired signal range.The distortion performance is also very good near the limitervoltages.
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s) whenit is between the limiter voltages VH (pin 8) and VL (pin 5).When the output tries to exceed VH or VL, the correspondinglimiter buffer takes control of the output voltage and holds itat VH or VL. Because the limiters act on the output, theiraccuracy does not change with the gain. The transition fromthe linear region of operation to output limiting is verysharp—the desired output signal can safely come to within30mV of VH or VL with no onset of non-linearity. The limitervoltages can be set to within 0.7V of the supplies (VL ≥ –VS+ 0.7V, VH ≤ +VS – 0.7V). They must also be at least 400mVapart (VH – VL ≥ 0.4V). When pins 5 and 8 are left open, VHand VL go to the default voltage limit; the minimum values aregiven in the electrical specifications. Looking at Figure 12 forthe zero bias current case shows the expected range of(VS – default limit voltages) = headroom.
DESIGN-IN TOOLSDEMONSTRATION FIXTURE
A printed circuit board (PCB) is available to assist in the initialevaluation of circuit performance using the OPA699. Thefixture is offered free of charge as an unpopulated PCB,delivered with user's guide. The summary information for thisfixture is shown in Table I.
Time (10ns/div)
Inpu
t and
Out
put V
olta
ge (
V)
4
3
2
1
0
–1
–2
–3
–4
VIN
VOUT
Lim
iter
Inpu
t Bia
s C
urre
nt (
µA)
Limiter Headroom (V)
0 1.00.5 4.0 4.53.53.02.52.01.5 5.0
100
75
50
25
0
–25
–50
–75
–100
Maximum Over Temperature
Minimum Over Temperature
Limiter Headroom = +VS – VH= VL – (–VS)
Current = IVH or –IVL
FIGURE 11. Schmitt Trigger Time Domain Response for a10MHz Sinewave.
ORDERING LITERATUREPRODUCT PACKAGE NUMBER NUMBER
OPA699ID SO-8 DEM-OPA-SO-1A SBOU009
TABLE I. Demonstration Fixture.
FIGURE 12. Limiter Bias Current vs Bias Voltage.
The demonstration fixture can be requested at the TexasInstruments web site (www.ti.com) through the OPA699product folder.
OPA69920SBOS261Dwww.ti.com
When the limiter voltages are more than 2.1V from thesupplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can usesimple resistor dividers to set VH and VL (see Figure 1). Makesure to include the limiter input bias currents (Figure 8) in thecalculations (that is, IVL = 50µA into pin 5, and IVH = +50µAout of pin 8). For good limiter voltage accuracy, run aminimum 1mA quiescent bias current through these resis-tors. When the limiter voltages need to be within 2.1V of thesupplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider usinglow impedance buffers to set VH and VL to minimize errorsdue to bias current uncertainty. This condition will typically bethe case for single-supply operation (VS = +5V). Figure 2runs 2.5mA through the resistive divider that sets VH and VL.This limits errors due to IVH and IVL < ±1% of the target limitvoltages. The limiters’ DC accuracy depends on attention todetail. The two dominant error sources can be improved asfollows:
• Power supplies, when used to drive resistive dividers thatset VH and VL, can contribute large errors (for example,±5%). Using a more accurate source, and bypassing pins5 and 8 with good capacitors, will improve limiter PSRR.
• The resistor tolerances in the resistive divider can alsodominate. Use 1% resistors.
Other error sources also contribute, but should have littleimpact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents.Select the resistors in the resistive divider(s) as describedabove.
• Consider the signal path DC errors as contributing touncertainty in the useable output swing.
• The limiter offset voltage only slightly degrades limiteraccuracy. Figure 13 shows how the limiters affect distor-tion performance. Virtually no degradation in linearity isobserved for output voltage swinging right up to the limitervoltages. In this plot a fixed ±1V output swing is drivenwhile the limiter voltages are reduced symmetrically. Untilthe limiters are reduced to ±1.1V, little distortion degrada-tion is observed.
OUTPUT DRIVE
The OPA699 has been optimized to drive 500Ω loads, suchas ADCs. It still performs very well driving 100Ω loads; thespecifications are shown for the 500Ω load. This makes theOPA699 an ideal choice for a wide range of high-frequencyapplications.
Many high-speed applications, such as driving ADCs, requireop amps with low output impedance. As shown in the typicalperformance curve Output Impedance vs Frequency, theOPA699 maintains very low closed-loop output impedanceover frequency. Closed-loop output impedance increaseswith frequency, since loop gain decreases with frequency.
THERMAL CONSIDERATIONS
The OPA699 will not require heat sinking under most oper-ating conditions. Maximum desired junction temperature willset a maximum allowed internal power dissipation as de-scribed below. In no case should the maximum junctiontemperature be allowed to exceed 150°C.
The total internal power dissipation (PD) is the sum ofquiescent power (PDQ) and the additional power dissipated inthe output stage (PDL) while delivering load power. PDQ issimply the specified no-load supply current times the totalsupply voltage across the part. PDL depends on the requiredoutput signals and loads. For a grounded resistive load, andequal bipolar supplies, it is at maximum when the output isat 1/2 either supply voltage. In this condition, PDL = VS2/(4RL)where RL includes the feedback network loading. Note that itis the power in the output stage, and not in the load, thatdetermines internal power dissipation.
The operating junction temperature is: TJ = TA + PD x θJA,where TA is the ambient temperature. For example, themaximum TJ for a OPA699ID with G = +6, RF = 750Ω,RL = 500Ω, and ±VS = ±5V at the maximum TA = +85°C iscalculated as:
P V mA mW
PV
mW
P mW mW mW
T C mW C W C
DQ
DL
D
J
= ×( ) =
=( )
× ( ) =
= + == ° + × ° = °
10 15 5 155
5
4 500 90019 4
155 19 4 174 4
85 174 4 125 107
2
.
||.
. .
. /
Ω Ω
This would be the maximum TJ from VO = ±2.5VDC. Mostapplications will be at a lower output stage power and havea lower TJ.
CAPACITIVE LOADS
Capacitive loads, such as the input to ADCs, will decreasethe amplifier phase margin, which may cause high-frequencypeaking or oscillations. Capacitive loads ≥ 2pF should beisolated by connecting a small resistor in series with theoutput, as shown in Figure 14. Increasing the gain from +2will improve the capacitive drive capabilities due to increasedphase margin.
Har
mon
ic D
isto
rtio
n (d
Bc)
± Limit Voltage (V)0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
−40
−50
−60
−70
−80
−90
3rd-Harmonic
2nd-Harmonic
VO = 0VDC ± 1VPf = 5MHzRL = 500Ω
FIGURE 13. Harmonic Distortion Near Limit Voltages.
OPA699 21SBOS261D www.ti.com
In general, capacitive loads should be minimized for optimumhigh-frequency performance. The capacitance of coax cable(29pF/ft for RG-58) will not load the amplifier when thecoaxial cable, or transmission line, is terminated in its char-acteristic impedance.
FREQUENCY RESPONSE COMPENSATION
The OPA699 is internally compensated to be unity-gainstable, and has a nominal phase margin of 60° at a gain of+6. Phase margin and peaking improve at higher gains.Recall that an inverting gain of –5 is equivalent to a gain of+6 for bandwidth purposes (that is, noise gain = 6). Standardexternal compensation techniques work with this device.For example, in the inverting configuration, the bandwidthmay be limited without modifying the inverting gain by placinga series RC network to ground on the inverting node. Thishas the effect of increasing the noise gain at high frequen-cies, which limits the bandwidth.
If a unity-gain stable amplifier is needed, the OPA698 isrecommended.
In applications where a large feedback resistor is required,such as a photodiode transimpedance amplifier, the parasiticcapacitance from the inverting input to ground causes peak-ing or oscillations. To compensate for this effect, connect asmall capacitor in parallel with the feedback resistor. Thebandwidth will be limited by the pole that the feedbackresistor and this capacitor create. In other high-gain applica-tions, use a three-resistor Tee network to reduce the RC timeconstants set by the parasitic capacitances.
PULSE SETTLING TIME
The OPA699 is capable of an extremely fast settling time inresponse to a pulse input. Frequency response flatness andphase linearity are needed to obtain the best settling times.For capacitive loads, such as an ADC, use the recom-mended RS in the typical performance curve RecommendedRS vs Capacitive Load. Extremely fine-scale settling (0.01%)requires close attention to ground return current in the supplydecoupling capacitors.
The pulse settling characteristics, when recovering fromoverdrive, are extremely good as shown in the typical char-acteristics.
DISTORTION
The OPA699 distortion performance is specified for a 500Ωload, such as an ADC. Driving loads with smaller resistancewill increase the distortion, as illustrated in Figure 15. Re-member to include the feedback network in the load resis-tance calculations.
NOISE PERFORMANCE
High slew rate, voltage-feedback op amps usually achievetheir slew rate at the expense of a higher input noise voltage.The 4.1nV/√Hz input voltage noise for the OPA699, how-ever, is much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred currentnoise terms, combine to give low output noise under a widevariety of operating conditions. Figure 16 shows the op ampnoise analysis model with all the noise terms included. In thismodel, all noise terms are taken to be noise voltage orcurrent density terms in either nV/√Hz or pA/√Hz.
OPA699
CLRLRT
RS
RG RF
VO
RL is optional
Har
mon
ic D
isto
rtio
n (d
Bc)
Load Resistance (Ω)100 1k
–55
–60
–65
–70
–75
–80
–85
–90
VO = 2VPPf = 5MHz
3rd-Harmonic
See Figure 1
2nd-Harmonic
4kTRG
RG
RF
RSOPA699
IBI
EOIBN
4kT = 1.6E –20Jat 290°K
ERS
ENI
4kTRS√
4kTRF√
FIGURE 14. Driving Capacitive Loads.
FIGURE 15. 5MHz Harmonic Distortion vs Load Resistance.
FIGURE 16. Op Amp Noise Analysis Model.
OPA69922SBOS261Dwww.ti.com
The total output spot noise voltage can be computed as thesquare root of the sum of all squared output noise voltagecontributors. Equation 5 shows the general form for theoutput noise voltage using the terms shown in Figure 16.
(5)
E E I R kTR NG I R kTR NGO NI BN S S BI F F= + ( ) + + ( ) +22 2 24 4
Dividing this expression by the noise gain (NG = (1+RF/RG))will give the equivalent input-referred spot noise voltage atthe noninverting input, as shown in Equation 6.
(6)
E E I R kTRI RNG
kTRNGN NI BN S S
BI F F= + ( ) + +
+2 22
44
Evaluating these two equations for the OPA699 circuit andcomponent values (see Figure 1) will give a total output spotnoise voltage of 27.4nV/√Hz and a total equivalent input spotnoise voltage of 4.6nV/√Hz. This total input-referred spotnoise voltage is only slightly higher than the 4.1nV/√Hzspecification for the op amp voltage noise alone. This will bethe case as long as the impedances appearing at eachop amp input are limited to a maximum value of 300Ω.Keeping both (RF || RG) and the noninverting input sourceimpedance less than 300Ω will satisfy both noise andfrequency response flatness considerations. Since the resis-tor-induced noise is negligible, additional capacitive decouplingacross the bias current cancellation resistor (RT) for theinverting op amp configuration of Figure 3 is not required, butis still desirable.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback opamp allows good output DC accuracy in a large variety ofapplications. The power-supply current trim for the OPA699gives even tighter control than comparable products. Al-though the high-speed input stage does require relativelyhigh input bias current (typically 3µA at each input terminal),the close matching between them may be used to reduce theoutput DC error caused by this current. The total output offsetvoltage may be considerably reduced by matching the DCsource resistances appearing at the two inputs. This reducesthe output DC error due to the input bias currents to the offsetcurrent times the feedback resistor. Evaluating the configura-tion of Figure 1, using worst-case +25°C input offset voltageand current specifications, gives a worst-case output offsetvoltage, with NG = noninverting signal gain, equal to:
±(NG • VOS(MAX)) ± (RF • IOS(MAX))
= ±(2 • 5mV) ± (750Ω • 2.0µA)
= ±11.5mV
A fine-scale output offset null, or DC operating point adjust-ment, is often required. Numerous techniques are availablefor introducing DC offset control into an op amp circuit. Mostof these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trimmethod, one key consideration is the impact on the desiredsignal path frequency response. If the signal path is intendedto be noninverting, the offset control is best applied as aninverting summing signal to avoid interaction with the signalsource. If the signal path is intended to be inverting, applyingthe offset control to the noninverting input may be consid-ered. However, the DC offset voltage on the summingjunction will set up a DC current back into the source whichmust be considered. Applying an offset adjustment to theinverting op amp input can change the noise gain andfrequency response flatness. For a DC-coupled invertingamplifier, Figure 17 shows one example of an offset adjust-ment technique that has minimal impact on the signal fre-quency response. In this case, the DC offsetting current isbrought into the inverting input node through resistor valuesthat are much larger than the signal path resistors. This willinsure that the adjustment circuit has minimal effect on theloop gain as well as the frequency response.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with the high-frequencyOPA699 requires careful attention to layout design andcomponent selection. Recommended PCB layout techniquesand component selection criteria are:
a) Minimize parasitic capacitance to any AC ground for allof the signal I/O pins. Open a window in the ground andpower planes around the signal I/O pins, and leave theground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regu-lators, ground plane and power planes to provide power.Place high frequency 0.1µF decoupling capacitors < 0.2"away from each power-supply pin. Use wide, short traces toconnect to these capacitors to the ground and power planes.Also use larger (2.2µF to 6.8µF) high-frequency decoupling
RF750Ω
±200mV Output Adjustment
= – = –5
Supply DecouplingNot Shown
5kΩ
5kΩ
328Ω0.1µF
RG150Ω
VI
20kΩ10kΩ
0.1µF
–5V
+5V
OPA699
+5V
–5V
VO
VOVI
RFRG
FIGURE 17. DC-Coupled, Inverting Gain of –5, with OffsetAdjustment.
OPA699 23SBOS261D www.ti.com
capacitors to bypass lower frequencies. They may be some-what further from the device, and be shared among severaladjacent devices.
c) Place external components close to the OPA699. Thisminimizes inductance, ground loops, transmission line ef-fects and propagation delay problems. Be extra careful withthe feedback (RF), input and output resistors.
d) Use high-frequency components to minimize parasiticelements. Resistors should be a very low reactance type.Surface-mount resistors work best and allow a tighter layout.Metal film or carbon composition axially-leaded resistors canalso provide good performance when their leads are as shortas possible. Never use wirewound resistors for high-fre-quency applications. Remember that most potentiometershave large parasitic capacitances and inductances. Multi-layer ceramic chip capacitors work best and take up littlespace. Monolithic ceramic capacitors also work very well.Use RF type capacitors with low ESR and ESL. The largepower pin bypass capacitors (2.2µF to 6.8µF) should betantalum for better high frequency and pulse performance.
e) Choose low resistor values to minimize the time con-stant set by the resistor and its parasitic parallel capacitance.Good metal film or surface mount resistors have approxi-mately 0.2pF parasitic parallel capacitance. For resistors> 1.5kΩ, this adds a pole and/or zero below 500MHz. Makesure that the output loading is not too heavy. The recom-mended 750Ω feedback resistor is a good starting point inmost designs.
f) Use short direct traces to other wideband devices onthe board. Short traces act as a lumped capacitive load.Wide traces (50 to 100 mils) should be used. Estimate thetotal capacitive load at the output, and use the series isola-tion resistor recommended in the typical performance curve,Recommended RS vs Capacitive Load. Parasitic loads < 2pFmay not need the isolation resistor.
g) When long traces are necessary, use transmission linedesign techniques (consult an ECL design handbook formicrostrip and stripline layout techniques). A 50Ω transmis-sion line is not required on board—a higher characteristicimpedance will help reduce output loading. Use a matchingseries resistor at the output of the op amp to drive atransmission line, and a matched load resistor at the otherend to make the line appear as a resistor. If the 6dB ofattenuation that the matched load produces is not accept-able, and the line is not too long, use the series resistor at thesource only. This will isolate the source from the reactive loadpresented by the line, but the frequency response will bedegraded. Multiple destination devices are best handled asseparate transmission lines, each with its own series sourceand shunt load terminations. Any parasitic impedances act-ing on the terminating resistors will alter the transmission linematch, and can cause unwanted signal reflections and reac-tive loading.
h) Do not use sockets for high-speed parts like the OPA699.The additional lead length and pin-to-pin capacitance intro-duced by the socket creates an extremely troublesomeparasitic network. Best results are obtained by soldering thepart onto the board.
POWER SUPPLIES
The OPA699 is nominally specified for operation using either±5V supplies or a single +5V supply. The maximum specifiedtotal supply voltage of 13V allows reasonable tolerances onthe supplies. Higher supply voltages can break down internaljunctions, possibly leading to catastrophic failure. Single-supply operation is possible as long as common modevoltage constraints are observed. The common-mode inputand output voltage specifications can be interpreted as arequired headroom to the supply voltage. Observing thisinput and output headroom requirement will allow design ofnon-standard or single-supply operation circuits. Figure 2shows one approach to single-supply operation.
INPUT AND ESD PROTECTION
The OPA699 is built using a very high-speed complementarybipolar process. The internal junction breakdown voltagesare relatively low for these very small geometry devices.These breakdowns are reflected in the Absolute MaximumRatings table. All device pins are protected with internal ESDprotection diodes to the power supplies, as shown in Figure18.
These diodes provide moderate protection to input overdrivevoltages above the supplies as well. The protection diodescan typically support 30mA continuous current. Where highercurrents are possible (e.g., in systems with ±15V supply partsdriving into the OPA699), current limiting series resistorsshould be added into the two inputs. Keep these resistorvalues as low as possible, since high values degrade bothnoise performance and frequency response.
ExternalPin
+VCC
–VCC
InternalCircuitry
FIGURE 18. I/O Pin ESD Protection.
OPA69924SBOS261Dwww.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION PAGE SECTION DESCRIPTION
12/08 D 2 Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.
3/06 C 19 Design-In Tools Board part number changed.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
OPA699ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA699
OPA699IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA699
OPA699IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA699
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA699 :
• Military: OPA699M
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
http://focus.ti.com/docs/prod/folders/print/opa699m.html
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
OPA699IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Nov-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA699IDR SOIC D 8 2500 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Nov-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP[5.80-6.19]
.069 MAX[1.75]
6X .050[1.27]
8X .012-.020 [0.31-0.51]
2X.150[3.81]
.005-.010 TYP[0.13-0.25]
0 - 8 .004-.010[0.11-0.25]
.010[0.25]
.016-.050[0.41-1.27]
4X (0 -15 )
A
.189-.197[4.81-5.00]
NOTE 3
B .150-.157[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)[1.04]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
54
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX[0.07]ALL AROUND
.0028 MIN[0.07]ALL AROUND
(.213)[5.4]
6X (.050 )[1.27]
8X (.061 )[1.55]
8X (.024)[0.6]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILS
EXPOSEDMETAL
OPENINGSOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASKDEFINED
EXPOSEDMETAL
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEEDETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )[1.55]
8X (.024)[0.6]
6X (.050 )[1.27]
(.213)[5.4]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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