WILDSTAR A5 /PCIe Hardware Reference Manual

WILDSTAR A5 /PCIe Hardware Reference

Manual

Document No:15199-0000, Revision 1.2

© Copyright 2014 by Annapolis Micro Systems, Inc. All rights reserved. Printed and published in the United States of America. WILDFIRE, WILDFIRE-XL, WILDCHILD, WILDFORCE, WILDFORCE-XL, WILD-ONE, WILD-ONE-XL, WILDTIME, WILDCARD, STARFIRE, WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4/5/6/7, WILDSTAR A, WILDSTAR-E, WSDP, WILDWARE, WILD, C2WILD, CoreFire, CoreFire Next and FIREBIRD are trademarks of Annapolis Micro Systems, Inc. All other trademarks and registered trademarks are owned by their respective owners. Patents Pending.

This is the standard Annapolis Micro Systems, Inc. Shrink Wrap license which covers all Annapolis Hardware, VHDL Drivers, APIs, Examples, and Reference Designs. CoreFire Next is covered by a different shrinkwrap license.

If this license is included in a purchase order, it supersedes any and all other Terms and Conditions regarding licensing and technical rights that are found in the Purchase Order.

ANNAPOLIS MICRO SYSTEMS, INC. - LICENSE AGREEMENT

WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4, WILDSTAR 5, WILDSTAR 6, WILDSTAR 7, WILDSTAR 5B, and WILDSTAR A5 Host Software, Device Drivers, Models, VHDL, Examples, Tools and PCI and FPGA-based Ethernet Controllers are supplied with a License Agreement. This License Agreement also covers the PLD designs, Reference designs, and Flash contents supplied with the board. Do not install or use this product and/or break the seal on the CD-ROM until you have read and agreed to the following terms and conditions. Should you choose not to be bound by the terms and conditions of this agreement, you should promptly return this product.

YOU ARE BOUND TO THE TERMS OF THIS AGREEMENT BY BREAKING THE SEAL ON THE CD-ROM

Under the terms of this License, you: • may make copies of the Licensed Product • may not transfer the Licensed Product to an unlicensed party • may modify the VHDL and the Examples • may not modify any other parts of the Licensed Product • may not decompile, reverse assemble or otherwise reverse engineer the Licensed Product • may run this product ONLY on an Annapolis Micro Systems, Inc. board• may run the FPGA vendor specific parts of this product ONLY on an Annapolis Micro Systems, Inc. board with FPGAs from that vendor

The Licensed Product is owned and copyrighted by Annapolis Micro Systems, Inc. You may not remove the copyright notice from the Licensed Product. You must use your best efforts to prevent any unauthorized copying of the Licensed Product.

The Licensed Product is provided “as is” without warranty of any kind including warranties for merchantability or fitness for a particular purpose. Annapolis Micro Systems, Inc. shall not be liable for any loss of profits, loss of use, interruption of business, nor for indirect, special, incidental or consequential damages of any kind whether under this agreement or otherwise.

Although Annapolis Micro Systems, Inc. does not warrant the functions contained in the Licensed Product, the medium on which the Licensed Product is furnished is warranted to be free from defects in materials and workmanship under normal use for a period of 90 days from date of delivery to you as evidenced by a copy of your receipt. Annapolis Micro Systems’ entire liability to you and your exclusive remedy shall be replacement of the Licensed Product if the medium on which the Licensed Product is furnished proves to be defective.

You understand that the Licensed Product may require a license from the US Department of Commerce or other government agency before it may be taken or sent outside of the United States. You agree to obtain any required licenses before taking or sending the Licensed Product out of the United States. You will not permit the re-export of the Licensed Product without obtaining required licenses or letter of further assurance.

Contents

Chapter 1: About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Key Words and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 WILDSTAR A5 /PCIe Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2 About the WILDSTAR A5 /PCIe Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.1 WILDSTAR A5 /PCIe Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 WILDSTAR Mezzanine I/O Daughter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 3: Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.1 Unpacking and Inspecting the WILDSTAR Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2 Board Illustrations and LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 4: Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.1 WILDSTAR A5 /PCIe Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.1.1 Power Up System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.1.2 WILDSTAR A5 /PCIe DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.2 WILDSTAR A5 /PCIe Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.2.1 WILDSTAR A5 /PCIe Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 5: Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.1 Board Identification Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 6: Hardware Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1 WILDSTAR A5 /PCIe Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.2 Thermal and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.2.1 WILDSTAR A5 /PCIe Heatsinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.2.2 Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.3 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Appendix A: CoreFire Next Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Appendix B: WILDSTAR Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix C: WILDSTAR A5 /PCIe Statement of Volatility . . . . . . . . . . . . . . . . . . . 59

Appendix D: WILDSTAR A5 /PCIe Generic I/O Connector Specification . . . . . . . 63

1WILDSTAR A5 /PCIe Hardware Reference ManualChapter 1: About This Manual

Chapter 1: About This Manual

2 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 1: About This Manual

15199-0000 Rev 1.2


All WILDSTAR A5 /PCIe boards operate with WD Host Software. Detailed software information can be found in the WD Software Reference Manual, included in hardcopy and as a PDF file on the WD Host Software CD-ROM. Installation instructions for VHDL and host software are located in the accompanying release notes.

This WILDSTAR A5 /PCIe Hardware Reference Manual is intended to help the user install, program, and maintain a high performance WILDSTAR A5 /PCIe motherboard from Annapolis Micro Systems, Inc.

Note: References throughout this manual to “WILDSTAR A5 /PCIe” typically pertain to all memories types, unless specifically indicated otherwise.

1.1 OverviewA brief description of each chapter appears below.

• Chapter 2: Introduction, discusses board architecture and performance features of WILDSTAR A5 /PCIe boards.

• Chapter 3: Getting Started, describes unpacking and inspection procedures for your WILDSTAR A5 /PCIe, as well as board LED definitions and locations.

• Chapter 4: Installation describes host system requirements, installation instructions, reset options, and switch descriptions.

• Chapter 5: Technical Support provides information for contacting Annapolis Micro Systems, Inc. Technical Support.

• Chapter 6: Hardware Reference describes hardware specifications, along with voltage and clocking.

• Appendix A: CoreFire Next Support contains information regarding CoreFire Next.

• Appendix B: WILDSTAR Mezzanine Cards contains WILDSTAR Mezzanine Card information.

• Appendix C: WILDSTAR A5 /PCIe Statement of Volatility contains the WILDSTAR A5 /PCIe Statement of Volatility.

• Appendix D: WILDSTAR A5 /PCIe Generic I/O Connector Specification contains the I/O connector specification for WILDSTAR A5 /PCIe boards.

15199-0000 Rev 1.2


1.2 ConventionsDifferent text styles are used throughout the manual to call attention to specific items:

Convention Description

Text represented as screen display

This typeface is used to represent displays appearing on the screen, such as at the “A:\” prompt.

Keys When specific keys are referenced, they are designated by their labels, such as “the Enter key” or “the Escape key,” or they may be shown as [Enter] or [Esc].When two or more keys are to be pressed simultaneously, the keys are linked with a plus sign (+). For example: [Ctrl] + [Alt] + [Del].

Clickable Links Text that references another area in the document. The user can click on the blue text and the document will jump directly to the section referenced.

15199-0000 Rev 1.2


1.3 Key Words and DefinitionsTerms used throughout the manual are defined below.

APIApplication Programming Interface

Application Programming InterfaceA set of functions coded in the C language allowing communication between an application and the board.

Block RAMAn architectural feature of the Stratix V FPGA in which blocks are reserved specifically for Random Access Memory.

CLBConfigurable Logic Block (CLB). CLBs provide the functional elements for constructing logic within the PE.

CoreFire Next Design SuiteAn FPGA design and debug application tool developed by Annapolis Micro Systems, Inc.

CPEComputational Processing Element. A Stratix V Field Programmable Gate Array (FPGA) comprises the basic processing unit on the WILDSTAR A5 /PCIe board. The Stratix V FPGA is used on WILDSTAR A5 /PCIe boards. CPEs are contained within Processing Modules (see definition below).

CPE0Computational Processing Element 0

CPE1Computational Processing Element 1

DDR3 DRAMDouble Data Rate DRAM. A high-performance, synchronous burst DRAM capable of single- and double-data operational modes.

DeprogramTo pulse the PROGRAM input to an FPGA causing its configuration to be cleared and placing it in a pre-configuration state.

Differential Signal PairTwo lines, one negative and one positive.

Differential SignalingTwo-wire signaling, in which the difference in voltage between two wires is used to signal data.

DLLDynamic Linkage Library

DMADirect Memory Access. In this document, DMA refers to data transfers initiated in the PEs which target host memory or other devices on the system bus.

15199-0000 Rev 1.2


DMA BusDirect Memory Access Bus. A high-bandwidth point-to-point bus between a PE and the PCI Controller which is dedicated to DMA transfers initiated by the PE.

DRAMDynamic Random Access Memory

DriverSoftware used to handle communication with one to four WILDSTAR A5 /PCIe boards.

External I/OExternal Input/Output

FPGAField Programmable Gate Array

HHSHigh Speed Serial

ICLKFixed, single-ended bus clock used for Local Address Data Bus transactions.

IOPEInput/Output Processing Element. A Stratix V Field Programmable Gate Array (FPGA) located on the WILDSTAR motherboard, responsible for the interface to mezzanine cards.

IRIG-BThe IRIG-B Adapter Card allows the sampling of IRIG-B Serial Time Code Data

LAD Bus Local Address Data Bus. Point-to-point bus from the PCI Controller to each PE. This bus is dedicated to Programmed Input/Output accesses from the host CPU to the PE.

LaneA set of differential signal pairs, one pair for transmission and one pair for reception. A PCI Express by-N Link is composed of N Lanes.

MCLK Reprogrammable differential memory clock, synchronous to PCLK.

Mezzanine I/O CardI/O daughter card designed for compatibility with WILDSTAR 4/5/6/7 families. Mezzanine I/O cards are classified using Class A and Class B.

ModelTech®An application used to simulate VHDL.

N/CNo Connection

PARPlace and Route

15199-0000 Rev 1.2


PCIPeripheral Component Interconnect

PCI Controller Device on the WILDSTAR A5 board which acts as a bridge between the PEs and the system bus. This device also provides a variety of board management functions.

PCI Express (PCIe)General performance I/O interconnect which maintains the fundamental attributes of PCI, but replaces the parallel bus implementation with a serial interface that offers new features and new levels of performance.

PCLKReprogrammable Differential Processing Element Clock asynchronous to MCLK.

PEProcessing Element. A Field Programmable Gate Array (FPGA) which comprises the basic processing unit on the WILDSTAR A5 /PCIe board. The Stratix V FPGA is used on WILDSTAR A5 /PCIe boards. Processing Elements can be subdivided into two categories; Computational Processing Elements (CPEs) and I/O Processing Elements (IOPEs).

Processing ModuleA basic unit in the WILDSTAR A5 /PCIe architecture consisting of a computational processing element (CPE) and its associated ports, buses, clocks, and Flash.

QDR II SRAMQuadruple-Data Rate II. A high-performance, synchronous burst SRAM capable of quadruple-data operational modes.

RxAbbreviation of “Receive”.

Single-ended SignalingUses one wire per signal, in which a single voltage is generated that the receiver compares with a fixed reference voltage.

SRAMSynchronous Random Access Memory

Slice A slice contains two look-up tables and two flip-flops for implementing logic within a CLB (Configurable Logic Block). On Stratix V FPGAs, there are four slices per CLB.

Synplicity®Manufacturer of Synplify ASIC®, an application used for synthesizing ASIC designs.

Tx Abbreviation of “Transfer”.

WD Host Software Application Programming Interface, Device Driver, and utilities.

WILDSTAR A5 /PCIe VHDL ModelsHardware models used for board-level VHDL simulation of application.

15199-0000 Rev 1.2


15199-0000 Rev 1.2

9WILDSTAR A5 /PCIe Hardware Reference ManualChapter 2: Introduction

Chapter 2: Introduction

10 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 2: Introduction

15199-0000 Rev 1.2


WILDSTAR A5 /PCIe computing is a revolutionary technology combining user-programmable, reconfigurable system gates with very high memory and I/O bandwidth capacities, which allow for high-density and high-performance system designs. The Stratix V family of products is an evolution of WILDSTAR family of products with enhancements that allow for more simplistic, but accelerated design development. Stratix V products allow for low power consumption, which enables higher clock frequency and better noise margins. This significant power savings greatly reduces cost.

The above FPGA platforms can be used on WILDSTAR A5 /PCIe mainboards for a variety of applications, dependent upon customer needs. WILDSTAR A5 /PCIe mainboards allow for one IOPE and two CPEs. CPEs are populated with QDRII+ SRAM or, optionally, DDR3 DRAM memories (see Figure 2-1).

To ensure safe and reliable processing, WILDSTAR A5 /PCIe boards come equipped with a proactive thermal management system. Integrated thermal solutions are available, depending on configuration, application requirements, and environmental requirements. Please refer to the thermal management section for more information. Sensors across the board monitor power and temperature, with automatic shutdown capability to prevent excessive heat buildup. WILDSTAR A5 /PCIe boards are built with a rugged, durable design.

WILDSTAR A5 /PCIe boards support both VHDL design flow tools and the CoreFire Next Design Suite.

• The VHDL flow consists of four steps: 1) creation of VHDL design using supplied VHDL model; 2) simulation using the ModelTech® application; 3) synthesis using Synplicity®, and 4) place-and-routing using Stratix V tools.

• CoreFire Next can be used to create FPGA designs for the WILDSTAR A5 /PCIe board. The CoreFire Next Design Suite, a design application tool developed by Annapolis Micro Systems, Inc., makes it possible to create designs in a fraction of the time required for a conventional VHDL-based control flow approach.

CautionTo prevent system damage, board damage, fire, and personal injury, never use the WILDSTAR A5 /PCIe board without an appropriate thermal solution. In addition, the operational PCI chassis should have adequate cooling and airflow to ensure a Tj < 85°C temperature for a commercial board option, and Tj < 100°C for an industrial board option. Temperatures above this range can result in performance degradation and component damage. Please refer to the thermal management section for more information.

15199-0000 Rev 1.2


2.1 WILDSTAR A5 /PCIe Board ArchitectureThe WILDSTAR A5 /PCIe architecture is best illustrated in terms of Computational Processing Elements (CPEs) and I/O Processing Elements (IOPEs). WILDSTAR A5 /PCIe boards are populated with CPE0, CPE1, and IOPE0. Both DRAM and SRAM memories can be built into the board. This manufacturing build option is specified when a board is purchased.

2.2 About the WILDSTAR A5 /PCIe BoardThe WILDSTAR A5 /PCIe architecture (see Figure 2-1) has a number of processing configuration options, with the full architecture containing three processing elements.

The host computer can communicate with the WILDSTAR A5/PCIe board using the Gen 3 16x PCIe bus. Full DMA is supported to and from the board for a theoretical bidirectional bandwidth of 16 GBytes per second. Each FPGA has an 8x PCIe Gen 3 bus connection.

The CPEs are connected by a 8 pin differential data bus, and 20 lanes of HSS. There are also an 8 pin differential data bus and seven lanes of HSS connecting each CPE to the IOPE.

The WILDSTAR A5 /PCIe card can support three QSFPs for rear panel high speed I/O.

The WILDSTAR A5 /PCIe board also supports stackable mezzanine cards, offering a variety of high-fidelity analog and high speed digital I/O solutions.

The external power connector allows for additional power input to the board. Please refer to Thermal and Power Management for more information.

The WILDSTAR A5 /PCIe is well-equipped for power monitoring and thermal management. For additional information, see Thermal and Power Management.

15199-0000 Rev 1.2


Figure 2-1: WILDSTAR A5 /PCIe Block Diagram

A host computer can communicate with the WILDSTAR A5 /PCIe board via the PCI Express interface. The PCIe switch has a Non Transparent Port facing the host system which allows PCIe traffic to reach the FPGAs through the switch and looks like a single endpoint to the host system.

CPE0

Altera Stratix® V

5SGSD4, 5SGSD5, 5SGSD6, 5SGSD8,

5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9, 5SGXAB

36

CPE1

Altera Stratix® V



8X/16X PCI Express (Gen 1, 2, 3)

96

Copyright 2012-14Annapolis Micro Systems, Inc.

QDRII+ SRAM2, 4, 8, 16 MB

IOPE0

Altera Stratix® V



Gen 3 PCIeSwitch

+12VExt PWRConn

IRIG-B Option

GPIO

12


DDR3 DRAM0GB, 2GB

DDR3 DRAM0GB, 2GB





36

3636

3636

3636

3636

3636







3636

3636

3636

3636

3636

3636

QSFP+QSFP+

QSFP+

Mezz 02nd Slot

Mezz 0

Mfg Options

OR

SignalTap

IRIG-B Data

6464

Trig/1PPS

8 Bits Data

8

8

8

8

7

4

4

7

4

4

2044

JTAG

8

16

96

DDR3 DRAM 0GB, 1GB

Alternate CPE Memory Option 32

Legend

Pluggable Module

Manufacturing Option

PCI Express Up to Gen3 (7 Gbytes/s per 8x connection)

Differential Pairs

Single Ended

HiSpeed Serial IOXCVR Speed 1 up to 14.1 Gbits/s (1.71 Gbytes/s per Lane)XCVR Speed 2 up to 12.5 Gbits/s (1.52 Gbytes/s per Lane)

15199-0000 Rev 1.2


2.2.1 WILDSTAR A5 /PCIe FeaturesWILDSTAR A5 /PCIe has the following system support features:

• Uses three Stratix V FPGAs with up to 952,000 logic blocks and 550 MHz performance. Both the IOPE and the CPEs can be populated with Stratix V 5SGSD4, 5SGSD5, 5SGSD6, 5SGSD8, 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 5SGXAB FPGAs.

• 8X/16X PCIe Gen1, Gen 2, or Gen 3 to Host

• Gen 3 PCIe Between FPGAs On Board with PCIe Switch

• Up to 3926 18x18 Variable Precision Multipliers

• 28-nm copper CMOS process

• 36 high speed serial (HSS) transceivers per FPGA operating at up to 14.1Gbps

• Two Memory Banks of DDR3 DRAM at up to 800 MHz (1600 MT/s) per IOPE

• Up to approximately 25 GB/s of DRAM bandwidth per IOPE

• Up to 4GBbyes of IOPE DDR3 DRAM per board

• Option of either Six Memory Banks of QDRII+ SRAM at up to 550 MHz or Six Memory Banks of DDR3 DRAM at up to 800 MHz per CPE

• Up to approximately 38 GB/s (DRAM option) or 39 GB/s (SRAM option) of memory bandwidth per CPE

• Up to 192 MBytes of CPE QDRII+ SRAM or 12 GBytes of DDR3 DRAM per board

• Three Optional QSFP+ Connectors Provide:

• Twelve 10 Gbps Ethernet or Three 40Gbps Ethernet or Three 14Gbps FDR Infiniband

• Multi-Thread Safe Software Support

• Supports PCI Express Standard External Power Connector

• Multicolor status LED for each PE

• Supports up to two standard I/O mezzanine cards. Two mezzanine cards requires stacking and two slots.

• Clocks

• PCLK: Processor Clock, independently programmable per FPGA and differential

• HSS Reference Clocks: Six High Speed Reference clocks per IOPE, two per CPE

15199-0000 Rev 1.2


• 8x8 clock mux circuit for advanced clocking and synchronization options

• Thermal Management

• Host software can monitor IOPE and CPE junction temperatures and ambient temperature

• Integrated Heat Sink

• Power Measurement and Control

• Host software can monitor board current consumption and power supply voltage levels

• Individual IOPE and CPE power supplies and management

• Board level I/V measurements

• Host Software: API and Device Drivers for Windows and Linux

• CoreFire Next Support

• VHDL Development Environment Supported

• JTAG SignalTap Support

2.3 WILDSTAR Mezzanine I/O Daughter CardsWILDSTAR mezzanine I/O daughter cards were designed to offer many advanced capabilities. Its small size allows for advanced air flow, which gives improved thermal management. Their size and location also allow more advanced thermal solutions for the motherboard FPGAs. Many of the heatsinks designed for these mezzanine cards also include integrated EMI shields for improved analog performance. Up to two mezzanine I/O cards can be mounted on one WILDSTAR A5 /PCIe. Mezzanine I/O cards are classified using Class A and Class B.

See Appendix B: WILDSTAR Mezzanine Cards for information regarding mezzanine I/O card types, classes, and chassis slot usage.

CautionNot all WILDTAR Mezzanine Cards are compatible with Stratix V. Please contact your local FAE or salesperson for an updated list of compatible cards. Plugging in an incompatible card could damage either the mezzanine card or the FPGA baseboard.

15199-0000 Rev 1.2


15199-0000 Rev 1.2

17WILDSTAR A5 /PCIe Hardware Reference ManualChapter 3: Getting Started

Chapter 3: Getting Started

18 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 3: Getting Started

15199-0000 Rev 1.2


3.1 Unpacking and Inspecting the WILDSTAR BoardThe WILDSTAR A5 /PCIe board is shipped in a sealed, static-sensitive package. In order to protect its sensitive components from moisture and static electricity damage, the board should remain in this package until installation time.

Your WILDSTAR A5 /PCIe shipment includes the following items:

• WILDSTAR A5 /PCIe board

• WD Host Software CD-ROM, containing:

• Driver API

• Release Notes

• PDF copy of the WD Host Software Reference Manual

• PDF copy of the WILDSTAR A5 /PCIe Hardware Reference Manual

• PDF copy of the WILDSTAR A VHDL Getting Started Guide

• Paper Copies:

• WILDSTAR A5 /PCIe Hardware Reference Manual

• WD Host Software Reference Manual

When handling the WILDSTAR A5 /PCIe board, avoid touching any of the components on the board’s surface, as they are sensitive and can be easily damaged.

Inspect the board thoroughly for damage that may have occurred during shipping. If there is any apparent damage to the board or any items missing from the shipment, contact Annapolis Micro Systems, Inc. using the information provided in Technical Support of this manual.

CautionBefore removing the board from its package, be sure to be grounded of all static electricity.

15199-0000 Rev 1.2


3.2 Board Illustrations and LED DefinitionsThe following illustrations show major component locations on all WILDSTAR A5 /PCIe boards. LED definitions are also described for each board type.

Component-side views (see Figure 3-1 and Figure 3-3) and solder-side views (see Figure 3-2 and Figure 3-4) of the WILDSTAR A5 /PCIe are shown below. LED definitions are outlined in Table 3-1 through Table 3-3. For a close up LED view see Figure 3-5.

CautionThe external power connector can ONLY be plugged in when power to computer is turned off.

15199-0000 Rev 1.2


P

c I/O ctors

Figure 3-1: WILDSTAR A5 /PCIe, Rev. D, SRAM/DRAM Mainboard, Component Side

Figure 3-2: WILDSTAR A5 /PCIe, Rev. D, SRAM/DRAM Mainboard, Solder Side

Dip Switch*

CPECPE

x16 Edge Finger Extension

Mezzanine Card Connectors

IOPE External Power Connector

PCI Retainer

*See section WILDSTAR A5 /PCIe DIP Switch Settings for information on jumpers.

PCIe Switch

Signal Tap JTAG Connector

LEDs*

CI Retainer

x16 Edge Finger Extension*LED names shown in Figure 3-5.

GeneriConne

CPE1 Done LED

CPE0 Done LED

PCI Done LEDBoard Status LED

IOPE0 Done LED

15199-0000 Rev 1.2


P

ic I/O ctors

Figure 3-3: WILDSTAR A5 /PCIe, Rev. A, DRAM/DRAM Mainboard, Component Side

Figure 3-4: WILDSTAR A5 /PCIe, Rev. A, DRAM/DRAM Mainboard, Solder Side

Dip Switch*

CPECPE


Mezzanine Card Connectors

IOPE External Power Connector

PCI Retainer

*See section WILDSTAR A5 /PCIe DIP Switch Settings for information on jumpers.

PCIe Switch

Signal Tap JTAG Connector

LEDs*

CI Retainer


*LED names shown in Figure 3-5.

GenerConne

CPE1 Done LED

CPE0 Done LED

PCI Done LEDBoard Status LED

IOPE0 Done LED

15199-0000 Rev 1.2


Figure 3-5: WILDSTAR A5 /PCIe, Mainboard, Close-Up LEDs, Top Solder Side

CP

E1

LE

D

IOP

E0

LED

0

CP

E0

LED

IOP

E0

LE

1

IOP

E0

LED

2

IOP

E0

LED

3

*See tables below for LED definitions.C

PE

0 L

ink

IOP

E0

Link

CP

E1

Link

PC

I Con

trol

ler

Link

Pow

er

Goo

d

Host System Link

15199-0000 Rev 1.2


te

Table 3-1: WILDSTAR A5 /PCIe Mainboard, User LEDs

Table 3-2: WILDSTAR A5 /PCIe Mainboard, PCIe Link LEDs

Table 3-3: WILDSTAR A5 /PCIe Mainboard, Status LEDs

LED Name Label LED Color Description Default State

CPE0 LED CPE0

Red/Green/Blue User-Controlled LEDs from FPGAs OFF

CPE1 LED CPE1

IOPE0 LED0 IOPE 0

IOPE0 LED1 IOPE 1

IOPE0 LED2 IOPE 2

IOPE0 LED3 IOPE 3

LED Name Label LED Color Description Default State

CPE0 Link PG0

Green

Shows PCIe link status of each PCIe link. Shows PCIe link status of each PCIe

link. The blink rate shows the bus speed as follows: 1 Hz: Gen1, 2 Hz: Gen 2,

Solid ON: Gen 3

OFF

CPE1 Link PG4 OFF

IOPE0 Link PG1 OFF

PCI Controller Link PG5 2 Hz

Host System Link PG8Host System Dependent

LED Name Label LED Color Description Default Sta

Board Status CONFIG_RGB Red/Green/BlueShows board is ready and when a transfer is

occurring to PCI controller.Green

CPE0 Done CPE0_Done

GreenShows device is programmed/operational.

OFF

CPE1 Done CPE1_Done OFF

IOPE0 Done IOPE0_Done OFF

PCI Controller Ready

D17 ON

Power Good PG_ALL Indicates board power is good. ON

15199-0000 Rev 1.2

25WILDSTAR A5 /PCIe Hardware Reference ManualChapter 4: Installation

Chapter 4: Installation

26 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 4: Installation

15199-0000 Rev 1.2

27WILDSTAR A5 /PCIe Hardware Reference ManualChapter 4: Installation

This chapter provides hardware installation instructions for WILDSTAR A5 /PCIe boards, as well as switch setting descriptions and PE, board, and system reset options.

Note:A PDF of the WILDSTAR A5 /PCIe Hardware Reference Manual can be found on the Documentation CD-ROM included with your board.

4.1 WILDSTAR A5 /PCIe InstallationFollow the steps below to install the WILDSTAR A5 /PCIe board into the host system.

1. To prevent static electricity damage to the board, ensure that you are wearing a properly connected ground strap.

2. Shut down the host system and power off.

3. Remove the chassis cover to access the motherboard’s PCI connectors.

4. For the available slot, remove the rear access panel.

5. Insert the WILDSTAR A5 /PCIe board into a PCI Express x8 or x16 slot. Make sure that the PCI backplate is lined up with the rear access panel.

6. Confirm that no two boards have any touching components.

7. Screw down the PCI backplate into the rear access panel.

8. Replace the cover to the host system chassis.

To remove the /PCIe board, connect a ground strap to the user and power off the host system.

CautionTo prevent system damage, board damage, fire, and personal injury, never use the WILDSTAR A5 /PCIe board without an appropriate thermal solution. In addition, the operational PCI chassis should have adequate cooling and airflow to ensure a Tj < 85°C temperature for a commercial board option, and Tj < 100°C for an industrial board option. Temperatures above this range can result in performance degradation and component damage. Please refer to the thermal management section for more information.

CautionTo prevent personal injury, never place your fingers near the WILDSTAR A5 /PCIe board’s heatsink fans.

CautionCare should be taken not to catch the QSFP connectors on the PCIe chassis when board is inserted, as it can damage the QSFP cage.

15199-0000 Rev 1.2

28 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 4: Installation

4.1.1 Power Up SystemAfter all cable connections have been made and the board has been properly plugged in, turn on power to the host system.

Once the board has been installed in the host system and the host machine has been powered up, the host soft-ware and VHDL models can be installed.

Note:Instructions for installing host software on WILDSTAR A5 /PCIe boards can be found in the host software release notes accompanying the board.

4.1.2 WILDSTAR A5 /PCIe DIP Switch Settings

Table 4-1: DIP Switch: SW1

4.2 WILDSTAR A5 /PCIe ResetsBelow are details for system resets on the WILDSTAR A5 /PCIe boards.

4.2.1 WILDSTAR A5 /PCIe ResetsA reset from the PCI Express bus will cause the WILDSTAR A5 /PCIe card’s PCI controller to be reset and all of its PEs to be deprogrammed. The board will need to be reopened after a PCI reset.

Position Label ON OFF Default Settings

1 Reserved OFF

2Flash Write

ProtectFlash Locked Flash Unlocked OFF

3 Reserved OFF

4 Reserved ON

15199-0000 Rev 1.2

29WILDSTAR A5 /PCIe Hardware Reference ManualChapter 5: Technical Support

Chapter 5: Technical Support

30 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 5: Technical Support

15199-0000 Rev 1.2

31WILDSTAR A5 /PCIe Hardware Reference ManualChapter 5: Technical Support

If you have any questions about installing, programming, using, or maintaining your WILDSTAR A5 /PCIe board, please call the WILDSTAR Technical Support team at (410) 841-2514, fax at (410) 841-2518, or send e-mail to [email protected]. Our web site address is http://www.annapmicro.com.

The suggestions listed below will help us respond to your questions more quickly.

5.1 Board Identification NumbersEach Annapolis Micro Systems board is prominently labeled with three unique codes: the Product Configuration Code (PCC), the Serial Number (SN), and the Revision Level Code (RLC). You can also find these codes by installing the board and running wsinst.exe from the host software CD.

• The Product Configuration Code (PCC) identifies PE type, memories, clocking, and other options selected for the particular board.

• The Serial Number (SN) is a unique number identifying each board.

• The Revision Level Code (RLC) includes information about revisions and engineering modifications made to the board.

See Figure 5-1 for the locations of these labels.

15199-0000 Rev 1.2

http://www.annapmicro.com

mailto:[email protected]

32 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 5: Technical Support

Figure 5-1: Labels for WILDSTAR A5 /PCIe Serial Number, PCC, and RLC

When contacting Annapolis Micro Systems with board-related questions, please include these codes in your query, as well as the information listed below:

• Board operating system

• Host software version

• Host platform

• Host OS

• VHDL version number

• API version

• Driver versions

• CoreFire Next version being used (if applicable)

RLC PCCSerial Number

15199-0000 Rev 1.2

33WILDSTAR A5 /PCIe Hardware Reference ManualChapter 6: Hardware Reference

Chapter 6: Hardware Reference

34 WILDSTAR A5 /PCIe Hardware Reference ManualChapter 6: Hardware Reference

15199-0000 Rev 1.2


This chapter contains hardware reference information for the WILDSTAR A5 /PCIe board, including thermal management, clocking, and backplane specifications, and optional mezzanine I/O cards.

6.1 WILDSTAR A5 /PCIe Board Specifications Table 6-1 specifies the physical dimensions and operating range for all WILDSTAR A5 /PCIe boards:

Table 6-1: WILDSTAR A5 /PCIe Specifications

Table 6-2: WILDSTAR A5 /PCIe Tolerances

Physical Dimensions:

Length: 312.00 mm/12.283 inWidth: 111.15 mm/4.376 inHeight:

1 Slot Active Cooling Option: 14.48mm/0.57 in2 Slot Active Cooling Option: 37.327mm/1.47 in

Weight: 1 Slot Active Cooling Option: 17.4oz./493g2 Slot Active Cooling Option 24.32 oz./689.45g

Operating Range:Temperature (Commercial): 0º to 70ºCTemperature (Industrial): -40º to +85ºC

Backplane Supplied Voltage Tolerance

+3.3V +/- 5%

+12.0V +/- 10%

15199-0000 Rev 1.2


6.2 Thermal and Power ManagementThis section describes WILDSTAR A5 /PCIe temperature sensing, voltage and current limits, heatsink information, power functions, as well as external power capabilities.

6.2.1 WILDSTAR A5 /PCIe HeatsinksWILDSTAR A5 /PCIe boards can be ordered with one of the following Cooling Solutions:

• 2 Slot Active Cooling - Recommended for high-power applications.

• 1 Slot Active Cooling - Only recommended for low power applications.

If two PCIe slots are available, the 2 Slot Active Cooling option provides the best cooling and has been demonstrated to allow very high power applications (200W+) to operate indefinitely while keeping temperatures inside of rated limits.

If two PCIe slots are not available, than a 1 Slot Cooling option must be selected.

The 1 Slot Active Cooling option is only recommended for relatively low power applications (<100W) in chassis which do not provide adequate airflow, as noted above.

Note:Regardless of the Cooling option selected, all temperature sensors must always be kept inside of rated limits. See Temperature Sensing for more information regarding Temperature Sensors.

Note:All WILDSTAR A5 /PCIe boards are shipped with a heatsink installed. The heatsink is not removable except by the factory.

Figure 6-1 and Figure 6-2 show multi-FPGA heatsinks mounted on WILDSTAR A5 /PCIe boards. As stated in Chapter 2: Introduction, using a multi-FPGA heatsink (heatsink that covers multiple FPGAs), boards can make use of a higher amount of power without exceeding maximum component junction temperature. These larger heatsinks also act as a stiffener for the boards, making them sturdier.

CautionWILDSTAR A5 /PCIe boards should never be run without the supported heatsink or heatsink/fan combination. Otherwise, the board could permanently be damaged.

15199-0000 Rev 1.2


Figure 6-1: WILDSTAR A5 /PCIe 1 Slot Active Cooling Mainboard, Component Side

Figure 6-2: WILDSTAR A5 /PCIe 2 Slot Active Cooling, Rev. A, DRAM/DRAM Mainboard, Component Side

1 Slot Active Cooing Heatsink

2 Slot Active Cooing Heatsink

15199-0000 Rev 1.2


6.2.2 Temperature SensingHigh performance computing engines, such as the WILDSTAR A5 /PCIe, can generate large amounts of power with ease. Without careful consideration of the operating environment, high power applications can create a buildup of heat which can cause the board to exceed its maximum temperature ratings. Chassis selection can have a large effect on the cooling capacity.

Airflow of greater than 1000LFM through the WILDSTAR A5 /PCIe heatsink is generally required. This airflow is generally met with an Enterprise Class Server. Desktop Workstations often do not provide adequate airflow to keep high performance applications within rated limits. Desktop Workstations generally require supplemental airflow to be provided via alternative means, such as an adjacent slot PCIe Slot VGA Cooler. For this reason, Enterprise Class Servers are strongly recommended.

All applications should monitor available sensors to ensure proper cooling has been provided to keep the sensors within their operating limits, as specified by Table 6-3.

Table 6-3: WILDSTAR A5 /PCIe Sensors

The PCI Controller, CPEs, and IOPEs on each board contain devices that monitor the junction temperatures of these components. Additional sensing diodes are located at various board locations to monitor ambient temperature. Information concerning temperatures can be revealed by using the Annapolis Micro Systems, Inc. software included in your WILDSTAR A5 /PCIe shipment.

See the WD Software Reference Manual for details regarding sensor and temperature monitoring interface calls.

Note:WILDSTAR A5 /PCIe temperatures monitoring sensors are accurate within +/- 1˚C.

Figure 6-3 shows temperature monitoring points on the WILDSTAR A5 /PCIe board. Temperature sensors are embedded within the labeled components. The components are located underneath the board’s heatsink.

Sensor Name Min (°C) Max (°C) Description

pciESwitch/temperature 0 102 PCIe Switch Junction temperature

temperature_ambient0 0 70 PCB (Ambient) temp sensor 0

temperature_ambient1 0 70 PCB (Ambient) temp sensor 1

iope0/temperature 0 85 IOPE0 Junction Temperature

cpe0/temperature 0 85 CPE0 Junction Temperature

cpe1/temperature 0 85 CPE1 Junction Temperature

CautionThe Stratix V CPE and IOPE junction temperatures on commercial WILDSTAR A5 /PCIe board types should never exceed 85˚C. CPE and IOPE junction temperatures on industrial WILDSTAR A5 /PCIe board types should never exceed 100˚C. Temperatures above these ranges may result in performance degradation and component damage.

CautionIf a WILDSTAR A5 /PCIe board fan fails, it must promptly be replaced at the factory to avoid heat damage to the board.

15199-0000 Rev 1.2


Figure 6-3: WILDSTAR A5 /PCIe Mainboard, Temperature Monitoring Points (Component Side)

Note:Temperature monitoring points are the same for the 1 Slot Active Cooling and 2 Slot Active Cooling configuration options.

CPE1CPE0

IOPE0PCI ControllerAmbient1

Ambient0

15199-0000 Rev 1.2


6.2.3 Power ManagementThe power consumed by the WILDSTAR A5 /PCIe board directly correlates to the total number of flip-flops in the design and the frequency at which it is run. It is important to consider the power consumption of each target application so that the restrictions of the target chassis can be met with respect to available power and adequate airflow.

Table 6-4: WILDSTAR A5 /PCIe Power Specifications for External Power Connector

Note:The PCIe slot may shut down if its power limit is exceeded. PCIe power slot limits vary according to machine. When the external power connector is populated, this potential problem is avoided because it will draw approximately 15W from the slot.

Table 6-5: External Power Connector Pinout

Input Voltage Range (V) Connector Current Rating (A)

+12V 10.8 to 13.2 24

PIN Number Power (V)

1 +12V

2 +12V

3 +12V

4 GND

5 GND/sense

6 GND


CautionPlease validate that the intended PCIe chassis connector plug is compatible with the WILDSTAR A5 /PCIe external power connector.

15199-0000 Rev 1.2


Figure 6-4: External Power Connector Pinout Illustration

CautionWILDSTAR A5 /PCIe Users (all revs):

According to PCIe specifications, the total power should not exceed 150 watts per slot when using one external power connector. If the power consumption for an application exceeds 150 watts per slot, the user must ensure that the chassis is capable of supplying adequate power and cooling to run the application.

CautionTo prevent system damage, fire, and personal injury, never use the WILDSTAR A5 /PCIe board without the heat sink fan installed. In addition, the operational PCI chassis should have adequate cooling and airflow to ensure a Tj < 85˚C temperature during application operation. Temperatures above this range may result in performance degradation and component damage.

15199-0000 Rev 1.2


6.3 Power ConnectorsThe right angle-back external power connector (see Figure 6-5) faces towards the PCI retainer handle on the right hand side of the board. The right-angle top external power connector (see Figure 6-6) appears the same as the

right angle-angle back external power connector, however, it is turned 90 counterclockwise to the connector orientation in Figure 6-5. The vertical power connector (see Figure 6-7) faces upward, perpendicular to the plane of the board.

Note:The right-angle external power connector used on the WILDSTAR A5 /PCIe is Molex P/N: 45558-0002. The vertical external power connector used on the WILDSTAR A5 /PCIe /PCIe is Molex P/N: 15-24-4557 (black).

Note:The mating part for the external power connector is Molex P/N: 15-24-4048. This plug is defined by the PCIe specification.

Figure 6-5: Right-Angle Back External Power Connector


Right-Angle Back External Power Connector

Top Edge of MainBoard PCI Retainer

15199-0000 Rev 1.2


Figure 6-6: Right-Angle Top External Power Connector

Figure 6-7: Vertical Power Connector

Right-Angle Top External Power Connector


Vertical Power Connector


15199-0000 Rev 1.2


6.4 ClockingThe WILDSTAR A5 /PCIe clocking structure (see Figure 6-8) is very flexible in that it allows all programmable clocks on a board to be synchronized to a common source. Each FPGA module has its own PLL so can run at different rates than other FPGA modules, if desired. The 8x8 crossbar and PLLs are programmed via provided software API.

Figure 6-8: WILDSTAR A5 /PCIe Clocking

• SYNCCLK: Designed to be a free-running clock that the Si5375 PLL can synchronize to, if desired

• 1PPSCLK: This clock can be a free-running clock or a trigger pulse. It goes directly into an FPGA pin

• PCLK: PCLK is the main processing clock for the FPGA

• MEMCLK (MCLK): MCLK is used to run the memory interfaces on the FPGA

• HSS REFCLKx: These clocks are for the high speed serial (HSS) interfaces. Each clock goes to each side of the device. The PCIe interface has it’s own fixed 100 MHz clock

• IO Card Clock x: These are clocks driven from the IO card. Often an ADC or DAC will provide a divided down version of the sample clock on these pins.

IOPE/CPE

Altera S5

Silabs Si5374

(4 PLLs)

1:5 clock buffer

125 MHz Oscillator

MEM CLK (2)

PL

LA

PL

LB

PL

LC

PL

LD

PCLK

HSS REFCLK1 (2)

HSS REFCLK0 (2)P

LL

AP

LL

BP

LL

CP

LL

DPLL REFCLK INPUTS (4)

SYNCCLK (1)

OTHER FPGA MODs

REF

(Can be used for Loop Timing)

Buffer/MuxPCIe System CLK OTHER FPGA

MODs/PCIe Switch

HSS REFCLK

Clock Mux(8x8 XBAR)

IO CARD Clock In 0

OTHER FPGA MODs

FPGA MODULE

1PPSCLK (1)

CC GPIO (SW Trigger)

IOPE0 FPGA Clock

FPCLK

SMA OUTFPCLK

FPGA Clock to ClockMux (From IOPE0 Only)

OTHER FPGA MODs

Silabs Si5374

(4 PLLs)

IOPE ONLY

PL

LA

PL

LB

PL

LC

PL

LD

PL

LA

PL

LB

PL

LC

PL

LD

REF

PLL REFCLK INPUTS (4)

HSS REFCLK2 (2)

HSS REFCLK3 (2)

HSS REFCLK4 (2)

HSS REFCLK5 (2)

Aux Ribbon Cable Connector

REFCLK

15199-0000 Rev 1.2


• PCI Controller GPIO: This is driven by a GPIO on PCI Controller. It can be used as a low precision SW trigger.

• IOPE0 FPGA Clock: This is driven by IOPE0 and can be either a clock or a trigger.

• FPCLK: This differential clock input is used to receive a clock/trigger via the ribbon cable connector.

• SMA OUT: This clock is used to send a clock/trigger out the ribbon cable connector (usually to SMA). The clock coming out will be a differential clock.

• Loop Timing Clocks: The FPGA can drive a source clock for any of the four clocks generated by the Si5375 PLL. This allows for one clock to be used for SONET loop timing where one HSS reclk provides the RX clock and one HSS REFCLK provides the TX clock based on the recovered RX clock fed to PLL from FPGA.

15199-0000 Rev 1.2


15199-0000 Rev 1.2

47WILDSTAR A5 /PCIe Hardware Reference ManualAppendix A: CoreFire Next Support

Appendix A: CoreFire Next Support

48 WILDSTAR A5 /PCIe Hardware Reference ManualAppendix A: CoreFire Next Support

15199-0000 Rev 1.2


The CoreFire Next Design Suite is a dataflow-based development system that brings new levels of ease and speed to FPGA programming on Annapolis Micro Systems, Inc. high-performance motherboards, I/O cards, and mezzanine cards.

The CoreFire Next environment supplies user-made connections between ready-made programming modules, or cores, and manages multiple domain requirements automatically. CoreFire Next eliminates the need for hardware design languages: the user simply creates dataflow diagrams by dragging and dropping cores, or building blocks, from the libraries, and connecting their ports. Cores automatically work together to handle synchronization, manage clocks and other low level hardware signals, and guarantee correct control by design. CoreFire Next allows standard data types and supports data type propagation, where modifying a data type will automatically propagate through the rest of the CoreFire Next design. As a result, CoreFire Next allows the user to program and debug complex FPGA designs at a high level of proficiency.

CoreFire Next’s drag-and-drop method of building designs allows for ease of use, which helps make the tool easy to learn. CoreFire Next presents the user with a simple way of visualizing designs, rather than extensive and confusing code. Because of this, the user does not have to be a skilled or experienced digital hardware designer. Designers of many different disciplines can use CoreFire Next to create applications.

The CoreFire Next Design Suite allows users to incorporate proprietary source code, such as VHDL, into CoreFire Next designs through the EDIF (Electronic Design Interchange Format). This can be useful in cases where users have “golden source” code.

CoreFire Next mitigates schedule risk by offering design reliability, whereas conventional designs can be inconsistent and undependable. CoreFire Next tools and modules are extensively optimized, tested, and validated before a release is completed. This ensures that the user can concentrate on solving the problem at hand. CoreFire Next works with Annapolis Micro Systems, Inc. COTS boards, which saves user’s valuable engineering time and development dollars. Training classes, as well as application support, are available to CoreFire Next customers.

CoreFire Next provides a straight forward and time efficient method of migrating current and future generation FPGA designs. To complete a design flow conversion, simply reimport the original diagram, make minor adjustments to compensate for architectural changes, and recompile the design. CoreFire Next will rebuild the design to allow for the desired support. Switching designs from one mainboard family to another, using CoreFire Next, can be done quickly and with ease. Alternative methods of design migration, VHDL and Verilog, are time consuming and complicated.

15199-0000 Rev 1.2


The CoreFire Next Design Suite is a grouping of all the tools necessary to design, build, test, and field an applica-tion.

Components of the CoreFire Next Design Suite include the following:

• CoreFire Next Application Builder – FPGA design and build tool

• CoreFire Next Application Debugger – Runtime debugging and analysis tool

• CoreFire Next Design Suite Online Help– Context-sensitive help for CoreFire Next interfaces and tools

• CoreFire Next Host API for the Java Platform – A java interface that allows developers to interact with CoreFire Next design cores, performing tasks such as initialization, debugging, and data monitoring.

• CoreFire Next ANSI-C Host API – Host API for C

• CoreFire Next Examples – See the CoreFire Next Getting Started Guide for examples showing how to build simple applications in CoreFire Next.

15199-0000 Rev 1.2


A.1 CoreFire Next Application BuilderAs the main interface of the CoreFire Next Design Suite, the Application Builder includes core libraries and a work area for assembling functional processing element (PE) design diagrams. CoreFire Next cores are the building blocks used to create PE designs in the CoreFire Next Application Builder. The Application Builder features a unique drag-and-drop capability for combining cores into ready-to-run programs. An extensive array of cores is available in the CoreFire Next core libraries, along with Annapolis Micro Systems, Inc. board-specific support packages. A board support core library tab will appear after the specific board is identified for a given FPGA design.

CoreFire Next protocol support allows application developers to use industry-standard and proprietary protocols for external communication. Each protocol is supported by a unique core or cores, and represents a protocol interface to a physical connection on the board.

Figure A-1: CoreFire Next Application Builder with Example Diagram

15199-0000 Rev 1.2


A.2 CoreFire Next Application DebuggerThe CoreFire Next Application Debugger is a tool that allows the user to interact with designs created in the CoreFire Next Application Builder. The user can add debugging cores to CoreFire Next designs and see their output in a custom debugger interface. Based on user settings, the Debugger controls the amount of data passed through each debug core and collects data from those cores for display and interpretation. By incorporating Debug cores into a design, the user can step dataflow through either a tabular or waveform interface.

The CoreFire Next Application Debugger has separate interfaces for accessing memory banks and registers. Along with monitoring dataflow, the Debugger can also display board temperatures and power numbers.The CoreFire Next Application Debugger can be run on Windows NT, 2000, XP, and Linux platforms. In order for the CoreFire Next Application Debugger to work properly, the WILDSTAR software for the target board must first be installed.

Figure A-2: CoreFire Next Application Debugger

15199-0000 Rev 1.2

http://www.annapmicro.com/





A.3 CoreFire Next Design Suite Online HelpCoreFire Next Design Suite Online Help can be accessed by choosing Help on the CoreFire Next main menu and choosing one of the following options:

• Help Contents: Open a new browser containing a searchable CoreFire Next Help interface.

• Search: Open an in-window tab with a search field for searching the CoreFire Next Help documentation.

• Dynamic Help: Open an in-window tab to display help associated with selected items.

The online help and this reference manual both describe CoreFire Next menus, toolbars, and program interfaces, as well as the cores residing in each library. Both also explain how to initiate a CoreFire Next project and describe the various programming and debugging tools available.

A.1 CoreFire Next Host API for the Java PlatformA java interface that allows developers to interact with CoreFire Next design cores, performing tasks such as initialization, debugging, and data monitoring.

A.2 CoreFire Next ANSI-C Host APIA C interface that allows developers to interact with CoreFire Next design cores, performing tasks such as initialization, debugging, and data monitoring.

A.3 Control Flow versus Data FlowCoreFire Next allows for dataflow-based FPGA programming, as opposed to conventional control-based FPGA programming. CoreFire Next dataflow cores represent data flow graphically as a series of mathematical and Boolean operations.

Users can utilize CoreFire Next to plan how data will flow through the system. As the user selects and connects cores, CoreFire Next automatically creates all design needs. It quickly and invisibly manages all core interconnections, multiple clock speed requirements, and other control-related tasks.

15199-0000 Rev 1.2


15199-0000 Rev 1.2

55WILDSTAR A5 /PCIe Hardware Reference ManualAppendix B: WILDSTAR Mezzanine Cards

Appendix B: WILDSTAR Mezzanine Cards

56 WILDSTAR A5 /PCIe Hardware Reference ManualAppendix B: WILDSTAR Mezzanine Cards

15199-0000 Rev 1.2

57WILDSTAR A5 /PCIe Hardware Reference ManualAppendix B: WILDSTAR Mezzanine Cards

Allowable mezzanine card configuration with Annapolis Micro Systems WILDSTAR mainboards is determined by card class. Table B-1 describes the differences between each class.

B.1 WILDSTAR Mezzanine Card Class Descriptions

Table B-1: Mezzanine I/O Card Class Descriptions

ClassStandard Connector

Stack HeightsOptional Connector

Stack Heights?PCI Slot Location

Class A 11 No 1 Only

Class B 5/19 Yes 2 Only

CautionNot all WILDTAR Mezzanine Cards are compatible with Stratix V. Please contact your local FAE or salesperson for an updated list of compatible cards. Plugging in an incompatible card could damage either the mezzanine card or the FPGA baseboard.

15199-0000 Rev 1.2

58

WILDSTAR A5 /PCIe Hardware Reference ManualAppendix B: WILDSTAR Mezzanine Cards

B.2 WILDSTAR Mezzanine Card Views

Figure B-1: Mezzanine Card Side View

Figure B-2: Mezzanine Card End View

15199-0000 Rev 1.2

59WILDSTAR A5 /PCIe Hardware Reference ManualAppendix C: WILDSTAR 6 Statement of Volatility

Appendix C: WILDSTAR A5 /PCIe Statement of Volatility

60 WILDSTAR A5 /PCIe Hardware Reference ManualAppendix C: WILDSTAR 6 Statement of Volatility

15199-0000 Rev 1.2

61

15199-0000 Rev 1.2

WILDSTAR A5 /PCIe Hardware Reference ManualAppendix C: WILDSTAR 6 Statement of Volatility

April 30, 2014

Dear Sir,

As you requested, here are details of the memory volatility of our WILDSTAR A5 /PCIe mainboards.

WILDSTAR A5 /PCIe mainboards have Static and Dynamic RAM, both of which are volatile.

WILDSTAR A5 /PCIe mainboards also have non-volatile flash memory for the PCI controller FPGA and for each CPE’s and IOPE’s FPGA.

The PCI controller flash loads the PCI controller FPGA upon boot-up of the host computer. We provide a firmware configuration upgrade utility that can overwrite the flash using update information compiled into the utility. This util-ity cannot program the flash with anything other than the supplied Annapolis Micro Systems, Inc. firmware configu-ration upgrade. Each release CD includes this utility.

If you have any additional questions about our products, please don’t hesitate to call.

Sincerely,

Paul KowalewskiGeneral Manager

62 WILDSTAR A5 /PCIe Hardware Reference ManualAppendix C: WILDSTAR 6 Statement of Volatility

15199-0000 Rev 1.2

63WILDSTAR A5 /PCIe Hardware Reference ManualAppendix D: WILDSTAR 6 /PCIe Generic I/O Connector Specification

Appendix D: WILDSTAR A5 /PCIe Generic I/O Connector

Specification

64

15199-0000 Rev 1.2

WILDSTAR A5 /PCIe Hardware Reference ManualAppendix D: WILDSTAR 6 /PCIe Generic I/O Connector Specification


Two ribbon cable connectors are located on the back of the WILDSTAR A5 /PCIe motherboard (see Figure D-1). Each connector has eight data pins which go to either CPE0 or CPE1, depending on the connector.

A Flat Flex cable is available to attach to the ribbon cable connectors (see Figure D-2). Part numbers are shown in Table D-1.

Table D-1: Flat Flex Cable Part Numbers

Cable Length Part Number

3 inch Molex 21020-0251

4 inch Molex 21020-0253

5 inch Molex 21020-0257

6 inch Molex 21020-0259

8 inch Molex 21020-0263

Caution

Signals in the two ribbon cable connectors are not 3.3V compatible.

15199-0000 Rev 1.2

66


Figure D-1: WILDSTAR A5 /PCIe Ribbon Cable Connector Locations

Ribbon Cable Connector (Closed)

Ribbon Cable Connector (Flipped Open to Allow for

Flat Flex Cable Installation)

15199-0000 Rev 1.2


Figure D-2: WILDSTAR A5 /PCIe Ribbon Cable Installation

Flat Flex Cable Installed (Connector Closed)

15199-0000 Rev 1.2

68


D.1 Signal Description

IO1_D[7:0]: Connected to CPE1. This bus can be eight single-ended bits. This bus can also be four differential sig-nals. D5 can be a Local Clock (LC) on the CPE for single-ended use, and D4/D5 can be used for the LC input when used differentially.

IO0_D[7:0]: Connected to CPE0. This bus can be eight single-ended bits. This bus can also be four differential sig-nals. D5 can be a Local Clock (LC) on the CPE for single-ended use, and D4/D5 can be used for the LC input when used differentially.

CLKIN +/-: LVDS clock input connects to the clock mux. This clock can be used for SYNCCLK, which is an addi-tional clock input to the IOPE used for the 1PPS clock or another clock frequency. This clock can also be used to source the board PCLK.

Requirements:• V(IH) Input High Voltage: 900-2500mV

• V(IL) Input Low Voltage: 0-(V(IH)-100mV)

• V(IN) Input Voltage Swing: 100-1700mV

• V(DIFF_IN) Differential input voltage: 200mV (min)

CLKOUT +/-: LVDS output connects from the clock mux. This clock can be PCLK, a clock from the IO card (such as an ADC/DAC sample clock) or CLKIN from above.

+5V_Conn0: +5V on connector 0. This pin can supply 1.5A and has a 1.5A fuse on the mainboard.

+5V_Conn1: +5V on connector 1. This pin can supply 1.5A and has a 1.5A fuse on the mainboard.

15199-0000 Rev 1.2


D.2 Connector Definition

Table D-2: Connector Definition

Note:The connectors are purposely mirrored to allow a ribbon cable to be connected between them for loopback testing.

Connector 0 (J13): Connector 1 (J14):

Pin Number

Signal DirectionSource/

DestionationSignal Direction

Source/Destionation

1 +5V_Conn0 OUT Power Not Connected N/A N/A

2 +5V_Conn0 OUT Power GND N/A Power

3 +5V_Conn0 OUT Power CLKOUT+ BI Clock MUX

4 GND N/A Power CLKOUT- BI Clock MUX

5 IO0_D0 BI CPE0 GND N/A Power

6 GND N/A Power IO1_D7 BI CPE1















21 CLKIN- IN Clock MUX GND N/A Power

22 CLKIN+ IN Clock MUX +5V_Conn1 OUT Power

23 GND N/A Power +5V_Conn1 OUT Power

24 Not connected N/A N/A +5V_Conn1 OUT Power

15199-0000 Rev 1.2

Date post:	11-Dec-2021
Category:	Documents
Upload:	others
View:	8 times
Download:	0 times

WILDSTAR A5 /PCIe Hardware Reference Manual

Documents