The increase of hot carrier degradation with decreasingwire width in nanowire gate-all-around (GAA)MOSFETshas been investigated through experiment and device simulation. From the systematical analysis of measure-ment and simulation, it is found that the increase of device degradation in narrow devices is dominantlygoverned by the increased current density, the large lateral and vertical fields, and the increased interface stategeneration rather than by the reducedfloating body effects. Themore significant hot carrier degradationwith de-creasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires.
Although hot carrier effects (HCE) in CMOS devices are thought to benot a serious reliability issue for the low operating voltages, HCE is still amajor concern for reliability issues in nanoscale CMOSdevices. In the lit-erature, there are contradicting reports showing that, compared withwide channel or fin width in FinFETs or tri-gate MOSFETs, a devicewith narrow channel or fin width showsmore or less hot carrier degra-dation [1–4]. The less hot carrier (HC) degradation in narrow deviceshas been explained by a reduced actual stress voltage due to the largevoltage drop at the source and drain regions [2], and a less floatingbody effect especially in SOI devices [3]. However, the enhanced HCdegradation in narrow devices has been explained by a higher electronconcentration at the fin corner and a higher concentration of danglingbonds at the side channel surface in FinFETs [4]. Currently there is an in-teresting report on a simple geometric effect explaining that the gateoxide captures more effectively the scattered hot carriers for narrowerfin devices [5]. Themajor hot carrier mechanismwith different channelor fin widths in FinFETs or tri-gate devices is still under debate. Ithas been also reported that HCE with decreasing narrow diameter isenhanced in gate-all-around twin silicon nanowire field effect transistordue to increased vertical electric field on the surface silicon nanowirechannel [6].
Generally, the electrons in the channel of theMOSFET can gain a suf-ficient energy from the high lateral field to trigger the impact ionization[7]. Some of the energetic electrons gain sufficient energy to overcomethe oxide energy barrier or tunnel into the gate oxide, leading to thegeneration of traps at the interface (Nit) or within the bulk oxide (Not)
ire width dependence of hotoi.org/10.1016/j.microrel.201
[8]. Therefore, hot carrier generation rate is determined by the productof the drain current and the lateral electric field. The device degradationis governed by the injected electron concentration and the Si–SiO2 in-terface quality. In our previous study [9], the increase of HC degradationwith decreasing wire width in GAA MOSFETs was explained by the in-crease of actual voltages stressed to the intrinsic part of the transistor.
In this work, we investigated several factors which affect theincrease of HC degradation with decreasing wire widths, such as, thedrain current density, lateral electric field, vertical electric field, andthe generation of interface traps. In addition, we investigated thefloating body effect which results in the less HC degradation in narrowdevices. There has been so far no systematic experimental study tounderstand the wire width dependence of HCE in GAA MOSFETs. Thiswork essentially addresses this aspect by comparing measurementwith simulation.
2. Transistor details and simulation
Silicon nanowire GAA MOSFETs fabricated on p-type (100) bulkwafer were studied. The suspended nanowires were completely sepa-rated from a substrate using the one-step route of reactive-ion etchingknown as the Bosch process [10]. The tetraethyl orthosilicate (TEOS)with thickness of 70 nm was employed for the device isolation aswhat STI does in conventional CMOS process. More detailed processwas explained in our previously reported work [11]. A 2 nm-thicktunneling oxide was thermally grown on a nanowire, and then a2 nm-thick trapping layer of SiN and a 2 nm-thick blocking oxidewere deposited using the LPCVD process. The wire height of fabricatednanowire GAA devices was finally 10 nm and the width was rangedfrom 10 nm to 130 nm. The gate length was 200 nm. In order to charac-terize HC degradation, the stress VDS and stress timewere 3.0 V and 1 h,
carrier degradation in silicon nanowire gate-all-aroundMOSFETs, Mi-5.06.127
respectively. Since the threshold voltage increases with a decrease of thewirewidth, the devices were stressed at the gate biases VGS−VT= 2.5 Vand VGS = 3.0 V.
In order to explain the wire width dependence of HC degradation innanowire GAA devices, the device simulation has been carried out usingthe 3-dimensional ATLAS software [12]. The physicalmodels accountingfor electric field-dependent carriermobility, velocity saturation, SRH re-combination and generation, and impact ionization have been includedin the simulation. The setup is matched with fabricated devices bysimulating with device dimension (i.e. a 200 nm gate length, a 2/2/2 nm SONOS gate dielectric, a wire width from 10 nm to 130 nm).The uniform p-type doping concentration of the nanowire is assumed asNA = 1 × 1015 cm−3.
3. Results and discussion
Fig. 1 shows a plot of HC induced drain current degradation in thesaturation region (ΔIDS/IDS) as a function of wire widths (W) for differ-ent stress VGS at room temperature. One can clearly see that ΔIDS/IDSincreases as the wire width becomes narrower. In the literature [1–4],HC degradations in double gate and tri-gateMOSFETs have been report-ed to either increase or decrease with fin width according to differentstudies. This inconsistent result can be attributed to the different HCmechanisms with the fin width because the electric field distributionis influenced according to different device structures and doping profile.In this work, we discussed in depth the reasons for the increase of HCdegradationwith decreasingwirewidths through 3-dimensional devicesimulation.
The first reason for the increase of HC degradation for narrow de-vices is the increase of HC generation which is determined by the prod-uct of the drain current and the lateral electric field. Fig. 2 shows themeasurement of the current density (IDS/A) as a function of the wirewidths. The cross section area of the nanowire (A) is given by the prod-uct of thewire height andwidth. The increase of the current density canbe observed with decreasing wire widths. To investigate this measuredresult, a plot comparing the contour of the current density along thewire width and height for devices with W = 10 nm and W = 130 nmwas plotted in Fig. 3. The current density of the device with W =10 nm is larger than that with W= 130 nm, especially at the wire cor-ner. From the simulation results (not shown here), we confirmed alsothat the lateral field of the device with W = 10 nm is larger than thatwithW=130 nm, especially at thewire corner. Therefore, we can con-clude that the HC generation is enhanced for narrow devices.
The second reason for the increase of HC degradation for narrow de-vices is the increase of the electron injection into the gatewhich leads tothe generationof Nit andNot. To investigate the injection of hot electronsinto the gate, a plot comparing the contours of the vertical electric fieldalong the gate length and the nanowire height for devices with W =10 nm and W = 130 nm was plotted in Fig. 4. One can clearly see that
Fig. 1. A plot of HC induced ΔIDS/IDS as a function of wire widths for different stress VGS.
Please cite this article as: J.H. Choi, J.T. Park,Wire width dependence of hotcroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.201
the lateral field near the drain region and the verticalfield on the surfaceof Si nanowire channel of the device with W = 10 nm are larger thanthose with W = 130 nm. This result provides also a proof for theincreased HC degradation with decreasing wire widths in nanowireGAA devices.
The third reason for the increase of HC degradation for narrowdevices is the increase in generation of Nit which depends on the sidesurface orientation and the curvature of the corner. To investigate thewire width dependence of Nit generation, the de-trapping experiment
Fig. 3. A plot of contour of the current density for W= 10 nm andW= 130 nm at stressbiases of VGS = VDS = 3.0 V.
carrier degradation in silicon nanowire gate-all-aroundMOSFETs, Mi-5.06.127
Fig. 6. A plot of Not and Nit as a function of wire widths.
Fig. 4. A plot of contour of the vertical electric field for W = 10 nm and W = 130 nm atstress biases of VGS = VDS = 3.0 V.
3J.H. Choi, J.T. Park / Microelectronics Reliability xxx (2015) xxx–xxx
has been performed. Fig. 5 shows a plot of IDS versus VGS after HC stressand de-trapping stress. For HC stress, the gate bias of VGS = 3.0 V anddrain bias of VDS = 3.0 V were initially applied for 60 min. After that,the negative gate bias of VGS = −3.0 V was applied to de-trap Not for30 min while the source and drain electrodes were grounded. The pos-itive shift of transfer curve under a negative gate bias for 30 min is dueto the de-trapping of Not. In this figure, ΔVot and ΔVit correspond to theI–V shifts due to the generation of Not and Nit after HC stress, respective-ly. The transfer curvewas not shifted further in the positive direction al-though the de-tapping stress continued. This result means that Nit was
Fig. 5. A plot of transfer characteristics after HC and de-trapping stress.
Please cite this article as: J.H. Choi, J.T. Park,Wire width dependence of hotcroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.201
generated during HC stressing and it could not be de-trapped under anegative gate stress bias.
Fig. 6 shows a plot of the dependence of Not and Nit on the wirewidth. The total trap generation (Nt) after HC stress for 60 min isincreased as the wire width decreases. It is interesting to note that Nit
becomes larger than Not as the wire width decreases. This result indi-cates that the effects of the side surface orientation and the curvatureof the corner become more enhanced as the wire width decreases. Asa result, it can be thought that the narrow devices are more dominantlygoverned by the side channel and the corner effects [13]. The increase ofNot with decreasing wire width may be attributed to the large verticalelectric field in narrow devices as shown in Fig. 4.
However, the more significant HC degradation in wide channel SOIdevice has been reported to be due to the nonlocal effects and reducedseries resistance and the enhancement of floating body effects [14,15].Fig. 7 shows the snap-back characteristics with the wire widths. It isclearly shown that the snap-back voltage (linked to a single transistorlatch-up) increases with decreasing wire widths. This means that theimpact ionization is enhanced in wide channel devices due to the en-hanced floating body effects [16], and thus HC degradation becomesless significant in narrow channel devices.
From the systematical analysis of the measurement and the simula-tion, we can conclude that the increase of HC degradation in the narrowdevices is dominantly governed by the increased current density, thelarge lateral and vertical fields, and the increased interface state gener-ation rather than by the reduced floating body effects.
Finally, the comparison of ΔIDS/IDS with the surface-to-volume ratioof nanowires (S/V) is plotted to investigate the geometric effects on theHC degradation as shown in Fig. 8. It is worth noting thatΔIDS/IDS and S/Vare monotonically decreased as the wire widths increase. This result
Fig. 7. A plot of snap-back characteristics for different wire widths.
carrier degradation in silicon nanowire gate-all-aroundMOSFETs, Mi-5.06.127
indicates that the narrow devices which have the large nanowire surfacearea are more likely to collect the scattered hot carriers as reported in aprevious work [4]. Therefore, one can simply predict HC degradation innanowire multiple gate MOSFETs by calculating the surface-to-volumeratio of nanowires. When a tested nanowire GAA MOSFET with SONOSgate stack is used for flash memory, we can speculate that the program-ming speed will be faster with smaller RW.
4. Conclusion
From the systematical analysis of the measurement and the simula-tion, the increase of HC degradation in narrow devices is dominantlygoverned by the increased current density, the large lateral and verticalfields, and the increased interface state generation rather than by thereduced floating body effects. It was shown that HC degradationwith wire width is proportional to the surface-to-volume ratio ofthe nanowires.
Please cite this article as: J.H. Choi, J.T. Park,Wire width dependence of hotcroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.201
Acknowledgment
This work was supported by the Incheon National UniversityResearch Grant in 2015.
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