The University of Victoria Faculty of Engineering

CENG499A

Final Project Report

Wireless ECG/EKG Monitoring System

By Matthew Green

Dennis Leote Kevin Harmon

Submitted to Dr. Pan Agathoklis

July 28, 2006

Table of Contents

Abstract ------------------------------------------------------------------------------ Page 1 Objective ----------------------------------------------------------------------------- Page 2 Project Design ----------------------------------------------------------------------- Page 3 Hardware ---------------------------------------------------------------------------- Page 3 The Power Supply --------------------------------------------------------- Page 4 Instrumentation Amplifier ----------------------------------------------- Page 5 Operational Amplifiers --------------------------------------------------- Page 5 Filters ------------------------------------------------------------------------ Page 6 Microcontroller ------------------------------------------------------------ Page 8 Transceivers ---------------------------------------------------------------- Page 8 MAX232 -------------------------------------------------------------------- Page 9 Software ------------------------------------------------------------------------------ Page 10 Transmitter Module ------------------------------------------------------- Page 10 Programming the PIC16F877A --------------------------------- Page 10 Analog to Digital Conversion (ADC) ---------------- Page 10 Sampling Rate -------------------------------------------- Page 11 Formatting ------------------------------------------------ Page 11 SPI --------------------------------------------------------- Page 11 RF Transmitter ---------------------------------------------------- Page 12 Receiver Module ---------------------------------------------------------- Page 12 RF Receiver ------------------------------------------------------- Page 12 PC Display ------------------------------------------------------------------ Page 13

i

Receiving the Data ------------------------------------------------ Page 14 X Plot --------------------------------------------------------------- Page 14 Y Plot --------------------------------------------------------------- Page 15 Reliability Considerations ------------------------------------------------ Page 15 Discussion and Recommendations ----------------------------------------------- Page 15 References ----------------------------------------------------------------------------Page 17

ii

List of Tables and Figures Figure 1 – ECG/EKG Lead Placement ------------------------------------------- Page 1 Figure 2 – Ideal I-Waveform ------------------------------------------------------ Page 1 Figure 3 – Present Day ECG -------------------------------------------------------Page 2 Figure 4 – Excessive Amount of Wires in the Operating Room -------------- Page 2 Figure 5 – Block Diagram of Transmitter and Receiver ----------------------- Page 3 Figure 6 – Power Supply Circuit ------------------------------------------------- Page 4 Figure 7– An Instrumentation Amplifier ---------------------------------------- Page 5 Figure 8 – The AD620 ------------------------------------------------------------- Page 5 Figure 9 – ECG Waveform with 60 Hz not removed -------------------------- Page 6 Figure 10 – High Pass RC Filter -------------------------------------------------- Page 6 Figure 11 – Low Pass RC Filter --------------------------------------------------- Page 6 Figure 12 – 2nd Order Active Butterworth Filter -------------------------------- Page 7 Figure 13 – RS232 voltages --------------------------------------------------------Page 9 Figure 14 – Transmitter Module Block Diagram ------------------------------- Page 10 Figure 15 – Activity Diagram for Transmitter Module ------------------------ Page 12 Figure 16 – Receiver Module Block Diagram ---------------------------------- Page 12 Figure 17 – Single Lead Display (Lead I) --------------------------------------- Page 13 Figure 18 – Multiple Lead Display -----------------------------------------------Page 14 Table 1 – Voltage Requirements ------------------------------------------------- Page 4 Table 2 – Filter Values ------------------------------------------------------------- Page 7 Table 3 – Data Format -------------------------------------------------------------- Page 11

iii

iv

Abstract In the human body, the heart is responsible for pumping oxygen carrying blood to the entire body. To do this, it emits a small electrical charge that will cause the muscles around the heart to contract in a sequential way such that the blood is pumped through arteries to the intended tissues. If there are deficiencies or abnormalities, the individual may be susceptible to serious health issues including cardiac arrest. Care givers in hospitals world wide must be able to monitor these electrical charges and, in doing so, be able to predict complications before they cause serious harm. To do this, a device called an electrocardiogram (ECG/EKG) is used. An ECG involves placing small pads in a triangular fashion on the patient’s chest, with the perimeter of the triangle completely encompassing the heart (Figure 1). The lead placements are labelled according to their location on the human body; Left Arm (LA), Right Arm (RA) and Left Leg (LL). The corresponding waveforms are numbered using Roman numerals. These pads are actually small leads connected back to a monitoring system that will measure the potential voltage differences around the heart. Figure 2 depicts an ideal I-Waveform taken from a healthy human body. When these results are displayed, the doctors and nurses will be able to verify proper operation or predict possible complications.

Figure 1 – ECG/EKG Lead Placement Figure 2 – Ideal I-Waveform

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Objective As mentioned above, currently the ECG/EKG machines consist of a minimum of 3 pads being placed on the body. These pads are wired back to a monitoring station where all of the required data manipulation is performed before displaying the results on a monitor. The main problem with the current method of monitoring a patient’s heart is very awkward and restricting. The leads are constantly being dislodged from the patient by the nurses, doctors, and even the patient themselves. This causes complications because it appears to the monitoring station that the patient is going into cardiac arrest. (Figures 3 & 4 show a typical operating room with an excess of wires)

Figure 3 – Present Day ECG

Figure 4 – Excessive Amount of Wires in the Operating Room

Another problem with the current system is that the mobility of the care givers is limited due to the number of wires connecting the patient to various monitoring equipment. It is not possible for a nurse or doctor to completely walk around the patient without having to navigate the wires. A solution to this would be to make the hospital utilize wireless data transmission as much as possible to eliminate the need for wires. This process is currently being experimented with. Currently there are various wireless applications in use in the hospital industry. The most common are wireless pulse oxymetry, a method for

2

measuring the oxygen content in the blood. Another example is wireless temperature sensors in which the patient swallows a small transponder that will constantly transmit the body’s core temperature. The objective of this project is to design a Wireless ECG Monitoring System. This product will reliably measure the electrical activity around the heart and transmit this data to a receiver connected to a PC. The data will then be displayed on the PC in the same manner that the current method already does. Project Design This project was split into two main tasks, hardware and software. It is the responsibility of the hardware to collect and compare the data, filter out the harmful 60 Hz signals and transmit the data. It is the software’s responsibilities to digitize the signal, package the data and synchronize the receiver and the transmitter. Hardware As mentioned above, the hardware is responsible for capturing and isolating the signal. The hardware was divided up into stages; the power supply, instrumentation amplifiers, operational amplifiers, filters, analog to digital converters, microcontroller, transceivers and a MAX232. Figure 5 shows a block diagram of how the transmitter and receiver are configured. The schematics and PCB layout are attached in Appendix A.

Figure 5 – Block Diagram of Transmitter and Receiver

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The Power Supply To supply power to the wireless transmitter of this project, a 12 Volt battery was chosen. Table 1 shows a list of all various components and their minimum input voltages.

Device VminInstrumentation Amplifiers ± 2.3 -18 Volts Operational Amplifiers ± 18 Volts Microcontroller 2.0 – 5.5 Volts MAX232 0.3 – 6 Volts Transceiver 3 Volts

Table 1 – Voltage Requirements

To guarantee the microcontroller received the required 5 volts, a voltage regulator was used, which required a minimum of 7 volts. Another issue that needed to be resolved was the DC offset. Since the typical ECG wave will contain both positive and negative values, it was important to bias the signal such that the ADC (analog to digital converter) would only see a level between zero and five volts. To accomplish this, a small power supply was designed (Figure 6) using zener diodes.

Point A is regulated by the 5.1V Zener Diode. This level would be used as a virtual ground reference for the instrumentation and operational amplifier stages. The benefit of this is that the amplifier stage would have supply voltage of +6.9V and -5.1V. This allowed the signal to be shifted slightly closer to ground. Point B, which is regulated to 3.3V, supplies the ground reference for the microcontroller stage. This leaves 8.7V for the voltage regulator. It had to be slightly below the reference voltage for the amplifiers to compensate for the signal when it dips below zero volts. The signal from the amplifiers can now be tuned to range from 0 to 5 volts at the ADC.

Figure 6 – Power Supply Circuit

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Instrumentation Amplifier To measure the difference in voltage between any two points on the human body, we used an instrumentation amplifier made by Analog Devices, called an AD620 (Data Sheets Attached in Appendix B). An instrumentation amplifier is a special type of differential amplifier that will amplify the difference between its two inputs (Figure 7). The gain can be set by adjusting only one resistor, Rgain. The resulting output will be:

)1)(( 12gain

out RRVVV +−=

Figure 7– An Instrumentation Amplifier

The AD620 is an instrumentation amplifier that has been combined in an integrated circuit. The benefit of this is that internal resistor values (R) are all perfectly matched. The gain can still be set by adjusting the one resistor between pins 1 and 8.

Figure 8 – The AD620 Operational Amplifiers The signal that is being analyzed on the individual’s chest has a typical maximum value of 1mV. To make this useful, the signal would need to be amplified to approximately 5Vpp, which equates to a gain of roughly 5000. The AD620 does offer a certain amount of gain; however it was observed that it functioned best when the gain was kept quite low. We therefore divided up the amplification into 2 stages. The first was done using the AD620 and the second done using a non-inverting op-amp. We chose the gain to be 5 for the first stage and 1000 – 2000 for the next. We included a potentiometer in the feedback loop of the op-amp to allow for some adjustment to the gain as necessary.

5

Filters The line interference (the 60Hz signal from the power lines) is abundant in the ECG signal. The human body acts like a giant antenna to this frequency, and the amplitude of the noise is roughly the same size of the ECG signal. It is therefore very difficult to monitor the ECG wave through the noise. Figure 9 shows a typical display of an ECG signal if the 60 Hz noise has not been removed.

Figure 9 – ECG Waveform with 60 Hz not removed The actual signal that is measured on the human body is in the range of 1-2 mV. The useful information is in the frequency range of 1-250 Hz, although the most important data is below 40Hz. It is therefore desirable to filter out all of unwanted signals. To do this some 4 stages of filtering was used. The intended result was to produce a Band Pass Filter with the pass frequency between 1 - 40Hz. The first stage of filtering was done prior to any amplification. It was a simple high pass filter (HPF) that was designed using a simple RC circuit (Figure 10). This pre-filter was designed to eliminate all of the low frequency noise. It was designed with a cut-off frequency of 0.5 Hz.

RC

fcutoff π21

=

Figure 11 – Low Pass RC Filter Figure 10 – High Pass RC Filter To eliminate the 60 Hz signal, a 4th order low pass filter (LPF) was used. This was designed by using a 1st order RC filter in series with a 2nd order Butterworth Filter and finally another the 1st order RC circuit. The RC circuit (Figure 11) is very similar to the HPF defined above. In fact the cut-off frequency is calculated the same way. These were designed to eliminate signals above 40Hz.

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The Butterworth Filter (Figure 12) is an active filter that uses an op-amp to help get rid of the noise. All filters will attenuate frequencies above and below the desired cut-off frequency. The goal is to pick a filter that will be the least damaging to the desired signal while offering maximum filtering to the unwanted signal. The benefit of the Butterworth is that it will have a much more accurate cut-off frequency. It will therefore allow for more of the desired signal to get through unscathed.

212121

CCRRfcutoff π

=

Figure 12 – 2nd Order Active Butterworth Filter The filter values were chosen according to the above formulas. In practice, however, these values were only helpful in getting us close to the desired signal. The actual values used were found by using a trial and error method. Various values were tested until the best signal resulted. The final values of our filters were: Filter # Filter Type Filter Order Cut-off Frequency

1 Passive RC 1 20 Hz 2 Active Butterworth 2 61.4 Hz 3 Passive RC 1 35 Hz

Table 2 – Filter Values

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Microcontroller The microcontroller performed all of the decision making processes. It was responsible for the analog to digital conversion (ADC), data packaging and transceiver synchronization. Refer to the following section on software for more information about this. The microcontroller used was a PIC16F877. The main reason this microcontroller was used was because we were most familiar with it. The main features that it has that made it quite useful are:

• Synchronous Serial Port with SPI • In circuit programming via RS232 • 10 bit ADC • Universal Synchronous Asynchronous Receiver Transmitter (USART) • Low operating current < 0.6 mA • 3 timers • Simple (35 single word instructions to learn)

Transceivers To transmit and receive all of the data, a single chip transceiver was chosen. The nRF24L01 by Nordic Semiconductor was used. This was chosen because of its’ wide range of features:

• Operates in the free to air ISM frequency band at 2.45 GHz • Built in power amplifier • Fully integrated frequency synthesizer • Receiver chain with demodulator • Crystal oscillator and modulator • ShockBurstTM for low power operation • Automatic CRC and preamble generation • Automatic retransmission of data packet • SPI interface • Low current consumption • Carrier detect for “listen before transmit” protocol • Adjustable transmit power

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MAX232 The final piece of hardware that was involved in the design of the wireless ECG machine was the MAX232. This IC is used to convert TTL to RS232 and vice versa. RS232 data will range from -5V to -15V for a logical high and +5V to +15V for a logical low (Figure 13). The microcontroller will output data in the range of 0-5V (TTL). The data must therefore be buffered before the two devices will be able to communicate with one another.

Figure 13 – RS232 voltages

The MAX232 buffers the signal in both directions allowing the microcontroller to communicate with the PC. The data can now be passed to the PC and displayed on the graphic user interface (GUI)

9

Software Once the electrical potential difference between leads has been acquired, the signal must then be converted to the digital domain and communicated to the monitor display. The software component of the ECG monitor includes processing the signal with the PIC 16f877A microprocessor, transmitting the signal to the display using the Nordic nRF24L01 transceiver modules and displaying the information on a PC oscilloscope application. The software was written in C for the microprocessor and in Basic to write the display application. The C compiler used was Hi-Tech C Trial version from Hi-Tech Software. The display application was designed using Visual Basic 6.0 by Microsoft. Transmitter Module The transmitter module is responsible for obtaining and converting the analog ECG signal into an 8-bit digital representation. It is also responsible for formatting and transmitting the data. The transmitter module is within the immediate proximity of the patient being monitored. As the system diagram presented in figure 1 shows, there are four main steps required to transmit the ECG signal.

Analog DAQ

ADC SPI timing &

Form-atting

nRF24L01

TX

PIC 16f877A

Figure 14 – Transmitter Module Block Diagram Programming the PIC 16f877A Analog to Digital Conversion (ADC) The amplified ECG signal is fed into the on-board ADC of the PIC. The PIC is capable of 10-bit resolution but an 8-bit digital representation provides enough accuracy and reduces the bit-rate by half. The three analog leads each have their own ADC channel and are sampled sequentially.

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Sampling Rate The sampling rate was determined by observing the highest frequency component of the ECG signal, the QRS complex as depicted in figure 2, and using the Nyquist criteria. The QRS complex has a possible range of frequencies between 12 Hz and 28 Hz. The Nyquist frequency is thus taken to be 28 Hz and a sampling rate of 2 * Nyquist frequency = 56 Hz must be observed. A sampling rate of 2 KHz was used for increased accuracy. The timing was accomplished manually using delay routines that wait 500us between sampling. Formatting The data obtained from the ADC is bundled into an array of 30 bytes. This is done to conform to the Enhanced ShockburstTM protocol employed by the nRF24L01 transceiver module. Enhanced ShockburstTM allows for packets containing up to 30 bytes of data. To maximize the ratio of data bits to total bits in a packet and thus increase efficiency, the full 30 bytes allowed was utilized. The format of used in constructing the 30-byte array is shown in Table 3 below.

A/D Chan1

Sample 1

A/D Chan2

Sample 1

A/D Chan2

Sample 1... A/D

Chan1 Sample 30

A/D Chan2

Sample 30

A/D Chan2

Sample 30

Table 3 – Data Format SPI To communicate with the nRF24L01 transceiver module, the Serial Port Interface (SPI) module on the PIC was used. The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. The SPI was configured with the following parameters:

• Master Mode – PIC is master with Clock as output • Clock Polarity – Idle state for clock is a low level • Clock rate – 1.25 MHz (fosc / 16). • Data Sampling – Input data sampled at middle of data output time

The activity diagram shown in figure depicts the general process followed by the PIC microprocessor.

11

A/D Conver

Wait 500 us

Transmit

Store Data

[array not full]

[array full]

Three channel conversion complete

Figure 15 – Activity Diagram for Transmitter Module RF Transmitter The nRF24L01 transceivers are configured to transmit 2Mbps at a frequency of 2.45GHz, within the ISM band. The data is encoded using Enhanced ShockburstTM (refer to nRF24L01 datasheet for detailed description). Receiver Module The process of receiving the digital data from the patient is the responsibility of the receiver module. The receiver is connected to a PC for display. As the system diagram presented in figure 16 shows, there are four main components required to receive before the data can be sent to the PC.

Nf24L01

Rx

PC Display

SPI Parsing

U A R T

PIC 16f877A

Figure 16 – Receiver Module Block Diagram

RF Receiver The nRF24L01 transceiver configured to perform as a receiver is much the same as the transmitter with the same parameters. Only one data pipe is used to transfer the data. This is in contrast to using a separate data pipe for each lead of the ECG. The reasoning behind this is that there is less overhead involved by eliminating the need to continuously change between data pipes.

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The data is transferred from the transceiver to the PIC via an SPI interface. The data is received in the format described in figure 16 and the 30 bytes of data is traversed beginning with byte 0. As each byte is received, the data is sent to the PC through the PIC’s on-board USART module at a baud rate of 115.2 kbps. The data is transmitted at regular intervals of 500 us which corresponds to the sampling rate. PC display The ECG signal is displayed on a PC through a basic oscilloscope application. The application was written in Visual Basic is included on the project CD as “ECGMonitor.exe”. The application includes one control bar for rescaling the time interval displayed.

Figure 17 – Single Lead Display (Lead I)

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Figure 18 – Multiple Lead Display Receiving the Data The data is received through the serial port using COMM 2 at a baud rate of 115.2 kbps in 500us intervals. The application receives the data for the three leads of the ECG signal continuously in the following order: LeadI data byte, LeadII data byte, LeadIII, data byte. As the data is received, the appropriate display area is updated. X Plot The display is meant to behave as an oscilloscope although limited in functionality. To observe the ECG signal moving in time from the left to right, the x-coordinate is incremented with each new data value received. A “scale factor” controls the rate that the screen is refreshed. Horizontal scaling provides a means of controlling the number of pulses displayed. The person observing the signal has limited control over how long it takes the ECG signal to pan the width of the display through a scroll bar located directly beneath the display. The horizontal range was chosen to be able to display 2 beats. Heart rates can vary between 40 and 240 beats per minute or 1.5 and 0.25 seconds per beat respectively so the refresh rate was chosen to vary between 0.125 sec and 3 sec. To achieve refresh rates

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wihthin0.125 sec and 3 sec, the display width was set to be between 500 and 6000 pixels. The scroll bar controls this “scale factor” Y Plot The y-coordinate is obtained directly from the incoming data. Since the incoming data is within the range of 0 to 255, the vertical scaling for each lead translates to the same range. Reliability Considerations The ECG monitor needs to be very reliable considering its’ application in the medical field. The transmission frequency of 2.45 GHz is within the ISM band which is the band reserved for non-commercial use of RF electromagnetic fields for industrial, scientific and medical purposes. To avoid interference and loss of data, the nRF24L01 transceiver modules are capable of addressing up to six data pipes per module. In addition, reliability is ensured in the form of error detection and correction. Each data packet includes one byte for a cyclic redundancy check (CRC) to detect the presence of errors. Upon detection of any errors, a retransmission is requested to recover the data that may have been lost. Up to 15 retransmissions will be requested before finally discarding the data packet and carry on. The system can handle up to four packet losses and still maintain the integrity of the displayed signal. Testing was performed to determine the range with which the transceivers could reliable operate within, i.e. 0 packet loss. The methodology used was to observe the number lost packets in software at various distances. A radius of up to 5m found to be reliable. This was the target radius since this is roughly the upper limit on the distance between transmitter and receiver in an operating room. Discussions & Recommendations The Wireless ECG/EKG Monitoring System was designed and built, and was very successful. A few modifications would be implemented if time permitted. The first and most obvious change involves the circuit board. It was very big and awkward. It served its purpose as a prototype board. However, if this product were to got to production, the board would need to be re-designed into a smaller package using surface mount components. Next time, the filtering would be done digitally using a DSP chip. This would allow for much more accurate filtering using an FIR or Wavelets. The final change that would be considered would be to allow for some sort of automatic adjustments of the gain. Every individual has a unique heartbeat. The amplitudes will vary from person to person. The current configuration allows the gain to be adjusted

15

manually, but this is a slow and tedious task. Next time the gain would be adjusted in firmware. This would be much faster and more accurate. The overall performance of this project was excellent. There was positive feedback from the judges, and we were awarded 3rd prize for our efforts. Below are a series of photos from the demonstration.

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References Robert M. Berne and Matthew N. Levy, Cardiovascular Physiology 2nd Edition The C.V. Mosby Company, St. Louis 1972 National Semiconductor - LM741 Operational Amplifier Datasheet Analog Devices – AD620 Instrumentation Amplifier Datasheet Nordic Semiconductor – Single chip 433/868/915 MHz Transceiver nRF905 Dallas Semiconductor - +5V-Powered, Multichannel RS-232 Drivers/Receivers datasheet Microchip - PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Datasheet

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Appendix A

PCB Files

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A2

Date: 30/07/2006 Sheet of File: C:\Documents and Settings\..\ecg.SCHDOCDrawn By:

1

2

3

4

5

6

7

8

AD620AN

U1

1

2

3

4

5

6

7

8

AD620AN

U2

1

2

3

4

5

6

7

8

AD620AN

U3

5.1V ZenerD1

3.3 V ZenerD2

1KR1

1KR2

123456

Header 6H

JP1

1KR3

1KR4

1KR5

8

53

26

74

1LM741

U7

8

53

26

74

1LM741

U9

8

53

26

74

1LM741

U4

8

53

26

74

1LM741

U5

8

53

26

74

1LM741

U6

Cap Pol3100uF

C1

Cap Pol3100uF

C2

Cap Pol3100uF

C3

2.2KR6

2.2KR7

2.2KR8

1KR9

1KR10

1KR11

1KR12

1KR13

1KR14

10KR17

200KR18

200KR20

3.9KR21

3.9KR23

1uF

C4

1uF

C5

1uF

C6

1uF

C7

1uF

C8

1uF

C9

+6V

-6V -6V

Vref (micro)

+6V

-6VLLLARA

+6V

-6V

+6V

+6V

-6V

-6V

LA

LA

LL

LL

RA

RA

82KR24

82KR25

82KR26

82KR27

82KR28

82KR29

10nFC10

10nFC11

10nFC12

100nF

C13

100nF

C14

100nF

C15

-6V

-6V

-6V

+6V

+6V

+6V

45KR30

45KR31

45KR32

100nFC16

100nFC17

100nFC18

Lead I

Lead II

Lead III

RA02

RA13

RA24

RA35

RA4/T0CKI6

RA5/SS7

RB0/INT33

RB134

RB235

RB336

RB437

RB538

RB639

RB740

RC0/T1OSI/T1CKI 15

RC1/T1OSO/CCP2 16

RC2/CCP1 17

RC3/SCK/SCL 18

RC4/SDI/SDA 23

RC5/SDO 24

RC6/TX/CK 25

RC7/RX/DT 26

RD0/PSP0 19

RD1/PSP1 20

RD2/PSP2 21

RD3/PSP3 22

RD4/PSP4 27

RD5/PSP5 28

RD6/PSP6 29

RD7/PSP7 30

RE0/RD 8

RE1/WR 9

RE2/CS 10VSS12

VSS31

MCLR/VPP1 OSC1/CLKI13

OSC2/CLKO 14

VDD 11

VDD 32

PIC16C65-20I/P

U10

4.7KR33

22pFC20

22pFC19

1 2

XTAL1

VDD

Vref (micro)Vref (micro)

OSC1

OSC2

SW-PBSW1

4.7KR34

D3

VDD

MCLR!

Vin VoutGND

5 Volt RegVR1

D6

22uFC21 0.1uF

C22470R35

1 2

D4

+6V

Vref (micro)

Vref (micro)

Vref (micro) Vref (micro)

VDD

12345678

Header 8

JP2Vref (micro)IRQMISOMOSISCKCSNCEVCC

47

R36

3.3 V ZenerD5

VDD

VCC

Vref (micro)

MCLR!

Lead ILead II

Lead III

VDD

Vref (micro)

OSC1

OSC2

CSNCESCKMISOMOSI

Vref (micro)

VDD

IRQ

8

53

26

74

1LM741

U8

-6V

+6V

+6V

+6V

-6V

-6V

10KR16

3.9KR22

1K200KR19

Res110K

R15

13

10

11

8

12

9

14

7

C1+1

C2+4

GND15

C1-3 VCC 16

C2-5

V- 6

V+ 2

MAX232

U11

0.1uFC23

0.1uF

C24

Cap0.1uF

C25

12345 6789

1110

D Connector 9J3

VDD

0.1uF

C26

VDD

Vref (micro) Vref (micro)

Vref (micro)

RX

RX

TX

TX

0.1uFC27

Vref (micro) Vref (micro)

Designator Description Footprint CommentC1 100u RAD-0.1 Cap Pol3C2 100u RAD-0.1 Cap Pol3C3 100u RAD-0.1 Cap Pol3C4 1u RAD-0.1 Cap Pol3C5 1u RAD-0.1 Cap Pol3C6 1u RAD-0.1 Cap Pol3C7 1u RAD-0.1 Cap Pol3C8 1u RAD-0.1 Cap Pol3C9 1u RAD-0.1 Cap Pol3C10 10n RAD-0.1 CapC11 10n RAD-0.1 CapC12 10n RAD-0.1 CapC13 100n RAD-0.1 CapC14 100n RAD-0.1 CapC15 100n RAD-0.1 CapC16 100n RAD-0.1 CapC17 100n RAD-0.1 CapC18 100n RAD-0.1 CapC19 22p RAD-0.1 CapC20 22p RAD-0.1 CapC21 0.1u RAD-0.1 Cap Pol1C22 22u RAD-0.1 CapC23 0.1u RAD-0.1 CapC24 0.1u RAD-0.1 CapC25 0.1u RAD-0.1 CapC26 0.1u RAD-0.1 CapC27 0.1u RAD-0.1 CapD1 5.1V Zener AXIAL-0.3 5.1V ZenerD2 3.3 V Zener AXIAL-0.3 3.3 V ZenerD3 D Zener AXIAL-0.3 D ZenerD4 LED1 AXIAL-0.3 LED1D5 3.3 V Zener AXIAL-0.3 3.3 V ZenerD6 Diode AXIAL-0.3 DiodeJ3 D Connector 9 DSUB1.385-2H9 D Connector 9JP1 Header 6H HDR1X6 Header 6HJP2 Header 8 HDR1X8 Header 8R1 1K AXIAL-0.3 Res1R2 1K AXIAL-0.3 Res1R3 1K AXIAL-0.3 Res1R4 1K AXIAL-0.3 Res1R5 1K AXIAL-0.3 Res1R6 2K2 AXIAL-0.3 Res1R7 2K2 AXIAL-0.3 Res1R8 2K2 AXIAL-0.3 Res1R9 1K VR4 RPot1R10 1K VR4 RPot1R11 1K VR4 RPot1R12 1K AXIAL-0.3 Res1R13 1K AXIAL-0.3 Res1R14 1K AXIAL-0.3 Res1

R15 10K AXIAL-0.3 Res1R16 10K AXIAL-0.3 Res1R17 10K AXIAL-0.3 Res1R18 200K VR4 RPot1R19 200K VR4 RPot1R20 200K VR4 RPot1R21 3K9 AXIAL-0.3 Res1R22 3K9 AXIAL-0.3 Res1R23 3K9 AXIAL-0.3 Res1R24 82K AXIAL-0.3 Res1R25 82K AXIAL-0.3 Res1R26 82K AXIAL-0.3 Res1R27 82K AXIAL-0.3 Res1R28 82K AXIAL-0.3 Res1R29 82K AXIAL-0.3 Res1R30 45K AXIAL-0.3 Res1R31 45K AXIAL-0.3 Res1R32 45K AXIAL-0.3 Res1R33 4K7 AXIAL-0.3 Res1R34 4K7 AXIAL-0.3 Res1R35 470R AXIAL-0.3 Res1R36 47R AXIAL-0.3 Res1SW1 Push Button Switch SPST-2 SW-PBU1 AD620AN DIP-8 AD620ANU2 AD620AN DIP-8 AD620ANU3 AD620AN DIP-8 AD620ANU4 LM741 DIP-8 LM741U5 LM741 DIP-8 LM741U6 LM741 DIP-8 LM741U7 LM741 DIP-8 LM741U8 LM741 DIP-8 LM741U9 LM741 DIP-8 LM741U10 PIC16C65-20I/P DIP-P40/X.85 PIC16C65-20I/PU11 MAX232 DIP-16/X1.5 MAX232VR1 5 Volt Reg SPDT-3 5 Volt RegXTAL1 XTAL RAD-0.1 XTAL

Appendix B

Datasheets

CONNECTION DIAGRAM

8-Lead Plastic Mini-DIP (N), Cerdip (Q)and SOIC (R) Packages

–IN

RG

–VS

+IN

RG

+VS

OUTPUT

REF

1

2

3

4

8

7

6

5AD620

TOP VIEW

REV. E

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

a Low Cost, Low PowerInstrumentation Amplifier

AD620FEATURESEASY TO USEGain Set with One External Resistor

(Gain Range 1 to 1000)Wide Power Supply Range (62.3 V to 618 V)Higher Performance than Three Op Amp IA DesignsAvailable in 8-Lead DIP and SOIC PackagingLow Power, 1.3 mA max Supply Current

EXCELLENT DC PERFORMANCE (“B GRADE”)50 mV max, Input Offset Voltage0.6 mV/8C max, Input Offset Drift1.0 nA max, Input Bias Current100 dB min Common-Mode Rejection Ratio (G = 10)

LOW NOISE9 nV/√Hz, @ 1 kHz, Input Voltage Noise0.28 mV p-p Noise (0.1 Hz to 10 Hz)

EXCELLENT AC SPECIFICATIONS120 kHz Bandwidth (G = 100)15 ms Settling Time to 0.01%

APPLICATIONSWeigh ScalesECG and Medical InstrumentationTransducer InterfaceData Acquisition SystemsIndustrial Process ControlsBattery Powered and Portable Equipment

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 © Analog Devices, Inc., 1999

PRODUCT DESCRIPTIONThe AD620 is a low cost, high accuracy instrumentation ampli-fier that requires only one external resistor to set gains of 1 to

0 5 10 15 20

30,000

5,000

10,000

15,000

20,000

25,000

0

TO

TA

L E

RR

OR

, PP

M O

F F

ULL

SC

ALE

SUPPLY CURRENT – mA

AD620A

RG

3 OP-AMP IN-AMP(3 OP-07s)

Figure 1. Three Op Amp IA Designs vs. AD620

SOURCE RESISTANCE – V100M10k1k 10M1M100k

10,000

0.1

100

1,000

10

1

RT

I VO

LTA

GE

NO

ISE

(0.1

– 1

0Hz)

– m

V p

-p

TYPICAL STANDARDBIPOLAR INPUTIN-AMP

AD620 SUPERbETABIPOLAR INPUTIN-AMP

G = 100

Figure 2. Total Voltage Noise vs. Source Resistance

1000. Furthermore, the AD620 features 8-lead SOIC and DIPpackaging that is smaller than discrete designs, and offers lowerpower (only 1.3 mA max supply current), making it a good fitfor battery powered, portable (or remote) applications.

The AD620, with its high accuracy of 40 ppm maximumnonlinearity, low offset voltage of 50 µV max and offset drift of0.6 µV/°C max, is ideal for use in precision data acquisitionsystems, such as weigh scales and transducer interfaces. Fur-thermore, the low noise, low input bias current, and low powerof the AD620 make it well suited for medical applications suchas ECG and noninvasive blood pressure monitors.

The low input bias current of 1.0 nA max is made possible withthe use of Superβeta processing in the input stage. The AD620works well as a preamplifier due to its low input voltage noise of9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,0.1 pA/√Hz input current noise. Also, the AD620 is well suitedfor multiplexed applications with its settling time of 15 µs to0.01% and its cost is low enough to enable designs with one in-amp per channel.

AD620–SPECIFICATIONS (Typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)

AD620A AD620B AD620S1

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

GAIN G = 1 + (49.4 k/RG)Gain Range 1 10,000 1 10,000 1 10,000Gain Error2 VOUT = ± 10 V

G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %

Nonlinearity, VOUT = –10 V to +10 V,G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppmG = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm

Gain vs. TemperatureG =1 10 10 10 ppm/°CGain >12 –50 –50 –50 ppm/°C

VOLTAGE OFFSET (Total RTI Error = VOSI + VOSO/G)Input Offset, VOSI VS = ±5 V to ±15 V 30 125 15 50 30 125 µV

Over Temperature VS = ±5 V to ±15 V 185 85 225 µVAverage TC VS = ±5 V to ±15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C

Output Offset, VOSO VS = ±15 V 400 1000 200 500 400 1000 µVVS = ±5 V 1500 750 1500 µV

Over Temperature VS = ±5 V to ±15 V 2000 1000 2000 µVAverage TC VS = ± 5 V to ±15 V 5.0 15 2.5 7.0 5.0 15 µV/°C

Offset Referred to theInput vs.Supply (PSR) VS = ±2.3 V to ±18 V

G = 1 80 100 80 100 80 100 dBG = 10 95 120 100 120 95 120 dBG = 100 110 140 120 140 110 140 dBG = 1000 110 140 120 140 110 140 dB

INPUT CURRENTInput Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA

Over Temperature 2.5 1.5 4 nAAverage TC 3.0 3.0 8.0 pA/°C

Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nAOver Temperature 1.5 0.75 2.0 nAAverage TC 1.5 1.5 8.0 pA/°C

INPUTInput Impedance

Differential 10i2 10i2 10i2 GΩipFCommon-Mode 10i2 10i2 10i2 GΩipF

Input Voltage Range3 VS = ±2.3 V to ±5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 VOver Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V

VS = ±5 V to ±18 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 VOver Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V

Common-Mode RejectionRatio DC to 60 Hz withI kΩ Source Imbalance VCM = 0 V to ±10 V

G = 1 73 90 80 90 73 90 dBG = 10 93 110 100 110 93 110 dBG = 100 110 130 120 130 110 130 dBG = 1000 110 130 120 130 110 130 dB

OUTPUTOutput Swing RL = 10 kΩ,

VS = ±2.3 V to ±5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 VOver Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V

VS = ±5 V to ±18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 VOver Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V

Short Current Circuit ± 18 ± 18 ± 18 mA

REV. E–2–

AD620AD620A AD620B AD620S1

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

DYNAMIC RESPONSESmall Signal –3 dB Bandwidth

G = 1 1000 1000 1000 kHzG = 10 800 800 800 kHzG = 100 120 120 120 kHzG = 1000 12 12 12 kHz

Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µsSettling Time to 0.01% 10 V Step

G = 1–100 15 15 15 µsG = 1000 150 150 150 µs

NOISE

Voltage Noise, 1 kHz Total RTI Noise = (e2

ni )+(eno /G)2

Input, Voltage Noise, eni 9 13 9 13 9 13 nV/√HzOutput, Voltage Noise, eno 72 100 72 100 72 100 nV/√Hz

RTI, 0.1 Hz to 10 HzG = 1 3.0 3.0 6.0 3.0 6.0 µV p-pG = 10 0.55 0.55 0.8 0.55 0.8 µV p-pG = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p

Current Noise f = 1 kHz 100 100 100 fA/√Hz0.1 Hz to 10 Hz 10 10 10 pA p-p

REFERENCE INPUTRIN 20 20 20 kΩIIN VIN+, VREF = 0 +50 +60 +50 +60 +50 +60 µAVoltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VGain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001

POWER SUPPLYOperating Range4 ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 VQuiescent Current VS = ±2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA

Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA

TEMPERATURE RANGEFor Specified Performance –40 to +85 –40 to +85 –55 to +125 °C

NOTES1See Analog Devices military data sheet for 883B tested specifications.2Does not include effects of external resistor RG.3One input grounded. G = 1.4This is defined as the same supply range which is used to specify PSR.

Specifications subject to change without notice.

REV. E –3–

AD620

REV. E–4–

NOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

2Specification is for device in free air:8-Lead Plastic Package: θJA = 95°C/W8-Lead Cerdip Package: θJA = 110°C/W8-Lead SOIC Package: θJA = 155°C/W

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 VInternal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mWInput Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±25 VOutput Short Circuit Duration . . . . . . . . . . . . . . . . . IndefiniteStorage Temperature Range (Q) . . . . . . . . . . –65°C to +150°CStorage Temperature Range (N, R) . . . . . . . . –65°C to +125°COperating Temperature Range

AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°CAD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature Range(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C

ORDERING GUIDE

Model Temperature Ranges Package Options*

AD620AN –40°C to +85°C N-8AD620BN –40°C to +85°C N-8AD620AR –40°C to +85°C SO-8AD620AR-REEL –40°C to +85°C 13" REELAD620AR-REEL7 –40°C to +85°C 7" REELAD620BR –40°C to +85°C SO-8AD620BR-REEL –40°C to +85°C 13" REELAD620BR-REEL7 –40°C to +85°C 7" REELAD620ACHIPS –40°C to +85°C Die FormAD620SQ/883B –55°C to +125°C Q-8

*N = Plastic DIP; Q = Cerdip; SO = Small Outline.

METALIZATION PHOTOGRAPHDimensions shown in inches and (mm).Contact factory for latest dimensions.

+VS OUTPUT

REFERENCE

+IN–VS

–IN

*FOR CHIP APPLICATIONS: THE PADS 1R G AND 8RG MUST BE CONNECTED IN PARALLEL TO THE EXTERNAL GAIN REGISTER R G. DO NOT CONNECT THEM IN SERIES TO RG. FOR UNITY GAIN APPLICATIONS WHERE R G IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY BE BONDED TOGETHER, AS WELL AS THE PADS 8R G.

4

5

678

8

RG*

1

1 2 3

RG*0.125

(3.180)

0.0708(1.799)

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD620 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD620

REV. E –5–

Typical Characteristics (@ +258C, VS = 615 V, RL = 2 kV, unless otherwise noted)

INPUT OFFSET VOLTAGE – mV

20

30

40

50

–40 0 +40 +80

PE

RC

EN

TA

GE

OF

UN

ITS

–80

SAMPLE SIZE = 360

10

0

Figure 3. Typical Distribution of Input Offset Voltage

INPUT BIAS CURRENT – pA

0

10

20

30

40

50

–600 0 +600

PE

RC

EN

TA

GE

OF

UN

ITS

–1200 +1200

SAMPLE SIZE = 850

Figure 4. Typical Distribution of Input Bias Current

10

20

30

40

50

–200 0 +200 +400

INPUT OFFSET CURRENT – pA

PE

RC

EN

TA

GE

OF

UN

ITS

–4000

SAMPLE SIZE = 850

Figure 5. Typical Distribution of Input Offset Current

TEMPERATURE – 8C

INP

UT

BIA

S C

UR

RE

NT

– n

A

+IB–IB

2.0

–2.0175

–1.0

–1.5

–75

–0.5

0

0.5

1.0

1.5

1257525–25

Figure 6. Input Bias Current vs. Temperature

CH

AN

GE

IN O

FF

SE

T V

OLT

AG

E –

mV

1.5

0.5

WARM-UP TIME – Minutes

2

00 51

1

432

Figure 7. Change in Input Offset Voltage vs.Warm-Up Time

FREQUENCY – Hz

1000

11 100k

100

10

10k1k100

VO

LTA

GE

NO

ISE

– n

V/!

Hz

GAIN = 1

GAIN = 10

10

GAIN = 100, 1,000GAIN = 1000BW LIMIT

Figure 8. Voltage Noise Spectral Density vs. Frequency,(G = 1–1000)

AD620–Typical Characteristics

FREQUENCY – Hz

1000

100

101 10 1000100

CU

RR

EN

T N

OIS

E –

fA/!

Hz

Figure 9. Current Noise Spectral Density vs. Frequency

RT

I NO

ISE

– 2

.0 m

V/D

IV

TIME – 1 SEC/DIV

Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

RT

I NO

ISE

– 0

.1m

V/D

IV

TIME – 1 SEC/DIV

Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div

100

1000

AD620A

FET INPUTIN-AMP

SOURCE RESISTANCE – V

TO

TA

L D

RIF

T F

RO

M 2

58C

TO

858

C, R

TI –

mV

100,000

101k 10M

10,000

10k 1M100k

Figure 12. Total Drift vs. Source Resistance

FREQUENCY – Hz

CM

R –

dB

+160

01M

+80

+40

1

+60

0.1

+140

+100

+120

100k10k1k10010

G = 1000

G = 100

G = 10

G = 1

+20

Figure 13. CMR vs. Frequency, RTI, Zero to 1 kΩ SourceImbalance

REV. E–6–

AD620

REV. E –7–

FREQUENCY – Hz

PS

R –

dB

160

1M

80

40

1

60

0.1

140

100

120

100k10k1k1001020

G = 1000

G = 100

G = 10

G = 1

180

Figure 14. Positive PSR vs. Frequency, RTI (G = 1–1000)

FREQUENCY – Hz

PS

R –

dB

160

1M

80

40

1

60

0.1

140

100

120

100k10k1k1001020

180

G = 10

G = 100

G = 1

G = 1000

Figure 15. Negative PSR vs. Frequency, RTI (G = 1–1000)

1000

100 10M

100

1

1k

10

100k 1M10k FREQUENCY – Hz

GA

IN –

V/V

0.1

Figure 16. Gain vs. Frequency

OU

TP

UT

VO

LTA

GE

– V

olts

p-p

FREQUENCY – Hz

35

01M

15

5

10k

10

1k

30

20

25

100k

G = 10, 100, 1000

G = 1

G = 1000 G = 100

BW

LIM

IT

Figure 17. Large Signal Frequency Response

INP

UT

VO

LTA

GE

LIM

IT –

Vol

ts(R

EF

ER

RE

D T

O S

UP

PLY

VO

LTA

GE

S)

20

+1.0

+0.5

50

+1.5

–1.5

–1.0

–0.5

1510SUPPLY VOLTAGE 6 Volts

+VS –0.0

–VS +0.0

Figure 18. Input Voltage Range vs. Supply Voltage, G = 1

20

+1.0

+0.5

50

+1.5

–1.5

–1.0

–0.5

1510SUPPLY VOLTAGE 6 Volts

RL = 10kV

RL = 2kV

RL = 10kV

OU

TP

UT

VO

LTA

GE

SW

ING

– V

olts

(RE

FE

RR

ED

TO

SU

PP

LY V

OLT

AG

ES

)

RL = 2kV

+VS –0.0

–VS +0.0

Figure 19. Output Voltage Swing vs. Supply Voltage,G = 10

AD620

REV. E–8–

OU

TP

UT

VO

LTA

GE

SW

ING

– V

olts

p-p

LOAD RESISTANCE – V

30

00 10k

20

10

100 1k

VS = 615VG = 10

Figure 20. Output Voltage Swing vs. Load Resistance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 21. Large Signal Pulse Response and Settling TimeG = 1 (0.5 mV = 0.01%)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 22. Small Signal Response, G = 1, RL = 2 kΩ,CL = 100 pF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 23. Large Signal Response and Settling Time,G = 10 (0.5 mV = 001%)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 24. Small Signal Response, G = 10, RL = 2 kΩ,CL = 100 pF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 25. Large Signal Response and Settling Time,G = 100 (0.5 mV = 0.01%)

AD620

REV. E –9–

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26. Small Signal Pulse Response, G = 100,RL = 2 kΩ, CL = 100 pF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 27. Large Signal Response and Settling Time,G = 1000 (0.5 mV = 0.01%)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 28. Small Signal Pulse Response, G = 1000,RL = 2 kΩ, CL = 100 pF

OUTPUT STEP SIZE – Volts

SE

TT

LIN

G T

IME

– m

s TO 0.01%

TO 0.1%

20

00 20

15

5

5

10

10 15

Figure 29. Settling Time vs. Step Size (G = 1)

GAIN

SE

TT

LIN

G T

IME

– m

s

1000

11 1000

100

10

10 100

Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31a. Gain Nonlinearity, G = 1, RL = 10 kΩ(10 µV = 1 ppm)

AD620

REV. E–10–

VB

–VS

A1 A2

A3

C2

RG

R1 R2

GAINSENSE

GAINSENSE

R3400V

10kV

10kV

I2I1

10kVREF

10kV

+IN– IN

20mA 20mA

R4400V

OUTPUT

C1

Q2Q1

Figure 33. Simplified Schematic of AD620

THEORY OF OPERATIONThe AD620 is a monolithic instrumentation amplifier based ona modification of the classic three op amp approach. Absolutevalue trimming allows the user to program gain accurately (to0.15% at G = 100) with only one resistor. Monolithic construc-tion and laser wafer trimming allow the tight matching andtracking of circuit components, thus ensuring the high level ofperformance inherent in this circuit.

The input transistors Q1 and Q2 provide a single differential-pair bipolar input for high precision (Figure 33), yet offer 10×lower Input Bias Current thanks to Superβeta processing. Feed-back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-tains constant collector current of the input devices Q1, Q2thereby impressing the input voltage across the external gainsetting resistor RG. This creates a differential gain from theinputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1.The unity-gain subtracter A3 removes any common-mode sig-nal, yielding a single-ended output referred to the REF pinpotential.

The value of RG also determines the transconductance of thepreamp stage. As RG is reduced for larger gains, the transcon-ductance increases asymptotically to that of the input transistors.This has three important advantages: (a) Open-loop gain isboosted for increasing programmed gain, thus reducing gain-related errors. (b) The gain-bandwidth product (determined byC1, C2 and the preamp transconductance) increases with pro-grammed gain, thus optimizing frequency response. (c) Theinput voltage noise is reduced to a value of 9 nV/√Hz, deter-mined mainly by the collector current and base resistance of theinput devices.

The internal gain resistors, R1 and R2, are trimmed to an abso-lute value of 24.7 kΩ, allowing the gain to be programmedaccurately with a single external resistor.

The gain equation is then

G = 49.4 kΩ

RG+ 1

so that

RG = 49.4 kΩ

G − 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31b. Gain Nonlinearity, G = 100, RL = 10 kΩ(100 µV = 10 ppm)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 kΩ(1 mV = 100 ppm)

AD620

VOUT

G=1G=1000

49.9V

10kV*1kV10T 10kV

499V

G=10G=100

5.49kV

+VS

11kV 1kV 100V

100kV

INPUT10V p-p

–VS

*ALL RESISTORS 1% TOLERANCE

71

2

3

8

6

4

5

Figure 32. Settling Time Test Circuit

AD620

REV. E –11–

Make vs. Buy: A Typical Bridge Application Error BudgetThe AD620 offers improved performance over “homebrew”three op amp IA designs, along with smaller size, fewer compo-nents and 10× lower supply current. In the typical application,shown in Figure 34, a gain of 100 is required to amplify a bridgeoutput of 20 mV full scale over the industrial temperature rangeof –40°C to +85°C. The error budget table below shows how tocalculate the effect various error sources have on circuit accuracy.

Regardless of the system in which it is being used, the AD620provides greater accuracy, and at low power and price. In simple

R = 350V

+10V

PRECISION BRIDGE TRANSDUCERAD620A MONOLITHICINSTRUMENTATIONAMPLIFIER, G = 100

“HOMEBREW” IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3PPM/8C TRACKING**DISCRETE 1% RESISTOR, 100PPM/8C TRACKING SUPPLY CURRENT = 15mA MAX

100V**

10kV*

10kV**

10kV*

10kV*

10kV**

10kV*

SUPPLY CURRENT = 1.3mA MAX

OP07D

OP07D

OP07DAD620ARG

499V

REFERENCE

R = 350V R = 350V

R = 350V

Figure 34. Make vs. Buy

Table I. Make vs. Buy Error Budget

AD620 Circuit “Homebrew” Circuit Error, ppm of Full ScaleError Source Calculation Calculation AD620 Homebrew

ABSOLUTE ACCURACY at TA = +25°CInput Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 16,250 10,607Output Offset Voltage, µV 1000 µV/100/20 mV ((150 µV × 2)/100)/20 mV 14,500 10,150Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 14,118 14,153CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100 14,791 10,500

Total Absolute Error 17,558 11,310DRIFT TO +85°C

Gain Drift, ppm/°C (50 ppm + 10 ppm) × 60°C 100 ppm/°C Track × 60°C 13,600 16,000Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 13,000 10,607Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100/20 mV (2.5 µV/°C × 2 × 60°C)/100/20 mV 14,450 10,150

Total Drift Error 17,050 16,757RESOLUTION

Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 14,140 10,140Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 141,14 13,127

Total Resolution Error 14,154 101,67

Grand Total Error 14,662 28,134

G = 100, VS = ± 15 V.

(All errors are min/max and referred to input.)

systems, absolute accuracy and drift errors are by far the mostsignificant contributors to error. In more complex systems withan intelligent processor, an autogain/autozero cycle will remove allabsolute accuracy and drift errors leaving only the resolutionerrors of gain nonlinearity and noise, thus allowing full 14-bitaccuracy.

Note that for the homebrew circuit, the OP07 specifications forinput voltage offset and noise have been multiplied by √2. Thisis because a three op amp type in-amp has two op amps at itsinputs, both contributing to the overall input error.

AD620

REV. E–12–

3kV

+5V

DIGITALDATAOUTPUT

ADC

REF

IN

AGND

20kV

10kV

20kV

AD620BG=100

1.7mA 0.10mA0.6mAMAX

499V

3kV

3kV3kV

2

1

8

37

6

5

4

1.3mAMAX

AD705

Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply

Pressure MeasurementAlthough useful in many bridge applications such as weighscales, the AD620 is especially suitable for higher resistancepressure sensors powered at lower voltages where small size andlow power become more significant.

Figure 35 shows a 3 kΩ pressure transducer bridge poweredfrom +5 V. In such a circuit, the bridge consumes only 1.7 mA.Adding the AD620 and a buffered voltage divider allows thesignal to be conditioned for only 3.8 mA of total supply current.

Small size and low cost make the AD620 especially attractive forvoltage output pressure transducers. Since it delivers low noiseand drift, it will also serve applications such as diagnostic non-invasive blood pressure measurement.

Medical ECGThe low current noise of the AD620 allows its use in ECGmonitors (Figure 36) where high source resistances of 1 MΩ orhigher are not uncommon. The AD620’s low power, low supplyvoltage requirements, and space-saving 8-lead mini-DIP andSOIC package offerings make it an excellent choice for batterypowered data recorders.

Furthermore, the low bias currents and low current noisecoupled with the low voltage noise of the AD620 improve thedynamic range for better performance.

The value of capacitor C1 is chosen to maintain stability of theright leg drive loop. Proper safeguards, such as isolation, mustbe added to this circuit to protect the patient from possibleharm.

G = 7

AD620A0.03HzHIGHPASS

FILTER

OUTPUT1V/mV

+3V

–3V

RG8.25kV

24.9kV

24.9kV

AD705J

G = 143C1

1MVR4

10kVR1 R3

R2

OUTPUTAMPLIFIER

PATIENT/CIRCUITPROTECTION/ISOLATION

Figure 36. A Medical ECG Monitor Circuit

AD620

REV. E –13–

Precision V-I ConverterThe AD620, along with another op amp and two resistors, makesa precision current source (Figure 37). The op amp buffers thereference terminal to maintain good CMR. The output voltageVX of the AD620 appears across R1, which converts it to acurrent. This current less only, the input bias current of the opamp, then flows out to the load.

AD620RG

–VS

VIN+

VIN–

LOAD

R1

IL

VxI =L R1

=IN+[(V ) – (V )] GIN–

R1

6

5

+ V –X

42

1

8

3 7

+VS

AD705

Figure 37. Precision Voltage-to-Current Converter(Operates on 1.8 mA, ±3 V)

GAIN SELECTIONThe AD620’s gain is resistor programmed by RG, or more pre-cisely, by whatever impedance appears between Pins 1 and 8.The AD620 is designed to offer accurate gains using 0.1%–1%resistors. Table II shows required values of RG for various gains.Note that for G = 1, the RG pins are unconnected (RG = ∞). Forany arbitrary gain RG can be calculated by using the formula:

RG = 49.4 kΩ

G − 1

To minimize gain error, avoid high parasitic resistance in serieswith RG; to minimize gain drift, RG should have a low TC—lessthan 10 ppm/°C—for the best performance.

Table II. Required Values of Gain Resistors

1% Std Table Calculated 0.1% Std Table CalculatedValue of RG, V Gain Value of RG, V Gain

49.9 k 1.990 49.3 k 2.00212.4 k 4.984 12.4 k 4.9845.49 k 9.998 5.49 k 9.998

2.61 k 19.93 2.61 k 19.931.00 k 50.40 1.01 k 49.91499 100.0 499 100.0

249 199.4 249 199.4100 495.0 98.8 501.049.9 991.0 49.3 1,003

INPUT AND OUTPUT OFFSET VOLTAGEThe low errors of the AD620 are attributed to two sources,input and output errors. The output error is divided by G whenreferred to the input. In practice, the input errors dominate athigh gains and the output errors dominate at low gains. Thetotal VOS for a given gain is calculated as:

Total Error RTI = input error + (output error/G)

Total Error RTO = (input error × G) + output error

REFERENCE TERMINALThe reference terminal potential defines the zero output voltage,and is especially useful when the load does not share a preciseground with the rest of the system. It provides a direct means ofinjecting a precise offset to the output, with an allowable rangeof 2 V within the supply voltages. Parasitic resistance should bekept to a minimum for optimum CMR.

INPUT PROTECTIONThe AD620 features 400 Ω of series thin film resistance at itsinputs, and will safely withstand input overloads of up to ±15 Vor ±60 mA for several hours. This is true for all gains, and poweron and off, which is particularly important since the signalsource and amplifier may be powered separately. For longertime periods, the current should not exceed 6 mA (IIN ≤VIN/400 Ω). For input overloads beyond the supplies, clampingthe inputs to the supplies (using a low leakage diode such as anFD333) will reduce the required resistance, yielding lowernoise.

RF INTERFERENCEAll instrumentation amplifiers can rectify out of band signals,and when amplifying small signals, these rectified voltages act assmall dc offset errors. The AD620 allows direct access to theinput transistor bases and emitters enabling the user to applysome first order filtering to unwanted RF signals (Figure 38),where RC < 1/(2 πf) and where f ≥ the bandwidth of theAD620; C ≤ 150 pF. Matching the extraneous capacitance atPins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.

–IN

1

2

3

4 5

6

7

8

R

R+IN

C

C

RG

Figure 38. Circuit to Attenuate RF Interference

AD620

REV. E–14–

COMMON-MODE REJECTIONInstrumentation amplifiers like the AD620 offer high CMR,which is a measure of the change in output voltage when bothinputs are changed by equal amounts. These specifications areusually given for a full-range input voltage change and a speci-fied source imbalance.

For optimal CMR the reference terminal should be tied to a lowimpedance point, and differences in capacitance and resistanceshould be kept to a minimum between the two inputs. In manyapplications shielded cables are used to minimize noise, and forbest CMR over frequency the shield should be properly driven.Figures 39 and 40 show active data guards that are configuredto improve ac common-mode rejections by “bootstrapping” thecapacitances of input cable shields, thus minimizing the capaci-tance mismatch between the inputs.

REFERENCE

VOUTAD620

100V

100V

– INPUT

+ INPUT

AD648

RG

–VS

+VS

–VS

Figure 39. Differential Shield Driver

100V

– INPUT

+ INPUT

REFERENCE

VOUTAD620

–VS

+VS

2RG

2RG

AD548

Figure 40. Common-Mode Shield Driver

GROUNDINGSince the AD620 output voltage is developed with respect to thepotential on the reference terminal, it can solve many groundingproblems by simply tying the REF pin to the appropriate “localground.”

In order to isolate low level analog signals from a noisy digitalenvironment, many data-acquisition components have separateanalog and digital ground pins (Figure 41). It would be conve-nient to use a single ground line; however, current throughground wires and PC runs of the circuit card can cause hun-dreds of millivolts of error. Therefore, separate ground returnsshould be provided to minimize the current flow from the sensi-tive points to the system ground. These ground returns must betied together at some point, usually best at the ADC package asshown.

DIGITAL P.S.+5VC

ANALOG P.S.+15V C –15V

AD574ADIGITALDATAOUTPUT

+

1mF

AD620

0.1mF

AD585S/H ADC

0.1mF1mF 1mF

Figure 41. Basic Grounding Practice

AD620

REV. E –15–

GROUND RETURNS FOR INPUT BIAS CURRENTSInput bias currents are those currents necessary to bias the inputtransistors of an amplifier. There must be a direct return pathfor these currents; therefore, when amplifying “floating” input

VOUTAD620

– INPUT

RG

TO POWERSUPPLY

GROUND

REFERENCE+ INPUT

+VS

–VS

LOAD

Figure 42a. Ground Returns for Bias Currents withTransformer Coupled Inputs

sources such as transformers, or ac-coupled sources, there mustbe a dc path from each input to ground as shown in Figure 42.Refer to the Instrumentation Amplifier Application Guide (freefrom Analog Devices) for more information regarding in ampapplications.

VOUT

– INPUT

+ INPUT

RG

LOAD

TO POWERSUPPLY

GROUND

REFERENCE

+VS

–VS

AD620

Figure 42b. Ground Returns for Bias Currents withThermocouple Inputs

100kV

VOUTAD620

– INPUT

+ INPUT

RG

LOAD

TO POWERSUPPLY

GROUND

REFERENCE

100kV –VS

+VS

Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs

AD620

REV. E–16–

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

Plastic DIP (N-8) Package

8

1 4

5

0.430 (10.92)0.348 (8.84)

0.280 (7.11)0.240 (6.10)

PIN 1

SEATINGPLANE

0.022 (0.558)0.014 (0.356)

0.060 (1.52)0.015 (0.38)

0.210 (5.33)MAX 0.130

(3.30)MIN

0.070 (1.77)0.045 (1.15)

0.100(2.54)BSC

0.160 (4.06)0.115 (2.93)

0.325 (8.25)0.300 (7.62)

0.015 (0.381)0.008 (0.204)

0.195 (4.95)0.115 (2.93)

Cerdip (Q-8) Package

8

1 4

5

0.310 (7.87)0.220 (5.59)

PIN 1

0.005 (0.13)MIN

0.055 (1.4)MAX

SEATINGPLANE

0.023 (0.58)0.014 (0.36)

0.200 (5.08)MAX 0.150

(3.81)MIN

0.070 (1.78)0.030 (0.76)

0.200 (5.08)0.125 (3.18)

0.100(2.54)BSC

0.060 (1.52)0.015 (0.38)

0.405 (10.29) MAX

15°0°

0.320 (8.13)0.290 (7.37)

0.015 (0.38)0.008 (0.20)

SOIC (SO-8) Package

0.1968 (5.00)0.1890 (4.80)

8 5

410.2440 (6.20)0.2284 (5.80)

PIN 1

0.1574 (4.00)0.1497 (3.80)

0.0688 (1.75)0.0532 (1.35)

SEATINGPLANE

0.0098 (0.25)0.0040 (0.10)

0.0192 (0.49)0.0138 (0.35)

0.0500(1.27)BSC

0.0098 (0.25)0.0075 (0.19)

0.0500 (1.27)0.0160 (0.41)

8°0°

0.0196 (0.50)0.0099 (0.25)

x 45°

C15

99c–

0–7/

99P

RIN

TE

D IN

U.S

.A.

LM741Operational AmplifierGeneral DescriptionThe LM741 series are general purpose operational amplifi-ers which feature improved performance over industry stan-dards like the LM709. They are direct, plug-in replacementsfor the 709C, LM201, MC1439 and 748 in most applications.

The amplifiers offer many features which make their appli-cation nearly foolproof: overload protection on the input and

output, no latch-up when the common mode range is ex-ceeded, as well as freedom from oscillations.

The LM741C is identical to the LM741/LM741A except thatthe LM741C has their performance guaranteed over a 0˚C to+70˚C temperature range, instead of −55˚C to +125˚C.

Features

Connection Diagrams

Metal Can Package Dual-In-Line or S.O. Package

00934102

Note 1: LM741H is available per JM38510/10101

Order Number LM741H, LM741H/883 (Note 1),LM741AH/883 or LM741CH

See NS Package Number H08C

00934103

Order Number LM741J, LM741J/883, LM741CNSee NS Package Number J08A, M08A or N08E

Ceramic Flatpak

00934106

Order Number LM741W/883See NS Package Number W10A

Typical Application

Offset Nulling Circuit

00934107

August 2000LM

741O

perationalAm

plifier

© 2004 National Semiconductor Corporation DS009341 www.national.com

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

(Note 7)

LM741A LM741 LM741C

Supply Voltage ±22V ±22V ±18V

Power Dissipation (Note 3) 500 mW 500 mW 500 mW

Differential Input Voltage ±30V ±30V ±30V

Input Voltage (Note 4) ±15V ±15V ±15V

Output Short Circuit Duration Continuous Continuous Continuous

Operating Temperature Range −55˚C to +125˚C −55˚C to +125˚C 0˚C to +70˚C

Storage Temperature Range −65˚C to +150˚C −65˚C to +150˚C −65˚C to +150˚C

Junction Temperature 150˚C 150˚C 100˚C

Soldering Information

N-Package (10 seconds) 260˚C 260˚C 260˚C

J- or H-Package (10 seconds) 300˚C 300˚C 300˚C

M-Package

Vapor Phase (60 seconds) 215˚C 215˚C 215˚C

Infrared (15 seconds) 215˚C 215˚C 215˚C

See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods ofsoldering

surface mount devices.

ESD Tolerance (Note 8) 400V 400V 400V

Electrical Characteristics (Note 5)

Parameter Conditions LM741A LM741 LM741C Units

Min Typ Max Min Typ Max Min Typ Max

Input Offset Voltage TA = 25˚C

RS ≤ 10 kΩ 1.0 5.0 2.0 6.0 mV

RS ≤ 50Ω 0.8 3.0 mV

TAMIN ≤ TA ≤ TAMAX

RS ≤ 50Ω 4.0 mV

RS ≤ 10 kΩ 6.0 7.5 mV

Average Input Offset 15 µV/˚C

Voltage Drift

Input Offset Voltage TA = 25˚C, VS = ±20V ±10 ±15 ±15 mV

Adjustment Range

Input Offset Current TA = 25˚C 3.0 30 20 200 20 200 nA

TAMIN ≤ TA ≤ TAMAX 70 85 500 300 nA

Average Input Offset 0.5 nA/˚C

Current Drift

Input Bias Current TA = 25˚C 30 80 80 500 80 500 nA

TAMIN ≤ TA ≤ TAMAX 0.210 1.5 0.8 µA

Input Resistance TA = 25˚C, VS = ±20V 1.0 6.0 0.3 2.0 0.3 2.0 MΩTAMIN ≤ TA ≤ TAMAX, 0.5 MΩVS = ±20V

Input Voltage Range TA = 25˚C ±12 ±13 V

TAMIN ≤ TA ≤ TAMAX ±12 ±13 V

LM74

1

www.national.com 2

Electrical Characteristics (Note 5) (Continued)

Parameter Conditions LM741A LM741 LM741C Units

Min Typ Max Min Typ Max Min Typ Max

Large Signal Voltage Gain TA = 25˚C, RL ≥ 2 kΩVS = ±20V, VO = ±15V 50 V/mV

VS = ±15V, VO = ±10V 50 200 20 200 V/mV

TAMIN ≤ TA ≤ TAMAX,

RL ≥ 2 kΩ,

VS = ±20V, VO = ±15V 32 V/mV

VS = ±15V, VO = ±10V 25 15 V/mV

VS = ±5V, VO = ±2V 10 V/mV

Output Voltage Swing VS = ±20V

RL ≥ 10 kΩ ±16 V

RL ≥ 2 kΩ ±15 V

VS = ±15V

RL ≥ 10 kΩ ±12 ±14 ±12 ±14 V

RL ≥ 2 kΩ ±10 ±13 ±10 ±13 V

Output Short Circuit TA = 25˚C 10 25 35 25 25 mA

Current TAMIN ≤ TA ≤ TAMAX 10 40 mA

Common-Mode TAMIN ≤ TA ≤ TAMAX

Rejection Ratio RS ≤ 10 kΩ, VCM = ±12V 70 90 70 90 dB

RS ≤ 50Ω, VCM = ±12V 80 95 dB

Supply Voltage Rejection TAMIN ≤ TA ≤ TAMAX,

Ratio VS = ±20V to VS = ±5V

RS ≤ 50Ω 86 96 dB

RS ≤ 10 kΩ 77 96 77 96 dB

Transient Response TA = 25˚C, Unity Gain

Rise Time 0.25 0.8 0.3 0.3 µs

Overshoot 6.0 20 5 5 %

Bandwidth (Note 6) TA = 25˚C 0.437 1.5 MHz

Slew Rate TA = 25˚C, Unity Gain 0.3 0.7 0.5 0.5 V/µs

Supply Current TA = 25˚C 1.7 2.8 1.7 2.8 mA

Power Consumption TA = 25˚C

VS = ±20V 80 150 mW

VS = ±15V 50 85 50 85 mW

LM741A VS = ±20V

TA = TAMIN 165 mW

TA = TAMAX 135 mW

LM741 VS = ±15V

TA = TAMIN 60 100 mW

TA = TAMAX 45 75 mW

Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isfunctional, but do not guarantee specific performance limits.

LM741

www.national.com3

Electrical Characteristics (Note 5) (Continued)Note 3: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under “Absolute MaximumRatings”). Tj = TA + (θjA PD).

Thermal Resistance Cerdip (J) DIP (N) HO8 (H) SO-8 (M)

θjA (Junction to Ambient) 100˚C/W 100˚C/W 170˚C/W 195˚C/W

θjC (Junction to Case) N/A N/A 25˚C/W N/A

Note 4: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.

Note 5: Unless otherwise specified, these specifications apply for VS = ±15V, −55˚C ≤ TA ≤ +125˚C (LM741/LM741A). For the LM741C/LM741E, thesespecifications are limited to 0˚C ≤ TA ≤ +70˚C.

Note 6: Calculated value from: BW (MHz) = 0.35/Rise Time(µs).

Note 7: For military specifications see RETS741X for LM741 and RETS741AX for LM741A.

Note 8: Human body model, 1.5 kΩ in series with 100 pF.

Schematic Diagram

00934101

LM74

1

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Physical Dimensions inches (millimeters)unless otherwise noted

Metal Can Package (H)Order Number LM741H, LM741H/883, LM741AH/883, LM741AH-MIL or LM741CH

NS Package Number H08C

LM741

www.national.com5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Ceramic Dual-In-Line Package (J)Order Number LM741J/883NS Package Number J08A

Dual-In-Line Package (N)Order Number LM741CN

NS Package Number N08E

LM74

1

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

10-Lead Ceramic Flatpak (W)Order Number LM741W/883, LM741WG-MPR or LM741WG/883

NS Package Number W10A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reservesthe right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMSWITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTORCORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or(b) support or sustain life, and whose failure to perform whenproperly used in accordance with instructions for useprovided in the labeling, can be reasonably expected to resultin a significant injury to the user.

2. A critical component is any component of a life supportdevice or system whose failure to perform can be reasonablyexpected to cause the failure of the life support device orsystem, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products StewardshipSpecification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘BannedSubstances’’ as defined in CSP-9-111S2.

National SemiconductorAmericas CustomerSupport CenterEmail: new.feedback@nsc.comTel: 1-800-272-9959

National SemiconductorEurope Customer Support Center

Fax: +49 (0) 180-530 85 86Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National SemiconductorAsia Pacific CustomerSupport CenterEmail: ap.support@nsc.com

National SemiconductorJapan Customer Support CenterFax: 81-3-5639-7507Email: jpn.feedback@nsc.comTel: 81-3-5639-7560

www.national.com

LM741

OperationalA

mplifier

General DescriptionThe MAX220–MAX249 family of line drivers/receivers isintended for all EIA/TIA-232E and V.28/V.24 communica-tions interfaces, particularly applications where ±12V isnot available. These parts are especially useful in battery-powered sys-tems, since their low-power shutdown mode reducespower dissipation to less than 5µW. The MAX225,MAX233, MAX235, and MAX245/MAX246/MAX247 useno external components and are recommended for appli-cations where printed circuit board space is critical.

________________________ApplicationsPortable Computers

Low-Power Modems

Interface Translation

Battery-Powered RS-232 Systems

Multidrop RS-232 Networks

Next-Generation Device Features

♦ For Low-Voltage, Integrated ESD ApplicationsMAX3222E/MAX3232E/MAX3237E/MAX3241E/MAX3246E: +3.0V to +5.5V, Low-Power, Up to1Mbps, True RS-232 Transceivers Using Four0.1µF External Capacitors (MAX3246E Availablein a UCSP™ Package)

♦ For Low-Cost Applications MAX221E: ±15kV ESD-Protected, +5V, 1µA,Single RS-232 Transceiver with AutoShutdown™

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________________________________________________________________ Maxim Integrated Products 1

Selection Table

19-4323; Rev 15; 1/06

PARTMAX220CPEMAX220CSEMAX220CWE 0°C to +70°C

0°C to +70°C0°C to +70°C

TEMP RANGE PIN-PACKAGE16 Plastic DIP16 Narrow SO16 Wide SO

MAX220C/D 0°C to +70°C Dice*MAX220EPEMAX220ESEMAX220EWE -40°C to +85°C

-40°C to +85°C-40°C to +85°C 16 Plastic DIP

16 Narrow SO16 Wide SO

MAX220EJE -40°C to +85°C 16 CERDIPMAX220MJE -55°C to +125°C 16 CERDIP

Power No. of Nominal SHDN RxPart Supply RS-232 No. of Cap. Value & Three- Active in Data RateNumber (V) Drivers/Rx Ext. Caps (µF) State SHDN (kbps) FeaturesMAX220 +5 2/2 4 0.047/0.33 No — 120 Ultra-low-power, industry-standard pinoutMAX222 +5 2/2 4 0.1 Yes — 200 Low-power shutdownMAX223 (MAX213) +5 4/5 4 1.0 (0.1) Yes 120 MAX241 and receivers active in shutdownMAX225 +5 5/5 0 — Yes 120 Available in SOMAX230 (MAX200) +5 5/0 4 1.0 (0.1) Yes — 120 5 drivers with shutdownMAX231 (MAX201) +5 and 2/2 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;

+7.5 to +13.2 same functions as MAX232MAX232 (MAX202) +5 2/2 4 1.0 (0.1) No — 120 (64) Industry standardMAX232A +5 2/2 4 0.1 No — 200 Higher slew rate, small capsMAX233 (MAX203) +5 2/2 0 — No — 120 No external capsMAX233A +5 2/2 0 — No — 200 No external caps, high slew rateMAX234 (MAX204) +5 4/0 4 1.0 (0.1) No — 120 Replaces 1488MAX235 (MAX205) +5 5/5 0 — Yes — 120 No external capsMAX236 (MAX206) +5 4/3 4 1.0 (0.1) Yes — 120 Shutdown, three stateMAX237 (MAX207) +5 5/3 4 1.0 (0.1) No — 120 Complements IBM PC serial portMAX238 (MAX208) +5 4/4 4 1.0 (0.1) No — 120 Replaces 1488 and 1489MAX239 (MAX209) +5 and 3/5 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;

+7.5 to +13.2 single-package solution for IBM PC serial portMAX240 +5 5/5 4 1.0 Yes — 120 DIP or flatpack packageMAX241 (MAX211) +5 4/5 4 1.0 (0.1) Yes — 120 Complete IBM PC serial portMAX242 +5 2/2 4 0.1 Yes 200 Separate shutdown and enableMAX243 +5 2/2 4 0.1 No — 200 Open-line detection simplifies cablingMAX244 +5 8/10 4 1.0 No — 120 High slew rateMAX245 +5 8/10 0 — Yes 120 High slew rate, int. caps, two shutdown modesMAX246 +5 8/10 0 — Yes 120 High slew rate, int. caps, three shutdown modesMAX247 +5 8/9 0 — Yes 120 High slew rate, int. caps, nine operating modesMAX248 +5 8/8 4 1.0 Yes 120 High slew rate, selective half-chip enablesMAX249 +5 6/10 4 1.0 Yes 120 Available in quad flatpack package

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Ordering Information continued at end of data sheet.*Contact factory for dice specifications.

AutoShutdown and UCSP are trademarks of Maxim IntegratedProducts, Inc.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243

ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)

Note 1: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.Note 2: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V.Note 3: Maximum reflow temperature for the MAX223A is +225°C.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ...............................................-0.3V to +6VV+ (Note 1) ..................................................(VCC - 0.3V) to +14VV- (Note 1) .............................................................+0.3V to +14VInput VoltagesTIN..............................................................-0.3V to (VCC - 0.3V)RIN (Except MAX220) ........................................................±30VRIN (MAX220).....................................................................±25VTOUT (Except MAX220) (Note 2) .......................................±15VTOUT (MAX220)...............................................................±13.2V

Output VoltagesTOUT...................................................................................±15VROUT.........................................................-0.3V to (VCC + 0.3V)

Driver/Receiver Output Short Circuited to GND.........ContinuousContinuous Power Dissipation (TA = +70°C)

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW

18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)..889mW20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW

Operating Temperature RangesMAX2_ _AC_ _, MAX2_ _C_ _.............................0°C to +70°CMAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°CMAX2_ _AM_ _, MAX2_ _M_ _.......................-55°C to +125°C

Storage Temperature Range .............................-65°C to +160°CLead Temperature (soldering, 10s) (Note 3) ...................+300°C

PARAMETER CONDITIONS MIN TYP MAX UNITS

RS-232 TRANSMITTERS

Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND ±5 ±8 V

Input Logic Threshold Low 1.4 0.8 V

All devices except MAX220 2 1.4Input Logic Threshold High

MAX220: VCC = 5.0V 2.4V

All except MAX220, normal operation 5 40

Logic Pullup/lnput Current SHDN = 0V, MAX222/MAX242, shutdown,MAX220

±0.01 ±1µA

VCC = 5.5V, SHDN = 0V, VOUT = ±15V,MAX222/MAX242

±0.01 ±10

VOUT = ±15V ±0.01 ±10Output Leakage Current

VCC = SHDN = 0VMAX220, VOUT = ±12V ±25

µA

Data Rate 200 116 kbps

Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M ΩVOUT = 0V ±7 ±22

Output Short-Circuit Current VOUT = 0VMAX220 ±60

mA

RS-232 RECEIVERS±30

RS-232 Input Voltage Operating RangeMAX220 ±25

V

All except MAX243 R2IN 0.8 1.3RS-232 Input Threshold Low VCC = 5V

MAX243 R2 IN (Note 4) -3V

All except MAX243 R2IN 1.8 2.4RS-232 Input Threshold High VCC = 5V

MAX243 R2 IN (Note 4) -0.5 -0.1V

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Note 4: MAX243 R2OUT is guaranteed to be low when R2IN is ≥ 0V or is floating.

ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

All except MAX220/MAX243, VCC = 5V, nohysteresis in SHDN

0.2 0.5 1.0

MAX220 0.3RS-232 Input Hysteresis

MAX243 1

V

3 5 7RS-232 Input Resistance TA = +25°C (MAX220)

3 5 7KΩ

IOUT = 3.2mA 0.2 0.4TTL/CMOS Output Voltage Low

IOUT = 1.6mA (MAX220) 0.4V

TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V

Sourcing VOUT = GND -2 -10TTL/CMOS Output Short-Circuit Current

Shrinking VOUT = VCC 10 30mA

TTL/CMOS Output Leakage CurrentSHDN = VCC or EN = VCC (SHDN = 0V forMAX222), 0V ≤ VOUT ≤ VCC

±0.05 ±10 µA

EN Input Threshold Low MAX242 1.4 0.8 V

EN Input Threshold High MAX242 2.0 1.4 V

Operating Supply Voltage 4.5 5.5 V

MAX220 0.5 2

No load MAX222/MAX232A/MAX233A/MAX242/MAX243

4 10

MAX220 12VCC Supply Current (SHDN = VCC),figures 5, 6, 11, 19

3kΩ load bothinputs MAX222/MAX232A/MAX233A/

MAX242/MAX24315

µA

TA = +25°C 0.1 10

TA = 0°C to +70°C 2 50

TA = -40°C to +85°C 2 50Shutdown Supply Current

MAX222/MAX242

TA = -55°C to +125°C 35 100

µA

SHDN Input Leakage Current MAX222/MAX242 ±1 µA

SHDN Threshold Low MAX222/MAX242 1.4 0.8 V

SHDN Threshold High MAX222/MAX242 2.0 1.4 V

MAX222/MAX232A/MAX233/MAX242/MAX243

6 12 30

Transition Slew Rate

CL = 50pF to2500pF, RL = 3kΩto 7kΩ, VCC = 5V,TA = +25°C,measured from+3V to -3V or -3V

MAX220 1.5 3 30.0

V/µs

MAX222/MAX232A/MAX233/MAX242/MAX243

1.3 3.5tPHLT

MAX220 4 10

MAX222/MAX232A/MAX233/MAX242/MAX243

1.5 3.5

Transmitter Propagation Delay TLL toRS-232 (Normal Operation), Figure 1

tPLHT

MAX220 5 10

µs

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__________________________________________Typical Operating Characteristics

MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243

10

8

-100 5 15 25

OUTPUT VOLTAGE vs. LOAD CURRENT

-4

-6

-8

-2

6

4

2

MAX

220-

01

LOAD CURRENT (mA)

OUTP

UT V

OLTA

GE (V

)

10

0

20

0.1µF

EITHER V+ OR V- LOADED

VCC = ±5VNO LOAD ONTRANSMITTER OUTPUTS(EXCEPT MAX220, MAX233A)

V- LOADED, NO LOAD ON V+

V+ LOADED, NO LOAD ON V-

1µF

1µF0.1µF

11

10

40 10 40 60

AVAILABLE OUTPUT CURRENTvs. DATA RATE

6

5

7

9

8

MAX

220-

02

DATA RATE (kbits/sec)

OUTP

UT C

URRE

NT (m

A)

20 30 50

OUTPUT LOAD CURRENTFLOWS FROM V+ TO V-

VCC = +5.25V

ALL CAPS1µF

ALL CAPS0.1µF

VCC = +4.75V

+10V

-10V

MAX222/MAX242ON-TIME EXITING SHUTDOWN

+5V+5V

0V

0V

MAX

220-

03

500µs/div

V+, V

- VOL

TAGE

(V)

1µF CAPSV+

V+

V-V-

SHDN

0.1µF CAPS

1µF CAPS

0.1µF CAPS

ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAX222/MAX232A/MAX233/MAX242/MAX243

0.5 1tPHLR

MAX220 0.6 3

MAX222/MAX232A/MAX233/MAX242/MAX243

0.6 1

Receiver Propagation Delay RS-232 toTLL (Normal Operation), Figure 2

tPLHR

MAX220 0.8 3

µs

tPHLS MAX242 0.5 10Receiver Propagation Delay RS-232 toTLL (Shutdown), Figure 2

tPHLS MAX242 2.5 10

µs

Receiver-Output Enable Time, Figure 3 tER MAX242 125 500 ns

Receiver-Output Disable Time, Figure 3 tDR MAX242 160 500 ns

Transmitter-Output Enable Time (SHDNGoes High), Figure 4

tET

MAX222/MAX242, 0.1µFcaps (includes charge-pumpstart-up)

250 µs

Transmitter-Output Disable Time (SHDNGoes Low), Figure 4

tDTMAX222/MAX242,0.1µF caps

600 ns

MAX222/MAX232A/MAX233/MAX242/MAX243

300Transmitter + to - Propagation DelayDifference (Normal Operation)

tPHLT - tPLHT

MAX220 2000

ns

MAX222/MAX232A/MAX233/MAX242/MAX243

100Receiver + to - Propagation DelayDifference (Normal Operation)

tPHLR - tPLHR

MAX220 225

ns

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VCC...........................................................................-0.3V to +6VV+................................................................(VCC - 0.3V) to +14VV- ............................................................................+0.3V to -14VInput VoltagesTIN ............................................................-0.3V to (VCC + 0.3V)RIN......................................................................................±30V

Output VoltagesTOUT ...................................................(V+ + 0.3V) to (V- - 0.3V)ROUT.........................................................-0.3V to (VCC + 0.3V)

Short-Circuit Duration, TOUT ......................................ContinuousContinuous Power Dissipation (TA = +70°C)14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW24-Pin Narrow Plastic DIP

(derate 13.33mW/°C above +70°C) ..........1.07W24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW

20-Pin Wide SO (derate 10 00mW/°C above +70°C).......800mW24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW24-Pin Narrow CERDIP

(derate 12.50mW/°C above +70°C) ..............1W24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW

Operating Temperature RangesMAX2 _ _ C _ _......................................................0°C to +70°CMAX2 _ _ E _ _ ...................................................-40°C to +85°CMAX2 _ _ M _ _ ...............................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +160°CLead Temperature (soldering, 10s) (Note 4) ...................+300°C

ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241

ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

CONDITIONS MIN TYP MAX UNITS

Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±7.3 V

VCC Power-Supply CurrentNo load,TA = +25°C

5 10

mA7 15

0.4 1

V+ Power-Supply Current1.8 5

mA5 15

Shutdown Supply Current TA = +25°C15 50

VInput Logic Threshold High

TIN 2.0

EN, SHDN (MAX223);EN, SHDN (MAX230/235/236/240/241)

2.4

Logic Pull-Up Current TIN = 0V 1.5 200

Receiver Input VoltageOperating Range

-30 +30 V

µA

µA1 10

VInput Logic Threshold Low TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235–241) 0.8

MAX231/239

MAX223/230/234–238/240/241

MAX232/233

PARAMETER

MAX239

MAX230/235/236/240/241

MAX231

MAX223

Note 4: Maximum reflow temperature for the MAX233/MAX235 is +225°C.

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V

0.8 1.2

PARAMETER MIN TYP MAX UNITSCONDITIONS

Normal operationSHDN = 5V (MAX223)SHDN = 0V (MAX235/236/240/241)

1.7 2.4

RS-232 Input Threshold LowTA = +25°C, VCC = 5V

0.6 1.5

VRS-232 Input Threshold HighTA = +25°C,VCC = 5V Shutdown (MAX223)

SHDN = 0V,EN = 5V (R4IN‚ R5IN)

1.5 2.4

ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued)(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)

Shutdown (MAX223)SHDN = 0V,EN = 5V (R4IN, R5IN)

Normal operationSHDN = 5V (MAX223)SHDN = 0V (MAX235/236/240/241)

RS-232 Input Hysteresis VCC = 5V, no hysteresis in shutdown 0.2 0.5 1.0 V

RS-232 Input Resistance TA = +25°C, VCC = 5V 3 5 7 kΩ

TTL/CMOS Output Voltage Low IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) 0.4 V

TTL/CMOS Output Voltage High IOUT = -1mA 3.5 VCC - 0.4 V

TTL/CMOS Output Leakage Current0V ≤ ROUT ≤ VCC; EN = 0V (MAX223); EN = VCC (MAX235–241 )

0.05 ±10 µA

MAX223 600nsReceiver Output Enable Time

Normal operation MAX235/236/239/240/241 400

MAX223 900nsReceiver Output Disable Time

Normal operation MAX235/236/239/240/241 250

Normal operation 0.5 10

µsSHDN = 0V(MAX223)

4 40Propagation DelayRS-232 IN toTTL/CMOS OUT,CL = 150pF 6 40

3 5.1 30

V/µsMAX231/MAX232/MAX233, TA = +25°C, VCC = 5V, RL = 3kΩ to 7kΩ, CL = 50pF to 2500pF, measured from+3V to -3V or -3V to +3V

4 30

Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 Ω

Transmitter Output Short-CircuitCurrent

±10 mA

tPHLS

tPLHS

Transition Region Slew Rate

MAX223/MAX230/MAX234–241, TA = +25°C, VCC = 5V, RL = 3kΩ to 7kΩ‚ CL = 50pF to 2500pF, measured from+3V to -3V or -3V to +3V

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8.5

6.54.5 5.5

TRANSMITTER OUTPUTVOLTAGE (VOH) vs. VCC

7.0

8.0

MAX

220-

04

VCC (V)

V OH

(V)

5.0

7.5

1 TRANSMITTERLOADED

3 TRANS-MITTERSLOADED

4 TRANSMITTERSLOADED

2 TRANSMITTERSLOADED

TA = +25°CC1–C4 = 1µFTRANSMITTERLOADS =3kΩ || 2500pF

7.4

6.00 2500

TRANSMITTER OUTPUT VOLTAGE (VOH)vs. LOAD CAPACITANCE AT

DIFFERENT DATA RATES

6.4

6.2

7.2

7.0

MAX

220-

05

LOAD CAPACITANCE (pF)

V OH

(V)

15001000500 2000

6.8

6.6

160kbits/sec80kbits/sec20kbits/sec

TA = +25°CVCC = +5V3 TRANSMITTERS LOADEDRL = 3kΩC1–C4 = 1µF

12.0

4.00 2500

TRANSMITTER SLEW RATEvs. LOAD CAPACITANCE

6.0

5.0

11.0

9.0

10.0

MAX

220-

06

LOAD CAPACITANCE (pF)

SLEW

RAT

E (V

/µs)

15001000500 2000

8.0

7.0

TA = +25°CVCC = +5VLOADED, RL = 3kΩC1–C4 = 1µF

1 TRANSMITTER LOADED

2 TRANSMITTERS LOADED

3 TRANSMITTERS LOADED

4 TRANSMITTERS LOADED

-6.0

-9.04.5 5.5

TRANSMITTER OUTPUTVOLTAGE (VOL) vs. VCC

-8.0

-8.5

-6.5

-7.0

MAX

220-

07

VCC (V)

V OL (

V)

5.0

-7.5

4 TRANS-MITTERSLOADED

TA = +25°CC1–C4 = 1µFTRANSMITTERLOADS =3kΩ || 2500pF

1 TRANS-MITTERLOADED

2 TRANS-MITTERSLOADED

3 TRANS-MITTERSLOADED

-6.0

-7.60 2500

TRANSMITTER OUTPUT VOLTAGE (VOL) vs. LOAD CAPACITANCE AT

DIFFERENT DATA RATES

-7.0

-7.2

-7.4

-6.2

-6.4

MAX

220-

08

LOAD CAPACITANCE (pF)

V OL (

V)

15001000500 2000

-6.6

-6.8 160kbits/sec80kbits/sec20Kkbits/sec

TA = +25°CVCC = +5V3 TRANSMITTERS LOADEDRL = 3kΩC1–C4 = 1µF

10

-100 5 10 15 20 25 30 35 40 45 50

TRANSMITTER OUTPUT VOLTAGE (V+, V-)vs. LOAD CURRENT

-2

-6

-4

-8

8

6

MAX

220-

09

CURRENT (mA)

V+, V

- (V)

4

2

0V+ AND V-EQUALLYLOADED

V- LOADED,NO LOADON V+

TA = +25°CVCC = +5VC1–C4 = 1µF

ALL TRANSMITTERS UNLOADED

V+ LOADED,NO LOADON V-

__________________________________________Typical Operating CharacteristicsMAX223/MAX230–MAX241

*SHUTDOWN POLARITY IS REVERSED FOR NON MAX241 PARTS

V+, V- WHEN EXITING SHUTDOWN(1µF CAPACITORS)

MAX220-13

SHDN*

V-

O

V+

500ms/div

Input Logic Threshold Low

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ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249

ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-erwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ...............................................-0.3V to +6VInput VoltagesTIN‚ ENA, ENB, ENR, ENT, ENRA,ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V)RIN .....................................................................................±25VTOUT (Note 5).....................................................................±15VROUT ........................................................-0.3V to (VCC + 0.3V)

Short Circuit (one output at a time)TOUT to GND............................................................ContinuousROUT to GND............................................................Continuous

Continuous Power Dissipation (TA = +70°C)28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W

Operating Temperature RangesMAX225C_ _, MAX24_C_ _ ..................................0°C to +70°CMAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C

Storage Temperature Range .............................-65°C to +160°CLead Temperature (soldering,10s) (Note 6) ....................+300°C

VCC = 0V, VOUT = ±15V

µATables 1a–1d

±0.01 ±25

Normal operation

Shutdown

Tables 1a–1d, normal operation

All transmitter outputs loaded with 3kΩ to GND

ENA, ENB, ENT, ENTA, ENTB =VCC, VOUT = ±15V

VRS-232 Input Hysteresis

RS-232 Input Threshold Low V

V±5 ±7.5Output Voltage Swing

Output Leakage Current (Shutdown)

±0.01 ±25

Ω300 10MVCC = V+ = V- = 0V, VOUT = ±2V (Note 7)Transmitter Output Resistance

µA

PARAMETER

±0.05 ±0.10

MIN TYP MAX UNITS

Normal operation, outputs disabled,Tables 1a–1d, 0V ≤ VOUT ≤ VCC, ENR_ = VCC

TTL/CMOS Output Leakage Current

10 30Shrinking VOUT = VCCmA

-2 -10Sourcing VOUT = GND

V3.5 VCC - 0.2IOUT = -1.0mATTL/CMOS Output Voltage High

V0.2 0.4IOUT = 3.2mATTL/CMOS Output Voltage Low

kΩ3 5 7

0.2 0.5 1.0VCC = 5V

1.4 0.8 V

TTL/CMOS Output Short-Circuit Current

V1.8 2.4

0.8 1.3VCC = 5V

RS-232 Input Resistance

V±25RS-232 Input Voltage Operating Range

mA±7 ±30VOUT = 0VOutput Short-Circuit Current

kbps120 64Data Rate

CONDITIONS

VCC = 5V

µA±0.01 ±1

Logic Pull-Up/lnput Current10 50

Tables 1a–1d

RS-232 Input Threshold High

V2 1.4Input Logic Threshold High

RS-232 TRANSMITTERS

RS-232 RECEIVERS

Note 5: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V.Note 6: Maximum reflow temperature for the MAX225/MAX245/MAX246/MAX247 is +225°C.

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Operating Supply Voltage4.75 5.25

V

Transmitter Enable Time

MAX225 10 20

tET

No loadMAX244–MAX249 11 30

5 10 30

MAX225 40VCC Supply Current (Normal Operation) 3kΩ loads on

all outputs MAX244–MAX249 57

mA

Transition Slew Rate

8 25

CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V, TA = +25°C, measured from +3V to -3V or -3V to +3V

TA = TMIN to TMAX

CONDITIONS

50

V/µs

MAX246–MAX249 (excludes charge-pump startup)

Shutdown Supply Current µA

5

tPHLT 1.3 3.5

µs

tPLHT 1.5 3.5

Transmitter Disable Time, Figure 4

Transmitter Propagation DelayTLL to RS-232 (Normal Operation), Figure 1

µs

tDT 100 ns

Transmitter + to - Propagation Delay Difference (Normal Operation)

tPHLT - tPLHT

UNITSMIN TYP MAX

350

PARAMETER

ns

Receiver + to - Propagation Delay Difference (Normal Operation)

tPHLR - tPLHR 350 ns

4.5 5.5MAX244–MAX249

MAX225

Leakage current ±1

Threshold low 1.4 0.8Control Input

Threshold high 2.4 1.4V

µA

TA = +25°C

tPHLR 0.6 1.5

tPLHR 0.6 1.5

Receiver Propagation DelayTLL to RS-232 (Normal Operation),Figure 2

µs

tPHLS 0.6 10

tPLHS 3.0 10

Receiver Propagation Delay TLL to RS-232 (Low-Power Mode), Figure 2

µs

Receiver-Output Enable Time, Figure 3 tER 100 500 ns

Receiver-Output Disable Time, Figure 3 tDR 100 500 ns

MAX225/MAX245–MAX249(includes charge-pump startup)

10 ms

POWER SUPPLY AND CONTROL LOGIC

AC CHARACTERISTICS

Note 7: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC =0V is 10MΩ as is implied by the leakage specification.

ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued)(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-erwise noted.)

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__________________________________________Typical Operating Characteristics

MAX225/MAX244–MAX249

18

20 1 2 3 4 5

TRANSMITTER SLEW RATEvs. LOAD CAPACITANCE

8

6

4

16 MAX

220-

10

LOAD CAPACITANCE (nF)

TRAN

SMIT

TER

SLEW

RAT

E (V

/µs)

14

12

10

VCC = 5V

EXTERNAL POWER SUPPLY1µF CAPACITORS

40kb/s DATA RATE 8 TRANSMITTERSLOADED WITH 3kΩ

10

-100 5 10 15 20 25 30 35

OUTPUT VOLTAGEvs. LOAD CURRENT FOR V+ AND V-

-2

-4

-6

-8

8

MAX

220-

11

LOAD CURRENT (mA)

OUTP

UT V

OLTA

GE (V

)

6

4

2

0

V+ AND V- LOADEDEITHER V+ OR V- LOADED

V+ AND V- LOADED

VCC = 5VEXTERNAL CHARGE PUMP1µF CAPACITORS 8 TRANSMITTERSDRIVING 5kΩ AND2000pF AT 20kbits/sec

V- LOADED

V+ LOADED

9.0

5.00 1 2 3 4 5

TRANSMITTER OUTPUT VOLTAGE (V+, V-)vs. LOAD CAPACITANCE AT

DIFFERENT DATA RATES

6.0

5.5

8.5 MAX

220-

12

LOAD CAPACITANCE (nF)

V+, V

(V)

8.0

7.5

7.0

6.5

VCC = 5V WITH ALL TRANSMITTERS DRIVENLOADED WITH 5kΩ

10kb/sec

20kb/sec

40kb/sec

60kb/sec

100kb/sec200kb/sec

ALL CAPACITIORS 1µF

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INPUT

OUTPUT

+3V

V+

0VV-

0V

tPLHT tPHLT

tPHLRtPHLS

tPLHRtPLHS

50%VCC

50%+3V

50%INPUT

OUTPUT

*EXCEPT FOR R2 ON THE MAX243 WHERE -3V IS USED.

0V*

50%GND

Figure 1. Transmitter Propagation-Delay Timing Figure 2. Receiver Propagation-Delay Timing

EN

RX IN

a) TEST CIRCUIT

b) ENABLE TIMING

c) DISABLE TIMING

EN INPUT

RECEIVEROUTPUTS

RX OUTRX

1kΩ

0V

+3V

EN

EN

+0.8V

+3.5V

OUTPUT ENABLE TIME (tER)

VCC - 2V

VOL + 0.5V

VOH - 0.5V

OUTPUT DISABLE TIME (tDR)

VCC - 2V

+3V

0V

150pF

EN INPUT

VOH

RECEIVEROUTPUTS

VOL

1 OR 0 TX

3kΩ 50pF

-5V

+5V

OUTPUT DISABLE TIME (tDT)V+

SHDN+3V

0V

V-

0V

a) TIMING DIAGRAM

b) TEST CIRCUIT

Figure 3. Receiver-Output Enable and Disable Timing Figure 4. Transmitter-Output Disable Timing

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ENT ENR OPERATION STATUS TRANSMITTERS RECEIVERS

0 0 Normal Operation All Active All Active

0 1 Normal Operation All Active All 3-State

1 0 Shutdown All 3-State All Low-Power Receive Mode

1 1 Shutdown All 3-State All 3-State

Table 1a. MAX245 Control Pin Configurations

ENT ENROPERATION

STATUSTRANSMITTERS RECEIVERS

TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5

0 0 Normal Operation All Active All Active All Active All Active

0 1 Normal Operation All Active All ActiveRA1–RA4 3-State,RA5 Active

RB1–RB4 3-State,RB5 Active

1 0 Shutdown All 3-State All 3-StateAll Low-PowerReceive Mode

All Low-PowerReceive Mode

1 1 Shutdown All 3-State All 3-StateRA1–RA4 3-State,RA5 Low-PowerReceive Mode

RB1–RB4 3-State,RB5 Low-PowerReceive Mode

Table 1b. MAX245 Control Pin Configurations

Table 1c. MAX246 Control Pin Configurations

ENA ENBOPERATION

STATUSTRANSMITTERS RECEIVERS

TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5

0 0 Normal Operation All Active All Active All Active All Active

0 1 Normal Operation All Active All 3-State All ActiveRB1–RB4 3-State,RB5 Active

1 0 Shutdown All 3-State All ActiveRA1–RA4 3-State,RA5 Active

All Active

1 1 Shutdown All 3-State All 3-StateRA1–RA4 3-State,RA5 Low-PowerReceive Mode

RB1–RB4 3-State,RA5 Low-PowerReceive Mode

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TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB4

0 0 0 0 Normal Operation All Active All Active All Active All Active

0 0 0 1 Normal Operation All Active All Active All ActiveAll 3-State, exceptRB5 stays active onMAX247

0 0 1 0 Normal Operation All Active All Active All 3-State All Active

0 0 1 1 Normal Operation All Active All Active All 3-StateAll 3-State, exceptRB5 stays active onMAX247

0 1 0 0 Normal Operation All Active All 3-State All Active All Active

0 1 0 1 Normal Operation All Active All 3-State All ActiveAll 3-State, exceptRB5 stays active onMAX247

0 1 1 0 Normal Operation All Active All 3-State All 3-State All Active

0 1 1 1 Normal Operation All Active All 3-State All 3-StateAll 3-State, exceptRB5 stays active onMAX247

1 0 0 0 Normal Operation All 3-State All Active All Active All Active

1 0 0 1 Normal Operation All 3-State All Active All ActiveAll 3-State, exceptRB5 stays active onMAX247

1 0 1 0 Normal Operation All 3-State All Active All 3-State All Active

1 0 1 1 Normal Operation All 3-State All Active All 3-StateAll 3-State, exceptRB5 stays active onMAX247

1 1 0 0 Shutdown All 3-State All 3-StateLow-PowerReceive Mode

Low-PowerReceive Mode

1 1 0 1 Shutdown All 3-State All 3-StateLow-PowerReceive Mode

All 3-State, exceptRB5 stays active onMAX247

1 1 1 0 Shutdown All 3-State All 3-State All 3-StateLow-PowerReceive Mode

1 1 1 1 Shutdown All 3-State All 3-State All 3-StateAll 3-State, exceptRB5 stays active onMAX247

Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations

MAX248OPERATION

STATUSENRBMAX247 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB5

TRANSMITTERS

ENRAENTBENTA

MAX249 TA1–TA3 TB1–TB3 RA1–RA5 RB1–RB5

RECEIVERS

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The MAX220–MAX249 contain four sections: dualcharge-pump DC-DC voltage converters, RS-232 dri-vers, RS-232 receivers, and receiver and transmitterenable control inputs.

Dual Charge-Pump Voltage ConverterThe MAX220–MAX249 have two internal charge-pumpsthat convert +5V to ±10V (unloaded) for RS-232 driveroperation. The first converter uses capacitor C1 to dou-ble the +5V input to +10V on C3 at the V+ output. Thesecond converter uses capacitor C2 to invert +10V to -10V on C4 at the V- output.

A small amount of power may be drawn from the +10V(V+) and -10V (V-) outputs to power external circuitry(see the Typical Operating Characteristics section),except on the MAX225 and MAX245–MAX247, wherethese pins are not available. V+ and V- are not regulated,so the output voltage drops with increasing load current.Do not load V+ and V- to a point that violates the mini-mum ±5V EIA/TIA-232E driver output voltage whensourcing current from V+ and V- to external circuitry.

When using the shutdown feature in the MAX222,MAX225, MAX230, MAX235, MAX236, MAX240,MAX241, and MAX245–MAX249, avoid using V+ and V-to power external circuitry. When these parts are shutdown, V- falls to 0V, and V+ falls to +5V. For applica-tions where a +10V external supply is applied to the V+pin (instead of using the internal charge pump to gen-erate +10V), the C1 capacitor must not be installed andthe SHDN pin must be tied to VCC. This is because V+is internally connected to VCC in shutdown mode.

RS-232 DriversThe typical driver output voltage swing is ±8V whenloaded with a nominal 5kΩ RS-232 receiver and VCC =+5V. Output swing is guaranteed to meet the EIA/TIA-232E and V.28 specification, which calls for ±5V mini-mum driver output levels under worst-case conditions.These include a minimum 3kΩ load, VCC = +4.5V, andmaximum operating temperature. Unloaded driver out-put voltage ranges from (V+ -1.3V) to (V- +0.5V).

Input thresholds are both TTL and CMOS compatible.The inputs of unused drivers can be left unconnectedsince 400kΩ input pull-up resistors to VCC are built in(except for the MAX220). The pull-up resistors force theoutputs of unused drivers low because all drivers invert.The internal input pull-up resistors typically source 12µA,except in shutdown mode where the pull-ups are dis-abled. Driver outputs turn off and enter a high-imped-ance state—where leakage current is typicallymicroamperes (maximum 25µA)—when in shutdown

mode, in three-state mode, or when device power isremoved. Outputs can be driven to ±15V. The power-supply current typically drops to 8µA in shutdown mode.The MAX220 does not have pull-up resistors to force theoutputs of the unused drivers low. Connect unusedinputs to GND or VCC.

The MAX239 has a receiver three-state control line, andthe MAX223, MAX225, MAX235, MAX236, MAX240,and MAX241 have both a receiver three-state controlline and a low-power shutdown control. Table 2 showsthe effects of the shutdown control and receiver three-state control on the receiver outputs.

The receiver TTL/CMOS outputs are in a high-imped-ance, three-state mode whenever the three-state enableline is high (for the MAX225/MAX235/MAX236/MAX239–MAX241), and are also high-impedance whenever theshutdown control line is high.

When in low-power shutdown mode, the driver outputsare turned off and their leakage current is less than 1µAwith the driver output pulled to ground. The driver outputleakage remains less than 1µA, even if the transmitteroutput is backdriven between 0V and (VCC + 6V). Below-0.5V, the transmitter is diode clamped to ground with1kΩ series impedance. The transmitter is also zenerclamped to approximately VCC + 6V, with a seriesimpedance of 1kΩ.

The driver output slew rate is limited to less than 30V/µsas required by the EIA/TIA-232E and V.28 specifica-tions. Typical slew rates are 24V/µs unloaded and10V/µs loaded with 3Ω and 2500pF.

RS-232 ReceiversEIA/TIA-232E and V.28 specifications define a voltagelevel greater than 3V as a logic 0, so all receivers invert.Input thresholds are set at 0.8V and 2.4V, so receiversrespond to TTL level inputs as well as EIA/TIA-232E andV.28 levels.

The receiver inputs withstand an input overvoltage upto ±25V and provide input terminating resistors with

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PART SHDN EN EN(R) RECEIVERS

MAX223 __LowHighHigh

XLowHigh

High ImpedanceActiveHigh Impedance

MAX225 __ __High ImpedanceActive

__

MAX235MAX236MAX240

LowLowHigh

__ __LowHighX

High ImpedanceActiveHigh Impedance

Table 2. Three-State Control of Receivers

LowHigh

SHDN

__

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nominal 5kΩ values. The receivers implement Type 1interpretation of the fault conditions of V.28 andEIA/TIA-232E.

The receiver input hysteresis is typically 0.5V with aguaranteed minimum of 0.2V. This produces clear out-put transitions with slow-moving input signals, evenwith moderate amounts of noise and ringing. Thereceiver propagation delay is typically 600ns and isindependent of input swing direction.

Low-Power Receive ModeThe low-power receive-mode feature of the MAX223,MAX242, and MAX245–MAX249 puts the IC into shut-down mode but still allows it to receive information. Thisis important for applications where systems are periodi-cally awakened to look for activity. Using low-powerreceive mode, the system can still receive a signal thatwill activate it on command and prepare it for communi-cation at faster data rates. This operation conservessystem power.

Negative Threshold—MAX243The MAX243 is pin compatible with the MAX232A, differ-ing only in that RS-232 cable fault protection is removedon one of the two receiver inputs. This means that controllines such as CTS and RTS can either be driven or leftfloating without interrupting communication. Differentcables are not needed to interface with different pieces ofequipment.

The input threshold of the receiver without cable faultprotection is -0.8V rather than +1.4V. Its output goespositive only if the input is connected to a control linethat is actively driven negative. If not driven, it defaultsto the 0 or “OK to send” state. Normally‚ the MAX243’sother receiver (+1.4V threshold) is used for the data line(TD or RD)‚ while the negative threshold receiver is con-nected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.).

Other members of the RS-232 family implement theoptional cable fault protection as specified by EIA/TIA-232E specifications. This means a receiver output goeshigh whenever its input is driven negative‚ left floating‚or shorted to ground. The high output tells the serialcommunications IC to stop sending data. To avoid this‚the control lines must either be driven or connectedwith jumpers to an appropriate positive voltage level.

Shutdown—MAX222–MAX242 On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ andMAX241‚ all receivers are disabled during shutdown.On the MAX223 and MAX242‚ two receivers continue tooperate in a reduced power mode when the chip is inshutdown. Under these conditions‚ the propagationdelay increases to about 2.5µs for a high-to-low inputtransition. When in shutdown, the receiver acts as aCMOS inverter with no hysteresis. The MAX223 andMAX242 also have a receiver output enable input (ENfor the MAX242 and EN for the MAX223) that allowsreceiver output control independent of SHDN (SHDNfor MAX241). With all other devices‚ SHDN (SHDN forMAX241) also disables the receiver outputs.

The MAX225 provides five transmitters and fivereceivers‚ while the MAX245 provides ten receivers andeight transmitters. Both devices have separate receiverand transmitter-enable controls. The charge pumpsturn off and the devices shut down when a logic high isapplied to the ENT input. In this state, the supply cur-rent drops to less than 25µA and the receivers continueto operate in a low-power receive mode. Driver outputsenter a high-impedance state (three-state mode). Onthe MAX225‚ all five receivers are controlled by theENR input. On the MAX245‚ eight of the receiver out-puts are controlled by the ENR input‚ while the remain-ing two receivers (RA5 and RB5) are always active.RA1–RA4 and RB1–RB4 are put in a three-state modewhen ENR is a logic high.

Receiver and Transmitter Enable Control Inputs

The MAX225 and MAX245–MAX249 feature transmitterand receiver enable controls.

The receivers have three modes of operation: full-speedreceive (normal active)‚ three-state (disabled)‚ and low-power receive (enabled receivers continue to functionat lower data rates). The receiver enable inputs controlthe full-speed receive and three-state modes. Thetransmitters have two modes of operation: full-speedtransmit (normal active) and three-state (disabled). Thetransmitter enable inputs also control the shutdownmode. The device enters shutdown mode when alltransmitters are disabled. Enabled receivers function inthe low-power receive mode when in shutdown.

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has no control pins and is not included in these tables.

The MAX246 has ten receivers and eight drivers withtwo control pins, each controlling one side of thedevice. A logic high at the A-side control input (ENA)causes the four A-side receivers and drivers to go intoa three-state mode. Similarly, the B-side control input(ENB) causes the four B-side drivers and receivers togo into a three-state mode. As in the MAX245, one A-side and one B-side receiver (RA5 and RB5) remainactive at all times. The entire device is put into shut-down mode when both the A and B sides are disabled(ENA = ENB = +5V).

The MAX247 provides nine receivers and eight driverswith four control pins. The ENRA and ENRB receiverenable inputs each control four receiver outputs. TheENTA and ENTB transmitter enable inputs each controlfour drivers. The ninth receiver (RB5) is always active.The device enters shutdown mode with a logic high onboth ENTA and ENTB.

The MAX248 provides eight receivers and eight driverswith four control pins. The ENRA and ENRB receiverenable inputs each control four receiver outputs. TheENTA and ENTB transmitter enable inputs control fourdrivers each. This part does not have an always-activereceiver. The device enters shutdown mode and trans-mitters go into a three-state mode with a logic high onboth ENTA and ENTB.

The MAX249 provides ten receivers and six drivers withfour control pins. The ENRA and ENRB receiver enableinputs each control five receiver outputs. The ENTAand ENTB transmitter enable inputs control three dri-vers each. There is no always-active receiver. Thedevice enters shutdown mode and transmitters go intoa three-state mode with a logic high on both ENTA andENTB. In shutdown mode, active receivers operate in alow-power receive mode at data rates up to 20kb/s.

__________Applications InformationFigures 5 through 25 show pin configurations and typi-cal operating circuits. In applications that are sensitiveto power-supply noise, VCC should be decoupled toground with a capacitor of the same value as C1 andC2 connected as close as possible to the device.

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TOP VIEW

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VCC

GND

T1OUT

R1INC2+

C1-

V+

C1+

MAX220MAX232

MAX232A R1OUT

T1IN

T2IN

R2OUTR2IN

T2OUT

V-

C2-

DIP/SO

V+

V-

2 +10VC1+C1

C2

1

34

5

11

10

12

9

6

14

7

13

8

T1IN

R1OUT

T2IN

R2OUT

T1OUT

R1IN

T2OUT

R2IN

+5V INPUT

C2+ -10V

C4

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND15

5kΩ

5kΩ

400kΩ

400kΩ+5V

+5V

+10V TO -10VVOLTAGE INVERTER

+5V TO +10VVOLTAGE DOUBLER

16

C3

C5

CAPACITANCE (µF)DEVICEMAX220MAX232MAX232A

C10.0471.00.1

C20.331.00.1

C30.331.00.1

C40.331.00.1

C50.331.00.1

C2-

C1-

VCC

5kΩ

DIP/SO

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

SHDN

VCC

GND

T1OUTC1-

V+

C1+

(N.C.) EN

R1IN

R1OUT

T1IN

T2INT2OUT

V-

C2-

C2+

109 R2OUTR2IN

MAX222MAX242

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

SHDN

VCC

GND

T1OUTC1-

V+

C1+

(N.C.) EN

N.C.

R1IN

R1OUT

N.C.T2OUT

V-

C2-

C2+

12

11

9

10

T1IN

T2INR2OUT

R2IN

MAX222MAX242

SSOP

( ) ARE FOR MAX222 ONLY.PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.

V+

V-

3 +10VC1

C2

2

45

6

12

11

13

7

15

8

14

9

T1IN

R1OUT

T2IN

R2OUT

T1OUT

(EXCEPT MAX220)

(EXCEPT MAX220)

R1IN

T2OUT

R2IN

+5V INPUT

C2+ -10V

C4

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND16

5kΩ

400kΩ

400kΩ+5V

+5V

+10V TO -10VVOLTAGE INVERTER

VCC+5V TO +10V

VOLTAGE DOUBLER

17

C3

C5

1

10

18SHDN

EN(N.C.)

ALL CAPACITORS = 0.1µF

C2-

C1+C1-

TOP VIEW

Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit

Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit

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13

14

28

27

26

25

24

23

22

21

1

2

3

4

5

6

7

8

VCC

VCC VCC

400kΩ

400kΩ

400kΩ

400kΩ

400kΩ

T1OUT+5V

+5V

0.1

+5V

3

28 27

4

25

24

23

26

5

6

7

22

GNDENRENR

GND

21

+5V

+5V

+5V

T2OUT

T3OUT

T4OUT

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

1413

21

T5OUT

T5OUT

R1IN

R2IN

R3IN

R4IN

R5IN

T1IN11

12

18

17

16

15

10

9

8

19

20

T2IN

T3IN

T4IN

T5IN

ENT

R2OUT

R3OUT

R4OUT

PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED.CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER.

R5OUT

R1OUT

VCC

ENT

T3INT2IN

T1IN

ENR

ENR

T4IN

T5IN

R4OUT

R5OUTR3IN

R3OUT

R2OUT

R1OUT

20

19

18

17

9

10

11

12

R5IN

R4IN

T3OUT

T4OUTT2OUT

T1OUT

R1IN

R2IN

SO

MAX225

16

15

T5OUT

MAX225 FUNCTIONAL DESCRIPTION5 RECEIVERS5 TRANSMITTERS2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

T5OUTGND

GND

TOP VIEW

Figure 7. MAX225 Pin Configuration and Typical Operating Circuit

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GND

10

27R3OUT

23R4OUT

R3IN

R4IN

5kΩ

5kΩ

5 4R2OUT R2IN

5kΩ

RS-232INPUTS

LOGICOUTPUTS

RS-232OUTPUTS

TTL/CMOSINPUTS

R2

8 9R1OUT R1IN

5kΩR1

R3

R4

19 18R5OUT R5IN

5kΩR5

27 T1IN T1OUT

+5V400kΩ

+5V

6 3T2IN T2OUTT2

400kΩ

20 T3OUT 1T3IN

+5V

T3

400kΩ

C1+

C1-

1.0µF

12VCC

+5V INPUT

11

17

1.0µF

131.0µF

+5V TO +10VVOLTAGE DOUBLER

26

1.0µF

T1

2821 T4IN T4OUT

+5V

400kΩ

T4

14

C2+

C2-

15

1.0µF 16+10V TO -10V

VOLTAGE INVERTER

V+

22

EN (EN)24 25

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

T4OUT

R3IN

R3OUT

SHDN (SHDN)

R4IN*

C2+

R4OUT*

T4IN

T3IN

R5OUT*

R5IN*

V-

C2-

C1-

V+

C1+

VCC

GND

R1IN

R1OUT

T1IN

T2IN

R2OUT

R2IN

T2OUT

T1OUT

T3OUT

Wide SO/SSOP

MAX223MAX241

EN (EN)

SHDN(SHDN)

*R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN

NOTE: PIN LABELS IN ( ) ARE FOR MAX241

V-

TOP VIEW

Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit

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20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

T5IN

N.C.

SHDNT2IN

T2OUT

T1OUT

T5OUT

T4IN

T3IN

V-C1+

VCC

GND

T1IN

12

11

9

10

C2-

C2+C1-

V+

DIP/SO

MAX230

V+

V-

9C1+C1-

810

1112

5

4

14

13

2

3

1

20

T3IN

T4IN

T2IN

T5IN

T1OUT

T2OUT

+5V INPUT

C2+C2-

RS-232OUTPUTS

TTL/CMOSINPUTS

GND6

400kΩ+5V

400kΩ+5V

400kΩ+5V

400kΩ+5V

400kΩ+5V

+10V TO -10VVOLTAGE INVERTER

VCC+5V TO +10V

VOLTAGE DOUBLER

7

1.0µF

1.0µF

1.0µF

1.0µF

19

15

16

T3OUT T4OUT

18x

T1IN

T3OUT

T4OUT

T5OUT

17

1.0µF

T2

T3

T4

T5

N.C. SHDN

T1

TOP VIEW

Figure 9. MAX230 Pin Configuration and Typical Operating Circuit

V+

V-

14C1+

C1-

1

2

8

7

3

11

4T2IN

T1IN T1OUT

T2OUT

+5V INPUT

RS-232INPUTS

TTL/CMOSOUTPUTS

GND

12 (14)

5kΩ

5kΩ

+12V TO -12VVOLTAGE CONVERTER

13 (15)

1.0µF

1.0µFC2

1.0µF

400kΩ

+5V

400kΩ

+5V

6

9 10R1IN

R2INR2OUT

R1OUT

5

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

V+

VCC

GND

T1OUTT2OUT

V-

C-

C+

MAX231

R1IN

R1OUT

T1IN

N.C.N.C.

T2IN

R2OUT

R2IN

SO

(12)

RS-232OUTPUTS

TTL/CMOSINPUTS

(11)

(13)(10)

VCC

PIN NUMBERS IN ( ) ARE FOR SO PACKAGE

14

13

12

11

10

9

8

1

2

3

4

5

6

7

V+

VCC

GND

T1OUTT2OUT

V-

C-

C+

MAX231

R1IN

R1OUT

T1INT2IN

R2OUT

R2IN

DIP

+7.5V TO +12V

(16)

T1

T2

R1

R2

TOP VIEW

Figure 10. MAX231 Pin Configurations and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 21

2

1

5

18T2IN

T1IN T1OUT

T2OUT

+5V INPUT

RS-232INPUTS

TTL/CMOSOUTPUTS

GND GND6 9

400kΩ

+5V

400kΩ+5V

5kΩ

5kΩ

7

20

3 4R1IN

R2INR2OUT

R1OUT

19

RS-232OUTPUTS

TTL/CMOSINPUTS

VCC

( ) ARE FOR SO PACKAGE ONLY.

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

R2IN

T2OUT

V-R1IN

R1OUT

T1IN

C2-

C2+

V+ (C1-)

C1- (C1+)(V+) C1+

VCC

GND

T1OUT

12

11

9

10

V- (C2+)

C2+ (C2-)(V-) CS-

GND

DIP/SO

MAX233MAX233A

T2IN R2OUT

C1+

C1-

V-

V-

V+

C2+

C2-

C2-

C2+

8 (13)

13 (14)

12 (10)

17

14 (8)

11 (12)

15

16

10 (11)

DO NOT MAKECONNECTIONS TO

THESE PINS

INTERNAL -10POWER SUPPLY

INTERNAL +10VPOWER SUPPLY

1.0µFTOP VIEW

Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

T3OUT

T4OUT

T4IN

T3INT1IN

T2IN

T2OUT

T1OUT

MAX234

V-

C2-

C2+

C1-V+

C1+

VCC

GND

DIP/SO

V+

V-

8C1+

C1-

1.0µF

1.0µF

1.0µF

7

9

10

11

4

3

13

14

12

1

3

16

15

T1IN

T3IN

T2IN

T4IN

T1OUT

T3OUT

T2OUT

T4OUT

+5V INPUT

C2-

C2+

RS-232OUTPUTS

TTL/CMOSINPUTS

GND5

+5V

+5V

+10V TO -10VVOLTAGE INVERTER

VCC+5V TO +10V

VOLTAGE DOUBLER

6

+5V

+5V

400kΩ

400kΩ

400kΩ

400kΩ

1.0µF

1.0µF

T1

T2

T4

T3

TOP VIEW

Figure 12. MAX234 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

22 ______________________________________________________________________________________

1.0µF+5V INPUT

GND

11

6

23

5R2OUT

RS-232INPUTS

TTL/CMOSOUTPUTS

14 13

21

R5OUT

5kΩ

17 18R4OUT

5kΩ

24R3OUT

5kΩ

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

R3IN

R3OUT

T5IN

SHDNT2OUT

T1OUT

T3OUT

T4OUT

EN

T5OUT

R4IN

R4OUTT1IN

T2IN

R2OUT

R2IN

16

15

14

13

9

10

11

12

T4IN

T3IN

R5OUT

R5INVCC

GND

R1IN

R1OUT

DIP

MAX235

5kΩ

9 10R1OUT R1IN

R2IN

R3IN

R4IN

R5IN

5kΩ

7

15

3

4T2IN

T3OUT RS-232OUTPUTS

TTL/CMOSINPUTS

22 19T5IN T5OUT

+5V

16 1T4IN T4OUT

+5V

2T3IN

+5V

+5V

8 T1IN T1OUT

+5V

T2OUT

T1

T1

R2

R3

R4

R5

T2

T3

T5

T4

400kΩ

400kΩ

400kΩ

400kΩ

400kΩ

SHDNEN20

12

VCC

TOP VIEW

Figure 13. MAX235 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 23

GND

8

23R2OUT RS-232INPUTS

TTL/CMOSOUTPUTS

17 16

21

R3OUT

R2IN

R3IN

5kΩ

5kΩ

5 4R1OUT R1IN

5kΩ

RS-232OUTPUTS

TTL/CMOSINPUTS

R1

R2

R3

27 T1IN T1OUT

+5V

T1

400kΩ

6 3T2IN

+5V

T2OUTT2

400kΩ

18 T3OUT 1T3IN

+5V

T3

400kΩ

19 24T4IN T4OUT

+5V

T4

400kΩ

SHDNEN20

11C1+

C1-

1.0µF

10

12

13

14

15

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10VVOLTAGE INVERTER

22

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T4OUT

R2IN

R2OUT

SHDNR1IN

T2OUT

T1OUT

T3OUT

T4IN

T3IN

R3OUTGND

T1IN

T2IN

R1OUT

16

15

14

13

9

10

11

12

R3IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX236 EN

1.0µF

1.0µF

TOP VIEW

V+

V-

Figure 14. MAX236 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

24 ______________________________________________________________________________________

GND

8

23R2OUT RS-232INPUTS

TTL/CMOSOUTPUTS

17 16R3OUT

R2IN

R3IN

5kΩ

5kΩ

5 4R1OUT R1IN

5kΩ

RS-232OUTPUTS

TTL/CMOSINPUTS

R1

R2

R3

27 T1IN T1OUT

+5V

T1

400kΩ

6 3T2IN

+5V

T2OUTT2

400kΩ

18 T3OUT 1T3IN

+5V

T3

400kΩ

21 20T5IN T5OUT

+5V

T5

400kΩ

11C1+

C1-

1.0µF

10

12

13

14

15

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10V

VOLTAGE INVERTER

22

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T4OUT

R2IN

R2OUT

T5INR1IN

T2OUT

T1OUT

T3OUT

T4IN

T3IN

R3OUTGND

T1IN

T2IN

R1OUT

16

15

14

13

9

10

11

12

R3IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX237 T5OUT

1.0µF

1.0µF

19 24T4IN T4OUT

+5V

T4

400kΩ

V+

V-

TOP VIEW

Figure 15. MAX237 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 25

GND

8

3R2OUT

22 23R3OUT

R2IN

R3IN

5kΩ

5kΩ

6 7R1OUT R1IN

5kΩ

RS-232OUTPUTS

TTL/CMOSINPUTS

RS-232INPUTS

TTL/CMOSOUTPUTS

R1

R2

R3

17 16R4OUT R4IN

5kΩ

R4

25 T1IN T1OUT

+5V400kΩ

+5V

18 1T2IN T2OUTT2

400kΩ

19 T3OUT 24T3IN

+5V

T3

400kΩ

11C1+

C1-

1.0µF

10

12

13

1415

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10V

VOLTAGE INVERTER

4

1.0µF

1.0µF

21 20T4IN T4OUT

+5V

T4

400kΩ

T124

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T3OUT

R3IN

R3OUT

T4INR2OUT

R2IN

T1OUT

T2OUT

TOP VIEW

T3IN

T2IN

R4OUTGND

R1IN

R1OUT

T1IN

16

15

14

13

9

10

11

12

R4IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX238 T4OUT

V+

V-

Figure 16. MAX238 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

26 ______________________________________________________________________________________

GND

3

18R3OUT

12R4OUT

R3IN

R4IN

5kΩ

5kΩ

22 21R2OUT R2IN

5kΩ

RS-232OUTPUTS

TTL/CMOSINPUTS

RS-232INPUTS

TTL/CMOSOUTPUTS

R2

1 2R1OUT R1IN

5kΩ

R1

R3

R4

10 9R5OUT R5IN

5kΩ

R5

1924 T1IN T1OUT

+5V400kΩ

+5V

23 20T2IN T2OUTT2

400kΩ

16 T3OUT 13T3IN

+5V

T3

400kΩ

C1+

C1-

1.0µF

6 VCC 8

+5V INPUT

4 5

1.0µF+10V TO -10V

VOLTAGE INVERTER

17

1.0µF

T1

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T1IN

T2IN

R2OUT

R2INVCC

GND

R1IN

R1OUT

T1OUT

R3IN

R3OUTV-

C-

C+

V+

16

15

14

13

9

10

11

12

T3IN

N.C.

EN

T3OUTR4IN

R4OUT

R5OUT

R5IN

DIP/SO

MAX239 T2OUT

7.5V TO 13.2VINPUT

7

V+

11

EN14 15N.C.

V-

TOP VIEW

Figure 17. MAX239 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 27

GND

18

4R3OUT

40R4OUT

R3IN

R4IN

5kΩ

5kΩ

13 10R2OUT R2IN

5kΩ

RS-232INPUTS

TTL/CMOSOUTPUTS

RS-232OUTPUTS

TTL/CMOSINPUTS

R2

16 17R1OUT R1IN

5kΩR1

R3

R4

36 35R5OUT R5IN

5kΩ

R5

715 T1IN T1OUT

+5V400kΩ

+5V

14 8T2IN T2OUTT2

400kΩ

37 T3OUT 6T3IN

+5V

T3

400kΩ

C1+

C1-

1.0µF

25VCC

+5V INPUT

19

30

1.0µF

261.0µF

+5V TO +10VVOLTAGE DOUBLER

3

1.0µF

T1

+5V

2 41T5IN T5OUTT5

400kΩ

538 T4IN T4OUT

+5V400kΩ

T4

27

C2+

C2-

28

1.0µF 29+5V TO -10V

VOLTAGE INVERTER

V+

39

EN42 43

Plastic FP

MAX240

SHDNENT5OUTR4INR4OUT

R5OUTR5INN.C.

N.C.

T3IN

T4IN

R2OUTT2INT1IN

R1OUTR1IN

N.C.N.C.N.C.

N.C.

VCC

GND

R2IN

N.C.

T4OU

T

T2OU

TT1

OUT

T3OU

T

N.C.

R3IN

R3OU

T

N.C.

T5IN

N.C.

C1+ C2V+ C1-

C2+

N.C. V-

N.C.

N.C.

N.C.

3332313029282726252423

3435363738394041424344

1234567891011

2221201918171615141312

SHDN

TOP VIEW

V-

Figure 18. MAX240 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

28 ______________________________________________________________________________________

V+

V-

2 +10VC1+

C1-

1

3

4

5

11

10

12

9

6

14

7

13

8

T1IN

R1OUT

T2IN

R2OUT

T1OUT

R1IN

T2OUT

R2IN

+5V INPUT

C2+

C2--10V

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND

15

5kΩ

5kΩ

400kΩ

400kΩ

+5V

+5V

+10V TO -10VVOLTAGE INVERTER

+5V TO +10VVOLTAGE DOUBLER

16

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

C1+ VCC

GND

T1OUT

R1IN

R1OUT

T1IN

T2IN

R2OUT

MAX243

DIP/SO

V+

C1-

V-

C2+

C2-

T2OUT

R2IN

0.1µF

0.1µF

0.1µF

0.1µFALL CAPACITORS = 0.1µF

0.1µF

RECEIVER INPUT≤ -3 VOPEN≥ +3V

R1 OUTPUTHIGHHIGHLOW

R2 OUTPUTHIGHLOWLOW

TOP VIEW

VCC

Figure 19. MAX243 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 29

400kΩ

+10V TO -10V VOLTAGE INVERTER

+5V TO +10V VOLTAGE DOUBLERVCC

400kΩ

400kΩ

GND

+5V +5V

+5V +5V

+5V

25

2423

2120

2

1µF

1µF

1µF 1µF

1µF

16

3

17

4

18

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

C2-C2+

C1-C1+

TA2OUT

TA2IN

TA3OUT

TA3IN

TA4OUT

TA4IN

9 RA1IN

10 RA1OUT

8 RA2IN

11 RA2OUT

7 RA3IN

12 RA3OUT

6 RA4IN

13 RA4OUT

5 RA5IN

14

19

RA5OUT

26

22

43

29

42

28

41

27

36

35

37

34

38

33

39

32

40

31

V-

V+

TB2OUT

TB2IN

400kΩ

2

15

TA1OUT

TA1IN

44

30

TB1OUT

TB1IN

TB3OUT

TB3IN

TB4OUT

TB4IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

MAX249 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVER 5 B-SIDE RECEIVER8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERSNO CONTROL PINS

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

TA3IN

V CC

R A5IN

MAX244

PLCC

TOP VIEWT A

4OUT

T A3O

UT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

TB4O

UT

R B5IN

GND V+C1+

C2+

C1- V-C2-

T B3IN

T B4IN

RB3IN

RB2IN

RB1IN

RB1OUT

RB2OUT

RB3OUT

RB4OUT

RB5OUT

TB1IN

TB2IN

TA2IN

TA1IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

7 39 RB4INRA3IN

6

18

R A4IN

T A4IN

+5V +5V

+5V +5V

Figure 20. MAX244 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

30 ______________________________________________________________________________________

400kΩ

VCC

400kΩ

400kΩ

GND

+5V +5V

+5V +5V

+5V

40

17

1µF

3

18

4

19

5

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

TA2OUT

TA2IN

TA3OUT

TA3IN

TA4OUT

TA4IN

1

11 RA1IN

10 RA1OUT

12 RA2IN

9 RA2OUT

13 RA3IN

8 RA3OUT

14 RA4IN

7 RA4OUT

15 RA5IN

6

20

RA5OUT

23

37

22

36

21

35

29

30

28

31

27

32

26

33

25

34

TB2OUT

TB2IN

TB3OUT

TB3IN

TB4OUT

TB4IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

+5V +5V

400kΩ

16

2

TA1OUT

TA1IN

24

38

TB1OUT

TB1IN

+5V +5V40 VCC

ENT

TB1IN

TB2IN

TB3IN

TB4IN

RB5OUT

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENR

TA1IN

TA2IN

TA3IN

TA4IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

RA5IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX245

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

MAX245 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTTERS 4 A-SIDE TRANSMITTERS2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

39ENR ENT

Figure 21. MAX245 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 31

400kΩ

VCC

400kΩ

GND

+5V

+5V

+5V

+5V

+5V

40

16

1µF

2

18

4

TA1OUT

TA1IN

TA3OUT

TA3IN

20

24

38

22

36

1 39

TB1OUT

TB1IN

TB3OUT

TB3IN

400kΩ

+5V17

3

TA2OUT

TA2IN

+5V23

37

TB2OUT

TB2IN

400kΩ

+5V19

5

TA4OUT

TA4IN

+5V21

35

TB4OUT

TB4IN

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

11 RA1IN

10 RA1OUT

12 RA2IN

9 RA2OUT

13 RA3IN

8 RA3OUT

14 RA4IN

7 RA4OUT

15 RA5IN

6 RA5OUT

29

30

28

31

27

32

26

33

25

34

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

40 VCC

ENB

TB1IN

TB2IN

TB3IN

TB4IN

RB5OUT

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENA

TA1IN

TA2IN

TA3IN

TA4IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

RA5IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX246

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

MAX246 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS2 CONTROL PINS ENABLE A-SIDE (ENA) ENABLE B-SIDE (ENB)

ENA ENB

Figure 22. MAX246 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

32 ______________________________________________________________________________________

400kΩ

VCC

400kΩ

GND

+5V

+5V

+5V

+5V

+5V

1

40

16

1µF

2

18

4

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

ENTA

TA1OUT

TA1IN

TA3OUT

TA3IN

6 RB5OUT

12 RA1IN

10 RA1OUT

13 RA2IN

9 RA2OUT

14 RA3IN

8 RA3OUT

15 RA4IN

7

20

RA4OUT

11

39

24

38

22

36

29

31

28

32

27

33

26

34

30ENRA

ENTB

TB1OUT

TB1IN

TB3OUT

TB3IN

RB1IN

5kΩ

25RB5IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

ENRB

400kΩ

+5V17

3

TA2OUT

TA2IN

+5V23

37

TB2OUT

TB2IN

400kΩ

+5V19

5

TA4OUT

TA4IN

+5V21

35

TB4OUT

TB4IN

40 VCC

ENTB

TB1IN

TB2IN

TB3IN

TB4IN

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENTA

TA1IN

TA2IN

TA3IN

TA4IN

RB5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX247

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

ENRA ENRB

MAX247 FUNCTIONAL DESCRIPTION9 RECEIVERS 4 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVERr B-SIDE (ENTB)

Figure 23. MAX247 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 33

400kΩ

+10V TO -10V VOLTAGE INVERTER

+5V TO +10V VOLTAGE DOUBLERVCC

400kΩ

GND

+5V

+5V

+5V

+5V

+5V

18

25

2423

2120

1

1µF

1µF

1µF1µF

1µF

14

3

16

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

ENTA

C2-C2+

C1-C1+

TA1OUT

TA1IN

TA3OUT

TA3IN

8 RA1IN

10 RA1OUT

7 RA2IN

11 RA2OUT

6 RA3IN

12 RA3OUT

5 RA4IN

13

19

RA4OUT

9

27

26

22

44

31

42

29

37

35

38

34

39

33

40

32

36ENRA

ENTB

V-

V+

TB1OUT

TB1IN

TB3OUT

TB3IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

ENRB

400kΩ

+5V2

15

TA2OUT

TA2IN

+5V43

30

TB2OUT

TB2IN

400kΩ

+5V4

17

TA4OUT

TA4IN

+5V41

28

TB4OUT

TB4IN

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

TA4IN

V CC

R A4IN

MAX248

PLCC

TOP VIEWT A

4OUT

T A3O

UT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

T A4O

UT

R B4IN

GND V+C1+

C2+

C1- V-C2-

T B4IN

ENTB

RB2IN

RB1IN

RB1OUT

RB2OUT

RB3OUT

RB4OUT

TB1IN

TB2IN

TB3IN

TA3IN

TA2IN

TA1IN

RA4OUT

RA3OUT

RA2OUT

RA1OUT

ENRA

RA1IN

7 39 RB3INRA2IN

6

18

R A3IN

ENRB

ENTA

MAX248 FUNCTIONAL DESCRIPTION8 RECEIVERS 4 A-SIDE RECEIVERS 4 B-SIDE RECEIVERS8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)

Figure 24. MAX248 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

34 ______________________________________________________________________________________

400kΩ

+10V TO -10V VOLTAGE INVERTER

+5V TO +10V VOLTAGE DOUBLERVCC

400kΩ

400kΩ

GND

+5V

+5V

+5V

+5V

+5V

+5V

+5V

18

25

2423

2120

1

1µF

1µF

1µF1µF

15

2

16

3

17

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

5kΩ

ENTA

C2-C2+

C1-C1+

TA1OUT

TA1IN

TA2OUT

TA2IN

TA3OUT

TA3IN

8 RA1IN

10 RA1OUT

7 RA2IN

11 RA2OUT

6 RA3IN

12 RA3OUT

5 RA4IN

13 RA4OUT

4 RA5IN

14

19

RA5OUT

9

27

26

22

44

30

43

29

42

28

37

35

38

34

39

33

40

32

41

31

36ENRA

ENTB

V-

V+

TB1OUT

TB1IN

TB2OUT

TB2IN

TB3OUT

TB3IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

ENRB

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

V CC

R A4IN

R A5IN

MAX249

PLCC

TOP VIEWT A

3OUT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

R B4IN

R B5IN

GND V+C1+

C2+

C1- V-C2-

T B3IN

ENTB

RB2IN

RB1IN

RB1OUT

MAX249 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS6 TRANSMITTERS 3 A-SIDE TRANSMITTERS 3 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)

RB2OUT

RB3OUT

RB4OUT

RB5OUT

TB1IN

TB2INTA3IN

TA2IN

TA1IN

RA4OUT

RA5OUT

RA3OUT

RA2OUT

RA1OUT

ENRA

RA1IN

7 39 RB3INRA2IN

6

18

R A3IN

ENRB

ENTA

1µF

Figure 25. MAX249 Pin Configuration and Typical Operating Circuit

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers

______________________________________________________________________________________ 35

___________________________________________Ordering Information (continued)

PART

MAX222CPN 0°C to +70°C

TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE

18 Plastic DIP

MAX222CWN 0°C to +70°C 18 Wide SO

MAX222C/D 0°C to +70°C Dice*

MAX222EPN -40°C to +85°C 18 Plastic DIP

MAX222EWN -40°C to +85°C 18 Wide SO

MAX222EJN -40°C to +85°C 18 CERDIP

MAX222MJN -55°C to +125°C 18 CERDIP

MAX223CAI 0°C to +70°C 28 SSOP

MAX223CWI 0°C to +70°C 28 Wide SO

MAX223C/D 0°C to +70°C Dice*

MAX223EAI -40°C to +85°C 28 SSOP

MAX223EWI -40°C to +85°C 28 Wide SO

MAX225CWI 0°C to +70°C 28 Wide SO

MAX225EWI -40°C to +85°C 28 Wide SO

MAX230CPP 0°C to +70°C 20 Plastic DIP

MAX230CWP 0°C to +70°C 20 Wide SO

MAX230C/D 0°C to +70°C Dice*

MAX230EPP -40°C to +85°C 20 Plastic DIP

MAX230EWP -40°C to +85°C 20 Wide SO

MAX230EJP -40°C to +85°C 20 CERDIP

MAX230MJP -55°C to +125°C 20 CERDIP

MAX231CPD 0°C to +70°C 14 Plastic DIP

MAX231CWE 0°C to +70°C 16 Wide SO

MAX231CJD 0°C to +70°C 14 CERDIP

MAX231C/D 0°C to +70°C Dice*

MAX231EPD -40°C to +85°C 14 Plastic DIP

MAX231EWE -40°C to +85°C 16 Wide SO

MAX231EJD -40°C to +85°C 14 CERDIP

MAX231MJD -55°C to +125°C 14 CERDIP

MAX232CPE 0°C to +70°C 16 Plastic DIP

MAX232CSE 0°C to +70°C 16 Narrow SO

MAX232CWE 0°C to +70°C 16 Wide SO

MAX232C/D 0°C to +70°C Dice*

MAX232EPE -40°C to +85°C 16 Plastic DIP

MAX232ESE -40°C to +85°C 16 Narrow SO

MAX232EWE -40°C to +85°C 16 Wide SO

MAX232EJE -40°C to +85°C 16 CERDIP

MAX232MJE -55°C to +125°C 16 CERDIP

MAX232MLP -55°C to +125°C 20 LCC

MAX232ACPE 0°C to +70°C 16 Plastic DIP

MAX232ACSE 0°C to +70°C 16 Narrow SO

MAX232ACWE 0°C to +70°C 16 Wide SO

MAX232AC/D

MAX232AEPE -40°C to +85°C 16 Plastic DIP

MAX232AESE

0°C to +70°C Dice*

-40°C to +85°C 16 Narrow SO

MAX232AEWE -40°C to +85°C 16 Wide SO

MAX232AEJE -40°C to +85°C 16 CERDIP

MAX232AMJE -55°C to +125°C 16 CERDIP

MAX232AMLP -55°C to +125°C 20 LCC

MAX233CPP 0°C to +70°C 20 Plastic DIP

MAX233EPP -40°C to +85°C 20 Plastic DIP

MAX233ACPP 0°C to +70°C 20 Plastic DIP

MAX233ACWP 0°C to +70°C 20 Wide SO

MAX233AEPP -40°C to +85°C 20 Plastic DIP

MAX233AEWP -40°C to +85°C 20 Wide SO

MAX234CPE 0°C to +70°C 16 Plastic DIP

MAX234CWE 0°C to +70°C 16 Wide SO

MAX234C/D 0°C to +70°C Dice*

MAX234EPE -40°C to +85°C 16 Plastic DIP

MAX234EWE -40°C to +85°C 16 Wide SO

MAX234EJE -40°C to +85°C 16 CERDIP

MAX234MJE -55°C to +125°C 16 CERDIP

MAX235CPG 0°C to +70°C 24 Wide Plastic DIP

MAX235EPG -40°C to +85°C 24 Wide Plastic DIP

MAX235EDG -40°C to +85°C 24 Ceramic SB

MAX235MDG -55°C to +125°C 24 Ceramic SB

MAX236CNG 0°C to +70°C 24 Narrow Plastic DIP

MAX236CWG 0°C to +70°C 24 Wide SO

MAX236C/D 0°C to +70°C Dice*

MAX236ENG -40°C to +85°C 24 Narrow Plastic DIP

MAX236EWG -40°C to +85°C 24 Wide SO

MAX236ERG -40°C to +85°C 24 Narrow CERDIP

MAX236MRG -55°C to +125°C 24 Narrow CERDIP

MAX237CNG 0°C to +70°C 24 Narrow Plastic DIP

MAX237CWG 0°C to +70°C 24 Wide SO

MAX237C/D 0°C to +70°C Dice*

MAX237ENG -40°C to +85°C 24 Narrow Plastic DIP

MAX237EWG -40°C to +85°C 24 Wide SO

MAX237ERG -40°C to +85°C 24 Narrow CERDIP

MAX237MRG -55°C to +125°C 24 Narrow CERDIP

MAX238CNG 0°C to +70°C 24 Narrow Plastic DIP

MAX238CWG 0°C to +70°C 24 Wide SO

MAX238C/D 0°C to +70°C Dice*

MAX238ENG -40°C to +85°C 24 Narrow Plastic DIP

* Contact factory for dice specifications.

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers___________________________________________Ordering Information (continued)

* Contact factory for dice specifications.

18 CERDIP-55°C to +125°CMAX242MJN

18 CERDIP-40°C to +85°CMAX242EJN

18 Wide SO-40°C to +85°CMAX242EWN

18 Plastic DIP-40°C to +85°CMAX242EPN

Dice*0°C to +70°CMAX242C/D

18 Wide SO0°C to +70°CMAX242CWN

18 Plastic DIP0°C to +70°CMAX242CPN

20 SSOP0°C to +70°CMAX242CAP

28 Wide SO-40°C to +85°CMAX241EWI

28 SSOP-40°C to +85°CMAX241EAI

Dice*0°C to +70°CMAX241C/D

28 Wide SO0°C to +70°CMAX241CWI

28 SSOP0°C to +70°CMAX241CAI

Dice*0°C to +70°CMAX240C/D

44 Plastic FP0°C to +70°CMAX240CMH

24 Narrow CERDIP-55°C to +125°CMAX239MRG

24 Narrow CERDIP-40°C to +85°CMAX239ERG

24 Wide SO-40°C to +85°CMAX239EWG

24 Narrow Plastic DIP-40°C to +85°CMAX239ENG

Dice*0°C to +70°CMAX239C/D

24 Wide SO0°C to +70°CMAX239CWG

24 Narrow Plastic DIP0°C to +70°CMAX239CNG

24 Narrow CERDIP-55°C to +125°C

24 Wide SO

PIN-PACKAGETEMP RANGE

-40°C to +85°C

MAX238MRG

24 Narrow CERDIP-40°C to +85°CMAX238ERG

MAX238EWG

PART PIN-PACKAGETEMP RANGEPART

44 PLCC-40°C to +85°CMAX249EQH

44 PLCC0°C to +70°CMAX249CQH

44 PLCC-40°C to +85°CMAX248EQH

Dice*0°C to +70°CMAX248C/D

44 PLCC0°C to +70°CMAX248CQH

40 Plastic DIP-40°C to +85°CMAX247EPL

Dice*0°C to +70°CMAX247C/D

40 Plastic DIP0°C to +70°CMAX247CPL

40 Plastic DIP-40°C to +85°CMAX246EPL

Dice*0°C to +70°CMAX246C/D

40 Plastic DIP0°C to +70°CMAX246CPL

40 Plastic DIP-40°C to +85°CMAX245EPL

Dice*0°C to +70°CMAX245C/D

40 Plastic DIP0°C to +70°CMAX245CPL

44 PLCC-40°C to +85°CMAX244EQH

Dice*0°C to +70°CMAX244C/D

44 PLCC0°C to +70°CMAX244CQH

16 CERDIP-55°C to +125°CMAX243MJE

16 CERDIP-40°C to +85°CMAX243EJE

16 Wide SO-40°C to +85°CMAX243EWE

16 Narrow SO-40°C to +85°CMAX243ESE

16 Plastic DIP-40°C to +85°CMAX243EPE

Dice*0°C to +70°CMAX243C/D

16 Wide SO0°C to +70°C

16 Plastic DIP0°C to +70°C

MAX243CWE

16 Narrow SO0°C to +70°CMAX243CSE

MAX243CPE

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

Package InformationFor the latest package outline information, go towww.maxim-ic.com/packages.

Revision HistoryPages changed at Rev 15: 2–5, 8, 9, 36

PRODUCT SPECIFICATION

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 1 of 41 December 2005

FEATURES

APPLICATIONS

• True single chip GFSK transceiver in a small 32-pin package (32L QFN 5x5mm)

• ShockBurst™ mode for low power operation • Power supply range 1.9 to 3.6 V • Multi channel operation – ETSI/FCC

Compatible • Channel switching time <650µs • Extremely low cost Bill of Material (BOM) • No external SAW filter • Adjustable output power up to 10dBm • Carrier detect for "listen before transmit"

protocols • Data Ready signal when a valid data packet

is received or transmitted • Address Match for detection of incoming

packet • Automatic retransmission of data packet • Automatic CRC and preamble generation • Low supply current (TX), typical 9mA @ -10dBm output power

• Low supply current (RX), typical 12.5mA

• Wireless data communication • Alarm and security systems • Home Automation • Remote control • Surveillance • Automotive • Telemetry • Industrial sensors • Keyless entry • Toys

GENERAL DESCRIPTION nRF905 is a single-chip radio transceiver for the 433/868/915 MHz ISM band. The transceiver consists of a fully integrated frequency synthesiser, receiver chain with demodulator, a power amplifier, a crystal oscillator and a modulator. The ShockBurstTM feature automatically handles preamble and CRC. Configuration is easily programmable by use of the SPI interface. Current consumption is very low, in transmit only 9mA at an output power of -10dBm, and in receive mode 12.5mA. Built in power down modes makes power saving easily realizable.

QUICK REFERENCE DATA

Parameter Value Unit Minimum supply voltage 1.9 V Maximum transmit output power 10 dBm Data rate 50 kbps Supply current in transmit @ -10dBm output power 9 mA Supply current in receive mode 12.5 mA Temperature range -40 to +85 °C Typical Sensitivity -100 dBm Supply current in power down mode 2.5 µΑ

Table 1 nRF905 quick reference data.

Single chip 433/868/915 MHz Transceiver nRF905

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 2 of 41 December 2005

ORDERING INFORMATION

Type Number Description Version nRF905 IC 32L QFN 5x5mm - nRF905-EVKIT 433 Evaluation kit 433MHz 1.0 nRF905-EVKIT 868/915 Evaluation kit 868/915MHz 1.0

Table 2 nRF905 ordering information.

BLOCK DIAGRAM

SPI interface

ShockBurst

Demod

Dataslicer

Address decode

CRC code/decode

GFSKfilter

RX - reg.Config-reg.

TX - reg.TX - addr.

PA

LNA

IF B

BF

FrequencySynthesiser

Voltage regulators

Crystal oscillator

MOSI (11)

MISO (10)

SCK (12)

CSN (13)

TRX_CE (1)

PWR_UP (2)

TX_EN (32)

CD (6)

AM (7)

DR (8)

uPCLK (3)

XC1 (14)

XC2 (15)

ANT1 (20)

ANT2 (21)

VDD_PA (19)

VS

S (5)

VS

S (16)

VS

S (18)

VS

S (22)

VS

S (24)

VS

S (27)

VS

S (28)

VS

S (29)

VS

S (30)

VD

D (4)

VD

D (17)

VD

D (25)

DV

DD

_1V2 (31)

IREF (23)

Manchesterencoder/decoder

VS

S (26)

VS

S (9)

Figure 1 nRF905 with external components.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 3 of 41 December 2005

TABLE OF CONTENTS

1 Pin Functions..................................................................................................................... 4 2 Pin Assignment ................................................................................................................. 5 3 Electrical Specifications.................................................................................................... 6 4 Current Consumption........................................................................................................ 8 5 Modes of Operation .......................................................................................................... 9

5.1 Active Modes ........................................................................................................... 9 5.2 Power Saving Modes................................................................................................ 9 5.3 nRF ShockBurst™ Mode ......................................................................................... 9 5.4 Typical ShockBurstTM TX...................................................................................... 10 5.5 Typical ShockBurstTM RX...................................................................................... 12 5.6 Power Down Mode................................................................................................. 14 5.7 Standby Mode......................................................................................................... 14

6 Device Configuration...................................................................................................... 15 6.1 SPI Register Configuration .................................................................................... 15 6.2 SPI Instruction Set.................................................................................................. 16 6.3 SPI Timing ............................................................................................................. 17 6.4 RF – Configuration Register Description............................................................... 19 6.5 Register Contents ................................................................................................... 20

7 Important Timing Data.................................................................................................... 21 7.1 Device Switching Times ........................................................................................ 21 7.2 ShockBurstTM TX timing........................................................................................ 21 7.3 ShockBurstTM RX timing........................................................................................ 22 7.4 Preamble................................................................................................................. 22 7.5 Time On Air ........................................................................................................... 23

8 Peripheral RF Information .............................................................................................. 24 8.1 Crystal Specification .............................................................................................. 24 8.2 External Clock Reference....................................................................................... 24 8.3 Microprocessor Output Clock ................................................................................ 24 8.4 Antenna Output ...................................................................................................... 25 8.5 Output Power Adjustment ...................................................................................... 25 8.6 Modulation ............................................................................................................. 25 8.7 Output Frequency................................................................................................... 26 8.8 PCB Layout and Decoupling Guidelines ............................................................... 27

9 nRF905 features .............................................................................................................. 28 9.1 Carrier Detect. ........................................................................................................ 28 9.2 Address Match........................................................................................................ 28 9.3 Data Ready ............................................................................................................. 28 9.4 Auto Retransmit ..................................................................................................... 29 9.5 RX Reduced Power Mode...................................................................................... 29

10 Package Outline .......................................................................................................... 30 10.1 Package marking .................................................................................................... 31

11 Application Examples................................................................................................. 32 11.1 Differential Connection to a Loop Antenna ........................................................... 32 11.2 PCB Layout Example; Differential Connection to a Loop Antenna ...................... 33 11.3 Single ended connection to 50Ω antenna ............................................................... 34 11.4 PCB Layout Example; Single Ended Connection to 50Ω Antenna ....................... 36

12 Absolute Maximum Ratings ....................................................................................... 37 13 Glossary of Terms....................................................................................................... 38 14 Definitions .................................................................................................................. 39

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 4 of 41 December 2005

1 PIN FUNCTIONS

Pin Name Pin function Description 1 TRX_CE Digital input Enables chip for receive and transmit 2 PWR_UP Digital input Power up chip 3 uPCLK Clock output Output clock, divided crystal oscillator full-swing clock 4 VDD Power Power supply (+3V DC) 5 VSS Power Ground (0V) 6 CD Digital output Carrier Detect 7 AM Digital output Address Match 8 DR Digital output Receive and transmit Data Ready 9 VSS Power Ground (0V) 10 MISO SPI - interface SPI output 11 MOSI SPI - interface SPI input 12 SCK SPI - Clock SPI clock 13 CSN SPI - enable SPI enable, active low 14 XC1 Analog Input Crystal pin 1/ External clock reference pin 15 XC2 Analog Output Crystal pin 2 16 VSS Power Ground (0V) 17 VDD Power Power supply (+3V DC) 18 VSS Power Ground 19 VDD_PA Power output Positive supply (1.8V) to nRF905 power amplifier 20 ANT1 RF Antenna interface 1 21 ANT2 RF Antenna interface 2 22 VSS Power Ground (0V) 23 IREF Analog Input Reference current 24 VSS Power Ground (0V) 25 VDD Power Power supply (+3V DC) 26 VSS Power Ground (0V) 27 VSS Power Ground (0V) 28 VSS Power Ground (0V) 29 VSS Power Ground (0V) 30 VSS Power Ground (0V) 31 DVDD_1V2 Power Low voltage positive digital supply output for de-coupling 32 TX_EN Digital input TX_EN=”1”TX mode, TX_EN=”0”RX mode

Table 3 nRF905 pin function.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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2 PIN ASSIGNMENT

nRF905

32L QFN 5x5

MOSI

VSS

CD

DVDD_1V2

AM

XC2 VSS

DR

VSS

ANT2

VDD_PA

VSS

ANT1

VSS

VSS VDD

VSS

TRX_CE

XC1

4

3

2

1

6

5

7

8

9 13 1412 1510 11 16

24

23

22

20

19

21

18

17

29 28 2730 26 253132

VDD

VSSTX_EN

IREF

VSS VSS VSS

MISO

PWR_UP

uPCLK

VDD

CSNSCK Figure 2 nRF905 pin assignment (top view) for a 32L QFN 5x5 package.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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3 ELECTRICAL SPECIFICATIONS Conditions: VDD = +3V VSS = 0V, TEMP = -40ºC to +85ºC (typical +27ºC)

Symbol Parameter (condition) Notes Min. Typ. Max. Units Operating conditions

VDD Supply voltage 1.9 3.6 V TEMP Operating temperature -40 85 ºC

Digital input/output VIH HIGH level input voltage 0.7·VDD VDD V VIL LOW level input voltage VSS 0.3·VDD V Ci Pin capacitance 5 pF IiL Pin leakage current 1) ±10 nA

VOH HIGH level output voltage (IOH=-0.5mA) VDD-0.3 VDD V VOL LOW level output voltage (IOL=0.5mA) VSS 0.3 V

General electrical specification Istby_eclk Supply current in standby, uCLK enabled 2) 100 µA Istby_dclk Supply current in standby, uCLK disabled 3) 12.5 µA

IPD Supply current in power down mode 4) 2.5 µA ISPI Supply current in SPI programming 5) 20 µA

General RF conditions fOP Operating frequency 6) 430 928 MHz

fXTAL Crystal frequency 7) 4 20 MHz ∆f Frequency deviation ±42 ±50 ±58 kHz BR Data rate 8) 50 kbps

fCH433 Channel spacing for 433MHz band 100 kHz fCH868/915 Channel spacing for 868/915MHz band 200 kHz

Transmitter operation PRF10 Output power 10dBm setting 9) 7 10 11 dBm PRF6 Output power 6dBm setting 9) 3 6 9 dBm PRF-2 Output power –2dBm setting 9) -6 -2 2 dBm PRF-10 Output power -10dBm setting 9) -14 -10 -6 dBm

PBW_-16 -16dBc bandwidth for modulated carrier 8) 173 kHz PBW_-24 -24dBc bandwidth for modulated carrier 8) 222 kHz PBW_-32 -32dBc bandwidth for modulated carrier 8) 238 kHz PBW_-36 -36dBc bandwidth for modulated carrier 8) 313 kHz

PRF1 1st adjacent channel transmit power 10) -27 dBc PRF2 2nd adjacent channel transmit power 10) -54 dBc

ITX10dBm Supply current @ 10dBm output power 30 mA ITX-10dBm Supply current @ -10dBm output power 9 mA

Receiver operation IRX Supply current in receive mode 12.5 mA

RXSENS Sensitivity at 0.1%BER -100 dBm RXMAX Maximum received signal 0 dBm C/ICO C/I Co-channel 11) 13 dB C/I1ST 1st adjacent channel selectivity C/I 200kHz 11) -7 dB C/I2ND 2nd adjacent channel selectivity C/I 400kHz 11) -16 dB C/I+1M Blocking at +1MHz 11) -40 dB C/I-1M Blocking at -1MHz 11) -50 dB C/I-2M Blocking at -2MHz 11) -63 dB C/I+5M Blocking at +5MHz 11) -70 dB C/I-5M Blocking at -5MHz 11) -65 dB C/I+10M Blocking at +10MHz 11) -69 dB C/I-10M Blocking at -10MHz 11) -67 dB C/IIM Image rejection 11) -36 dB

Table 4 nRF905 electrical specifications.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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1) Max value determined by design and characterization testing. 2) Output frequency is 4MHz load of external clock pin is 5pF, Crystal is 4MHz. 3) Crystal is 4MHz. 4) Pin voltages are VSS or VDD. 5) Chip in power down, SPI_SCK frequency is 1MHz. 6) Operates in the 433, 868 and 915 MHz ISM band. 7) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) 8) Data is Manchester-encoded before GFSK modulation. 9) Optimum load impedance, please see peripheral RF information. 10) Channel width and channel spacing is 200kHz. 11) Channel Level +3dB over sensitivity, interfering signal a standard CW, image lies 2MHz above wanted.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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4 CURRENT CONSUMPTION

MODE CRYSTAL FREQ. [MHZ]

OUTPUT CLOCK

FREQ. [MHZ]

TYPICAL CURRENT

Power Down 16 OFF 2.5 uA Standby 4 OFF 12 uA Standby 8 OFF 25 uA Standby 12 OFF 27 uA Standby 16 OFF 32 uA Standby 20 OFF 46 uA Standby 4 0.5 110 uA Standby 8 0.5 125 uA Standby 12 0.5 130 uA Standby 16 0.5 135 uA Standby 20 0.5 150 uA Standby 4 1 130 uA Standby 8 1 145 uA Standby 12 1 150 uA Standby 16 1 155 uA Standby 20 1 170 uA Standby 4 2 170 uA Standby 8 2 185 uA Standby 12 2 190 uA Standby 16 2 195 uA Standby 20 2 210 uA Standby 4 4 260 uA Standby 8 4 275 uA Standby 12 4 280 uA Standby 16 4 285 uA Standby 20 4 300 uA Rx @ 433 16 OFF 12.2 mA Rx @ 868/915 16 OFF 12.8 mA Reduced Rx 16 OFF 10.5 mA Tx @ 10dBm 16 OFF 30 mA Tx @ 6dBm 16 OFF 20 mA Tx @ -2dBm 16 OFF 14 mA Tx @ -10dBm 16 OFF 9 mA

Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load capacitance of external clock = 13pF, Crystal load capacitance = 12pF

Table 5 nRF905 current consumption.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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5 MODES OF OPERATION The nRF905 has two active (RX/TX) modes and two power-saving modes

5.1 Active Modes

• ShockBurst™ RX • ShockBurst™ TX

5.2 Power Saving Modes

• Power down and SPI - programming • Standby and SPI - programming

The nRF905 mode is decided by the settings of TRX_CE, TX_EN and PWR_UP.

PWR_UP TRX_CE TX_EN Operating Mode 0 X X Power down and SPI – programming 1 0 X Standby and SPI – programming 1 X 0 Read data from RX register 1 1 0 Radio Enabled - ShockBurstTM RX 1 1 1 Radio Enabled - ShockBurstTM TX

Table 6 nRF905 operational modes.

5.3 nRF ShockBurst™ Mode The nRF905 uses the Nordic Semiconductor ASA ShockBurst™ feature. ShockBurstTM makes it possible to use the high data rate offered by the nRF905 without the need of a costly, high-speed micro controller (MCU) for data processing/clock recovery. By placing all high speed signal processing related to RF protocol on-chip, the nRF905 offers the application micro controller a simple SPI interface, the data rate is decided by the interface-speed the micro controller itself sets up. By allowing the digital part of the application to run at low speed, while maximizing the data rate on the RF link, the nRF905 ShockBurst™ mode reduces the average current consumption in applications. In ShockBurstTM RX, Address Match (AM) and Data Ready (DR) notifies the MCU when a valid address and payload is received respectively. In ShockBurstTM TX, the nRF905 automatically generates preamble and CRC. Data Ready (DR) notifies the MCU that the transmission is completed. All together, this means reduced memory demand in the MCU resulting in a low cost MCU, as well as reduced software development time.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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5.4 Typical ShockBurstTM TX 1. When the application MCU has data for a remote node, the address of the

receiving node (TX-address) and payload data (TX-payload) are clocked into nRF905 via the SPI interface. The application protocol or MCU sets the speed of the interface.

2. MCU sets TRX_CE and TX_EN high, this activates a nRF905 ShockBurst™ transmission.

3. nRF905 ShockBurst™: • Radio is automatically powered up. • Data packet is completed (preamble added, CRC calculated). • Data packet is transmitted (100kbps, GFSK, Manchester-encoded). • Data Ready is set high when transmission is completed.

4. If AUTO_RETRAN is set high, the nRF905 continuously retransmits the packet until TRX_CE is set low.

5. When TRX_CE is set low, the nRF905 finishes transmitting the outgoing packet and then sets itself into standby mode.

If TX_EN is set low while TRX_CE is kept high, the nRF905 finishes transmitting the outgoing packet and then enter RX-mode in the channel already programmed in the RF-CONFIG register. The ShockBurstTM mode ensures that a transmitted packet that has started always finishes regardless of what TRX_EN and TX_EN is set to during transmission. The new mode is activated when the transmission is completed. Please see subsequent chapters for detailed timing For test purposes such as antenna tuning and measuring output power it is possible to set the transmitter so that a constant carrier is produced. To do this TRX_CE must be maintained high instead of being pulsed. In addition Auto Retransmit should be switched off. After the burst of data has been sent then the device will continue to send the unmodulated carrier.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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SPI - programming

uController loading ADDRand PAYLOAD data

(Configuration register if changes since last TX/RX)

NO

YES

nRF ShockBurst TX

Generate CRC and preambleSending package

DR is set high when completed

Transmitter is powered up

TRX_CE= HI ?

AUTO_RETRAN

= HI ?

YES

NO

YES

NO

ADDR PAYLOAD

Data Package

Bit in configuration register

TRX_CE= HI ?

Radio in Standby

TX_EN = HIPWR_UP = HITRX_CE = LO

ADDR PAYLOAD CRCPre-

amble

DR is set low

after pre-amble

Figure 3 Flowchart ShockBurstTM transmit of nRF905.

NB: DR is set low under the following conditions after it has been set high:

• If TX_EN is set low • If PWR_UP is set low

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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5.5 Typical ShockBurstTM RX 1. ShockBurstTM RX is selected by setting TRX_CE high and TX_EN low. 2. After 650µs nRF905 is monitoring the air for incoming communication. 3. When the nRF905 senses a carrier at the receiving frequency, Carrier

Detect (CD) pin is set high. 4. When a valid address is received, Address Match (AM) pin is set high. 5. When a valid packet has been received (correct CRC found), nRF905

removes the preamble, address and CRC bits, and the Data Ready (DR) pin is set high.

6. MCU sets the TRX_CE low to enter standby mode (low current mode). 7. MCU can clock out the payload data at a suitable rate via the SPI interface. 8. When all payload data is retrieved, nRF905 sets Data Ready (DR) and

Address Match (AM) low again. 9. The chip is now ready for entering ShockBurstTM RX, ShockBurstTM TX or

power down mode. If TX_EN is set high while TRX_CE is kept high, the nRF905 would enter ShockBurstTMTX and start a transmission according to the present contents in the SPI-registers. If TRX_CE or TX_EN is changed during an incoming packet, the nRF905 changes mode immediately and the packet is lost. However, if the MCU is sensing the Address Match (AM) pin, it knows when the chip is receiving an incoming packet and can therefore decide whether to wait for the Data Ready (DR) signal or enter a different mode. To avoid spurious address matches it is recommended that the address length be 24 bits or higher in length. Small addresses such as 8 or 16 bits can often lead to statistical failures due to the address being repeated as part of the data packet. This can be avoided by using a longer address. Each byte within the address should be unique. Repeating bytes within the address reduces the effectiveness of the address and increases its susceptibility to noise hence increasing the packet error rate. The address should also have several level shifts (i.e. 10101100) to reduce the statistical effect of noise and hence reduce the packet error rate.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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Figure 4 Flowchart ShockBurstTM receive of nRF905.

NO

YES

Receiver ispowered up

NO

YES

Receivingdata

ReceiverSensing for incomming data

CD is set high if carrier

AM is sethigh

NO

DR high isset high

Radio entersSTBY

MCU clocks out payload viathe SPI interface

DR and AM are set low

YES

YES

NOAM is set low

Radio in StandbyTX_EN = LO

PWR_UP = HI

TRX_CE= HI ?

CorrectADDR?

CorrectCRC?

TRX_CE = HI ?

PAYLOAD

Data Package

ADDR PAYLOAD CRCPre-

amble

RX RemainsOn

MCU clocks out payload viathe SPI interface

DR and AM are set low

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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5.6 Power Down Mode In power down the nRF905 is disabled with minimal current consumption, typically less than 2.5µA. When entering this mode the device is not active which will minimize average current consumption and maximizing battery lifetime. The configuration word content is maintained during power down.

5.7 Standby Mode Standby mode is used to minimize average current consumption while maintaining short start up times to ShockBurstTM RX and ShockBurstTM TX. In this mode part of the crystal oscillator is active. Current consumption is dependent on crystal frequency, Ex: IDD= 12µA @4MHz and IDD =46µA @20MHz. If the uP-clock (pin 3) of nRF905 is enabled, current consumption increases and is dependent on the load capacitance and frequency. The configuration word content is maintained during standby.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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6 DEVICE CONFIGURATION All configuration of the nRF905 is via the SPI interface. The interface consists of five registers; a SPI instruction set is used to decide which operation shall be performed. The SPI interface can be activated in any mode however Nordic Semiconductor ASA recommends the chip be in standby or power down mode.

6.1 SPI Register Configuration The SPI interface consists of five internal registers. A register read-back mode is implemented to allow verification of the register contents.

TX-PAYLOAD

EN

DTA

CLK

I/O-regCSN

MOSI

MISO

SCK

RF - CONFIGURATION REGISTER

EN

DTA

CLK

TX-ADDRESS

EN

DTA

CLK

RX-PAYLOAD

EN

DTA

CLK

STATUS-REGISTER

EN

DTA

CLK

Figure 5 SPI – interface and the five internal registers.

Status – Register

Register contains status of Data Ready (DR) and Address Match (AM).

RF – Configuration Register

Register contains transceiver setup information such as frequency and output power ext.

TX – Address

Register contains address of target device. How many bytes used is set in the configuration register.

TX – Payload

Register containing the payload information to be sent in a ShockBurst TM packet. How many bytes used is set in the configuration register.

RX – Payload

Register containing the payload information derived from a received valid ShockBurst TM packet. How many bytes used is set in the configuration register. Valid data in the RX-Payload register is indicated with a high Date Ready (DR) signal.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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6.2 SPI Instruction Set The available commands to be used on the SPI interface is shown below. Whenever CSN is set low the interface expects an instruction. Every new instruction must be started by a high to low transition on CSN.

Instruction set for the nRF905 SPI Serial Interface Instruction Name Instruction

Format Operation

W_CONFIG (WC)

0000 AAAA Write Configuration-register. AAAA indicates which byte the write operation is to be started from. Number of bytes depends on start address AAAA.

R_CONFIG (RC)

0001 AAAA Read Configuration-register. AAAA indicates which byte the read operation is to be started from. Number of bytes depends on start address AAAA.

W_TX_PAYLOAD (WTP)

0010 0000 Write TX-payload: 1 – 32 bytes. A write operation will always start at byte 0.

R_TX_PAYLOAD (RTP)

0010 0001 Read TX-payload: 1 – 32 bytes. A read operation will always start at byte 0.

W_TX_ADDRESS (WTA)

0010 0010 Write TX-address: 1 – 4 bytes. A write operation will always start at byte 0.

R_TX_ADDRESS (RTA)

0010 0011 Read TX-address: 1 – 4 bytes. A read operation will always start at byte 0

R_RX_PAYLOAD (RRP)

0010 0100 Read RX-payload: 1 – 32 bytes. A read operation will always start at byte 0.

CHANNEL_CONFIG (CC)

1000 pphc cccc cccc

Special command for fast setting of CH_NO, HFREQ_PLL and PA_PWR in the CONFIGURATION REGISTER. CH_NO= ccccccccc, HFREQ_PLL = h PA_PWR = pp

STATUS REGISTER N.A. The content of the status-register (S[7:0]) will always be read to MISO after a high to low transition on CSN as shown in Figure 6 and 7.

Table 7 Instruction set for the nRF905 SPI interface.

A read or a write operation may operate on a single byte or on a set of succeeding bytes from a given start address defined by the instruction. When accessing succeeding bytes one will read or write MSB of the byte with the smallest byte number first.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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6.3 SPI Timing The interface supports SPI mode 0. SPI operation and timing is given in Figure 6 to Figure 8 and in Table 8. The device must be in one of the power saving modes for the configuration registers to be read or written to.

C7 C6 C5 C4 C3 C2 C1 C0

S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8

CSN

SCK

MOSI

MISO

Figure 6 SPI read operation.

C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8

S7 S6 S5 S4 S3 S2 S1 S0

CSN

SCK

MOSI

MISO

Figure 7 SPI write operation.

C7 C6 C0

S7 S0

TcdzTcdTcsd

TdhTdc

TcchTclTclTchTcc Tch

TcwhTcwhCSN

SCK

MOSI

MISO

Figure 8 SPI NOP timing diagram.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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PARAMETER SYMBOL MIN MAX UNITS Data to SCK Setup Tdc 5 ns SCK to Data Hold Tdh 5 ns CSN to Data Valid Tcsd 45 ns SCK to Data Valid Tcd 45 ns SCK Low Time Tcl 40 ns SCK High Time Tch 40 ns SCK Frequency Tsck DC 10 MHz SCK Rise and Fall Tr,Tf 100 ns CSN to SCK Setup Tcc 5 ns SCK to CSN Hold Tcch 5 ns CSN Inactive time Tcwh 500 ns CSN to Output High Z Tcdz 45 ns

Table 8 SPI timing parameters (Cload = 10pF).

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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6.4 RF – Configuration Register Description Parameter Bitwidth Description

CH_NO 9 Sets center freq. together with HFREQ_PLL (default = 001101100b = 108d). fRF = ( 422.4 + CH_NOd /10)*(1+HFREQ_PLLd) MHz

HFREQ_ PLL

1 Sets PLL in 433 or 868/915 MHz mode (default = 0). '0' – Chip operating in 433MHz band '1' – Chip operating in 868 or 915 MHz band

PA_PWR 2 Output power (default = 00). '00' -10dBm '01' -2dBm '10' +6dBm '11' +10dBm

RX_RED_ PWR

1 Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default = 0). '0' – Normal operation '1' – Reduced power

AUTO_ RETRAN

1 Retransmit contents in TX register if TRX_CE and TXEN are high (default = 0). '0' – No retransmission '1' – Retransmission of data packet

RX_AFW 3 RX-address width (default = 100). '001' – 1 byte RX address field width '100' – 4 byte RX address field width

TX_AFW 3 TX-address width (default = 100). '001' – 1 byte TX address field width '100' – 4 byte TX address field width

RX_PW 6 RX-payload width (default = 100000). '000001' – 1 byte RX payload field width '000010' – 2 byte RX payload field width . '100000' – 32 byte RX payload field width

TX_PW 6 TX-payload width (default = 100000). '000001' – 1 byte TX payload field width '000010' – 2 byte TX payload field width . '100000' – 32 byte TX payload field width

RX_ ADDRESS

32 RX address identity. Used bytes depend on RX_AFW (default = E7E7E7E7h).

UP_CLK_ FREQ

2 Output clock frequency (default = 11). '00' – 4MHz '01' – 2MHz '10' – 1MHz '11' – 500kHz

UP_CLK_ EN

1 Output clock enable (default = 1). '0' – No external clock signal available '1' – External clock signal enabled

XOF 3 Crystal oscillator frequency. Must be set according to external crystal resonant-frequency (default = 100). '000' – 4MHz '001' – 8MHz '010' – 12MHz '011' – 16MHz '100' – 20MHz

CRC_EN 1 CRC – check enable (default = 1). '0' – Disable '1' – Enable

CRC_ MODE

1 CRC – mode (default = 1). '0' – 8 CRC check bit '1' – 16 CRC check bit

Table 9 Configuration-register description.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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6.5 Register Contents

RF-CONFIG_REGISTER (R/W) Byte # Content bit[7:0], MSB = bit[7] Init value

0 CH_NO[7:0] 0110_1100

1 bit[7:6] not used, AUTO_RETRAN, RX_RED_PWR, PA_PWR[1:0], HFREQ_PLL, CH_NO[8]

0000_0000

2 bit[7] not used, TX_AFW[2:0] , bit[3] not used, RX_AFW[2:0] 0100_0100

3 bit[7:6] not used, RX_PW[5:0] 0010_0000

4 bit[7:6] not used, TX_PW[5:0] 0010_0000

5 RX_ADDRESS (device identity) byte 0 E7

6 RX_ADDRESS (device identity) byte 1 E7

7 RX_ADDRESS (device identity) byte 2 E7

8 RX_ADDRESS (device identity) byte 3 E7

9 CRC_MODE,CRC_EN, XOF[2:0], UP_CLK_EN, UP_CLK_FREQ[1:0] 1110_0111

TX_PAYLOAD (R/W)

Byte # Content bit[7:0], MSB = bit[7] Init value 0 TX_PAYLOAD[7:0] X

1 TX_PAYLOAD[15:8] X

- - X

- - X

30 TX_PAYLOAD[247:240] X

31 TX_PAYLOAD[255:248] X

TX_ADDRESS (R/W)

Byte # Content bit[7:0], MSB = bit[7] Init value 0 TX_ADDRESS[7:0] E7

1 TX_ADDRESS[15:8] E7

2 TX_ADDRESS[23:16] E7

3 TX_ADDRESS[31:24] E7

RX_PAYLOAD (R)

Byte # Content bit[7:0], MSB = bit[7] Init value 0 RX_PAYLOAD[7:0] X

1 RX_PAYLOAD[15:8] X

- X

- X

30 RX_PAYLOAD[247:240] X

31 RX_PAYLOAD[255:248] X

STATUS_REGISTER (R)

Byte # Content bit[7:0], MSB = bit[7] Init value 0 AM, bit [6] not used, DR, bit [0:4] not used X

Table 10 RF register contents.

The length of all registers is fixed. However, the bytes in TX_PAYLOAD, RX_PAYLOAD, TX_ADDRESS and RX_ADDRESS used in ShockBurst TM RX/TX are set in the configuration register. Register content is not lost when the device enters one of the power saving modes.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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7 IMPORTANT TIMING DATA The following timing must be obeyed during nRF905 operation.

7.1 Device Switching Times

nRF905 timing Max. PWR_DWN ST_BY mode 3 ms

STBY TX ShockBurst™ 650 µs STBY RX ShockBurst™ 650 µs RX ShockBurst™ TX ShockBurst™ 550 1µs TX ShockBurst™ RX ShockBurst™ 550 1µs

Notes to table: 1) RX to TX or TX to RX switching is available without re-programming of the RF

configuration register. The same frequency channel is maintained.

Table 11 Switching times for nRF905.

7.2 ShockBurstTM TX timing

M O S I

C S N

P W R _ U P

T X _ E N

T R X _ C E

T X D A T A

T IM E

T 0 = R a d io E n a b le dT 1 = T 0 + 1 0 u S M in im u m T R X _ C E p u ls eT 2 = T 0 + 6 5 0 u S .S ta r t o f T X D a ta t ra n s m is s io nT 3 = E n d o f D a ta P a c k e t , e n te r S ta n d b y m o d e

P ro g r a m m in g o f C o n f ig u r a t io n R e g is te r a n d T X D a ta R e g is te r

T 0 T 1 T 2 T 3T ra n s m it te d D a ta 1 0 0 k b p s M a n c h e s te r E n c o d e d

Figure 9 Timing diagram for standby to transmit.

After a data packet has finished transmitting the device will automatically enter Standby mode and wait for the next pulse of TRX_CE. If the Auto Re-Transmit function is enabled the data packet will continue re-sending the same data packet until TRX_CE is set low.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 22 of 41 December 2005

7.3 ShockBurstTM RX timing P W R _ U P

T X _ E N

T R X _ C E

R X D A T A

T IM E

A M

D R

C D

T 0 = R e c e iv e r E n a b le d - L is t e n in g f o r D a taT 1 = C a r r ie r D e te c t f in d s a c a r r ie rT 2 = A M - C o r r e c t A d d r e s s F o u n dT 3 = D R - D a ta p a c k e t w i t h c o r r e c t A d d r e s s / C R C

6 5 0 u S t o e n te r R X m o d e f r o m T R X _ C E b e in g s e t h ig h .

T 0 T 1 T 2 T 3

6 5 0 u S

Figure 10 Timing diagram for standby to receiving.

After the Data Ready (DR) has been set high a valid data packet is available in the RX data register. This may be clocked out in RX mode or standby mode. After the data has been clocked out via the SPI interface the Data Ready (DR) and Address Match (AM) pins are reset to low. The RX register is reset if the PWR_UP pin is taken low or if the device is switched into TX mode i.e. TXEN is taken high. This will also results in the Data Ready(DR) and Address Match (AM) pins being reset to low.

7.4 Preamble In each data-packet transmitted by the nRF905 a preamble is added automatically. The preamble is a predefined bit-sequence used to adjust the receiver for optimal performance. A ten-bit sequence is used as preamble in nRF905. The length of the preamble, tpreamble, is then 200µs.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 23 of 41 December 2005

7.5 Time On Air The time-on-air is the sum of the radio start-up time and the data-packet length. The length of the preamble, address field, payload and CRC-checksum give the data-packet length while the radio start-up time is given in Table 11. While preamble length and start-up time are fixed the user sets the other parameters in the RF-configuration register. The below equation shows how to calculate TOA

BR

NNNttTOA

CRCpayloadaddresspreamblestartup

++++=

tstartup and tpreamble are RF-start-up time and preamble time respectively. Naddress, Npayload and NCRC are numbers of bits in the address, payload and CRC-checksum while BR is the bitrate, which is equal to 50kbps.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 24 of 41 December 2005

8 PERIPHERAL RF INFORMATION

8.1 Crystal Specification Tolerance includes initially accuracy and tolerance over temperature and aging.

Frequency CL ESR C0max Tolerance @ 868/915 MHz

Tolerance @ 433 MHz

4MHz 8pF – 16pF 150Ω 7.0pF ±30ppm ±60ppm 8MHz 8pF – 16pF 100Ω 7.0pF ±30ppm ±60ppm

12MHz 8pF – 16pF 100Ω 7.0pF ±30ppm ±60ppm 16MHz 8pF – 16pF 100Ω 7.0pF ±30ppm ±60ppm 20MHz 8pF – 16pF 100Ω 7.0pF ±30ppm ±60ppm

Table 12 Crystal specification of nRF905.

To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying a lower value of crystal parallel equivalent capacitance, Co=1.5pF is also good, but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal specified for Co_max=7.0pF. The crystal load capacitance, CL, is given by:

2222111121

21 '',''

''IPCBIPCBL CCCCandCCCCwhere

CC

CCC ++=++=

+⋅

=

C1 and C2 are 0603 SMD capacitors as shown in the application schematics. CPCB1 and CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pin respectively; the value is typical 1pF.

8.2 External Clock Reference An external reference clock, such as a MCU clock, may be used instead of a crystal. The clock signal should be applied directly to the XC1 pin, the XC2 pin can be left high impedance. When operating with an external clock instead of a crystal the clock must be applied in standby mode to achieve low current consumption. If the device is set into standby mode with no external clock or crystal then the current consumption will increase up to a maximum of 1mA.

8.3 Microprocessor Output Clock By default a microprocessor clock output is provided. Providing an output clock will increase the current consumption in standby mode. The current consumption in standby will depend on frequency and load of external crystal, frequency of output clock and capacitive load of the provided output clock. Typical current consumption values are found in Table 5.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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8.4 Antenna Output The “ANT1 & ANT2” output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD_PA, either via a RF choke or via the center point in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in the range 200-700Ω. The optimum differential load impedance at the antenna ports is given as: 900MHz 225Ω+j210 430MHz 300Ω+j100 A low load impedance (for instance 50Ω) can be obtained by fitting a simple matching network or a RF transformer (balun). Further information regarding balun structures and matching networks may be found in the Application Examples chapter.

8.5 Output Power Adjustment The power amplifier in nRF905 can be programmed to four different output power settings by the configuration register. By reducing output power, the total TX current is reduced.

Power setting RF output power DC current consumption

00 -10 dBm 9.0 mA 01 -2 dBm 14.0 mA 10 6 dBm 20.0 mA 11 10 dBm 30.0 mA

Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 400 Ω.

Table 13 RF output power setting for the nRF905.

8.6 Modulation The modulation of nRF905 is Gaussian Frequency Shift Keying (GFSK) with a data-rate of 100kbps. Deviation is ±50kHz. GFSK modulation results in a more bandwidth effective transmission-link compared with ordinary FSK modulation. The data is internally Manchester encoded (TX) and Manchester decoded (RX). That is, the effective symbol-rate of the link is 50kbps. By using internally Manchester encoding, no scrambling in the microcontroller is needed.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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8.7 Output Frequency The operating RF-frequency of nRF905 is set in the configuration register by CH_NO and HFREQ_PLL. The operating frequency is given by:

MHzPLLHFREQNOCHfOP )_1())10/_(4.422( +⋅+=

When HFREQ_PLL is ‘0’ the frequency resolution is 100kHz and when it is ‘1’ the resolution is 200kHz. The application operating frequency has to be chosen to apply with the Short Range Devise regulation in the area of operation.

Operating frequency HFREQ_PLL CH_NO 430.0 MHz [0] [001001100] 433.1 MHz [0] [001101011] 433.2 MHz [0] [001101100] 434.7 MHz [0] [001111011]

862.0 MHz [1] [001010110] 868.2 MHz [1] [001110101] 868.4 MHz [1] [001110110] 869.8 MHz [1] [001111101]

902.2 MHz [1] [100011111] 902.4 MHz [1] [100100000] 927.8 MHz [1] [110011111]

Table 14 Examples of real operating frequencies.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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8.8 PCB Layout and Decoupling Guidelines nRF905 is an extremely robust RF device due to internal voltage regulators and requires the minimum of RF layout protocols. However the following design rules should still be incorporated into the layout design. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The nRF905 DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. It is preferable to mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel with the smaller value capacitors. The nRF905 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the nRF905 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to place via holes as close as possible to the VSS pins. A minimum of one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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9 nRF905 FEATURES

9.1 Carrier Detect. When the nRF905 is in ShockBurst TM RX, the Carrier Detect (CD) pin is set high if a RF carrier is present at the channel the device is programmed to. This feature is very effective to avoid collision of packets from different transmitters operating at the same frequency. Whenever a device is ready to transmit it could first be set into receive mode and sense whether or not the wanted channel is available for outgoing data. This forms a very simple listen before transmit protocol. Operating Carrier Detect (CD) with Reduced RX Power mode is an extremely power efficient RF system. Typical Carrier Detect level (CD) is typically 5dB lower than sensitivity, i.e. if sensitivity is –100dBm then the Carrier Detect function will sense a carrier wave as low as –105dBm. Below –105dBm the Carrier Detect signal will be low, i.e. 0V. Above –95dBm the Carrier Detect signal will be high, i.e. Vdd. Between approximately -95 to -105 the Carrier Detect Signal will toggle.

9.2 Address Match When the nRF905 is in ShockBurst TM RX mode, the Address Match (AM) pin is set high as soon as an incoming packet with an address that is identical with the device’s own identity is received. With the Address Match pin the controller is alerted that the nRF905 is receiving data actually before the Data Ready (DR) signal is set high. If the Data Ready (DR) pin is not set high i.e. the CRC is incorrect then the Address Match (AM) pin is reset to low at the end of the received data packet. This function can be very useful for an MCU. If Address Match (AM) is high then the MCU can make a decision to wait and see if Data Ready (DR) will be set high indicating a valid data packet has been received or ignore that a possible packet is being received and switch modes.

9.3 Data Ready The Data Ready (DR) signal makes it possible to largely reduce the complexity of the MCU software program. In ShockBurst TM TX, the Data Ready (DR) signal is set high when a complete packet is transmitted, telling the MCU that the nRF905 is ready for new actions. It is reset to low at the start of a new packet transmission or when switched to a different mode i.e. receive mode or standby mode. In ShockBurst TM TX Auto Retransmit the Data Ready (DR) signal is set high at the beginning of the pre-amble and is set low at the end of the preamble. The Data Ready (DR) signal therefore pulses at the beginning of each transmitted data packet. In ShockBurst TM RX, the signal is set high when nRF905 has received a valid packet, i.e. a valid address, packet length and correct CRC. The MCU can then retrieve the payload via the SPI interface. The Data Ready (DR) pin is reset to low once the data has been clocked out of the data buffer or the device is switched to transmit mode.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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9.4 Auto Retransmit One way to increase system reliability in a noisy environment or in a system without collision control is to transmit a packet several times. This is easily accomplished with the Auto Retransmit feature in nRF905. By setting the AUTO_RETRAN bit to “1” in the configuration register, the circuit keeps sending the same data packet as long as TRX_CE and TX_EN are high. As soon as TRX_CE is set low the device will finish sending the packet it is currently transmitting and then return to standby mode.

9.5 RX Reduced Power Mode To maximize battery lifetime in application where the nRF905 high sensitivity is not necessary; nRF905 offers a built in reduced power mode. In this mode, the receive current consumption reduces from 12.5mA to only 10.5mA. The sensitivity is reduced to typical –85dBm, ±10dB. Some degradation of the nRF905 blocking performance should be expected in this mode. The reduced power mode is an excellent option when using Carrier Detect to sense if the wanted channel is available for outgoing data.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

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10 PACKAGE OUTLINE nRF905 uses the QFN 32L 5x5 green package with a mat tin finish. Dimensions are in mm. Recommended soldering reflow profile can be found in application note nAN400-08, QFN soldering reflow guidelines, www.nordicsemi.no.

+

Package Type A A1 A2 b D E e J K L QFN32

(5x5 mm) Min typ. Max

0.8

0.9

0.0

0.05

0.65

0.69

0.18 0.23 0.3

5 BSC

5 BSC

0.5 BSC

3.2 3.3 3.4

3.2 3.3 3.4

0.3 0.4 0.5

Figure 11 nRF905 package outline.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 31 of 41 December 2005

10.1 Package marking

Figure 12 nRF905 package marking layout

Abbreviations: DDDDDD – Product number, e.g. 905 B Build Code, i.e. unique code for silicon revision, production site,

package type and test platform X – "X" grade, i.e. Engineering Samples (optional) YY – 2 digit Year number WW – 2 digit Week number LL – 2 letter wafer lot number code

n R F B X D D D D D D Y Y W W L L

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 32 of 41 December 2005

11 APPLICATION EXAMPLES

11.1 Differential Connection to a Loop Antenna

C222pF0603

C64.7nF0603

C533pF0603

R222K0603

C710nF0603

VDD

C122pF0603

R1

1M

X1

16 MHz

TRX_CE1 VSS 24

VSS 18

VDD 17

VSS

16

PWR_UP2

uPCLK3

VDD4

VSS5

CD6

AM7

DR8

VSS

9

MIS

O10

MO

SI11

SCK

12

XC

215

XC

114

CSN

13

VDD_PA 19ANT1 20ANT2 21VSS 22IREF 23nRF905

VD

D25

VSS

26V

SS27

VSS

28V

SS29

VSS

30D

VD

D_1

V2

31TX

EN32

U1nRF905

VDD

C43.3nF0603

C833pF0603

VDD

TXENTRX_CEPWR_UP

CDAMDR

SPI_MISOSPI_MOSISPI_SCKSPI_CSN

uPCLK

C3180pF

C106.8pF

C114.7pF

aaaaaaaa

J1Loop Antenna, 433MHz35x20mm

C93.9pF

aaaaaaaa

aaaaaaaa

aaaa

aaaa

C1227pF

C1327pF

Figure 13 nRF905 Application schematic, differential connection to a loop antenna (433MHz).

Component Description Size Value Tol. Units

C1 NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 ±5% pF C2 NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 ±5% pF C3 NP0 ceramic chip capacitor, (PA supply decoupling) 0603 180 ±5% pF C4 X7R ceramic chip capacitor, (PA supply decoupling) 0603 3.3 ±10% nF C5 NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 ±5% pF C6 X7R ceramic chip capacitor, (Supply decoupling) 0603 4.7 ±10% nF C7 X7R ceramic chip capacitor, (Supply decoupling) 0603 10 ±10% nF C8 NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 ±5% pF C9 NP0 ceramic chip capacitor, (Antenna tuning) 0603 3.9 ±0.1 pF

C10 NP0 ceramic chip capacitor, (Antenna tuning) 0603 6.8 ±0.1 pF C11 NP0 ceramic chip capacitor, (Antenna tuning) 0603 4.7 ±0.1 pF C12 NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 ±5% pF C13 NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 ±5% pF R1 0.1W chip resistor, (Crystal oscillator bias) 0603 1 ±5% MΩ R2 0.1W chip resistor, (Reference bias) 0603 22 ±1% kΩ U1 nRF905 Transceiver QFN32L/5x5 X1 Crystal, CL = 12pF LxWxH =

4.0x2.5x0.8 16 ±60ppm MHz

Table 15 Recommended external components, differential connection to a loop antenna (433MHz).

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 33 of 41 December 2005

11.2 PCB Layout Example; Differential Connection to a Loop Antenna

Figure 14 shows a PCB layout example for the application schematic in Figure 13. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. There is no ground plane beneath the antenna.

a) Top silk screen

No components in bottom layer

b) Bottom silk screen

c) Top view

d) Bottom view

Figure 14 PCB layout example for nRF905, differential connection to a loop antenna.

A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 34 of 41 December 2005

11.3 Single ended connection to 50ΩΩΩΩ antenna

C222pF

C64.7nF

C533pF

R222K

C710nF

VDD

C122pF

R1

1M

X1

16 MHz

TRX_CE1 VSS 24

VSS18

VDD17

VSS

16

PWR_UP2

uPCLK3

VDD4

VSS5

CD6

AM7

DR8

VSS

9

MIS

O1

0

MO

SI

11

SCK

12

XC

21

5X

C1

14

CS

N1

3

VDD_PA19ANT120ANT221

VSS 22IREF 23nRF905

VD

D2

5V

SS

26

VS

S2

7V

SS

28

VS

S2

9V

SS

30

DV

DD

_1V

23

1T

XE

N3

2

U1nRF905

VDD

L1

C3

C11Optional

C12

L3

L2

C9

C10

C43.3nF

C833pF

VDD

C13Optional

C3

C9

C10

C11

C12

C13

L1

L2

L3

868/915MHz 433MHz

33pF, ±5%

3.9pF, ±0.25pF

3.9pF, ±0.25pF

Optional Optional

2.2pF, ±5%

Optional

12nH, 5%

18nH, 5%

18nH, 5%

180pF, ±5%

18pF, ±5%

18pF, ±5%

6.8pF, ±5%

Optional

12nH, 5%

39nH, 5%

39nH, 5%

50 ohm RF I/OTXEN

TRX_CEPWR_UP

CDAMDR

SPI_MISOSPI_MOSISPI_SCKSPI_CSN

uPCLK

aaaaaaaa

aaaaaaaa

aaaaaaaa

aaaa

aaaa

Figure 15 nRF905 Application schematic, single ended connection to 50Ω antenna by using a differential to single ended matching network.

It is recommended to add pull up or pull down resistors on signals that can enter a floating state. For the nRF905 it is recommended to have pull up on the CSN signal and pull down on the MOSI and SCK signal.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 35 of 41 December 2005

Component Description Size Value Tol. Units

C1 NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 ±5% pF C2 NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 ±5% pF C3 NP0 ceramic chip capacitor, (PA supply decoupling)

@ 433MHz @ 868MHz @ 915MHz

0603

180 33 33

±5% pF

C4 X7R ceramic chip capacitor, (PA supply decoupling) 0603 3.3 ±10% nF C5 NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 ±5% pF C6 X7R ceramic chip capacitor, (Supply decoupling) 0603 4.7 ±10% nF C7 X7R ceramic chip capacitor, (Supply decoupling) 0603 10 ±10% nF C8 NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 ±5% pF C9 NP0 ceramic chip capacitor, (Impedance matching)

@ 433MHz @ 868MHz @ 915MHz

0603 18 3.9 3.9

±5%

<±0.25pF <±0.25pF

pF

C10 NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz

0603 18 3.9 3.9

±5%

<±0.25pF <±0.25pF

pF

C11 NP0 ceramic chip capacitor, (Impedance matching) 0603 Not fitted pF C12 NP0 ceramic chip capacitor, (Impedance matching)

@ 433MHz @ 868MHz @ 915MHz

0603 6.8 2.2 2.2

±5% ±5% ±5%

pF

C13 NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz

0603 Not fitted Not fitted Not fitted

pF

L1 Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz

0603

12 12 12

±5% nH

L2 Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz

0603

39 18 18

±5% ±5% ±5%

nH

L3 Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz

0603

39 12 12

±5% ±5% ±5%

nH

R1 0.1W chip resistor, (Crystal oscillator bias) 0603 1 ±5% MΩ R2 0.1W chip resistor, (Reference bias) 0603 22 ±1% kΩ U1 nRF905 Transceiver QFN32L/5x5 X1 Crystal, CL = 12pF LxWxH =

4.0x2.5x0.8 16 ±30ppm MHz

Table 16 Recommended external components, single ended connection to 50Ω antenna.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 36 of 41 December 2005

11.4 PCB Layout Example; Single Ended Connection to 50ΩΩΩΩ Antenna

Figure 16 shows a PCB layout example for the application schematic in Figure 15. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane.

a) Top silk screen

No components in bottom layer

b) Bottom silk screen

c) Top view

d) Bottom view

Figure 16 PCB layout example for nRF905, single ended connection to 50Ω antenna by using a differential to single ended matching network.

A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 37 of 41 December 2005

12 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD.............................. - 0.3V to + 3.6V VSS .....................................................0V Input Voltage VI..........................- 0.3V to VDD + 0.3V Output Voltage VO.........................- 0.3V to VDD + 0.3V

Total Power Dissipation PD (TA=85°C) ................................ 200mW Temperatures Operating temperature ........................................... - 40°C to + 85°C Storage temperature .............................................. - 40°C to + 125°C Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device.

ATTENTION! Electrostatic sensitive device. Observe precaution for handling.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 38 of 41 December 2005

13 GLOSSARY OF TERMS

Term Description ADC Analog to Digital Converter AM Address Match CD Carrier Detect CLK Clock CRC Cyclic Redundancy Check DR Data Ready GFSK Gaussian Frequency Shift Keying ISM Industrial-Scientific-Medical kSPS kilo Samples per Second MCU Micro Controller Unit PWR_DWN Power Down PWR_UP Power Up RX Receive SPI Serial Programmable Interface CSN SPI Chip Select Not MISO SPI Master In Slave Out MOSI SPI Master Out Slave In SCK SPI Serial Clock SPS Samples per Second STBY Standby TRX_EN Transmit/Receive Enable TX Transmit TX_EN Transmit Enable

Table 17 Glossary of terms.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 39 of 41 December 2005

14 DEFINITIONS Product Specification Identification Product Status Definition Objective Product Specification Planned or Under Development. This specification contains

the design objectives for product development. nRF: Specifications may change in any manner without notice.

Preliminary Product Specification Engineering Samples and Pre Production series. This specification contains preliminary data. nRF: Nordic Semiconductor reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Product Specification The product is qualified for production. Changes will be notified according to industry standard criteria for Product/Process Change Notifications.

Obsolete Product Specification Not In Production. This specification contains specifications on a product that has been discontinued by Nordic Semiconductor. The specification is printed for reference information only.

Table 18 Product status definitions

Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Product specification revision date: 06.12.2005 Datasheet order code: 061205nRF905 All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 40 of 41 December 2005

YOUR NOTES

PRODUCT SPECIFICATION nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989 Revision: 1.3 Page 41 of 41 December 2005

Nordic Semiconductor ASA – World Wide Distributors

For Your nearest dealer, please see http://www.nordicsemi.no

Main Office: Vestre Rosten 81, N-7075 Tiller, Norway

Phone: +47 72 89 89 00, Fax: +47 72 89 89 89

Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no

Appendix C

Source Code

delay.h 10/07/2006

/*

delay.h

*/

#ifndef __DELAY_H#define __DELAY_H

//20MHz#define dly200n asm("nop")#define dly400n dly200n;dly200n

#define WaitFor1Us dly200n; dly200n; dly200n; dly200n; dly200n#define Jumpback asm("goto $ - 2")

#define dly1u dly200n; dly200n; dly200n; dly200n#define dly2u dly1u; dly1u

void DelayUs(unsigned char x);

void DelayMs(unsigned char cnt);

#endif

1

delay.c 30/07/2006

/****************************************************************************** File: delay.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provide the functions to perform delays between 0 - 255 us, and 0 - 255 ms for a PIC 16f877A u controller with a

20 MHz crystal. ******************************************************************************/

#ifndef __DELAY_C#define __DELAY_C

#include <pic.h>#include "delay.h"

unsigned char delayus_variable;

/* * Function: DelayUs * Input: 8-bit value which defines the delay time (0 - 255 us) * Output: None * * Description: Will delay execution of further instructions (except Interrupts) * for a length of 0 - 255 us defined by x */void DelayUs(unsigned char x)

delayus_variable=x;WaitFor1Us;asm("decfsz _delayus_variable,f");Jumpback;

/* * Function: DelayMs * Input: 8-bit value which defines the delay time (0 - 255 ms) * Output: None * * Description: Will delay execution of further instructions (except Interrupts) * for a length of 0 - 255 ms defined by x */void DelayMs(unsigned char cnt)

unsigned char i;do

i = 4;do

DelayUs(250);DelayUs(57); // fine tuning

while(--i); while(--cnt);

#endif

1

mainRx.c 30/07/2006

/****************************************************************************** File: main.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program runs on th PIC 16f877A uController for use with an nRF24L01 tranceiver Module configured as a receiver. Information is accepted in a 30-byte array and each byte is output to a PC via the UART in 0.5 ms intervals. ******************************************************************************/

#include <pic.h>#include "Rx24L01.h"#include "C:\ekg\includes\delay.h"#include "C:\ekg\includes\uart.h"#include "C:\ekg\includes\spi.h"

void main(void)

spiConfig(); // configure 16f877A SPISetupComPort(); // configure 16f877A UARTconfigure16f877_for_24L01(); // configure 16f877A I/Oconfigure_Rx24L01(); // configure nRF24L01 receiver

TRISB1 = 0;RB1 = 0;

while(1) while(IRQ); // wait for next received data packetRx24L01(); // receive the next data packet and output to PC

1

mainTx.c 30/07/2006

/****************************************************************************** File: main.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This Program performs an A/D conversion on three input channels into the PIC 16f877A uController in regular 0.5ms intervals and saves the data in an 30-byte array. Once the array is full. The information is sent to an nRF24L01 tranceiver via the SPI interface on the PIC. ******************************************************************************/

#include <pic.h>#include "C:\ekg\includes\delay.h"#include "C:\ekg\includes\uart.h"#include "C:\ekg\includes\spi.h"#include "Tx24L01.h"

#define CHAN1 1#define CHAN2 2#define CHAN3 3

void ekgTxInit(void);char getData(char);void convertByteToBits(char);

main()

char leads[30], dataToSend[30];int i, j = 0;

ekgTxInit();SetupComPort();configure16f877_for_24L01();configure_Tx24L01();

PORTD = 0x00;

while(1)

// obtain 10 bytes of data from each of the A/D input channelsfor (i = 0; i < 30;)

leads[i++] = getData(CHAN1); // lead I dataleads[i++] = getData(CHAN2); // lead II dataleads[i++] = getData(CHAN3); // lead III data

// delay 0.5 ms until next conversion.if (i != 30)

DelayUs(250);DelayUs(250);

// transmit data through nRF24L01Tx24L01(leads);

// wait until transmission completewhile (IRQ);

/* * Function: ekgTxInit * Input: None

1

mainTx.c 30/07/2006

* Output: None * * Description: Configure the PIC A/D for three input channels. * RA0 = Lead I, RA1 = Lead II, RA5 = Lead III * RA2 = reference voltage - 0V * RA3 = reference voltage - 5V */void ekgTxInit(void)

TRISD = 0x00; // output A/D resultTRISA0 = 1; // A/D channel 0TRISA1 = 1; // A/D channel 1TRISA2 = 1; // Vref-TRISA3 = 1; // Vref+TRISA5 = 1; // A/D channel 2

ADCON0 = 0x81; // set Fosc/32 and channel 0 (RA0)ADCON1 = 0x09; // RA0 = Analogue input, Vref+/Vref- = VDD/VSS;

/* * Function: getData * Input: channel - chooses which channel to perform the A/D conversion * Output: Result of A/D conversion. Stored in an 8-bit char * * Description: Performs the A/D conversion on a single channel defined by * "channel" input and obtains the lower 8 bits of the 10 bit * result. */char getData(char channel)

// select channelswitch(channel)

case CHAN1: ADCON0 = 0x81; break;case CHAN2: ADCON0 = 0x89; break;case CHAN3: ADCON0 = 0xA1; break;default: break;

// begin conversionDelayUs(50);ADGO = 1;while(ADGO);return ADRESH;

/* * Function: convertByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */void convertByteToBits(char byte_value)

char tmp;char i;

// parse the byte bit-by-bit and send the appropriate '0' or '1' to UARTfor (i = 128; i > 0;)

tmp = byte_value & i;if (tmp == 0) uartTx('0');else uartTx('1');i >>= 1;

2

mainTx.c 30/07/2006

uartTx(32);NEW_LINE; // move cursor to next line

3

Rx24L01.c 30/07/2006

/****************************************************************************** File: Rx24L01.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provides the functions necessary to interface with the Nordic Semiconductor nRF24L01 Transceiver modules. The is configured as a receiver with a 5-byte datapipe address, datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst. ******************************************************************************/

#include <pic.h>#include "Rx24L01.h"#include "C:\ekg\includes\uart.h"#include "C:\ekg\includes\delay.h"#include "C:\ekg\includes\spi.h"

void byteToBits(char);

/* * Function: configure16f877_for_24L01 * Input: None * Output: None * * Description: Configures the PIC 16f877A uController to interface with the * transceiver through the SPI. */void configure16f877_for_24L01(void)

spiConfig();TRISB5 = 1; // IRQ pinTRISC2 = 0; // CE pinTRISC1 = 0; // CSN pin

CE = 0;CSN = 1;

/* * Function: configure_Rx24L01 * Input: None * Output: None * * Description: Configures the nRF24L01 transceiver to perform as a receiver */void configure_Rx24L01(void)

wReg(0x00, 0x09); // set this device as PRXwReg(0x01, 0x3F); // enable auto acknowledge (Tx)wReg(0x02, 0x03); // enable auto acknowledge (Rx)wReg(0x03, 0x03); // set address width to 5 ByteswReg(0x04, 0x1F); // disable retransmitwReg(0x05, 0x02); // set channel 2 (default value)wReg(0x06, 0x0F); // set data rate = 2 Mbps

// set Rx (pipe 1) address to E7E7E7E7E7CSN = 0;spiTx(0x2A);spiTx(0xE7);spiTx(0xE7);spiTx(0xE7);spiTx(0xE7);spiTx(0xE7);CSN = 1;

1

Rx24L01.c 30/07/2006

DelayUs(10);

// set Rx (pipe 1) address to C2C2C2C2C2CSN = 0;spiTx(0x2B);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);CSN = 1;DelayUs(10);

wReg(0x11, 0x1E); // set # bytes in payload (pipe 0)wReg(0x12, 0x1E); // set # bytes in payload (pipe 1)wReg(0x00, 0x0B); // power up

CE = 1;

/* * Function: Rx24L01 * Input: None * Output: None * * Description: Receives a 30 byte array and sends the information through the * PIC UART for display on a PC in 0.5 ms intervals. */void Rx24L01(void)

int i, data[3];char status;

CE = 0; // Power down RF front endCSN = 0;status = spiTx(0x61); // receive payload

for (i = 0; i < 30;)

// LeadI datadata[i] = spiRx();uartTx(data[i++]);

// LeadII datadata[i] = spiRx();uartTx(data[i++]);

// LeadIII datadata[i] = spiRx();uartTx(data[i++]);

// delay 0.5 msif (i != 30)

DelayUs(250);DelayUs(250);

RB1 ^= 1;CSN = 1;DelayUs(10);

flushRx(); // flush Rx FIFOwReg(0x07, 0x7F); // clear previous interrupts

CE = 1; // power up RF front end

2

Rx24L01.c 30/07/2006

/* * Function: getStatus * Input: None * Output: Value of the nRF24L01 Staus register * * Description: Obtains the value of the nRF24L01 status register for debugging * purposes. */char getStatus(void)

char status;

CSN = 0;status = spiTx(0xFF);CSN = 1;DelayUs(10);

return status;

/* * Function: showStatus * Input: None * Output: Value of the nRF24L01 Status register * * Description: Obtains and displays Status register and sends the value to * the PIC 16f877A UART for display on PC */char showStatus(void)

char status;

CSN = 0;status = spiTx(0xFF);CSN = 1;DelayUs(10);byteToBits(status);return status;

/* * Function: wReg * Input: address - addr of nRF24L01 register, value - byte value to be written * register at "address" * Output: Value of Staus register * * Description: This function writes an 8-bit value to one of the configuration * registers of the nRF24L01. The contents of the "Status" register * is returned for debugging purposes. */char wReg(char address, char value)

char addr, status;

addr = address | 0x20;CSN = 0;status = spiTx(addr);spiTx(value);CSN = 1;DelayUs(10);

3

Rx24L01.c 30/07/2006

return status;

/* * Function: rReg * Input: address - addr of configuration register to be read * Output: Contents of the register being addressed. * * Description: This function reads the value of the configuration register * at "address" */char rReg(char address)

char reg_value;

CSN = 0;spiTx(address);reg_value = spiRx();CSN = 1;byteToBits(reg_value);DelayUs(10);return reg_value;

/* * Function: flushTx * Input: None * Output: None * * Description: Flushes the Transmit Stack of any values currently being stored */void flushTx(void)

// flush tx stackCSN = 0;spiTx(0xE1);CSN = 1;DelayUs(10);

/* * Function: flushRx * Input: None * Output: None * * Description: Flushes the Receive Stack of any values currently being stored */void flushRx(void)

// flush rx stackCSN = 0;spiTx(0xE2);CSN = 1;DelayUs(10);

/* * Function: readRegisters * Input: None * Output: None * * Description: Reads the values of the first seven configuration registers for * debugging purposes. */void readRegisters(void)

4

Rx24L01.c 30/07/2006

uartTx('R');NEW_LINE;

rReg(0x00);rReg(0x01);rReg(0x02);rReg(0x03);rReg(0x04);rReg(0x05);rReg(0x06);

/* * Function: ByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */void byteToBits(char byte_value)

char tmp;char i;

for (i = 128; i > 0;) tmp = byte_value & i;if (tmp == 0) uartTx('0');else uartTx('1');i >>= 1;

NEW_LINE;

5

Rx24L01.h 29/06/2006

#ifndef __RX24L01_H#define __RX24L01_H

#define CE RC2 // Chip Enable#define CSN RC1 // Chip Select NOT#define IRQ RB5 // Interrupt Request

#define COMMAND 1#define DATA 0

void configure16f877_for_24L01(void);void configure_Rx24L01(void);void Rx24L01(void);void byteToBits(char);void readRegisters(void);char getStatus(void);char showStatus(void);char wReg(char, char);char rReg(char);void flushTx(void);void flushRx(void);#endif

1

spi.c 30/07/2006

/****************************************************************************** File: spi.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This file rovides the functions necessary to use the PIC 16f877A SPI interface running on a 20MHz crystal oscillator. ******************************************************************************/

#include <pic.h>#include "spi.h"#include "delay.h"

/* * Function: spiConfig * Input: None * Output: None * * Description: Configures the 16f877 SPI */void spiConfig(void)

STAT_CKE = 1; // Data transmitted on rising edge of SCKSTAT_SMP = 0; // Input data sampled at middle of data outputtimeCKP = 0; // Idle state for clock is a low level

SSPEN = 1; // Enables serial port and configrues SCK, SDO,SDI, and SS as the source of the serial port pinsSSPM0 = 1; // SPI Master mode, clock = Fosc/16TRISC5 = 0; // SDOTRISC3 = 0; // SCK

/* * Function: spiTx * Input: 8-bit data value * Output: Value of the nRF24L01 Staus register * * Description: This function sends one byte of data to an nRF24L01 tranceiver * module through the SPI interface. The value of the Status * register is returned */char spiTx(char data)

char buf_value;

SSPBUF = data;while(!SSPIF);buf_value = SSPBUF;SSPIF = 0;

return buf_value;

/* * Function: spiRx * Input: None * Output: 8-bit value * * Description: Obtains one byte of data from the nRF24L01 tranceiver module */char spiRx(void)

1

spi.c 30/07/2006

char value;

TRISC5 = 1;value = spiTx(0x00);TRISC5 = 0;

return value;

2

spi.h 28/06/2006

#ifndef __SPI_H#define __SPI_H

void spiConfig(void);char spiTx(char);char spiRx(void);

#endif

1

Tx24L01.c 30/07/2006

/****************************************************************************** File: Tx24L01.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provides the functions necessary to interface with the Nordic Semiconductor nRF24L01 Transceiver modules. The is configured as a transmitter with a 5-byte datapipe address, datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst. ******************************************************************************/

#include <pic.h>#include "Tx24L01.h"#include "C:\ekg\includes\uart.h"#include "C:\ekg\includes\delay.h"#include "C:\ekg\includes\spi.h"

void byteToBits(char);

/* * Function: configure16f877_for_24L01 * Input: None * Output: None * * Description: Configures the PIC 16f877A uController to interface with the * transceiver through the SPI. */void configure16f877_for_24L01(void)

spiConfig(); // configure the SPI with clock = 20MHz / 16TRISB5 = 1; // IRQ pinTRISC2 = 0; // CE pinTRISC1 = 0; // CSN pin

CE = 0;CSN = 1;

// RB0 used for debuggingTRISB1 = 0;RB0 = 0;

/* * Function: configure_Tx24L01 * Input: None * Output: None * * Description: Configures the nRF24L01 transceiver to perform as a transmitter */void configure_Tx24L01(void)

CE = 0;CSN = 0;

wReg(0x00, 0x08); // set PTXwReg(0x01, 0x3F); // enable auto acknowledge (Tx)wReg(0x02, 0x03); // enable auto acknowledge (Rx)wReg(0x03, 0x03); // set address width to 5 ByteswReg(0x04, 0x1F); // four retransmit attemptswReg(0x05, 0x02); // set channel 2 (default value)wReg(0x06, 0x0F); // set data rate = 2 Mbps

// set Rx address to E7E7E7E7E7

1

Tx24L01.c 30/07/2006

CSN = 0;spiTx(0x2A);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);CSN = 1;DelayUs(50);

// set Tx address to E7E7E7E7E7CSN = 0;spiTx(0x30);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);spiTx(0xC2);CSN = 1;DelayUs(50);

/* * Function: Tx24L01 * Input: 30-byte array * Output: None * * Description: Transmits the input array */void Tx24L01(char leads[])

int i;

wReg(0x07, 0x7F); // clear previous interruptswReg(0x00, 0x0A); // power upflushTx();

// Transmit dataCSN = 0;

spiTx(0xA0);for(i = 0; i < 30; i++)

spiTx(leads[i]);

CSN = 1;DelayUs(10);

CE = 1;DelayUs(20);CE = 0;

/* * Function: showStatus * Input: None * Output: None * * Description: Sends the contents of the nRF24L01 status register through * the UART for display in Hyperterminal - Used for debugging */void showStatus(void)

char status;

CSN = 0;status = spiTx(0xFF);

2

Tx24L01.c 30/07/2006

CSN = 1;DelayUs(10);byteToBits(status);

/* * Function: wReg * Input: address - addr of nRF24L01 register, value - byte value to be written * register at "address" * Output: Value of Staus register * * Description: This function writes an 8-bit value to one of the configuration * registers of the nRF24L01. The contents of the "Status" register * is returned for debugging purposes. */char wReg(char address, char value)

char addr, status;

addr = address | 0x20;CSN = 0;status = spiTx(addr);spiTx(value);CSN = 1;DelayUs(10);

return status;

/* * Function: rReg * Input: address - addr of configuration register to be read * Output: Contents of the register being addressed. * * Description: This function reads the value of the configuration register * at "address" */char rReg(char address)

char reg_value;

CSN = 0;spiTx(address);reg_value = spiRx();CSN = 1;byteToBits(reg_value);DelayUs(10);return reg_value;

/* * Function: flushTx * Input: None * Output: None * * Description: Flushes the Transmit Stack of any values currently being stored */void flushTx(void)

// flush tx stackCSN = 0;spiTx(0xE1);CSN = 1;

3

Tx24L01.c 30/07/2006

DelayUs(10);

/* * Function: flushRx * Input: None * Output: None * * Description: Flushes the Receive Stack of any values currently being stored */void flushRx(void)

// flush rx stackCSN = 0;spiTx(0xE2);CSN = 1;DelayUs(10);

/* * Function: readRegisters * Input: None * Output: None * * Description: Reads the values of the first seven configuration registers for * debugging purposes. */void readRegisters(void)

uartTx('R');NEW_LINE;

rReg(0x00);rReg(0x01);rReg(0x02);rReg(0x03);rReg(0x04);rReg(0x05);rReg(0x06);

/* * Function: ByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */void byteToBits(char byte_value)

char tmp;char i;

for (i = 128; i > 0;) tmp = byte_value & i;if (tmp == 0) uartTx('0');else uartTx('1');i >>= 1;

NEW_LINE;

4

Tx24L01.h 29/06/2006

#ifndef __TX24L01_H#define __TX24L01_H

#define CE RC2 // Chip Enable#define CSN RC1 // Chip Select NOT#define IRQ RB5 // Interrupt Request

#define COMMAND 1#define DATA 0

void configure16f877_for_24L01(void);void configure_Tx24L01(void);void Tx24L01(char data[]);void readRegisters(void);void showStatus(void);char wReg(char, char);char rReg(char);void flushTx(void);void flushRx(void);

#endif

1

uart.c 30/07/2006

/****************************************************************************** File: uart.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This file provides the functions necessary to use the PIC 16f877A Universal Asynchronous Receiver Transmitter (UART) interface. ******************************************************************************/

#include <pic.h>#include "uart.h"

/* * Function: SetupComPort * Input: None * Output: None * * Description: Will setup COM port for 20Mhz clk with 115200 Baud */void SetupComPort(void)

char dummy;TRISC6 = 1;TRISC7 = 1;SPBRG = 10; // 115200 Baud

// SPBRG = (20000000/(16UL * 19200) -1); // 19200 Baud

BRGH = 1; // High data rate for sending

TX9 = 0; // 8-bit transmission

RX9 = 0; // 8-bit receptionSYNC = 0; // Asynchronous

SPEN = 1; // Enable serial port pins

RCIF = 0; // Clear the RCIF interrupt flag

CREN = 1; // Enable reception

TXEN = 1; // Enable the transmitter

dummy = RCREG; // Clear the RCREG

/* * Function: uartTx * Input: One byte value to transmit * Output: None * * Description: Will transmit a given character defined by txChar */void uartTx(char txChar)

while(!TXIF); // Wait while other transmission is overTXREG = txChar; // Place the given character in tx bufferResetRx(); // Clears Interrupt flags

/* * Function: uartRx * Input: None

1

uart.c 30/07/2006

* Output: One byte value received by UART * * Description: Receive a character from object interfaced to by UART */char uartRx(void)

char dummy = '\0';

if (RCIF) // If receive interrupt flag is set

dummy = RCREG; // Get the character stored in rx bufferResetRx(); // Clears the interrupt flagsResetTx(); // Clears the interrupt flags

return dummy;

/* * Function: uartTxLine * Input: String to be transmitted * Output: None * * Description: Sends a string of characters through the UART one byte at a time */void uartTxLine(char *line_out)

int i;while(line_out[i] != '\0') uartTx(line_out[i++]);

/* * Function: ResetTx * Input: None * Output: None * * Description: Resets the interrupt flags associated with the UART to prepare * for next transmission. */void ResetTx(void)

TXEN = 0;TXEN = 1;

/* * Function: ResetRx * Input: None * Output: None * * Description: Resets the interrupt flags associated with the UART to prepare * for next reception. */void ResetRx(void)

CREN = 0;CREN = 1;

2

uart.h 28/06/2006

#ifndef __UART_H#define __UART_H

#define NEW_LINE uartTx(10);uartTx(13)

void SetupComPort(void); // Setup for 19200 Baudvoid uartTxLine(char*); // Transmit a linevoid ResetTx(void); // Reset Transmittervoid ResetRx(void); // Reset Receiverchar uartRx(void); // Receieve a charvoid uartTx(char); // Transmit a char

#endif

1