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WLP Probing Technology Opportunity and Challenge Clark Liu
WLP Probing Technology Opportunity and Challenge
Clark Liu
PTI Group Overview Founded : May/15/97’
Capital : USD 246 Millions
Total Assets : USD 2.2B
Employees : 11,100 (Greatek included)
Major Services : Chip Probing, Bumping,
Packaging, Final Test & Module Assembly
IPO : 4/3/03’ in Taiwan
PTI HQ
Group Overview- Global Network
Payton in China
Suzhou Plant
15 min drive
BHuKou Industrial Park
Headquarter
Hsinpu Plant
4 hrs by air
ChinaHSIP Plant
Greatek Electronic
30 min
drive
Chung-Li Plant
Customer Success !!
Singapore Plant Southeast Asia
Xi’an Plant
Put more resource for next technology!
4Clark Liu
2012 SWTW ASE_SV 50um Pitch Array 2014 SWTW FFI 80um Pitch CPB
Probing at 2G Wide I/O Bump Pad
5Clark Liu
Source : 2011 IEEE _ Samsung
WLP(Wafer Level Packages)
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Source : 2013 SEMI _ Yole
Wafer-level-packages have emerged in many different varieties that can be categorized into different advanced packaging technology platforms
Map of WLP manufacturing companies
7Clark Liu
Source : 2015 Yole
7 Companies
27 Companies
7 Companies
WLP Key Connection Technology
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Wafer Level Package
Bump RDL TSV CPB
From Kid View!
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Wafer Level Package
Bump like
RDLlike
TSV like
CPB like
Electrical Tests for WLP Connectivity Fault Model
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Source : 2010 IEEE 3D IC Workshop _TSMC
Fault Model for different test items
11Clark LiuSource : 2010 IEEE 3D IC Workshop _TSMC
Supplier A or C
Supplier B or D
Supplier A
Supplier B
WLP Probing
WoW !
12Clark LiuSource : Taipei 101
13Clark Liu
Opportunity?Challenge?
Technology?
Cost? New Model?
Cooperation?
Source : NTHU
Case1: Tools Short Delivery Cycle Time?
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DesignType Out Wafer Process Wafer Test
4~10 Weeks
DesignType Out
WLP Process WLP Test
2~3 Weeks
MP card
MP card??
Early Plan??
Eng Card??
Gap
[Ex] WLCSP 256DUT Probe card
15Clark Liu
• Bump Type: WLCSP – a. Diameter: 300um– b. Height: 170um ± 10%.– c. Pitch: 500um– d. TD : 10– f. Total Pin Count 2560 Pins
Delivery Time 8 Weeks
Case2: Process Change for more Chip Probing?
16Clark Liu
Exist Process
Wafer Process
Wafer Test Assembly Finial Test
Process X Wafer Process
Wafer Test(KGD) WLP WLP Test
Process Y Wafer Process WLP WLP Test
(KGD)
Assembly
Assembly
More WLP Test or More Finial Test?
• WLP Test • Finial Test
17Clark Liu
Pictures Source : Mitsubishi
Pitch Limit
Clean/10K Cleanness
Package Base
Fine Pitch
Contact Force
Silicon Baseum mm
Wafer Test or Finial Test Vender @ WLP Testing?
• Wafer Test Vender
• Cycle Time Challenge• Cost Challenge• New Process Challenge
• Finial Test Vender
• Cooperation Model Challenge• Wafer Level Requirement and
Quality
18Clark Liu
Gap
<500 Mhz
<3G Mhz
>3G Mhz
Speed
WLCSP / WLCPB Probe Card
Source : SWTW
Bump Process & WLP Probing Roadmap
20Clark Liu
400um 200um 100um 80um 60um 40um 20um
Mature Production
Production / Pilot Run
R&D
Bum
p Pr
oces
sW
LP
Te
st
Mature Production
Gap
Ideal Probe Force v.s Over Drive @ WLP Probing
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Probe ForceDepend on
Material
Over Drive SlopeDepend on
Material
Electrical All Pass
Point
Low Force Keep No Damage
Case 3: Probe mark analysis Technology
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AOI Probe Mark Analysis Challenge
Bump RDL CPBD
iffer
ent
Laye
r
What Expect data from those Probe mark?
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AOI Probe mark Analysis
User ExpectData
Data Mining:
(1) ProberPerformance(2)Probe cardPerformance
[Keep Under Development]
Chip Design Wafer Process
Case 4: Business or Process Change?
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Chip Design Wafer Process
WLP Design
WLP Process
WL Test A.P Finial Test
WLP Test
Customer Foundry OSAT
Cost
Tech
Yield
Probe card Vender B
Same Issue but different site?
25Clark Liu
ATE Vender
ProberVender A
Probe card Vender A
Customer
Foundry COSAT C
Recipe
Cont act
Alignment
Foundry B OSAT B
Foundry AOSAT A
CooperationProber
Vender B
Gap
AOI Vender
Clean Vender
Conclusion
26Clark Liu
• Cooperation from Customer to Supplier (Design House /Foundry/OSAT/Vender).
• New opportunity for Wafer/Finial Test I/F vender.
• The Evolution Business Model will start change something.
