WLPS Prototype Development: Implementation of a Wireless Digital Transmitter at 2.4 GHz band J. Pourrostam Yinfei Fu. Jason Shim Nick Ware Department of Electrical and computer Engineering Michigan Technological University Summer 2005 Abstract: In this report we provide the results of the activities of WLPS prototype development during summer 2005. First we summarize the previous work done by WCE and IME (enterprise groups at Michigan Tech) then the summer activities is presented. The summer work can be divided into two main groups: DSP programming and hardware implementation. The summer group succeeded to build a digital transmitter which will be used at both TRX and DBS (essential units of WLPS). The activities of transmitter implementation are presented step by step in this communication. Some guidelines are given to improve the implemented structure.
Transcript
WLPS Prototype Development: Implementation of a Wireless Digital Transmitter at 2.4 GHz band
J. PourrostamYinfei Fu.Jason ShimNick Ware
Department of Electrical and computer EngineeringMichigan Technological University
Summer 2005
Abstract:
In this report we provide the results of the activities of WLPS prototype development during summer 2005. First we summarize the previous work done by WCE and IME (enterprise groups at Michigan Tech) then the summer activities is presented. The summer work can be divided into two main groups: DSP programming and hardware implementation. The summer group succeeded to build a digital transmitter which will be used at both TRX and DBS (essential units of WLPS). The activities of transmitter implementation are presented step by step in this communication. Some guidelines are given to improve the implemented structure.
1. IntroductionThe Wireless Local Positioning System (WLPS) is a National Science Foundation
funded project led by Dr. Reza Zekavat. The goal of the WLPS project is to develop a local positioning system for use in areas where Global Positioning Systems (GPS) are ineffective or cost restrictive. Dr. Zekavat has employed the summer team to continue where his prior teams left off and most importantly build the first working prototype.
GPS are used in a variety of applications today such as navigation, tracking, and command and control. However the GPS has a major limitation of requiring a clear, line of sight view to the network of satellites. This means that operation of the system in enclosed environments like buildings and mines is impractical.
The idea behind a local positioning system is to operate in an area where a GPS system would be impractical. Local positioning systems use two types of positioning, remote and self. Self-positioning deals with the objects orientation compared to a reference point or node. In remote positioning the system finds the relative location of one node by comparing the relative locations of others. In other words the nodes can only know where they are as long as other nodes exist.
The WLPS can be utilized in several applications such as homeland security, automotive collision detection and avoidance, robot operation and positioning, health care, and many others. The WLPS system includes two major parts the transponder unit (TRX) and the dynamic base station (DBS). The TRX is a simple system; its task is to listen for ID request signals and when one is heard to respond with its ID. The DBS is responsible for sending the ID request signals. Once a signal request is sent the DBS waits and listens for the incoming IDs. When an ID is received the time-of-arrival and direction-of-arrival are used to calculate distance and direction to the responding TRX.
Objects can be equipped with a TRX, DBS or both systems at the same time. This allows for DBS units to locate other DBS units. For example if a WLPS was implemented in an airport, passengers would be equipped with TRX units, while security guards would be equipped with both. This would allow for a security guard to locate himself in respect to a specific passenger or a specific security guard.
In the fourteen weeks the summer team was employed the goal was to take the already purchased hardware and create a single antenna prototype. This means the first prototype would only be able to detect distance and not direction (To detect the direction multiple antenna receiver at DBS is required). If this was completed the team was then to move on to designing the multiple antenna system which would allow for detecting both direction and distance. However at the end of summer duration the team succeeded to implement some part of this general structure (which is a digital transmitter). In this report the general structure of WLPS is presented, and then the implementation of its digital transmitter is explained step by step. At the end of the report the guidelines for transmitter improvement and receiver implementation are included.
2. System StructureThe Wireless Local Positioning System structure can be split in to two major sub-
systems, the Dynamic Base Station (DBS) and the Transponder unit (TRX). The TRX is the simpler of the two systems. The TRX units will sit waiting for an ID request from the DBS units. Once an ID request has been received and processed it sends out its ID for the DBS to hear. At DBS when ID is received, it estimates the time-of-arrival and the direction-of-arrival of received signal to calculate distance and direction to the responding TRX.
2.1. The Structure of TRX
Since the function of TRX is a simpler than DBS the sub-system structure is also simpler. Figure 1 is a block diagram of the TRX unit structure. As shown in this figure TRX has three main stages, the RF stage, the DAC/ADC stage, and the DSP. In the RF stage of the TRX you have the antennas for receiving and transmitting, the power amplifier for transmission, the band-pass filters for receiving and transmitting, and finally the transceiver itself. The transmission part of the RF stage is setup like most other radios, taking an input on a baseband frequency and generating a modulated carrier at radio frequency while filtering it of possible noise. The receiver portion is also setup like most other radios taking an input from an antenna, filtering out what noise it can then demodulating the radio frequency to baseband frequency. At receiver side the ADC takes demodulated baseband signal and runs it through an analog to digital conversion procedure to prepare the data for the Digital Signal Processor (DSP) to process. At transmission side the output of DSP (which is digital form of pulse shaped data) goes through a Digital to Analog Converter (DAC) to translate the digital voltages data to an analog waveform that can then be modulated and sent out as radio wave. Because the system is using a (Quadrature Phase Shift Keying) QPSK modulation the baseband signal includes I signal and a Q signal. The DSP section of the TRX is where all of the data processing is done. When the TRX receives an ID request, the data is sent to the DSP and is further filtered of noise and then processed to see if the correct code has been sent. Once it has been determined the correct code is sent the DSP sends the necessary data to the DAC and RF sections to send its ID code back to the requesting DBS.
2.2. The Structure of DBS
The DBS sub-system is more complicated. The DBS must be able to handle sending an omni-directional request signal and then receive multiple IDs while determining their distance and direction. This system can be split in three smaller sub-systems, the receive sub-system, the transmit sub-system and the processing sub-system. In the DBS the receive sub-system contains a 6 element phased-array antenna, 6 demodulators, and 6 ADCs. The transmit sub-system contains 1 omni-directional antenna, a modulator, and a digital to analog converter. In the processing sub-system, to achieve a fast processing time a Field Programmable Gate Array (FPGA) is employed to handle the data from all 6 receivers and the transmitter. The FPGA is tasked with determining signal time of arrival
and using that data to produce a distance. The DSP is tasked with estimating signal direction of arrival. This increases the efficiency of the overall system. Figure 2 is the block diagram of the DBS sub-system.
DSP
MAX1198
AD9765
MAX2247
8 Bit Bus for I
8 Bit Bus for Q
DCI Bandpass
DCI Bandpass
ADC
DAC
Digital I and Q
OutAnalog I
Analog Q
Analog I
Analog Q
HGV-2409-USimple High Gain Dipole
HGV-2409-USimple High Gain Dipole
Clock to ADC
Clock to DAC
Max2825
RX Section
TX Section
IQ
RX/TX Control
Reference Frequency
P.A.
Figure 1: TRX block diagram
FPGA
MAX1198 #1AD8347 #1
MAX1198 #6AD8347 #6
ADF4360-0
8 Bit Bus for I
8 Bit Bus for Q
DCI Bandpass #1
DCI Bandpass #6
Demodulator
Demodulator
ADC
ADCAnalog I
Analog Q
Analog I
Analog Q
Lo IN
Lo IN
Local Oscillator
Array Element 1
Array Element 6
8 B
it B
us fo
r I
8 B
it B
us fo
r Q
AD9761AD8346DCI
Bandpass modulator Analog I
Analog Q
Lo IN
HGV-2409-USimple High Gain Dipole
DAC
DSP
10 bit I and Q Bus
10 b
it I a
nd Q
Bus
16 Bit Data bus
Figure 2: DBS block diagram
2.3. Breaking the system down to a simpler starting point
According to the WLPS complexity it was decided that the multiple antenna system was too complicated to be implemented at once. So the multiple antenna system was broken down into a single antenna system. This means that instead of using the phased array of patch antennas for the receiver of the DBS would use a single dipole. Proving that if the DBS sent a request and the TRX received and replied to the request was the primary goal of this simplification. Once this system was operating correctly the multiple antennas and FPGA would be added back into the system. This would be a starting block for the construction of the more difficult multiple antenna system. The structure of the TRX doesn’t change, however the DBS structure is simplified to the block diagram shown in Figure3.
DSP
MAX1198AD8347
AD9761AD8346MAX2247
ADF4360-0
8 Bit Bus for I
8 Bit Bus for Q
DCI Bandpass
DCI Bandpass
Demodulator
Modulator
ADC
DAC
Digital I and Q
Out
Analog I
Analog Q
Analog I
Analog Q
Lo IN
Lo IN
Local Oscillator
HGV-2409-USimple High Gain Dipole
HGV-2409-USimple High Gain Dipole
Clock to ADC
Clock to DAC
Figure 3: Single antenna DBS block diagram
The overall structure of the receiver side of DBS hasn’t changed; there are just fewer parts. Instead of 6 antennas, 6 power amplifiers, 6 demodulators and 6 ADC’s there is only one. As you can see the largest change in the simplification is the subtraction of the FPGA. This was done to help simplify the system to a manageable starting point. After breaking the system down our activities aimed to implement the transmit part of TRX. It is clear that the same concepts and method should be taken into account at the transmit side of DBS. In next section all activities around the implementation of a digital transmitter is explained and illustrated.
3. Providing Required Blocks and Evaluation KitsBefore starting summer activities, two enterprise groups had started working on
WLPS implementation. They provided general structures of TRX and DBS (presented in previous section) and attempted to supply required hardware to implement these structures. Evaluation boards were chosen for the ease of implementation and
experimentation. Because of the high frequencies the project works at PCB design of this system is more complicated and time consuming. Also the electrical engineering department at Michigan Tech only has a system that can create a two layer PCB. This project would call for a 4-layer board minimum. Evaluation kits are designed to allow the user to test the functionality and specifications of the chip being evaluated without first having to design a whole system for this purpose. This allows for each part of the system to be tested independently and then integrated together. The details of selecting and purchasing required blocks are available in the reports from enterprise groups. Here we provide a summary of what they have purchased.
3.1. The TRXTRX unit includes:
3.1.1. Digital to Analog Converter the AD9765An Analog Devices AD9765 digital to analog converter was purchased for the TRX.
The AD9765 is a dual 12-bit DAC with a maximum sampling rate of a 125MSPS. The high rate of samples allows for a higher data rate. The high data rate and dual 12-bit inputs meet the needs of the high-speed end of the TRX. Dual channels are needed for producing I and Q signals required by the QPSK system. An evaluation board was purchased for $200.00.
3.1.2. Analog to Digital Converter the MAX1198A Maxim-Dallas MAX1198 was chosen for the analog to digital converter for both the
TRX and the DBS. The MAX1198 is a dual 8-bit ADC with a capability of running at maximum rate of 100MSPS. Again dual channels are needed for handling I and Q signals of the QPSK system. TRX system benefits from the smallest delay through the entire system as possible. Because of this the high sampling rate of the MAX1198 aids in bringing the data rate of the system up and brings the delay of the system down.
3.1.3. Transceiver the MAX2825/2827The Maxim-Dallas MAX282* series of transceivers was chosen because single chip
design. The MAX282* series can modulate and demodulate I and Q signals at 2.4GHz band. The chip came in a simple to use evaluation kit, which was one of the major deciding factors for its purchase. The MAX2825 chip is one of the two single band versions in the series. It allows for operation in the 802.11b standard of 2.4 to 2.5GHz. Testing of the original MAX2825 evaluation kit found that part of the board was malfunctioning after purchase. The board was sent back to the manufacturer for repair or replacement. The company was not able to get any more 2825 evaluation kits in a minimum of 14 weeks and instead opted to send us the MAX2827 evaluation kit instead. The MAX2827 operates the same way as the MAX2825 but it is a multi-band solution. The MAX2827 has a software configurable band select, allowing the user to change from 802.11b to 802.11a standards. This means the chip can transmit between 2.4 to 2.5GHz and also between 5.15 to 5.35GHz.
3.1.4. Power Amplifier the MAX2247
The Maxim-Dallas MAX2247 power amplifier was chosen because it was recommended in the data sheet of the MAX2825/2827 data sheet. The MAX2247 can amplify a 2.4 to 2.5GHz signal up to 24dB. The PA allows for a variable gain through bias circuitry provided on the evaluation kit. It also features a shutdown mode in which the power amplifier can be put into a power saving mode when not in use perfect for the TRX.
3.1.5. Band-pass filters A band-pass filter would be required on both transmit and receive antenna to help
eliminate noise. An Amplitronix ABDFF0123 RF band-pass filter was originally looked at for this project. This filter is in an ultra-small surface mount package, which would be needed for the final product but would have been impractical for the first prototype. Another limiting factor was cost. These filters cost $69 a piece and Amplitronix requires a minimum order of 25. This would mean a minimum of $1725 dollars would have to be spent to purchase this type of filter.
Digital Communications Inc. produces an affordable prototype option band-pass filter. However the large size of this filter could only be used for initial prototypes. The DCI band-pass filter was a simple pre-tuned passive filter. The pass band for the filter is 2.4 to 2.483GHz. At only $50 dollars each and no minimum order size made this the desirable filter for both DBS and TRX.
3.1.6. Single Antenna the HGV-2409UThe TRX requires omni-directional transmit and receive antennas. The HGV-2409U
from Hyper Gain was chosen because of its 360-degree horizontal coverage and its 15 degrees of vertical beam width. The antenna has a 9dBi gain and a low VSWR. The limiting factor of this antenna is its size. At 20 inches long the antenna is way too large to be used in a small transponder unit. It is suggested that by the end of the project that this antenna be replaced with a simple single patch antenna much like the ones that are hidden in today’s PCMCIA wireless adapters.
3.2. The DBSThe DBS system is more complicated then the TRX. The DBS needs to be able to
transmit an omni-directional ID request and then listen for replies from the TRXs and determine distance and direction via an array of antennas and a complicated processing method. The chosen blocks for DBS are:
3.2.1. Digital to Analog Converter the AD9761The Analog Devices AD9761 was chosen for the DBS because of its pair of 10-bit
40MSPS DACs with low distortion performance. These can be used to generate I and Q signals required by the system. The AD9761 also features an adjustable bias control, which affects the supply currents. By reducing supply currents we can increase efficiency of the system
3.2.2. Analog to Digital Converter the MAX1198
As with the TRX the Maxim-Dallas MAX1198 analog to digital converter was chosen. The dual 8-bit 100MSPS ADCs are perfect for changing I and Q signals into digital format for the FPGA and DSP.
3.2.3. TransceiverThe transceiver in the DBS is much different than the transceiver in the TRX. Because
of the antenna array used for determining direction of the incoming signal no single chip solution could be used. The DBS needed one DAC and transmitter but multiple receivers and ADCs. The three major parts of the transceiver of the DBS is the Analog Devices AD8436 QPSK modulator, the Analog devices AD8437 QPSK demodulator and the Analog Devices ADF4360-0 local oscillator.
The AD8346 QPSK modulator was chosen because it can modulate the baseband signal directly to Radio Frequency (RF) without using any Intermediate Frequency (IF) stages. The modulator output operates in the 2.4GHz range and allows for an input bandwidth of up to 70MHz.
The AD8347 QPSK demodulator was chosen because it is in the same family of products as the modulator. The AD8347 demodulates the RF frequency directly to the baseband frequency. Again this feature allows us to get rid of costly and complicated IF stages. The demodulator also has 65MHz bandwidth.
The ADF4360-0 Local Oscillator (LO) is an integrated synthesizer and voltage controlled oscillator. It has an output frequency range of 2.4GHz to 2.725GHz. This local oscillator gives us a flexible range of LO frequencies we can provide the modulator and demodulator allowing us to customize the DBS transceiver to a certain application or area.
3.2.4. Power Amplifier the MAX2247The Maxim-Dallas MAX2247 power amplifier was chosen for the DBS side as well.
The reasons for choosing the MAX2247 were again, its variable gain and power conserving shutdown mode.
3.2.5. Band-pass filtersFor prototyping reasons the DCI band-pass filter, with a pass band of 2.4 to 2.483GHz
was purchased for the DBS. Its bulky size won’t allow for use in the final design but will work for the initial proto-types.
3.2.6. Antenna structureThe DBS uses two different antenna structures for transmission and reception. First
the transmission of the ID request needs to be an omni-directional signal. A Hyper Gain HGV-2409U omni-directional antenna was chosen for the transmitter. Again it should be noted that at 20 inches long this antenna is impractical for a final design and that a patch antenna should be designed to be used with the system.
The major antenna structure in the DBS side is the receive phased-array antenna used for determining the direction of the incoming signal and beamforming. A primary phased-array antenna was designed in house by a team of engineers from the Wireless Communication Enterprise (WCE). The team designed a six-linear arrayed antenna, which is fed by using the aperture-coupled technique. For more information on the design of this antenna please refer to pages 30 to 39 of the Project Doom Star WCE report.
4. DSP Programming
In this part DSP block is studied and its general features which is used in our application will be explained. TMS320C6713 digital signal processor is used for TRX and DBS. The three main features used to implement WLPS are external memory interface (EMIF), enhanced direct memory device (EDMA) and programmable phase lock loop (PLL). These three features are configured, mainly to make sure data is properly transfer between DSP and external devices such as digital to analog converter (DAC) or analog to digital controller (ADC). DSP is programmed to implement square root raise cosine pulse shaping (at digital transmitter) and match filtering (at digital receiver). The flow of the program will be discussed in section 4.4.
4.1. EMIF
External Memory Interface (EMIF) is used to provide parallel interface between DSP with variety of external devices including Synchronous DRAM (SDRAM), pipelined synchronous-burst SBSRAM and asynchronous devices. For WLPS implementation, asynchronous interface is configured. This is chosen mainly because it provides more timing flexibility compare to using other devices formats. The flexibility is important because different devices such as different digital to analog converter (DAC) or analog to digital converter (ADC) would require various timing requirement between data assertion and clock assertion.
Asynchronous interface’s timing is programmable. In Figure 4 a write timing diagram for a certain configuration of EMIF asynchronous interface is being showed. The interface is being divided into 3 states. They are setup, strobe and hold state. The length of each state corresponds to the number of EMIF clock, which is the first timing labeled Clock. Note that Clock signal is used for internal reference where as AWE is the actual signal used as clock signal for external devices.
4.2. PLL
Software programmable phase lock loop (PLL) is used to control the clock frequency of DSP. Figure 5 shows the logic configuration of PLL and clock generator. Notice that EMIF clock in this figure is known as ECLKOUT. Through trial and error, it is determined that EMIF clock cannot exceed 200MHz and less than 10MHz.
For TMS320C6713, the external clock used for CLKIN is 50MHz. The code for configuring PLL is available in appendix B.
Figure 4: Asynchronous Timing Diagram for Write
Figure 5: PLL and Clock Generator Logic
4.3. EDMA
Enhanced Direct Memory Access controller (EDMA) is used to handle all data transfers between level-two (L2) cache/memory controller and the device peripherals on C6713 DSP. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. Figure 7 below shows the block diagram of DSP and where EDMA is located at.
Figure 6: DSP Block Diagram
For WLPS implementation, DSP uses EDMA to transfer data from internal memory to EMIF space and vice versa. This allows DSP to continue the execution of next instruction while data transfer is taking place. This also allows data to be transferred in terms of frame, block or element.
To transfer data from DSP to external device such as DAC, a QDMA is used as it requires lesser configurations and is a one time execution. To receive data from external device to DSP, a ping pong buffer configuration is being implemented. The code for configuring QDMA and ping pong buffer are shown in appendix C.
5.4. Pulse Shaping
Square root-raised-cosine pulse shaping is implemented into the program mainly because it is a conventional pulse shaping method in practical systems. This function allows the change of various parameters. They include roll off factor, delay period and sampling rate. As a result of that, one can set various configuration of square root raised cosine pulse shaping and choose the best configuration.
The function will first generate a set of samples representing root raised cosine filter coefficient using the parameters assigned. Before filtering of input sequence takes place, an error checking will be done to make sure the parameter assigned meets the range of value. For example, an error will be shown and program will be terminated if the roll off factor is more than or equal to 1 or less than or equal to 0.
The output of pulse shaping will be a representation of voltage level for DAC. Appendix D shows the code of pulse shaping filtering. In future, various types of filters will be implemented in this function, such as raised cosine.
ID Bit Generation
EXTERNAL DEVICES IE: DAC / ADC
Pulse Shapping
EDMA (trigger )
DSP MemoryDAC code
EMIFDAC Code Conversion
Digital Signal Processing (DSP) Chip
Peripherals
Software Functions
Configurations (PLL, EDMA, EMIF)
Transfer completiondetected
Figure 7: Flow Chart of DSP program for transmit mode
4.5. Program Flow For Transmit
To transmit, DSP program will start off by setting up configurations mainly PLL, EMIF and EDMA. PLL is configured to have EMIF clock running at a rate of 100MHz and EDMA is configured to transmit data in a frame synchronized mode with each frame having the size of 512 elements. Each element is 32 bits wide. Where as EMIF is configured to have one EMIF clock cycle for write setup and write strobe and two EMIF clock for write hold. With these configurations, data will be transmitted to digital to analog (DAC) converter at 25 mega samples per second. Note that several trial and errors have been carried out in able to find the optimum configurations.
Next, a set of ID bits will be generated and be passed into square root raised cosine pulse shaping filter. At present, a random bits sequence will be generated to test the
design instead of ID bits. As the output of pulse shaping filter represents the voltage level of DAC, the output will need to be converted into DAC code and store into an allocated internal memory address of DSP.
After storing all DAC code into DSP internal memory, EDMA will be triggered to transfer data from internal memory to EMIF. EMIF in turn will generate high and low signal for all the proper pins, which will be connected to external device. The external device connected for transmitting is DAC. When the program detected the completion of data transfer, it will trigger EDMA to transfer the same set of code again. This will repeat itself until program gets terminated manually or power supply of DSP is turn off.
A flow chart is included in figure 7 and the main function of program is given in appendix E to give further explanation of program flow for transmit.
5. Implementation of a digital transmitter In this part we explain the activities for implementation of a digital transmitter at 2.4
GHz band step by step and in details. Test and experimentation of each block is illustrated and the results of integration at each part are presented. To demonstrate the function of transmitter we will chose BPSK modulation with squared root-raised-cosine pulse shaping. However implementation of QPSK modulation would be very straightforward.
5.1. Launching the DAC
Testing of the Analog Devices AD9765 Digital to Analog converter began in the second week of May. The data sheet for the AD9765 calls for two separate voltage supplies set 3V for the digital side and 5V for the analog side for best performance. However both sides can be run at the same voltage thus allowing for one power supply. The input to the DAC is a 12 bit digital word. The voltage value for logic high on input can be scaled to whatever the supply voltage is using a set of pull up or pull down resistors. In the testing that was conducted one Lodestar 8102 dual power supply was used with both sides set to 5V.
The DAC uses 4 clock signals to control the data as it passes through the chip. These can all be supplied from one clock or be supplied independently. It was chosen to operate all four clocks simultaneously via the one clock provided by the word generator for timing reasons during testing.
The AD9765 is a differential current digital to analog converter. In other words the
output of the AD9765 is in the form of two currents IoutA and IoutB. These two currents are related by the DAC transfer function found in the data sheet. Below are selected equations that were used in the testing process.
IoutFSDACCODEIoutA ×
=
4096(1)
( ) IoutFSDACCODEIoutB ×
−=
40964095
(2)
Where DACCODE is the decimal value of the digital word and IoutFS is the full-scale output current. The maximum value of IoutFS for the AD9765 is 20mA for this testing IoutFS
was not scaled in anyway and was left at 20mA. To change these currents in to the voltage needed by the transmitter the DAC evaluation board uses a set capacitors and resistors which change the current into voltage. The voltage and current are related to the value of the resistor by these simple equations.
RloadIoutAVoutA ×= (3)RloadIoutBVoutB ×= (4)
Where Rload is the load seen by the outputs of the DAC board in this case it was assumed Rload would be 50Ω because the input of the next stage is considered to be 50Ω. From these four equations the DACCODE can be solved for a specific voltage and IoutFS. The simplified equation looks like this.
2
40954096 +
×
=
IoutFSRloadVoutT
DACCODE
(5)
Where VoutT is the voltage desired at the output terminal. The output then needs to be filtered and the data sheet provides a few different ideas of how to filter the output. The evaluation kit uses a Mini-Circuits T1-1T RF transformer to accomplish this.
Inputs to DAC are 12-bit digital words. These digital words are combinations of logic high and logic low values sent at a certain speed to achieve a certain output speed. The overall WLPS system will use the DSP to generate the words as well as the clock for the DAC. In testing the words and clock were provided by a word generator. The IME team purchased an Interface Technology 670 digital word generator. The 670 was found to have the ability generate 12 bit words with a minimum word period of 50ns and 8-bit words with a minimum word of 25ns. This allows for a maximum input speed of 20MHz with a 12-bit word and 40MHz with an 8-bit word. The word generator also has two different output clocks, a free running 40MHz clock and a gated variable clock with a maximum speed of 40MHz. During testing it was found that the gated clock best suited the timing needs of the DAC and during initial testing 12-bit words were used. The initial test was to create a 2MHz 1V peak-to-peak ramp wave. To do this using 12-bit words to create a 2 MHz wave with the input data speed of 20MHz that the wave would have to be split up into 10 samples. Table1 shows the values used in this test. The Hex Word column is the hexadecimal equivalent of the DACCODE, the 670 word generator allows for entry of digital words in Hexadecimal format to save time during setup.
Table 1: Required digital words to generate a ramp waveSample # Voltage (V) DACCODE Hex Word
Later tests show that due to the most significant bit operations the DAC does that 8 bit words could be found by using the same transfer function and dropping the least significant bit of the hexadecimal value. Allowing us to test the DAC at 40MHz. using a similar process the 20 word 2MHz 100mVrms ramp wave was calculated. In this test the functionality of the dual DAC was tested by sending the needed 2MHz sine wave to both sides of the DAC but with a 90 degree phase shift on the B side. Below is a picture of the output of the DAC signals as seen by the oscilloscope. As the picture shows the phase shift and frequency of the wave are almost totally synchronous, however the RMS value of the wave is off by about 25 mV this could be accounted for in insertion loss of some of the connectors and the input of the DAC not being exactly the assumed 50Ω load.
Figure 8: Output of the DAC using the digital word generator5.2. DSP-DAC Integration
After general code for the DSP was written it was decided to test the integration of the DAC and DSP. The parameters for integration were chosen as:
• BPSK modulation (one channel of DAC channels is used)• Root raised-cosine pulse shaping with roll off factor of 0.5• Information Bit rate: 5 Mbps• DAC sampling rate: 20 Msps (4 samples per bit)• The DAC input words include 10 bits
To create the desired base band analog signal out of DAC board, DSP should provide suitable clock as well as proper input words for DAC. Note that the clock and input
should satisfy timing requirements of DAC (rising edge of clock must occur when input is stabilized). According to above mentioned parameters DSP should provide a clock with the frequency of 20 MHz and samples of pulse shaped signal. As explained in the section 4 with correct configuration and programming of DSP we could achieve this objective. Figures 9 and 10 show the clock signal and timing diagram of the DSP output. Figure 9 was obtained using an oscilloscope and a logic analyzer was utilized to acquire Figure 10. As seen in Figure 10 the proper timing between DAC input and clock is achieved and data and clock are ready to feed into DAC board. An appropriate connector was made and DSP out put signals was applied to the DAC kit. Figure 11 illustrate DSP-DAC integration and the out put of the DAC. As seen the output of DAC is as expected, however there is a problem with this signal that is related to the output configuration of the DAC board. We will discuss this issue section 6.
Figure 9: Provided clock signal (AWE pin)
Figure 10: Timing diagram of DSP output
Figure 11: Integration of DSP and DAC
5.3. Including RF Section
Upon completion of DSP-DAC and getting the desired baseband output, we were ready to work on RF part. As mentioned Maxim-Dallas MAX282* series of transceivers is used as RF section in TRX. The available evolution kit can be used as up converter for transmission and down converter for reception. The carrier frequency and output gain of the chip can be adjusted using software. As a transmitter it accepts two inputs for I and Q signals, however for BPSK signal we just provide I signal. The evaluation kit requires an external signal as a reference and applies it to an internal circuit (inside the chip) to generate desired carrier signal. For the sake of experimentation we used a signal generator to provide reference frequency, but finally this reference should be generated with another block inside the system. Using available software we set carrier frequency to 2.437 GHz. A spectrum analyzer is used to test the output signal of RF board. The result of this experiment is shown in Figure 12. As seen the desired spectrum is obtained around carrier frequency and it is ready to be amplified and transmitted via antenna.
Figure 12: Integration of baseband part and RF part
5.4. Including Power Amplifier and antenna
After completing the base-band and pass-band modulation the generated signal should be amplified and applied to an antenna. We used the available power amplifier for transmitter of TRX i.e. Maxim-Dallas MAX2247. The output of power amplifier is ready to be applied to omni-directional antenna HGV-2409U. This configuration is illustrated in Figure 13. To test the transmission of the generated RF signal a receive antenna which is connected to spectrum analyzer can be used. However in this set-up a very short range for transmission and reception was chosen because the signal power wasn’t maximized. As picture shows the spectrum analyzer is receiving a signal around transmission carrier frequency and form of spectrum is the same as transmitted signal’s spectrum. This means the transmission is occurring correctly and if an appropriate receiver is used, transmitted bits can be detected.
Figure 13: Including Power amplifier and antenna
6. Conclusion
In this report implementation of a digital transmitter at 2.4 GHz range was considered. Transmission of a BPSK signal with carrier frequency of 2.437 GHZ was completed and tested successfully. This implementation can be used at both TRX and DBS units of WLPS system. However for TRX and DBS required changes should be applied (especially in software part).
The prototype developing team believes that this was a very useful experience. They tried to utilize their knowledge toward building a practical system. . First and foremost we experienced working on part of a large scale project and breaking the large scale goal down into simpler smaller goals and work with people of all levels knowledge. Throughout the time of WLPS development we learned the basic structure and features of DSP chip as well as its capabilities and limitations. In addition to DSP programming we were given a chance in implementing digital communication algorithms and hardware. We also became more familiar with equipments used in an electronics and communications project, such as logic analyzer and spectrum analyzer.
As the final point the future work for improving the implemented structure and moving WLPS prototype development ahead, is listed as:
• Closer inspection of the DAC evaluation kit showed that the differential current outputs of the DAC is being changed single ended output voltage using a transformer. The grounded centertap on the primary of the transformer causes the output of the DAC swing around ground. In other words, this configuration tries to remove the DC component of the DAC output. The effect of this problem can be seen in figure 11 (the slope of the output voltage when consecutive 1s or -1s are transmitted). One solution to this problem is changing the output configuration of the DAC chip. For more information reader is referred to available documents about DAC chip and evaluation kit.
• Transmission of QPSK modulation (To achieve higher bit rate) with minor changes in DSP software and some changes in connections between different blocks.
• Providing the reference signal for transceiver board without using a laboratory signal generator. Some studies should be done to see whether DSP can provide proper reference or another block should be added to system structure.
• In this work we used the transceiver evaluation board just for transmission and transmit mode was set manually (setting related jumpers by hand). However for WLPS system switching between transmit and receive modes as well as output settings (carrier frequency, gain, etc) should be done automatically. This problem also should be studied.
• Maximizing transmit power
• Implementation of a digital receiver and testing the validity of digital and reception of ID (or IDR) signal.
Acknowledgement:
The team would like to acknowledge all people who helped group during this work. Specially Michael R. Chase and John J. Miller which support us with providing required equipments and Bernard from TI technical support who gave technical advice in DSP programming.
APPENDIX A: EMIF Configuration Code// DATE: 20th Aug 2005// Written by: Jason Shim
#include "trx_header.h"// desired library or header file needed in program's header file//#include <csl_emif.h>//#include <csl.h>void setEmif( );
// This function configure the desired Emif function // part. // Some useful information about EMIF:// SPRS186J: (datasheet)// Page 19 - EMIF register descriptions// Page 36 - register's bit for configuring// Page 53 - pin functions of EMIF// Page 96 - EMIF device speed// SPRU266D: ( peripheral reference guide ) // Read all to understand EMIF// section 3.7 - Registers descriptions// Section 1.5 - Asynchronous interface //// Page 3-4 of technical reference TMS320C6713 shows the pin // allocation of EMIF// Page 1-5 of technical reference show the memory map of C67xx// Useful Schematic: page A-5 technical reference// // CE space 2 is assigned for transmit and CE space 3 is assigned // for receive. Both CE space is configured for AWE format. CE space// 0 which is used for SDRAM is being reconfigured to AWE format// as SDRAM is not needed and its refresh mode will cause // undesired interrupt when transmitting//// EMIF input clock source//// Then initialize it./**********************************************************************/void setEmif( )/* Initialization of the EMIF */
EMIF_Config MyConfig = 0x00003078, /* gblctl */ // default value0x10518121, /* cectl0 */ // set it to non sdram mode0x02208802, /* cectl1: CPLD & flash - Read hold = 2, MTYPE = 8-bit asynchronous interface Read Strobe = 8, TA = 2, Read Setup = 0, Write hold = 2 Write strobe = 16, Write setup = 0 */ // cannot be changed 0x10681121, /* cectl2 */0x00000040, /* cectl3 */0x56115000, /* SDCTL */0x00318578, /* SDTIM */
0x000A8529 /* SDEXT */; // end of EMIF_Config
EMIF_config(&MyConfig);return; // end of setEmif
APPENDIX B: PLL Configuration Code
#include "trx_header.h"
// library to be included in header file// #include <csl_pll.h>// desired defined constant in header file//# define DIVISION0 0x0 // value for divider 0 50MHz/1 = 50MHz. Actual value has to be added by 1 //# define MULTIPLY 0x8 // value for multiplyer 50MHz * 8 = 400MHz//# define DIVISION1 0x3 // value for divider 1 400MHz/4 = 100MHz//# define DIVISION2 0x7 // value for divider 2 400MHz/8 = 50MHz//# define DIVISION3 0x4 // value for divider 3 400MHz/5 = 100MHz
// 20th May 2005. Complete timing synchronization// As EMIF Is used in this program. EMIF response according to // ECLKOUT. // PLLInit is used to configure PLL so that CLKOUT2, ECLKOUT // CLOUT3 can be controlled. More information can be obtained // at document SPRS186J page 78. // Notice that Sysclk 1 cannot exceed DSP Core timing which is // 225MHz.
// external declarationvoid setPLL( );
void setPLL( void )
int *myRegister; // PLL register pointer// Note: To have a proper setting, you need to // ground the DC_DET pin by connecting pin 75 of // peripheral expansion connector with a 1kOhm // resistor and connect the other end to one of // the ground. This is a pin that enables the// daughtercard connectors by enabling buffer // that may be blocking ECLKOUT signal.//
// set SDRAM registers value from 1 to 2^16-1
// One-time only initialization of DSK6713 library and the CSL library and of CSL // module to be used. Must be done before calling any // CSL module API. Refer to SPRU401f Appendix A for an example of using CSL// set the device configuration register value
myRegister = ( int* ) 0x019c0200; // point to device cfg register
*myRegister = 0x00000000; // set EMIF input clock source to ECLKIN External pin
myRegister = ( int* ) 0x01800000; // point to Global control of EMIF*myRegister = *myRegister | 0x00000010; // enable EKEN
//modify the clock here. Refer to document SPRU233C pg 12 section 3.1.1PLL_bypass( ); // set PLL to bypass modeDSK6713_waitusec( 100 ); // wait for 5 cycles of the slowest of PLLOUT, CLKIN and OSCINPLL_reset( ); // reset PLL device
PLL_setPllRatio( PLL_DIV0 , DIVISION0 ); // set PLLDIV0 value to 1 cause output as 50MHzPLL_enablePllDiv( PLL_DIV0 ); // enable the division valueDSK6713_waitusec(100);
PLL_setMultiplier( MULTIPLY ); // set the mutlipliear value to eight to cause output as 400MHzPLL_setOscRatio( 0x1 ); // set the oscillator divide ratio
DSK6713_waitusec(100); // wait for 1 microsecond for PLL to be properly resetted
//Sequence of setting Divider 2 and 1 are very important, refer to page 80 paragraph 4 // of document SPRS186J
// if the current divider 2 is smaller than DIVISION2 valueif( PLL_getPllRatio(PLL_DIV2) < DIVISION2 )// set Divider 2 first only then divider 1PLL_setPllRatio( PLL_DIV2 , DIVISION2 ); // set the division ratio of divider 2 to 10. This
// will give you 40MHz from the output of Clockout2PLL_enablePllDiv( PLL_DIV2 ); // enable divider 2DSK6713_waitusec(100); // wait for 1 microsecond
PLL_setPllRatio( PLL_DIV1 , DIVISION1 ); // set the divisoin ratio of divider 1 to 1PLL_enablePllDiv( PLL_DIV1 ); // enable divider 1DSK6713_waitusec(100); // wait for 1 microsecond
// end of if command
else// set divider 1 followed by 2// each divider will need to wait for a 8 cycle of the slowest of old and new clockPLL_setPllRatio( PLL_DIV1 , DIVISION1 ); // set the divisoin ratio of divider 1 PLL_enablePllDiv( PLL_DIV1 ); // enable divider 1DSK6713_waitusec(100); // wait for 1 microsecond
PLL_setPllRatio( PLL_DIV2 , DIVISION2 ); // set the division ratio of divider 2 PLL_enablePllDiv( PLL_DIV2 ); // enable divider 2DSK6713_waitusec(100); // wait for 1 microsecond
// end of else command
PLL_setPllRatio( PLL_DIV3 , DIVISION3 ); // set the division ratio of divider 3 PLL_enablePllDiv( PLL_DIV3 ); // enable divider 3DSK6713_waitusec(100); // wait for 1 microsecond
PLL_deassert( ); // releases the PLL device from reset// wait for PLL to lock
// Although PLL lock time is 188 microsecond, it usually is not enough. As// a result of that, the board will not responds and upon halting the program// the system will show an emulator problem ( not familiar with this problem ). // To solve the problem, reset the DSP board by pressing the reset button // provided by the board. Then, press cancel button or shut off the whole // Code Composer Studio ( CCS ). Rerun CCS, reopen the project ( if CCS is // turn off ), open the source file and set PLL lock time to more than the // current value ( normally 200 microsecond should be enough ). Recompile, // reload the program and run it again.
DSK6713_waitusec( 200 );
PLL_enable( ); // // note that printf will output to Stdout if only there is \n in the end
myRegister=(int*)0x01B7C120;
myRegister = ( int* ) 0x019c0200;
myRegister=(int*)0x01800000;
return;
// end of PLLInit
APPENDIX C: EDMA Configuration Code
// DATE: 20th August 2005// Created by Jason Shim// This file contains two types of edma configuration. One is QDMA and another// one is EDMA ping pong buffer configuration
/******************************************************************************//* Submit a QDMA request to transfer the data *//******************************************************************************/
void submit_qdma( void )
EDMA_Config config;
// In each register value, set the desired value and shift to the proper location of the registerconfig.opt= (Uint32) /* 0x21200001 */( ( EDMA_OPT_PRI_HIGH << _EDMA_OPT_PRI_SHIFT ) | ( EDMA_OPT_ESIZE_32BIT << _EDMA_OPT_ESIZE_SHIFT )| ( EDMA_OPT_2DS_NO << _EDMA_OPT_2DS_SHIFT )| ( EDMA_OPT_SUM_INC << _EDMA_OPT_SUM_SHIFT )| ( EDMA_OPT_2DD_NO << _EDMA_OPT_2DD_SHIFT )| ( EDMA_OPT_DUM_NONE << _EDMA_OPT_DUM_SHIFT )| ( EDMA_OPT_TCINT_NO << _EDMA_OPT_TCINT_SHIFT )| ( EDMA_OPT_TCC_DEFAULT << _EDMA_OPT_TCC_SHIFT )| ( EDMA_OPT_LINK_NO << _EDMA_OPT_LINK_SHIFT )| ( EDMA_OPT_FS_YES << _EDMA_OPT_FS_SHIFT ));
EDMA_qdmaConfig(&config); // Set qdma configuration
/* end submit_qdma */
/*******************************************************************************//* Wait until the transfer completes, as indicted by the status of low-priority*//* queue in the queue status register (QSR) *//*******************************************************************************/void wait( void )
while( !EDMA_getPriQStatus() & EDMA_OPT_PRI_HIGH ); /* end wait */
/*******************************************************************************/// set_PingPong(void)// set EDMA ping pong method for receive// //*******************************************************************************void set_PingPong()// at this moment is left blankreturn;// end of set_PingPong method
APPENDIX D: Pulse Shaping Code// DATE: 28/07/2005// Created by Jason Shim
//// This functions filter a set of bit sequence using //// root raised cosine pulse shaping system and then return a set //// of value corresponding to voltage level //
// This program is referencing all the matlab's demorcos function //// and all those functions used by demorcos //// For this program to work properly, the header file (in this //// case is trx_header.h) must have several parameters which //// include Fs = Sampling frequency (samples per second) //// Fb = bit frequency or known as baseband frequency //// DELAY = the number of delay in cycles that a filter should have //// R = The roll off factor //// sampleSize = the number of samples to represent one bit ( Fs/Fb)//// filterSize = the size of a filter = (DELAY*2)*sampleSize + 1 //// upsampleSize = The filtered samples from Transmit side = //// (input data size + DELAY*2 - 1)*sampleSize + 1 //// matchSampleSize = The size of samples after match filtering //// = upsampleSize + DELAY * 2 * sampleSize //// --------------------------------------------------------------- //
#include "trx_header.h"
void rcosine( int type, float *output );void rcosFilter(float * out, float * filter, Bool * dataFb, float * dataFs, int type );void rrcosFil( float* out );void saveFile(char* fName, float* input, int size);
/*-----------------------------------------------------------------*/// rcosine( char *type )// Design an FIR raised cosine filter to filter a digital signal with // the digital transfer sampling frequency Fb. The filter sampling // frequency is Fs. Fs/Fb must be a positive integer. // Other parameters include the rolloff factor R, delay which is // delay/Fb seconds. // // All these parameters are accessible and changeable through rcos // header file.//// Parameter:// int type -> Decide the specific filter design instructions. // 1 = 'fir' Design the FIR raised cosine filter// 2 = 'iir' Design an IIR approximatio to the FIR raised cosine filter.// 3 = 'normal' Design the regular raised cosine filter ( default )// 4 = 'sqrt' Design square root raised cosine filter.// 5 = 'default' Use the default ( FIR, Normal raised cosine filter ).//// float *output -> Pointer to the buffer where filtered results are stored//// Return:// The size of the filter//*************************************************************************void rcosine( int type, float *output )
//int tol = 0.01; // set the tolerrance value of the filterint FsDFb = Fs/Fb;
// check if roll off factor is within 1 and 0if( R < 0 || R > 1 )
printf( "Roll off factor must be more than 0 and less than 1 \n" );exit( 1 );
// end of if command
// check if delay is a positive integerif( DELAY - (int)DELAY != 0 | DELAY < 0 )
printf( "DELAY variable must be a positive integer \n " );exit( 1 );
printf( "Fs/Fb in RCOSINE must be an integer greater than 1.\n" );exit( 1 );
// end of if command// check filter typeif( type==1 )printf( "fir design currently not available \n" );exit(1); // end of if command
else if( type == 2 )
printf( "iir design currently not available \n" );exit(1);
// end of else if command
else if( type == 3 )
printf( "normal design currently not available \n" );exit(1);
// end of else if command
else if( type == 4 )
printf( "sqrt raise cosine filter \n" );
// call the function that design this filter and return the size of the filterrrcosFil( output );//saveFile("rrcosFil", output, filterSize );
// end of else if command
else
printf( "invalid type. Has been setted to default type.\n" );exit(1);
//end of else statement
return; // end of rcosine function
//------------------------------------------------------------------------------ ////------------------------------rcosFilter-------------------------------------- //// rcosFilter filter the input signal using a raised cosine filter //// Sample frequency for the input, data is Fb, where as the sample frequency for //// output out is Fs. The int type specify the filter design or filtering options //// The rolloff factor R determines the width of the width of the transition band //// of the filter. DELAY is the time delay from the beginning of the filter to //// the peak of the impulse response. ////
//// out is pointer to the upsampled, filtered input stream data. The length of //// out is Fs/Fd*(length(data) + 2 * DELAY ). ////
//// type is an integer representing many types of filterring //// 1 = Design an FIR filter and use it to filter data. //// 2 = Design an IIR filter and use it to filter data. //// 3 = Design a normal raised cosine filter and use it to filter data. The //// filter coefficients are normalized so the peak coefficient is one. //// 4 = Design a square root raised cosine filter and use it to filter X. //// The filter coefficients are normalized so that the impulse response of //// this filter when convolved with itself will result in an impulse response //// that is approximately equal to the 'normal' raised cosine filter. //// 5 = data is input with sample frequency Fs ( ie: The input signal has Fs/Fd //// samples per symbol).In this case the input signal is not upsampled from //// Fd to Fs but is simply filtered by the raised cosine filter. This is //// useful for filtering an oversampled data stream at the receiver. When //// using the type 5, the length of vector, out is length(data)+Fs/Fd*2*DELAY //// 6 = Means the filter is provided by the user. When using the filter, the //// filter coefficent is under variable filter. Data is coming in at a rate //// Fb for transmit side
//// 7 = Same as 6 but data rate is coming at a rate of Fs. For receiver side //// parameter:
//// float * out -> filtered data
//// float * filter -> Filter coefficient if needed
//// char * data -> The set of input signal. In char format as it required less bit//// int type -> The type of filterring to be done. //
//
void rcosFilter(float * out, float * filter, Bool * dataFb, float * dataFs, int type )
// minus previous out value with current filter valueout[outInd] -= filter[filInd];filInd++;
// end of for loop
// end of else command
inInd++; // increment
// end of while loop
// make sure the out size does not exceed buffer sizeif(outInd > txBUFFSIZE)
printf( " ERROR: outInd(%d) > upsampleSize (%d) \n ", outInd, upsampleSize );exit( 1 ); // stop the process
// end of if command
// otherwise return the function
//end of if command
//////////////////////////////// ATTENTION: need to be evaluated laterelse if( type == 7 ) // if inputs comes in rate of Fs// expand the input data into a sample size plus 2*DELAY.
// add previous out value with current filter valueout[outInd] += dataFs[inInd] * filter[filInd];filInd++;
// end of for loop
inInd++; // increment
// end of while loop
// make sure the out size does not exceed upsampled sizeif(outInd > matchSampleSize)
printf( " ERROR: outInd(%d) > matchSampleSize (%d) \n ", outInd, matchSampleSize );exit( 1 ); // stop the process
// end of if command
// otherwise return the function
// end of else if commandelse
// the rest is not designed yetprintf( " Filter type %d is not designed yet \n", type);exit(1);
// end of else command/*printf("Printing filtered value\n");for( outInd = 0; outInd < BUFFSIZE; outInd++ )
printf("%f\n",out[outInd]); // end of for loop*/return; // end of rcosFilter
//----------------rcosfil-----------------------------------------------------// Design a root raise cosine filter // parameter:// float *samples// A pointer to the space for storing filter coefficient. //------------------------------------------------------------------------------void rrcosFil( float *samples )
int temp = DELAY * sampleSize;int ind = 0;float count = 0;float curVal = 0;
// generate sequence of samples from -DELAY*2 to DELAY*2 at a step of 1for( count = -temp; count <= temp; count++ )
/********************************************************************//* dacQDMA_main.c *//* Written by Jason Shim. Reference from SPRA636 Appendix A example *//* code A.1 on July 2nd 2005 *//* dacQDMA.c uses the QDMA to perform a simple block transfer from *//* internal (L2) memory to external (CE2) memory *//* This main program does what is listed below: *//* 1. Filter a set of 1 and 0 sequence into root raised cosine *//* 2. Transmit generated root raised cosine filter samples through *//* QDMA to CE2
//----------------------------------------------------------------------int i1=0; // index number used in loopint i2=0; // index number used in nested loop
/******************************************************************************//* Main code body
/* Create the buffers. We want to align the buffers to be cache friendly *//* by aligning them on an L2 cache line boundary. */int index = 0;float filter[filterSize]; // an array to store the set of samples generated by rrcos pulse shaping filterfloat *output = 0; // pointer to the array of filtered resultsfloat *retrieve = 0; // pointer to the retrieved file
// allocate memory for this variables. It is very important to do so as // the program will react very unstable without doing so.output = malloc(txBUFFSIZE + 1);retrieve = malloc(matchSampleSize + 1);for(index = 0; index < txBUFFSIZE; index++ )
sequence[index] = rand()%2;
// generate root raised cosine filter and set the pointer to the first coefficientrcosine( 4, filter ); // 4 means root raised cosine filter
// filter the input data with a the new filter coefficientrcosFilter(output, filter, sequence, (float*) 0, 6); // six means filter input data
while ( DSK6713_DIP_get(3) == 1 );DSK6713_LED_on(0);for ( index = 0; index <= 3; index++ )
submit_qdma();wait();index--;
// printf("The end \n" );
exit( 0 ); //end of main function
//************************For Testing Purposes**********************************///*****************************cfg_data******************************************//* Store a given data array in the source memory space. This data will be *//* transferred by the EDMA *//* Parameter: *//* dataArray[] => An array of signals ( 32 bits unsign integers ) *//* signal is high if value is 1 and low if value is 0 *//* dataSize => Int representing the size of the signal *//* SS => int representing the size of the high or low samples set *//*
*//* Method:
*//* set the first five spaces of source memory to 0 so that the starting point *//* of the data can be distinguished *//* Starting on the next source memory space, look at the first data of dataSet *//* if the bit is 1 and if there are still 20 spaces left before the end of *//* EL_COUNT value, copy the sampleHigh array into the memory. Or copy sampleLow*/
/* array into the memory if the bit is -1. Increment memory address for every *//* sample inputed. Repeat the same procedure for the next dataSet bit until *//* the end of samples. The rest of the memory space will be set to 0 if exist *//*******************************************************************************/void cfg_data( Bool dataArray[], int dataSize, int SS )
int *sourceRegister = (int*)txMEM_SRC;int count = txEL_COUNT;
*sourceRegister = 0;
for( i1 = 0; i1 < dataSize; i1++ )
// check if the memory space has sampleSize more space leftif( (count-SS) < 0 )
return;
// end of if command
// input sampleSize data either high or low to the next 16 memory spaceif( dataArray[ i1 ] == 1 ) // high
![SpacecraftFormationOrbitEstimationUsing WLPS …downloads.hindawi.com/journals/ijno/2011/654057.pdfspace-based solar power transfer applications [24, 25]. In the futuristic space-based](https://static.documents.pub/doc/80x56/605224bef12cb448c4134594/spacecraftformationorbitestimationusing-wlps-space-based-solar-power-transfer-applications.jpg)
