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474 EE Department Texas A&M University

1

T

WO

AND

ONE

S

TAGES

OTA

F. Maloberti

Department of ElectronicsIntegrated Microsystem Group

University of Pavia, 27100 Pavia, [email protected]

tel. +39-382-505205; fax. +39-0382-505677


2

F

UNDAMENTAL

OF

O

PERATIONAL

A

MPLIFIER

The ideal operational amplifier is a voltage controlled voltage sourcewith infinite gain, infinite input impedance and zero output impedance.

In all applications the op-amp is used in feedback configuration.

+

_

A(v - v )+


3

The feedback configuration:

❒

If the gain of the op-amp is not infinite, an error of the order of 1/A results. This error must be smaller or comparable to the impedance matching.

_

+

Z 1

4

V

Z 3

Z 2

Z

1

V2

V0

V 0 V 2

Z 4

Z 3 Z+ 4---------------------

Z 1 Z 2+

Z 1--------------------- V 1

Z 2

Z 1-------–=


4

❒

If impedances are implemented with capacitors and switches, it result that, after a transient, the load of the op-amp is made of pure capacitors. Their voltage can be obtained with stages having high output resistance (transconductance operational amplifier).

_

+- Q (t)

g vr C

C

m i00

δ

v 0 0+( ) QC0-------–= v i 0+( ) Q– 1

C0------- 1

C----+

=

V i t( ) V 0 t( ) QC----–=


5

The output resistance must be high in order to have

gm v 0 ∞( ) QC----––

v 0 ∞( )r 0

---------------= v 0 ∞( ) QC----

gmr 0

1 gmr 0+------------------------⋅=

v0 ∞( ) QC----→

g vr C

m i00

C

Q+

v (t)

t

0v 0 t( ) v o 0+( ) v 0 ∞( ) v 0 0+( )–[ ] 1 e t τ⁄––[ ]+=

τ Cgm-------≅

474 EE Department Texas A&M University 6

PERFORMANCE CHARATCTERISTICS

Actual op-amps deviate from ideal behavior. The differences are de-scribed by the performance characteristics.

DC differential gain :

is the open loop voltage gain measured at DC with a small differentialinput signal. Typically Ad = 80 - 100 dB

+

vi noutv


Common mode gain:

is the open loop voltage gain with a small signal applied to both theinput terminals. Acm = 20 - 40 dB.

Common mode rejection ratio:

is defined as the ratio between the differential gain and the commonmode gain. Typically CMRR = 40 - 80 dB

+vi n

outv


Power supply rejection ratio:

if a small signal is applied in series with the positive or negative powersupply, it is transferred to the output with a given gain Aps+ (or Aps-).The ratios between differential gain and power supply gains furnishthe two PSRRs.

Typically: PSRR = 90 dB (DC)PSRR = 60 dB (1KHZ)PSRR = 30 dB (100 KHZ)

+

vps

ov =A vps ps


Input offset voltage:

in real circuits if the two input terminals are set at the same voltage theoutput saturates close to VDD or to VSS.

Offset compensates the effect.

Typically |Vos| = 5 - 15 mV

Input common mode range:

it is the maximum range of the common mode input voltage which donot produce a significant variation of the differential gain.

+

outv

osv


Output voltage swing:

is the swing of the output node without generating a defined amountof harmonic distortion.

Equivalent input noise:

The noise performances can be described in terms of an equivalentvoltage source at the input of the op-amp.Typically = 40 - 50 nV/ at 1 kHz; in a wide band (1MHz) it results 10 - 50 µV RMS

Vn Hz

+ outv

nv |v |n2

log(f)

[dB]


Unity-gain bandwidth (f t):

is the frequency at which the open

loop gain is zero. It is also the -3 dB

bandwidth for unity-gain closed loop

conditions. Typically ft = 20 MHz

Slew rate:

it is the maximum slope of the output voltage for a steply signal applied at theinput. Usually measured with the op-amp in the buffer configuration. The posi-tive slew rate can be different from the negative slew rate, depending on thespecific design. Typically 5-20 V/µsec. For micropower operations they dropsto much lower levels.

+ outv

|A |

log(f)

[dB]0

fT

+ outv slope

v

t

out


Settling time:

if the phase margin is not good enough the response to an input stepcan be affected by some ringing. The settling time is the time requiredto settle the output within a given range (usually ± 0.1%) of the finalvalue.

Power dissipation:

it depends on the request of speed and bandwidth of the circuit. Typ-ically, for 5 V supply, is around 1 mW. For lower supply the power con-sumption doesn’t scale proportionally


Technology 0.8 µm CMOS

Supply voltage 3.3 V

DC gain 80 dB

gain-bandwidth 20 MHz

Slew rate 5 V/µsec

Settling time 1V, Cl=4pf 400 n sec

CMRR 40 dB

PSRR, DC 90 dB

PSRR, 1 kHz 60 dB

PSRR, 100 kHz 30 dB

Offset 6 mV

Input common range 2 V

Output swing 2.5 V

Input referred noise 100 nV/√Hz at 1 kHz

Power dissipation 1 mW

Area 100 x 100 µm


Basic Op-Amp Internal Functions

Key requirement:

❒ Need absolute stability in unity gain closed loop conditions when driving maximum load.

❒ Use minimum number of gain stages.

Differ.Gain

Differ.S. End.

2nd gainStage

OutputStage


Two stages op-amp (transconductance)

Key design issue:

❒ Open loop DC gain

❒ DC offset

❒ PSRR

M1I Ref

M2

M3M5

M6M7

M B

M4

Cc Out


Open loop DC gain:

DC offset:

The input offset is composed of two terms:

• Systematic offset• Random offset

Av A1A2

gm1

gds2 gds4+-------------------------------

gm5

gds5 gds6+-------------------------------

K WL

------1

WL

------5

I7 I6---------------------------------⋅ ⋅

K ′ WL

------1

WL

------5

IRefWL

------7

WL

------6

--------------------------------------= = =


Systematic offset:

❒ It is assumed that the device are perfectly matched.

❒ The systematic offset can be reduced to zero with a careful design. For zero input differential signal the scheme is equivalent to:

The transistors M6 and M7 must operate is saturation. Hence:

M1I Ref

M3M5

M61/2 M7

M B

Out

W L⁄( )3

W L⁄( )5---------------------

12---

W L⁄( )7

W L⁄( )6---------------------=


Random offset:

❒ Due to the geometrical mismatching and process dependent inaccuracies.

❒ Dominated by the offset of the input stage

❒ Higher than bipolar counterpart

vos1

-A 1vos2

-A 2

v os v os1

v os2

A1----------- v os1≅–=


For zero input signal, the output is:

∆V is neutralized with an input offset voltage such that:

+

-

R 21R

I I

∆V I1R2 I2R2–I2---∆R= =

gm1R0v 0s ∆– V= v 0s12--- I

gm1----------∆R

R0--------–=


Bipolar:

Mosfet:

Assuming:

it results:

Igm------- 26mV≈

Igm-------

V GS V T h–

2----------------------------- 150 300mV–≅=

∆R2R0----------- 0.01=

v os bip, 0.26mV=

v os MOS, 1.5 3mV–=


Power supply rejection:

❒ A signal on the positive bias line determines a modulation in the reference current, which, in turn, gives an equal modulation of the currents in M5 and M6 if the condition of the zero systematic offset is fulfilled.

M1I Ref

M2

M3

M5

M6M7

M B

M4

Cc Out

VD D

vn

VD D

vn

34

-

+


❒ A signal on the negative bias line is divided by the network made by M7, M1, M3. The signal on node 4 (by symmetry equal to the one on 3) is given by:

The DC PSRR is usually larger than the DC gain.

❒ At high frequency the PSRR is determined only in the second stage

❒ The impedance of the compensation capacitances Cc decreases, resulting an effective shorting of gate to drain of M5.

v 4 v -=v -

1 gm1gm3r ds1r ds7+-------------------------------------------------------–

v gs5 v - v 4–=

v 0 v gs5– A2v -A2

gm1gm3r ds1r ds7--------------------------------------------–= =


It results:

❒ The negative supply PSRR is approximately 0 dB at the unity gain frequency of the op-amp.

VDD

rds6

M5

n

v-n

v out

v n+

-----------1 gm5⁄

1 gm5⁄ r ds6+------------------------------------=

v out

v n-

-----------r ds6

1 gm5⁄ r ds6+------------------------------------ 1≅=


Coupling through the virtual ground

❒ Gives an high frequency contribution to the PSRR when the op-amp is used as integrator.

❒ Due to the capacitive coupling between power supply lines and the input led.

❒ Put input transistors in well attached to source. The body effect, which changes VTh, hence VGS, is eliminated.

❒ Careful layout: no crossover, shielding.

+

VDD

C-

C+

CI

vout

VSSv 0 αv n

+ βVn-

–[ ]–=


FREQUENCY RESPONSE AND COMPENSATION

❒ A two gain stages scheme with poles in the same frequency range needs compensation.

❒ A single pole system is always stable.

❒ Strategy: approach single pole performance by splitting the two poles apart.

I1 I2

P1

P2C c


❒ Miller capacitance moves p1 at lower frequency.

❒ Shunt feedback moves p2 ar higher frequency

Small signal equivalent circuit for two stages operational amplifier.

g vR C

m2

22

C

g vR C

m11

i n1

c

1

v 1v

0

v 1 g1 sC1+( ) v 1 v 0–( )+ sCc gm1+ vin 0=

v 0 g2 sC2+( ) v 0 v 1–( )+ sCc gm2+ v 1 0=

V 0

V in--------- gm1= R1gm2R2

1sCc

gm2-----------–

1 sR1+ R2gm2Cc S2R1R2 C1C2[+ C1 C2+( )+ Cc

------------------------------------------------------------------------------------------------------------------------------------------


The circuit displays two poles and a zero in the right half plane.

since in practice Cc > C1; Cc ≈ C2 and gm1 > 1/R1; gm2 > 1/R2 it results:

Assuming p1 as dominant, the unity gain angular frequency wT is:

p11–

gm2R2R1Cc----------------------------------≅ p2

gm2– Cc

C1C2 C1 C2+( )Cc+---------------------------------------------------------≅

z +=gm2

Cc----------

p11

R1C1---------------« p2

gm2

C2----------≅ 1

R2C2---------------»

ωT p1= A01

gm2R2R1Cc----------------------------------= gm1gm2R1R2

gm1

Cc----------=


The locations of the second pole p2 and of the zero with respect to wTare derived by considering:

for stability > 2 to 4;p2

ωT-------

gm2

gm1----------=

Cc

C2-------

zωT-------

gm2

gm1----------=


if Cc > C2 and gm2 > gm1

❒ The right half-plane worsen the phase margin.

❒ In bipolar technology gm2 >> gm1 because the current in the second stage is normally higher than the one in the first stage.

AA

AAAA

AA

AA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

|A|[dB]

log(f)

-90°

-180°

-270°

Φ

AA AAAAA

with left half-plane zerolog(f)

AA

AAAAAAAAA


❒ In CMOS technology because is proportional to the square root of I; moreover, the transconductance of the input pair must be high in order to reduce their thermal noise contribution.

❒ In real situations the obtainable phase margin does not guarantee the stability.

Eliminating right half-plane zero:

❒ •Source follower

❒ •Zero nulling resistor

The zero is due to a signal feedforwardto a point that is 180° out of phase

I2


Solution: eliminate feedforward with a source follower

Disadvantages:❒ Area❒ Power dissipation❒ Actually creates a doublet in the feedback path. Potentially not stable.❒ Alternative, a substrate emitter follower may be used. (The bipolar

transistor is smaller and has higher gm)

I2

1

I2


Zero nulling resistor:Zero’s position is pushed away with a resistance in series with Cc

It results:

R z Cc

1

V 0

V in---------

A0 1 s Rz 1 gm2⁄–( )Cc+[ ]

1 sp1------+

1 sp2------+

-----------------------------------------------------------------------≅


❒ The pole locations are closed to the original

❒ The zero is moved depending on Rz

❒ If Rz = 1/gm2 the zero is moved at the infinite

❒ If Rz = 1/gm2 the zero is located in the left half-plane

Implementation:

z 1

Cc1

gm2---------- Rz–

-------------------------------------=

V1

VDD

VSS

V0

gm21

Rn-------=

1Rp-------+


In non saturation:

Choose and such that:

and:

Problem: Supply sensitivity.

Since the swing of the node 1 is A2 less than the output swing, onlyone transistor with supply independent bias can be used.

1Rn------- k 'n=

WL

------

nV DD V 1– V Th n,–[ ] 1

Rp------- k 'p=

WL

------

pV 1 V ss V Th p,––[ ]

WL

------

n

WL

------

p

k 'nWL

------

nk 'p=

WL

------

p

gm2 k n=WL

------

nV DD V SS V T h n, V T h p,–––[ ]


SLEW RATE

(CL includes the feedback capacitor)For large input signal:

❒ M1, M4 are off so the current IB1 charges Cc through M2. Assuming M5 able to drive the current request by Cc, CL and IB2

IB1 IB2

Cc

M1

M3

M5

M4

M2

CL

SR+∆V +

∆t-----------

max

IB1

Cc--------= =


❒ M2, M5 are off so the current IB1 mirrored by M4 discharges Cc; CL is discharged by IB2

In order to have SR+ = SR- it must be:

Since , it results

For , (VGS - VTh) = 600 mV, SR ≈ 10 V/µsec.

SR-∆V -

∆t----------

max

IB2

Cc CL+----------------------= =

IB1

Cc--------

IB2

Cc CL+----------------------=

ωT

gm1

Cc----------=

SRIB1

gm1----------= ωT V GS1 V Th–( )= ωT

ωT 2π 5 106⋅ ⋅=


SINGLE STAGE SCHEMES

High gain is get with a cascode scheme.

❍ Telescopic cascode

❍ Mirrored cascode

❍ Folded cascode


Telescopic cascode:

J DC gain ≈ (gmrds)2

J Low power consumption

J Only one high impedance node:

compensated with a capacitance load

(if necessary)

L Low output swing

L Reference of the input close to the negative supply

L Two bus lines (VB1, VB2)

L 5 Transistors in series

M1

M4M3

M6M5

M8M7

M2

M9

VB1

VB2

+ _


Mirrored cascode:

J Optimum input common mode

range

J Only 4 transistors in series

J Improved output swing

L Speed of the mirror

L Higher power consumption

M1

M4M3

M6M5

M8M7

M2

M9

VB1

VB2

+ _

M10 M11 M12 M13

Out

V outmax V B1max V GS4 V sat–+=

V B1max V DD V sat– V GS4–=

V outmax V DD 2V sat–= V outmax V GS7 V sat+=


Conventional Folded cascode:

M1

M4M3

M6M5

M8M7

M2

M9

VB1

VB2

+_

M10M11

Out

VB3


Modified Folded cascode:

Modified in order to improve the going down output swing

M1

M4M3

M6M5

M8M7

M2

M9

VB1

VB2

+_

M10M11

Out

VB3

M B

MA


TWO STAGES AMPLIFIER VS SINGLE STAGE AMPLIFIER

Two stages:

J Voltage gain less affected by resistive loading

J Maximum signal swing

J Less bussing of bias lines

L Requires additional capacitor for frequency compensation

L More power consumption


Single stage:

J No need for additional compensation capacitor

J Lower power consumption

J Better CMRR

L Lower signal swing

L More bussing of bias lines


CLASS AB A MPLIFIER

Class AB: a circuit which can have an output current which is largerthan its DC quiescent current.

❒ Two stages amplifier with class AB second stage

M6 and M7 act as a levelshifterM8 and M9 act as a class ABpush-pull amplifier M1

M3

M5

M4

M2

M8M6

M7

M9VB

A2gm8 gm9+

gds8 gds9+-------------------------------=


The quiescent current in the output stage is bias voltage and technologicalvariation dependent.

neglecting the body effect:

Typically with VDD = 5V the numerator is around 1.6 V; if it is assumed VDD= (5 ± 0.5)V and DVTh = ± 200 mV, it results that the numerator can changefrom 0.7 V to 2.5 V; hence, Imin = 0.3 Inom; Imax = 2.5 Inom

V DD V GS8 V GS6 V GS9+ +=

V DD V T h p,= 2V T h n,2

k 'n------- L

W------

6I6+

2k 'p------- L

W------

8I 2

k 'n------- L

W------

9I+ + +

IV DD V T h p,– 2V T h n,–

2k 'n------- L

W------

6I6–

2k 'p------- L

W------

8

2k 'n------- L

W------

9

+

---------------------------------------------------------------------------------------------------=


❒ Single stage class AB amplifier (only inverting)

The input pair M1 and M2operate source followersand it drives the commongate stages M3 and M4

for Vin = 0

for Vin > 0 I1 and I2

K8,9 and K5,6 mirror fac-tors (assumed equal)

M1

M8

M3

M4

M2

M6M5

M9

M10

M7

VB

VB

VB

VB

I B

I B

VB VTh n,= VTh p, Vov n, Vov p,+ + +

I1 I2 IBias= =

Iout K8 9, I1= K5 6, I2–


It results:

until I1 or I2 goes to zero, for a largerVin, Iout increases quadratically withVin

V B V in+ V GS2 V GS4+ V T h n, V T h p,2

k 'n------- W

L------

2

2k 'p------- W

L------

4

+

I2+ += =

V B V in– V GS1 V GS3+ V T h n, V T h p,2

k 'n------- W

L------

3

2k 'p------- W

L------

1

+

I1+ += =

Iout K 8 9,= I1( I2 )– αK 8 9,= V BV in

Iout

Vin


Small signal gain :

Gm is the transconductance of the cross coupled input stage

Av 2Gm= r out

M4

M2

A

In

A

gm2 (vin - vA )

-gm4 vA

gm2 V in V A–( ) gm4= V A

V Agm2V in

gm2 gm4+----------------------------=

Iout gm4= V Agm2gm4

gm2 gm4+----------------------------= V in GmV in=


FULLY DIFFERENTIAL SCHEMES

The use of fully differential paths through analog signal processorgives benefits on:

➣ PSRR➣ Dynamic range➣ Clock feedthrough cancellation

Consider an integrator and its fully differential version

-

in

+

R

C

outin

in

+

+

R

R

C

C

+

+

--

-

-out

out


J Noise from the power supply and clock feedthrough are common

mode signal.

J The output swing is (Vmax+ - Vmax- = 2Vmax) doubled. Since the

noise is unchanged, the dynamic range improves by 6 dB.

L Single ended to differential and double ended to single ended converters are necessary

L Larger area

L More bussing of bias lines

L Common mode feedback is necessary

SE/DEDifferent.Processor DE/SE


The blocks SE/DE and DE/SE increase the complexity and introducenoise. Differential approach is convenient if the differential processorcontains more than 4 stages.

The feedback around the op-amp control the difference of the inputterminal voltages and not their mean value. In turn, there is no controlon the output common mode voltage.

-

in

+

R

C

outin

in

+

+

R

R

C

C

+

+

--

-

-out

out


M1

M4M3

M6M5

M8M7

M2

M9

VB1

VB2

+_

M10M11

Out-

VB3

VB4

VB5

Out+

+ +CMFB

VB3

VB2

VB5oror


COMMON MODE FEEDBACK

➣ Continuous time➣ Sampled data

Continuous time feedback:

M3

M1 M2

I out

V V+ -

BV


❒ VB is such that M1 and M2 are in the linear region; (W/L)1 = (W/L)2❒ M1 and M2 are like the parallel of two voltage dependent resistance

❒ With a differential signal Iout = cost

❒ With a common mode signal: for positive, Iout increasefor negative, Iout decrease

I112---= k ' W

L------

1

2 V + V Th–( )V DS V DS2

–[ ]

I212---= k ' W

L------

1

2 V - V Th–( )V DS V DS2

–[ ]

Iout I1 I2+12---= = k ' W

L------

3

V B V DS V Th––[ ] 2


FULLY DIFFERENTIAL FOLDED CASCODE WITH CMFB

M1

M3

M5

M7

M2

M9

VB2

+ _

M10

M11M12

Out +

VB1

M4

M6

M8

Out -V

B3

VB3

VB5

V C M


M1

M4M3

M6M5

M8M7

M2

M9

VB2

V B3

+ _

M10

M11 M12

Out +Out

_

VB1

V B4V B5


Problems:

❒ Dynamic range

❒ Linearity

Compensation of the non linearities of the n-channel and p-channelCMFB cell.

V+

V-

outII


Simple data feedback:

❒ The common mode feedback operates on slowly variable signal. It can be implemented at discrete time interval.

❒ The sampled data feedback is essential for low bias voltage and low power.

J Lineartity (mean value

with capacitors)

J Low power consumption

J No limitation to the

dynamic range

L Clock phases necessary

L Clock feedthrough effect

1 2

12

1 2

12

C

C

VCM

V+ V-I Ref

OutI

C'


MICROPOWER OP-AMPS❒ Required in battery operated system (pocket calculators, pace makers,

hearing aids, electronic telephone, ...)

❒ Consumption < 1 µA

❒ Use of MOS transistors in weak inversion (subthreshold)

❒ Low current has, as consequence, low slew rate.

M1

M8M7

M2

M5 M3 M4 M61 B1C

1

B/C


AMPLIFIER WITH ADAPTIVE BIAS

Basic idea:

Generate |I1 - I2| and increase the current in the differential stage byD|I1 - I2|.

M1

M8M7

M2

M5

M3 M4

M6

1 D 1 D

12D(I -I )D(I -I )1 2

IB


Since |I1 - I2| = α [I0 +D |I1 - I2|]:

For transistors in weak inversion

The increase of the current in the differential stages becomes signifi-cant around:

Typical performances

❒ DC gain 95 dB❒ ft 130 kHz❒ SR 0.1 V/µ sec❒ I0 0.5 µA

❒ Itot 2.5 µA

I1 I2–α I0

1 Dα–-----------------=

αv i

2nv T--------------tanh=

Dv i

2nv T--------------tanh 1=


CLASS AB SINGLE STAGE WITH DYNAMIC BIASING

❒ In order to have a maximum output swing the bias voltages BIAS1 - BIAS2 must be kept as close as possible to the bias voltages

M1

M6

M3

M4

M2

M8

M5

M7

In+ In-Out+

Out-

Bias1

Bias4

Bias3

Bias2


❒ During the slewing the current source of the output cascodes can be pushed in the linear region, hence loosing the advantage of the AB operation.

❒ The problem is solved with the dynamic biasing

M1

M6

M3

M4

M2

M8

M5

M7

Out-

Bias2


NOISE

❒ The noise of an operational amplifier is described with an input

referred voltage source Vn.

❒ The spectrum of Vn is made of a white term and 1/f term.

❒ Vn is due to the contributions, referred to the input, of the noise

generators associated to all the transistors of the circuit (assumed

uncorrelated).


consider the input stage of a two stages op-amp.

The output noise voltage is given by:

M1

vn1

vn3 vn4

vn2

M4M3

M5

M2

V n out,2 V n1

2( V n22 )gm1

2 V n32( V n4

2 )+ + gm32

+[ ] 1gds2 gds4+-------------------------------

2=


Where it is assume gm1 = gm2; gm3 = gm4 (it is assumed that the noisesource of M5 does not contribute) moreover since usually W1 =W2;L1 = L2; W3 =W4; L3 =L4; V2

n1 = V2n2; V

2n3 = V2

n4;

❒ if we refer Vn,out to the input, we get:

❒ The contribution of the active loads is reduced by the square of the ratio gm3/gm1

❒ It is worth to remember that

V nout2

A12

--------------- V n in,2 V n out,

2

gm12

-----------------= gds2 gds4+( )2 2 V n12 gm3

gm1----------

2V n3

2+= =

gm 2µCoxWL

------I=

V n2 8

3---kT

gm-------

K F

2µC2ox

-------------------- 1WL---------+

= ∆f


The attenuation by the factor (gm3/gm1)2 gives, for the white term:

and for the 1/f term:

Where KF1 and KF2 are the flicker noise coefficient of the type of transistor ofwhich M1 and M3 are made.

❒ The white contribution of the active load is reduced by choosing (W/L)input >> (W/L)load

❒ The 1/f noise contribution of the active load is reduced by choosing Linput < Lload

❒ If the above conditions are satisfied the input noise is dominated by the input pair.

V n in ω, ,2 2V n1

2= 1

gm3

gm1----------+

2V n1

2 1µ3I3W L⁄ 3

µ1I1W L⁄ 1----------------------------+

=

V n in 1 f⁄, ,2 K F 1

µ1C2ox W 1L1

------------------------------------= 1K F 3I3L1

2

K F 1I1L32

-----------------------+


Cascode scheme:

❒ The noise is contributed by the input pair and the current sources of the cascode load

I1

M1

M4

M3

M2

vn1

vn4

Out

V n in,2 2 V n1

2 gm4

gm1----------

+2V n4

2=


Folded Cascode scheme:

❒ The noise contributed by the same source as in the cascode and by the current source M2

I1

M1

M5

M4

M3

M2

vn1

vn5

Out

V n in,2 2 V n1

2 gm2

gm1----------

+2V n2

2 gm5

gm1----------

2V n5

2+=


Two stages amplifier: (feedforward + zero nulling compensation)

❒ The noise is modelled with two input referred noise sources: one at the input of the first stage and the other at the input of the second stage.

g r Cm1

11

vi1

+

vn1

Out

g r Cm2

22

vi2

+vn2

RzCc


❒ In the low frequency range the noise is dominated by Vn1.

❒ In the high frequency range the noise is dominated by Vn2.

p1v

outvn1

[dB]

log(f)

p2

p1

vout

vn2

[dB]

log(f)

p2

1/|A |v1


Frequency response:

❒ The input referred noise generator is transmitted to the output as a conventional input signal

❒ The feedback network around the op-amp must be taken into account.

One stage amplifier:

The cutoff frequency is:

p1 = -gm/C0

g r Cm

00

v i+

v n

p1v

outv

n

[dB]

log(f)

Out


Power of the noise:

➣ We consider only the white term.

❒ One stage amplifier:

❒ Two stages amplifier: we consider only the white term contributed by the noise source of the second stage.

Vn02 Vn

2

0

∞

∫df

1 s p1⁄+2

---------------------------- 2α83---kT 1

gm1----------

0

∞

∫= =df

1 2( πfC0 gm1 )⁄ 2+

------------------------------------------------- 2α83---kT

12πC0-------------- dx

1 x2+

---------------0

∞∫

43---α kT

C0-------= =

Vn22 2α'=

83--- kT

gm2----------

Vn02 Vn2

2

0

∞∫=

df

1 s p2⁄+2

----------------------------

p2 gm2

C1 C2+--------------------–=

Vn02 4

3---α' kT

C1 C2+( )-------------------------=


LAYOUT

Rules:

❒ Use poly connection only for signal, never for current because the offset RI ≈ 15 mV.

❒ Minimize the line length, especially for lines connecting high impedance nodes (if they are not the dominant node).

❒ Use matched structure. If necessary common centroid arrangement.

❒ Respect symmetries (even respect power devices).

❒ Only straight-line transistors.

❒ Separate (or shield) the input from the output line, to avoid feedback.

❒ Shielding of high impedance nodes to avoid noise injection from the power supply and the substrate.

❒ Regular shape and use a layout oriented design.


Stacked layout:

Structure A:

Structure B:Source

DrainAA

AAAAAA

w

AA

AA

w/2

Drain

Drain

Source

AA

w/3

Drain

Drain

Source

AA

Source

A B

AA Source

Drain

AAA

AAAAAAAAAA

d

AAA

AAAw

LAAAAAA

Csb Cdb CjbW d 2xj+( )= =

Csb12---Cdb Cjb

W2----- d 2xj+( )= =

Csb Cdb Cjb2W3

--------- d 2xj+( )= =


❒ Capacitances are further reduced if the diffusion area is shared between different transistors

❒ Key point: use of equal width transistors (or part of transistors)

❒ Transistors with arbitrary width are not allowed

Placement and routing:

❒ If we divide a transistor in an odd number of parallel transistors the resulting stack has the source on one side and the drain on the other side

❒ If we divide a transistor in an even number of parts the resulting stack has source or drain on the two sides.

Drain

Drain

Source

Drain

Drain

Source

Source

Drain

Source


Example:

1

2

3 4 5

150 200 200 150

2

2

1 1 1 1 1 13 3 44 5 51


Routing into stacks: use of comb connections or serpentine connections.

AA A

A

AA

AA

A

A

A

A

A

A A


Fully differential folded cascode. Example

Features, symmetry, common centroid input pair, minimum mine length.

9 3 3 9 10 4 4 10

1 1 2 2 1 1 2 2

11 13 13 13 13 13 13 12

7 5 5 7 8 6 6 8

M1

M4M3

M6M5

M8M7

M2

M9

VB2

VB3

+ _

M10

M11 M12

Out+

Out_

VB1

VB4

VB5

M13

22

44

11

66

22

22

44

11

22

22

22

22

22


VDD

VB1

VB2

V+

V_

VB4

VB5

VB3

VSS

Date post:	12-Aug-2020
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