Wolf Zimmermann- On the Correctness of Transformations in Compiler Back-Ends

8/3/2019 Wolf Zimmermann- On the Correctness of Transformations in Compiler Back-Ends

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1 Wolf Zimmermann

On the Correctness of

Transformations inCompiler Back-Ends

Wolf Zimmermann

Universitat Halle

Joint work with the Verifix Teams in Karlsruhe, Kiel, and Ulm


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1. Motivation

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program

Processor

Compiler


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1. Motivation

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Processor

Compiler

correct program

(w.r.t. a specification)

Program verification


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1. Motivation

2 Wolf Zimmermann

Processor

Compiler

correct

Hardware verification

program




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1. Motivation

2 Wolf Zimmermann

Processor

Compiler




programcorrect

?


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:

u Borland Pascal Compiler Bug List

contains ca. 50 compiler errorsu Java Compiler Bug Database from Sun

contains ca. 90 compiler errors


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:




Goal of Verifix: Construction of Correct Compilers


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1. Motivation

2 Wolf Zimmermann

Processor

Compiler




programcorrect

?

Compiler Bugs:




Goal of Verifix: Construction of Correct Compilersu Programming languages in commercial use


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:




Goal of Verifix: Construction of Correct Compilersu Programming languages in commercial useu Machine language of commercially available processor families


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:




Goal of Verifix: Construction of Correct Compilersu Programming languages in commercial useu Machine language of commercially available processor familiesu efficiency of generated code comparable with code generated by unverified

compilers


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:





compilers

Idea: Use well-established compiler technology


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1. Motivation

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Processor

Compiler




programcorrect

?

Compiler Bugs:





compilers

Idea: Use well-established compiler technologyHere: Back-Ends


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2. A Practical Notion of Correctness

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Refinement based: refines the semantics of a language construct


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Refinement based: refines the semantics of a language construct traditional approach


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u Many optimizations are illegal


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Preservation of observable behaviour I/O-behaviour of a compiled program im-plements an I/O-behaviour of the corresponding source program


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Preservation of observable behaviour I/O-behaviour of a compiled program im-plements an I/O-behaviour of the corresponding source programu Memory overflows, time overflows, arithmetic overflows?


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Preservation of observable behaviour upto resource limitations Violation ofresource limitations is allowed


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u Every program SL compiles into program TL such that preserves the observable behaviour of upto resource limitations


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u Every program SL compiles into program TL such that preserves the observable behaviour of upto resource limitationsr

compilation of programs with more than 1 000 000 000 000 000 lines ofcode?


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compilation of programs with more than 1 000 000 000 000 000 lines ofcode? Almost all programs cannot be compiled


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compilation of programs with more than 1 000 000 000 000 000 lines ofcode? Almost all programs cannot be compiledu Compiler C : SL TL is correct iffr For every program SL that is compiled into a program TL,r preserves the observable behaviour of upto resource limitations


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3. Proving the Correctness of a Compiler

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intermediate code

target code as graph

attributed syntax tree

target program as binary code

source program

Front End Generator

Generator

Generator

attribute grammar

Com

pilingSpecification

im

plementationinhigh

levelprogramminglanguage

implementationasbinarycode

LALR(1)grammar

abstract syntax

graph rewriting rules

term rewriting rules

intermediate code

generation

code generation

assembly

Compiler Compiler


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3. Proving the Correctness of a Compiler

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source program

attributed syntax tree

target program as binary code

target code as graph

intermediate code

This Talk

This Talk

Front End Generator

Generator

Generator

attribute grammar

Com

pilingSpecification

im

plementationinhigh

levelprogramminglanguage

intermediate code

generation

implementationasbinarycode

LALR(1)grammar

abstract syntax

graph rewriting rules

term rewriting rulescode generation

assembly

Compiler Compiler


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4. Semantics and Abstract State Machines

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Requirements: on programming language semantics


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u Same specification technique for all levels of

programming languages used in compilers


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u Proof techniques


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u Proof techniques

u Formal definition of static parts of programming languages such

as arithmetic, data types, addresses etc.


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u Proof techniques



Verifix:


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u Proof techniques



Verifix:

u Operational semantics


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u Proof techniques



Verifix:


u States describe algebras


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u Proof techniques



Verifix:


u States describe algebras

Abstract state machines


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Example: DEC-Alpha Machine Language Semantics

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State Space and Macros:


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State Space and Macros:reg : RADDR QUADfreg : RADDR QUAD

mem : QUAD BYTEpc : QUAD


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mem : QUAD BYTEpc : QUADAuxiliary Functions:opcode : LONG OPCODE opcoderega : LONG ?RADDR register atype : LONG ?TFCODE operation typeimmed : LONG ?WORD constant operanddisp : LONG ?WORD const. relative addressimbyte : LONG ?BYTE byte in ZAP-instr.


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mem(a) concat([mem(a), . . . , mem(a Q 7)])


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mem(a) concat([mem(a), . . . , mem(a Q 7)])mem(a) := q mem(a) := split8(q)0

...mem(a Q 7) := split8(q)7


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...mem(a Q 7) := split8(q)7pc is ADD

opcode(pc) = 010000pc is ADDQ pc is ADD

type(pc) = 00000100000


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type(pc) = 00000100000Proceed pc := pc Q 4


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type(pc) = 00000100000Proceed pc := pc Q 4ra rega(pc)


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State Transitions:


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State Transitions:

ifpc is ADDQ thenreg(rc) := reg(ra) Q reg(rb)Proceed

endif


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State Transitions:


endififpc is ADDI then

reg(rc) := reg(ra) Q SExt16(immed(pc))Proceed

endif


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State Transitions:




endififpc is LDQ then

reg(ra) := mem(reg(rb) SExt16(disp))Proceed

endififpc is LDA then

reg(ra) := reg(rb) SExt16(disp)Proceed


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State Transitions:








endif

ifpc is LDAH thenreg(ra) := reg(rb) LogShift(SExt16(disp), 16))Proceed

endif


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mem(a) concat([mem(a), . . . , mem(a Q 7)])mem(a) := q mem(a) := split8(q)0.

..mem(a Q 7) := split8(q)7pc is ADD



State Transitions:








endif


endififpc is STQ then

mem(reg(rb) SExt16(disp)) := reg(ra)Proceed

endif


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State Transitions:








endif




endififpc is ZAP then

reg(rc) := zerobytes(reg(ra), imbyte(pc))Proceed

endif


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State Transitions:








endif




endififpc is ZAP then

reg(rc) := zerobytes(reg(ra), imbyte(pc))Proceed

endififpc is BR then

reg(ra) := pc 4pc := pc Q 4 Q LogShift(SExt21(disp, 2))

endif

G


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Example: Basic Block Graphs

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base:ADDR sp:ADDR hp:ADDR

VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn

E l B i Bl k G h


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VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn

eval : EXPR VALUEeval(int

ck) = SExt

k(c)

eval(addrck) = base A SExtk(c)eval(ldI(x)) = mem(eval(x))eval(ldA(x)) = mem(eval(x))eval(x +I y) = eval(x) I eval(y)eval(x +A y) = eval(x) A eval(y)I, A is integer/addressaddition on the target machine

E l B i Bl k G h


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VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn

eval : EXPR VALUEeval(int

ck) = SExt

k(c)

eval(addrck) = base A SExtk(c)eval(ldI(x)) = mem(eval(x))eval(ldA(x)) = mem(eval(x))eval(x +I y) = eval(x) I eval(y)eval(x +A y) = eval(x) A eval(y)I, A is integer/addressaddition on the target machineinstr((l, k)) = lab1(l)k

E l B i Bl k G h


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VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn

eval : EXPR VALUEeval(intck) = SExtk(c)


if ip is ASSIGN thenmem(eval(lhs(ip))) := eval(rhs(ip))Proceed

endif

E l B i Bl k G h


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VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn




endifif ip is JMP thenip := (target(ip), 0)

endif

E l B i Bl k G h


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VALUEmem:ADDR

ip:LABELNN

l: instr0

instrk

instrn




endifif ip is JMP thenip := (target(ip), 0)

endif

Macros:ip is T instr(ip) TProceed ip := (ip

1, ip

2+1)

5 C d G ti b T R iti


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5. Code Generation by Term-Rewriting

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Code Selection by Term-Rewrite Rules:



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t X {m1, . . . , mn} intermediate language expressions

t {m1, . . . , mn} intermediate language instructionsm1, . . . , mn are machine instructionsregister assignment associates X with a machine register



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Example:

5 Code Generation b Term Re riting


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Example:ldI(c16) X {LDQ X, (c16)R31} Rule 1

5 Code Generation by Term Rewriting


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Example:ldI(c16) X {LDQ X, (c16)R31} Rule 1X +I intc16 Z {ADDI X, #c16, Z} Rule 2



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intc32 X {LDA X, (c32.L)R31; ZAP X, #fc, X; LDAH X, (c32.H)X} Rule 3



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intc32 X {LDA X, (c32.L)R31; ZAP X, #fc, X; LDAH X, (c32.H)X} Rule 3addrc16 :=I Y {STQ Y, (c16)R30} Rule 4



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Rule 1

addr28

int1

addr28

I

I

ld

:=I

+

addr28 :=I ldI(addr28) +I int1



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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1



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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2



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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30

5 Code Generation by Term-Rewriting


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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1



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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2



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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2 Z = R2



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5. Code Generation by Term Rewriting

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Rule 1

addr28

int1

addr28

I

I

R2

:=I

+

ld

R2

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2 Z = R2 ADDIR2, #1, R2



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Rule 1

Rule 2

ld

addr28

R2

R2

addr +I

Iint

28

1

:=I

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2 Z = R2 ADDIR2, #1, R2addr28 :=I R2



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Rule 1

Rule 2

ld

addr28

R2

R2

addr +I

Iint

28

1

:=I

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2 Z = R2 ADDIR2, #1, R2addr28 :=I R2 (4)X = R2



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Rule 1

Rule 2

ld

addr28

R2

R2

addr +I

Iint

28

1

:=I

addr28 :=I ldI(addr28) +I int1(1) X = R2 LDQ R2, (28)R30addr28 :=I R2 +I int1 (2)X = R2 Z = R2 ADDIR2, #1, R2addr28 :=I R2 (4)X = R2 STQ R2, (28)R30



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Rule 1

Rule 2

ld

addr28

R2

R2

addr +I

Iint

28

1

:=I




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Rule 1

Rule 2

Rule 4

int

28addr

R2

I

I

addr

1

28

:=I

+

ld

R2




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Rule 1

Rule 2

Rule 4

int

28addr

R2

I

I

addr

1

28

:=I

+

ld

R2


6. Local and Global Correctness


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Simulation Proofs:



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O

Local Correctness:



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O

Local Correctness:

1)ra(m )

ra(m instr[ra(X)]

instr[t]

n0

q1

q n+1q1q nqn1

q0

q

Rule t X{m1, . . . , mn}



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Simulation Proofs:

observable

abstraction

observable

abstraction

I/O

I/O

I/O

I/O

Local Correctness:

1)ra(m )

ra(m instr[ra(X)]

instr[t]

n0

q1

q n+1q1q nqn1

q0

q

Rule t X{m1, . . . , mn}

1)ra(m

t

ra(m

)n qn

1q

1q0

q0

qn1q

Rule t {m1, . . . , mn}

Global Correctness


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Global Correctness Single simulations stemming from program transformationsare sequentially composable to simulations

Global Correctness


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Global Correctness Theorem: (JUCS1997)

Global Correctness


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Global Correctness Theorem: (JUCS1997)u Let T be a set of term-rewrite rules specifying code selection

Global Correctness


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Global Correctness Theorem: (JUCS1997)u Let T be a set of term-rewrite rules specifying code selectionu Suppose each rule of T is locally correct

Global Correctness


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Global Correctness Theorem: (JUCS1997)u Let T be a set of term-rewrite rules specifying code selectionu Suppose each rule of T is locally correct andu for every rule t X{m1; . . . ; mn} register ra(X) does not contain a live

value.

Global Correctness


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value.Then, every target program that can be obtained from a source program usingT preserve the observable behaviour of upto resource constraints

Global Correctness


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Discussion:

Global Correctness


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Discussion:

u No specific assumption on intermediate languages except basic block graphs

Global Correctness


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Discussion:

u No specific assumption on intermediate languages except basic block graphsu No specific assumption on processor assembly languages except register

machines

Global Correctness


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Discussion:


machinesu No specific assumption on term-rewrite rules

Global Correctness


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Discussion:


machinesu No specific assumption on term-rewrite rules

Specific compilers require only local correctness proofs

7. Local Correctness Proofs


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Problem: Real compiler back-ends often have more than 2000 term-rewrite rules



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Problem: Real compiler back-ends often have more than 2000 term-rewrite rulesu Manual proofs are impossible



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Problem: Real compiler back-ends often have more than 2000 term-rewrite rulesu Manual proofs are impossibleu Machine proofs must be readable



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Proof Strategies:



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:r Compute symbolically eval(t)



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:r Compute symbolically eval(t)r Symbolically execute state transitions associated with m1; . . . ; mn



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:r Compute symbolically eval(t)r Symbolically execute state transitions associated with m1; . . . ; mnr Check whether reg(X) = eval(t)



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:r Compute symbolically eval(t)r Symbolically execute state transitions associated with m1; . . . ; mnr Check whether reg(X) = eval(t)u Rules t {m1; . . . ; mn}:



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Proof Strategies:

u Rules t X{m1; . . . ; mn}:r Compute symbolically eval(t)r Symbolically execute state transitions associated with m1; . . . ; mnr Check whether reg(X) = eval(t)u Rules t {m1; . . . ; mn}:r Symbolically compose state transitions associated with m1; . . . ; mn into

single state transition


P bl R l l b k d f h h l


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Proof Strategies:


single state transitionr Compare this with the state transition associated with t


P bl R l il b k d f h h 2000 i l


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Proof Strategies:



Observations:




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Proof Strategies:


u Rules t {m1; . . . ; mn}:r Symbolically compose state transitions associated with m1; . . . ; mn into


Observations:

u Proof strategies are complete for expressions and instructions




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Proof Strategies:


u Rules t {m1; . . . ; mn}:r Symbolically compose state transitions associated with m1; . . . ; mn into


Observations:

u Proof strategies are complete for expressions and instructionsu Proof strategies can be easily mechanized using simplification mechanisms

Examples

E l 32 X {LDA X ( 32 L)R31 ZAP X #f X LDAH X ( 32 H)X}


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Example: c32 X; {LDA X, (c32.L)R31; ZAP X, #fc, X; LDAH X, (c32.H)X}

Examples



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Example: c32 X; {LDA X, (c32.L)R31; ZAP X, #fc, X; LDAH X, (c32.H)X}u eval(intc32) = SExt32(c32)

Examples



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reg(X) =?

Examples



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reg(X) =? LDA X, (c32.L)R31

Examples

Example: 32 X {LDA X ( 32 L)R31 ZAP X #fc X LDAH X ( 32 H)X}


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reg(X) =? LDA X, (c32.L)R31 reg(X) := reg(X) SExt16(c32.L)

Examples

Example: c32 X; {LDA X (c32 L)R31; ZAP X #fc X; LDAH X (c32 H)X}


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reg(X) = [b15, . . . , b15 | { z }

48 times

, b15, . . . , b0]

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times

, b15, . . . , b0] ZAP X, #fc, X

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times

, b15, . . . , b0] ZAP X, #fc, X reg(X) := zerobytes(reg(X), #fc)

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times

, b15, . . . , b0]

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times

, b15, . . . , b0] LDAH X, (c32.H)X

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times

, b15, . . . , b0] LDAH X, (c32.H)X reg(X) := reg(X)

LShft(SExt16(c32.H), 16)

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)

Example: addrc16 :=I Y {STQ Y, (c16)R30}

Examples



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reg(X) = [b15, . . . , b15 | { z }

48 times


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)

Example: addrc16 :=I Y {STQ Y, (c16)R30}u State transition for addrc16 :=I Y:

Examples



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12 Wolf Zimmermann



reg(X) = [b15, . . . , b15 | { z }

48 times, b15, . . . , b0] ZAP X, #fc, X reg(X) := zerobytes(reg(X), #fc)

reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)


mem(eval(addrc16)) := eval(rg(Y))

Examples



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12 Wolf Zimmermann



reg(X) = [b15, . . . , b15 | { z }


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)


mem(eval(addrc16)) := eval(rg(Y)) = mem(base SExt16(c16)) := reg(Y)

Examples



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12 Wolf Zimmermann

Example: c3 X; { X, (c3 L)R3 ; X, # c, X; X, (c3 H)X}u eval(intc32) = SExt32(c32)


reg(X) = [b15, . . . , b15 | { z }


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)


mem(eval(addrc16)) := eval(rg(Y)) = mem(base SExt16(c16)) := reg(Y)= mem(reg(R30) SExt16(c16)) := reg(Y)

Examples



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12 Wolf Zimmermann

p ; { , ( ) ; , # , ; , ( ) }u eval(intc32) = SExt32(c32)


reg(X) = [b15, . . . , b15 | { z } 48 times


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)



u State transition for STQ Y, (c16)R30:

Examples



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12 Wolf Zimmermann

p ; { , ( ) ; , # , ; , ( ) }u eval(intc32) = SExt32(c32)


reg(X) = [b15, . . . , b15 | { z } 48 times


reg(X) = [0, . . . , 0 | { z }

48 times



reg(X) = [b31, . . . , b31 | { z }

32 times

, b31, . . . , b0] = SExt32(c32)



u State transition for STQ Y, (c16)R30:

mem(reg(R30) SExt16(c16)) := reg(Y)

Skip assembly

7. Assembly

After Code Selection: Basic Block Graph with Machine Instructions


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13 Wolf Zimmermann

p

7. Assembly



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13 Wolf Zimmermann

u Binary Format except jumps

7. Assembly



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u Binary Format except jumps Linearize basic block graphs and map jumps

7. Assembly



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13 Wolf Zimmermann


Mapping Jumps: Labels are mapped to jump targets

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb

Relative distance small

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb


Relative address cannot beencoded in instruction

7. Assembly

After Code Selection: Basic Block Graph with Machine Instructionsu Bi F j


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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb



a:

a:

JMP bb2Instructions

for computing a

JMP R

bb1

bb2

bb1

bb2

stored in R

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb



a:

a:

JMP bb2Instructions

for computing a

JMP R

bb1

bb2

bb1

bb2

stored in R

Relative distance large

7. Assembly



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13 Wolf Zimmermann



bb2

bb

2

2bb

1bb

JMP bb

1

No jump necessary

a+c:

a:JMP bb2

1

bb

bb1

2

2

JMP c

bb

bb



a:

a:

JMP bb2Instructions

for computing a

JMP R

bb1

bb2

bb1

bb2

stored in R

Relative distance largeAbsolute address of jumptarget must be computedin a register

Example: DEC-Alpha

Term-Rewrite Rules: Lett is the address of the jump instruction


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14 Wolf Zimmermann

current is the address of the jump instruction,

Example: DEC-Alpha

Term-Rewrite Rules: Letcurrent is the address of the jump instruction


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current is the address of the jump instruction,addrbb(L) is the address of the first instruction of basic block with label L

Example: DEC-Alpha



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14 Wolf Zimmermann

current is the address of the jump instruction,addrbb(L) is the address of the first instruction of basic block with label L

l = addrbb(L) current,

Example: DEC-Alpha


8/3/2019 Wolf Zimmermann- On the Correctness of Transformation

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Wolf Zimmermann- On the Correctness of Transformations in Compiler Back-Ends

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