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STTP on Digital System Design & FPGA organized

at GEC Gandhinagar Delivered by eiTRA

Digital System Design & FPGA

(15th

-19th

June, 2015)

Expert : Ms. Ekata Mehul

Head, eiTRA

Mr. Ashish Purani

Technical Associate – VLSI (FPGA),

eiTRA

Venue : Govt. Engineering College

Sector-28,

Gandhinagar,

Gujarat, 382028

Date : 15th

& 19th June, 2015

Timing : 10:30 AM – 5:30 PM

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STTP on Digital Design using FPGA using Xilinx Spartan FPGA Development Kits

Five days industry oriented Short Term Training Program (STTP) on Digital Design on FPFA using Xilinx FPGA

Development Kits, funded by TEQIP program, was successfully organized by eiTRA at GEC, Gandhinagar. Ms. Ekata

Mehul (Head, eiTRA) started the STTP with a brief and precise explanation about the topics such as role of FPGA,

FPGA vs ASIC development and current trends in VLSI industry. Expert in FPGA domain, Mr. Ashish Purani

delivered and shared his rich practical knowledge on wide range of topics such as Digital Design concepts and

implementation, Verilog coding styles as well as writing Testbenches, ASIC and FPGA Design flow, FPGA

Architecture concepts, FPGA implementation, using readily available IP Cores and debugging designs using Chipscope

Pro.

About the Experts

Ms. Ekata Mehul is currently working as Head, eiTRA. She has a rich experience in the field of Computer

Engineering, IT, & Embedded Systems. She has previously worked as a training coordinator for ASIC division at

eInfochips for almost 3 years and has a rich teaching experience of around 14 years in the field of software,

networking and embedded.

Mr. Ashish Purani is currently working as a Technical Associate in VLSI-FPGA domain at eiTRA. He has

experience in VLSI backend as well as frontend design flow covering entire ASIC design cycle. He has done his

Masters degree in VLSI from Nirma University, Ahmedabad and has a total experience of more than 2.5 years in

the field of Digital Design and FPGA.

Participants of the Workshop

Total 9 professors and 22 students from GEC Gandhinagar College actively participated in the STTP.

Technical Learnings

Current Trends and role of Programmable logic devices in VLSI Design Industry

Digital Design concepts & implementation

Verilog concepts

Different Modelling styles used in Verilog

DUT verification by simulation using Directed Testbenches

Synthesizable coding targeted to Xilinx devices

FPGA Architecture basics

ASIC & FPGA Design flow

Synthesis and FPGA Implementation

IPCoregen Flow: Using Xilinx IP’s

Chipscope Pro Flow: Advance Debugging of Design

Practical Hands-on

Digital Design using Logicworks

Xilinx ISE software for writing HDL codes

Verifying the HDL codes by writing Testbenches using ISim (Xilinx ISE)

Synthesis of HDL codes on Xilinx FPGA Kits

IPCoregen flow

Xilinx ISE Design flow

Chipscope Pro flow

List of FPGA Practicals –Full Adder, Ripple-carry Adder, DFF, Counters, Shifters, ALU, RAM/ROM etc.

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Software & Boards Specification

Logicworks 5.0

Xilinx ISE 14.2 and its associated Toolchain

Xilinx Spartan 3 and 6 FPGA Development kits

Major Take-away from the workshop

Participants got hands-on experience on Digital Logic Design concepts and implementation, Verilog basics and

understanding the powerful features of the language. Participants also got introduced to ASIC vs. FPGA Design flows.

They were introduced with the concepts of FPGA internal architecture and finally they also got exposure to the FPGA

design flow by themselves synthesizing their own HDL codes into the various development kits from Xilinx.

Participants also got hands on experience for using the Xilinx IP’s provided as a part of package in their design.

Certification – Certificate of knowledge enhancement and participation was given to all the participants.

eiTRA Contact Details eiTRA Ahmedabad, 2

nd Floor, CIASIS Building,

Near Umiya Campus, Sola Bhagwat, Ahmedabad – 380060. Contact: (M) 99099 84110 Email: info@eitra.org

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