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CS6201-DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 1

Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Introduction to Unit IV Time: 45 Minutes Lesson. No Unit IV-Lesson No.1/9

1.CONTENT LIST: Introduction to Unit IV

2. SKILLS ADDRESSED: x Listening

3.OBJECTIVE OF THIS LESSON PLAN: To make the students learn the topics to be covered in unit IV.

4.OUTCOMES: i. Learn the major topics in Unit IV.

ii. Describe the uses in designing Synchronous sequential circuits. 5.LINK SHEET:

i. What is Asynchronous sequential circuits ii. Compare Asynchronous and synchronous sequential circuits

iii. List the major topics in synchronous sequential circuits. iv. Mention the uses in designing the synchronous sequential circuits.

6. EVOCATION :( 5 Minutes)

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Analogy for asynchronous circuits

6.LECTURE NOTES: (40 Minutes) Asynchronous sequential Circuits The change of internal state occurs when there is a change in the input variables. Memory elements are unclocked flip-flops or time-delay elements. When an input variable changes in value, the y secondary variables do not change instantaneously.

In steady-state condition, the y's and the Y's are the same, but during transition they are not. Comparison between synchronous and asynchronous circuits

Synchronous Sequential Circuits Asynchronous Sequential Circuits

Timing problems are eliminated by triggering all flip-flops with pulse edge.

Care must be taken to ensure that each new state is stable even though a feedback path exists.

Memory elements are clocked flip-flops Memory elements are unclocked flip-flops or time-delay elements.




Topics to be covered Introduction to asynchronous sequential circuits Analysis of asynchronous sequential circuits Design of asynchronous sequential circuits Reduction of state and flow tables Race-free state assignment Hazards

Uses in designing the logic circuits Asynchronous Sequential Circuits

The change of internal state occurs when there is a change in the input variables. Analysis of asynchronous sequential circuits

x Transition Table x Flow Table x Race Conditions x Stability Consideration from the logic diagram

Design of asynchronous sequential circuits x Design Specification x Primitive Flow Table x Implication Table x Reduction of the Primitive Flow Table x State Assignment and Transition Table x Logic Diagram

Reduction of state and flow tables Two states are equivalent if for each possible input; they give exactly the same output and go to the same next states or to equivalent next states.

Race-free state assignment The primary objective in choosing a proper binary state assignment is the prevention of critical races. Critical races can be avoided by making a binary state assignment.

Hazards Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays.

8. TEXT BOOKS: Sanjay kumar Suman, L. Bhagyalakshmi, Porseli, “Digital Principles and System Design”, Vijay Nicole Publications.

9. APPLICATIONS Application of asynchronous circuits: high performance, low power, improved noise and electromagnetic compatibility (EMC) properties, and natural match with heterogeneous system timing.



SRIVIDYA COLLEGE OF ENGINEERING AND TECHNOLOGY, VIRUDHUNAGAR


Sri Vidya College of Engineering and Technology Department of Information Technology

Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Analysis of asynchronous sequential circuits Time: 45 Minutes Lesson. No Unit IV-Lesson No.2/9

1.CONTENT LIST: Analysis of asynchronous sequential circuits

2. SKILLS ADDRESSED: x Remembering x Applying x Learning

3.OBJECTIVE OF THIS LESSON PLAN: To make the students apply the steps of implementation in analyzing asynchronous sequential circuits.

4.OUTCOMES: i. Understand the analysis procedure of asynchronous sequential circuits

ii. Illustrate the procedure with an example 5.LINK SHEET:

i. Discuss the analysis procedure with major steps. ii. Give an example to illustrate the analysis procedure of asynchronous sequential

circuits.




iii. Derive the Transition Table, Flow Table, Race Condition and stability consideration

6.EVOCATION:(5 Minutes)

Analogy for analysis of asynchronous sequential circuits 7. LECTURE NOTES: (40 Minutes)

Analysis Procedure of asynchronous sequential circuits: To analyze the circuits with basic operation and steps

¾ Transition Table ¾ Flow Table-map ¾ Race Conditions ¾ Stability Consideration

Example to illustrate analysis procedure Analyze the given circuit according to the major steps and transition equation, Y1 = xy1 + x'y2, Y2 = xy'1 + x'y2

Transition Table For a state to be stable, the value of Y must be the same as that of y = y1y2 Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2




In general, if a change in the input takes the circuit to an unstable state, y will change until it reaches a stable state.

Flow Table-map

Transition table whose states are named by letter symbol instead of binary values. It is called primitive flow table because it has only one stable state in each row. It is a flow table with more than one stable state in the same row.




Race Conditions

Two or more binary state variables change value in response to a change in an input variable

Stability Consideration Column 11 has no stable state. With input x1 x2 = 11, Y and y are never the same.




8. TEXT BOOKS:

Sanjay kumar Suman, L. Bhagyalakshmi, Porseli, “Digital Principles and System Design”, Vijay Nicole Publications.

9. APPLICATIONS They are useful in applications in which input signals may change at any time. Also cost less than the sequential circuits, therefore, for economical reasons, they find useful applications.





Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Design of asynchronous sequential circuits Time: 45 Minutes Lesson. No Unit IV-Lesson No.3/9

1.CONTENT LIST: Design of asynchronous sequential circuits

2. SKILLS ADDRESSED: x Remembering x Analyzing

3.OBJECTIVE OF THIS LESSON PLAN: To make the students apply the major procedure of implementation in designing asynchronous sequential circuits.

4.OUTCOMES: i. Understand the design procedure of asynchronous sequential circuits

ii. Illustrate the procedure with an example 5.LINK SHEET:

i. Discuss the design procedure with major steps. ii. Give an example to illustrate the design procedure of asynchronous sequential

circuits. iii. Design the circuit based on transition table and primitive flow table.


Analogy for design of asynchronous sequential circuits




7. LECTURE NOTES: (40 Minutes)

Design Procedure of asynchronous sequential circuits: To design the circuits with basic operation and steps

¾ State the design specifications ¾ Derive a primitive flow table ¾ Reduce the flow table by merging the rows ¾ Assign output to unstable states ¾ Make a race-free binary state assignment ¾ Obtain the transition table and output map ¾ Obtain the logic diagram using SR latch

Example to illustrate design procedure Design a negative-edge-triggered flip-flop. The circuit has two inputs, T (toggle) and C (clock), and one output, Q.

Specification of Total States

State

Inputs Output

Comments T C Q

a b c d e f g h

1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1

0 1 1 0 0 0 1 1

Initial input is 0 After state a Initial input is 1 After state c After state d or f After state e or a After state b or h After state g or c

Primitive Flow Table ¾ Obtain the flow table by listing all possible states ¾ Dash marks are given when both inputs change simultaneously ¾ Outputs of unstable states are don’t care




Implication Table

1.Build the implication chart 2.Delete the node with unsatisfied conditions 3.Repeat step 2 until equivalent states found

Merging the Flow Table

a. Determine all compatible pairs. b. Find the maximal compatibles c. Find a minimal closed collection of compatibles

(a, f ) ( b, g ) (b, h ) (c, h ) (d, e ) (d, f ) (e, f ) ( g, h )

The maximal compatible set: A group of compatibles that contains all the possible combinations of compatible states ( a, f ) ( b, g, h ) ( c, h ) ( d, e, f ) Reduced flow table




Two or more rows can be merged into one row if there are non-conflicting states and outputs in every columns

Assigning Output to Unstable States

1. Assign a 0 to an output variable associated with an unstable state that is a transient state between two stable states that have a 0 in the corresponding output variable.

2. Assign a 1 to an output variable associated with an unstable state that is a transient state between two stable states that have a 1 in the corresponding output variable.

3. Assign a don't-care condition to an output variable associated with an unstable state that is a transient state between two stable states that have different values in the corresponding output variable.

State Assignment and Transition Table. Assign a binary value to each state to generate the transition table




Logic Diagram An circuit without latch for triggered (T Flip-flop) is produced

8. TEXT BOOKS:


9. APPLICATIONS The circuits use handshaking between their components in order to perform the necessary synchronization, communication, and sequencing of operations.





Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Design of asynchronous sequential circuits Time: 45 Minutes Lesson. No Unit IV-Lesson No.4/9

1.CONTENT LIST: Design of asynchronous sequential circuits

2. SKILLS ADDRESSED: x Analyzing x Applying

3.OBJECTIVE OF THIS LESSON PLAN: To make the students apply the concept of procedure in designing asynchronous sequential circuits

4.OUTCOMES: i. Understand the key points of procedure in designing asynchronous sequential

circuits ii. Illustrate the procedure with given example

5.LINK SHEET: i. Discuss the key points of design procedure for asynchronous sequential circuit

ii. Give the main features of Gated D latch circuit iii. Design the Gated D latch circuit with transition table and primitive flow table.


Analogy for design of asynchronous sequential circuits




7. LECTURE NOTES: (40 Minutes)

Key points of design procedure � Reduction of the Primitive Flow Table � Assigning Output to Unstable States � Transition Table and Logic Diagram � Implementation with SR Latch

Design a Gated D latch Circuit Features of Gated D latch circuit Accept the value of D when G=1.Retain this value after G goes to 0 (D has no effects now)

Two inputs G (gate) and D (data), and one output Q. Primitive Flow table

Obtain the flow table by listing all possible states. Dash marks are given when both inputs change simultaneously. Outputs of unstable states are don’t care

State

Inputs Output

comments D G Q

a 0 1 0 D =Q because G = 1

b 1 1 1 D =Q because G = 1

c 0 0 0 After state a or d

d 1 0 0 After state c

e 1 0 1 After state b or f

f 0 0 1 After state e

Reduction of the Primitive Flow Table Two of more rows in the primitive flow table can be merged into one row if there are non-conflicting states and outputs in each of the columns.




Assigning Output to Unstable States

¾ Assign a 0 to an output variable that has a 0 in the corresponding output variable. ¾ Assign a 1 to an output variable associated that have a 1 in the corresponding

output variable. ¾ Assign a don't-care condition to an output variable s that has different values in

the corresponding output variable. Transition Table and Logic Diagram

¾ Assign a binary value to each state to generate the transition table.a=0, b=1 in this example

¾ Directly use the simplified Boolean function for the excitation variable Y ¾ An asynchronous circuit without latch is produced




Implementation with SR Latch Listed according to the transition table and the excitation table of SR latch

8. TEXT BOOKS:


9. APPLICATIONS The circuits use handshaking between their components in order to perform the necessary synchronization, communication, and sequencing of operations.





Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Reduction of state and flow tables Time: 45 Minutes Lesson. No Unit IV-Lesson No.5/9

1.CONTENT LIST: Reduction of state and flow tables

2. SKILLS ADDRESSED: x Learning x Applying

3.OBJECTIVE OF THIS LESSON PLAN: To make the students understand the concept of reduction in state and flow table

4.OUTCOMES: i. Understand the basic idea of state table and flow table

ii. Learn in brief the major steps underlined in reducing state and flow table. 5.LINK SHEET:

i. Define state reduction and flow table. ii. List the major steps underlined in reducing state and flow table.

iii. Explain the steps of reducing state and flow table in detail. 6.EVOCATION:(5 Minutes)




Reduction of states and flow table 7. LECTURE NOTES: (40 Minutes)

State Reduction and Flow table State Reduction

Two states are equivalent if they have the same output and go to the same (equivalent) next states for each possible input

Flow table x Similar to a transition table except the states are represented by letter symbols .Can also

include the output values. x Suitable to obtain the logic diagram from it x Primitive flow table: only one stable state in each row.

Steps underlined in reducing state and flow table x Implication Table Method x Merge the Flow Table x Compatible Pairs x Maximal Compatibles x Closed Covering Condition

Implication Table Method: x It is a chart that consists of squares, one for every possible pair of states. x On the left side along the vertical are listed all the states defined in the state table

except the last. x Across the bottom horizontally are listed all the states except the last. x The states that are not equivalent are marked with (X) in the corresponding

squares. x The states that are equivalent are marked with ( ) in the corresponding squares. x Some of the squares have entries of implied states that must be further

investigated to determine whether they are equivalent or not. Procedure to design implication table




¾ Build the implication chart ¾ Delete the node with unsatisfied conditions ¾ Repeat step 2 until equivalent states found

Merge the Flow Table x The state table may be incompletely specified. x Some next states and outputs are don’t care Primitive flow tables are always

incompletely specified. x Several synchronous circuits also have this property Incompletely specified states

are not “equivalent” x Instead, we are going to find “compatible” states x Two states are compatible if they have the same output and compatible next states

whenever specified x Three procedural steps:

1.Determine all compatible pairs. 2.Find the maximal compatibles 3.Find a minimal closed collection of compatibles

Compatible Pairs Implication tables are used to find compatible states. We can adjust the dashes to fit any desired condition. Must have no conflict in the output values to be merged .

Maximal Compatibles A group of compatibles that contains all the possible combinations of compatible state

Closed Covering Condition The set of chosen compatibles must cover all the states and must be closed Closed covering. The closure condition is satisfied if

� There are no implied states � The implied states are included within the

set 8. TEXT BOOKS:


. 9. APPLICATIONS

¾ The complexity in designing logic circuits is reduced. ¾ Bugs can be noticed and rectified. ¾ Easy to design many sequential circuits.





Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Reduction of state and flow tables Time: 45 Minutes Lesson. No Unit IV-Lesson No.6/9

1.CONTENT LIST: Reduction of state and flow tables

2. SKILLS ADDRESSED: x Analyzing x Applying

3.OBJECTIVE OF THIS LESSON PLAN: To make the students apply the basic procedure for reduction of state and flow table

4.OUTCOMES: i. Understand the basic concept of reduction of state and flow table.

ii. Illustrate the concept of reduction with an example. 5.LINK SHEET:

i. Define concept of reduction of states and flow table ii. Give an example to understand the concept for reduction of states and flow table.

iii. Derive Implementation table, maximal and compatible maximal pairs and merging of flow table.





Reduction of states and flow table 7. LECTURE NOTES: (40Minutes)

Reduction of states and flow table Two states are equivalent if they have the same output and go to the same (equivalent) next states for each possible input. For eg: The characteristic of equivalent states is that if (a,b) imply (c,d) and (c,d) imply (a,b), then both pairs of states are equivalent.

Steps underlined in reducing state and flow table x Implication Table Method x Merge the Flow Table x Compatible Pairs x Maximal Compatibles x Closed Covering Condition.

Example to illustrate the concept of reducing states and flow table Implication Table Method:

Two states are equivalent if, for each possible input, they give exactly the same output and go to the same next states or to equivalent next states.

a and b have the same output for the same input, their next states are c and d for x=0 and b and a for x = 1

If we can show that (c and d) are equivalent, then (a and b) are equivalent. [(a,b) imply (c,d)]

x It is a chart that consists of squares, one for every possible pair of states. x On the left side along the vertical are listed all the states defined in the state table

except the last. x Across the bottom horizontally are listed all the states except the last. x The states that are not equivalent are marked with (X) in the corresponding

squares. x The states that are equivalent are marked with ( ) in the corresponding squares. x Some of the squares have entries of implied states that must be further

investigated to determine whether they are equivalent or not.




Procedure to design implication table ¾ Build the implication chart ¾ Delete the node with unsatisfied conditions ¾ Repeat step 2 until equivalent states found.

� The equivalent states are: (a, b), (d, e), (d, g), (e, g). � Combine pairs of states into larger groups of equivalent states. (a, b), (d, e, g) � The equivalent states found from the implication table [(a, b) (d, e, g)] � All the remaining states in the state table that are not equivalent to any � other state. [(c) , (f)]

Merge the Flow Table

x The state table may be incompletely specified. x Some next states and outputs are don’t care Primitive flow tables are always

incompletely specified. x Several synchronous circuits also have this property Incompletely specified states

are not “equivalent” x Instead, we are going to find “compatible” states x Two states are compatible if they have the same output and compatible next states

whenever specified




x Three procedural steps: 4.Determine all compatible pairs. 5.Find the maximal compatibles 6.Find a minimal closed collection of compatibles

Compatible Pairs Implication tables are used to find compatible states. We can adjust the dashes to fit any desired condition. Must have no conflict in the output values to be merged.

Maximal Compatibles Maximal compatible is a group of compatibles that contains all the possible

combinations of compatible states. A merger diagram can be used to obtain the maximal compatible.

All possible compatibles can be found from the geometrical patterns in which states

are connected to each other.




Closed Covering Condition

The set of chosen compatibles must cover all the states and must be closed Closed covering. The closure condition is satisfied if

� There are no implied states � The implied states are included within the

set

¾ In the last example, the maximal compatibles are (a , b) (a , c , d) (b , e , f),if we remove (a , b), we get a set of two compatibles: (a , c , d) (b , e , f)

¾ All the six states are included in this set. ¾ There are no impiled states for (a,c); (a,d);(c,d);(b,e);(b,f) and (e,f) [you can

check the implication table] . the closer condition is satisfied The original primitive flow table can be merged into two rows, one for each of the compatibles.

¾ From the given implication table, we have the following compatible pairs: a , b ) ( a , d ) ( b , c ) ( c , d ) ( c , e ) ( d , e )

¾ From the merger diagram, we determine the maximal compatibles: ( a , b ) ( a , d ) ( b , c ) ( c , d , e )

¾ If we choose the two compatibles a , b ) ( c , d , e )

8. TEXT BOOKS: Sanjay kumar Suman, L. Bhagyalakshmi, Porseli, “Digital Principles and System Design”, Vijay Nicole Publications.

9. APPLICATIONS




¾ The complexity in designing logic circuits is reduced. ¾ Bugs can be noticed and rectified. ¾ Easy to design many sequential circuits.


Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Race-free state assignment Time: 45 Minutes Lesson. No Unit IV-Lesson No.7/9

1.CONTENT LIST: Race-free state assignment

2. SKILLS ADDRESSED: x Remembering x Learning

3.OBJECTIVE OF THIS LESSON PLAN: To make the students understand the basic concepts of race free state assignment

4.OUTCOMES: i. Understand the basic concept of race free state assignment

ii. Illustrate the concept of race free state assignment with various examples. 5.LINK SHEET:

i. Define race and non race condition ii. What is the need of using race free state assignment

iii. Deduce race free state assignment for various row method 6.EVOCATION:(5 Minutes)




Race free state asignment 7. LECTURE NOTES: (40 Minutes)

Race Conditions Two or more binary state variables change value in response to a change in an input variable

Noncritical race The final stable state that the circuit reaches does not depend on the order in which the state variables change.

Need of using race free state assignment � The primary objective in choosing a proper binary state assignment is the

prevention of critical races. � Critical races can be avoided by making a binary state assignment in such a way

that only one variable changes at any given time when a state transition occurs in the flow table.

Examples of race free state assignment Three-Row Flow-Table Example This assignment will cause a critical race during the transition from a to c.

The transition from a to c must now go through d, thus avoiding a critical race.




Multiple-Row Method

In the multiple-row assignment, each state in the original flow table is replaced by two or more combinations of state variables.

Note: a2 is adjacent to d2, c1, b2. 8. TEXT BOOKS:


9. APPLICATIONS ¾ A state assignment technique is he state assignment technique described adds cycles

and states, always attempts to use the minimum or near-minimum number of state variables and states.




¾ This technique has been implemented and incorporated into an ASLC design automation system introduced for synthesizing large-scale asynchronous sequential logic circuits (ASLCs).


Class I year, 02 sem Subject Code CS6201 Subject Digital Principles & System Design Prepared By S.Seedhanadevi Lesson Plan for Hazards Time: 45 Minutes Lesson. No Unit IV-Lesson No.8/9

1.CONTENT LIST: Hazards

2. SKILLS ADDRESSED: x Remembering x Applying

3.OBJECTIVE OF THIS LESSON PLAN: To make the students understand the basic concepts of Hazards

4.OUTCOMES: i. Understand the basic concept of Hazards

ii. Learn the hazards in combinational and sequential circuits 5.LINK SHEET:

i. Define Hazards. ii. List the types of hazards.




iii. Explain Hazards in combinational and sequential circuits. iv. Define essential hazard. v. Give an example to design hazard free circuits.


7.LECTURE NOTES: (40 Minutes) Hazards Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delay. Types of Hazards

¾ The first implementation may cause the output to go to 0 when it should remain at 1 (Static 1‐hazard), while the second implementation may cause the output to go to 1 when it should remain at 0 (Static 0‐hazard).

¾ The dynamic hazard causes the output to change three or four times when it should change from 1 to 0 or from 0 to 1.

Hazards in Combinational Circuits




Before the output of gate 2 changes to 1.

In that case, the output goes to 0 for short interval of time.

Y = x1 x2 + x2 ' x3 or Y = (x1 + x2 ' )(x2 + x3 )

(sum of products) (product of sums) Hazards in Sequential Circuits

If the circuit is in total state yx1x2 = 111 and input x2 changes from 1 to 0, the next total state should be 110. However, because of the hazard, output Y may go 0 momentarily.

If this false signal feeds back into gate 2, the output of gate 2 will remain at 0 and the circuit will switch to the incorrect total state 010. This problem can be eliminated by adding an extra gate.




Essential Hazards ¾ An Essential Hazard: is caused by unequal delays along two or more paths that

originate from the same input. ¾ Essential hazards cannot be corrected by adding redundant gates as in static

hazards. ¾ The problem can be corrected by adjusting the amount of delay in the affected

paths. Hazard Free Circuit The hazard exists because the change of input results in a different product term covering the two minterms.

The remedy for eliminating a hazard is to enclose the two minterms in question with another product term that overlap both grouping.

8. TEXT BOOKS:


9. APPLICATIONS ¾ Fast ¾ Efficient ¾ Accurate ¾ Cost in designing combinational and sequential circuits.


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