09/04/97 1
Xilinx Cadence Alliance Series
Technology through Teamwork
09/04/97 2
Agenda
Product Overview
Design Flow Methodology
XACT 5.2.1 to M1 Migration
09/04/97 3
Product Overview
Cadence FPGA Products
XACT (pre-M1) Cadence Interface
Cadence Releases
Xilinx M1.3 Development System
Xilinx Releases
09/04/97 4
Cadence FPGA Products
Schematic Concept
(Originally from Valid,used mostly by systemlevel designers)
Composer
(Cadence home-grown, used more byASIC designers)
Simulation Verilog-XL
(Verilog simulator)
Leapfrog
(VITAL-compliantVHDL simulator)
Synthesis Synergy
(Cadence synthesisengine; Runsstandalone or withschematic integration,infers LogiBLOX)
FPGA Designer
(Cadence front-endGUI for Synergyengine and FPGAimplementation tools)
Supported in XACTstep 5.2.x, but no longer supported in the Xilinx M1.3 release
09/04/97 5
Xilinx Cadence Comments
DS-381-xx 51020 (Concept) +51022 (Composer)
Interface & Libraries forConcept, Composer, andVerilog)
DS-CDN-STD-xx 51020 (Concept) +51022 (Composer) +Xilinx Core
DS381 + Xilinx DS-3PA-STD (DS502 & DS550 -P&R)
N/A FPGA Designer :
51170 (incl. 51021)
51070 (incl. 51023)
FPGA Designer:
51021 or 51023 + Synergylibraries + Cadence GUIdesign manager
XACT Cadence Interface (pre-M1)
Effective 11/1/96, Cadence no longer distributes the Xilinx Core tools.Xilinx has exclusive ownership of both maintenance and support of these tools.
09/04/97 6
Cadence Releases
Release Date Platform Comments
9604 11/96 Sun, Solaris, HP,RS6000
Integrated with XACTStep 5.2.x
97A 04/97 Sun, Solaris, HP,RS6000
Integrated with XACTStep M1.3
4KE/EX, 9K Synergy libsavailable on Cadence FTP
97B 11/97 Sun, Solaris, HP,RS6000
4KE/EX, 9K Synergy libsavailable on the 97B CD
Compatible with Xilinx M1.3 Release
09/04/97 7
M1 Software ProductsProduct Series PC & WS Device Support
Alliance Base XC9500, XC7300, XC3000x,
up to XC4008E/XL
up to XC5206
Standard XC9500, XC7300, XC3000x,
XC4000E/XL, XC5200
Foundation Base XC9500, XC7300, XC3000x,
up to XC4008E/XL
up to XC5206
Standard XC9500, XC7300, XC3000x,
XC4000E/XL, XC5200
Cadence interface libraries and netlisters must be obtained from Cadence
09/04/97 8
M1 Cadence InterfaceM1 Cadence Interface Component Applications
Concept Unified Libraries Xilinx Unified Library schematicsymbols for Concept design entry.
Concept VAN-compiled UnifiedLibraries
Cadence VAN-compiled libraries usedduring the CONCEPT2XIL netlistingprocess.
Unified Verilog Simulation Libraries Libraries for front-end Verilog HDLDirect functional simulation of Conceptand Synergy designs.
Concept Front-end Netlister:CONCEPT2XIL
Generate Verilog functional simulationnetlist from Concept schematic design.
Translate Concept schematic design toEDIF 2 0 0 netlist for Xilinx M1 designimplementation.
Xilinx Back-end Verilog Netlister:NGD2VER
Generate structural Verilog simulationnetlist (*.v), SDF timing file (*.sdf) andVerilog simulation test fixture template(*.tv). These files are read by theCadence Verilog-XL simulator.
Board-level Back-end Netlister:XIL2CDS
Generate board-level simulationinterface data: “chips_prt” and “body”files.
09/04/97 9
M1 Cadence InterfaceM1 Cadence Interface Component Applications
M1.3 Quick Start Guide, App. A Installation and setup, Cadence M1 flowintroduction and highlights
Cadence Interface User Guide andTutorial
Describes Concept-Xilinx designimplementation. Includes sample designtutorial.
Cadence XACT to M1 DesignConversion Guide
Conversion guide for migrating existingConcept/XACT designs to the ConceptM1 flow.
09/04/97 10
Xilinx M1 Releases
Release Date Platform Comments
XACTStep5.2.X
07/95 Sun, HP,Solaris
Supports 3K, 4KE, 5K, 7K only
M1.2AlliancePre-release
05/97 Sun, HP,Solaris
Cadence interface solutionfirst introduction (Beta release)
M1.3 07/97 Sun, HP,Solaris,RS6000
Cadence interface FCSrelease4KE/EX/XL, 7K and 9Ksuppport
M1.4 11/97 Sun, HP,Solaris,RS6000
Performance and qualityenhancements, 4KXV, 3K and5K support
09/04/97 11
Design Flow Methodology
M1 Flow
Schematic Entry
HDL Synthesis
M1 Implementation
Verilog Timing Simulation
Summary
09/04/97 12
Xilinx M1 Design Flow
VerificationVerification
PointPoint
IntegrationIntegration
DDesignesignSSourcourcee
ImplementationImplementation
KK nowledgenowledge-DDrivenriven
• Schematic entry: CONCEPT• HDL entry: SYNERGY• Interface netlist: EDIF
• Device Implementation: Xilinx Design Manager & Flow Engine
• Interface Netlist: Verilog or VHDL• Simulator: Verilog-XL or VITAL-
compliant simulator (Leapfrog)
09/04/97 13
Concept Schematic Flow
Concept Unified Sch. Libraries
Optional
LogiCores
LogiBLOXmodule.v
Via HDL_Direct
Schematic Design
Schematic Entry
Genview
SymbolBody
CONCEPT
ConstraintsFile
Implementation Tools
Knowledge Driven
module.ngoVerilog *.v
EDIF *.edf
CONCEPT2XIL CONCEPT2XIL -sim_only
.v file .vf fileUser-SpecifiedVerilog Testbench
Verilog Unified
SimulationLibraries
Functional Simulation
Verilog-XL
- netlister from Cadence
09/04/97 14
Synergy Synthesis Flow
ConstraintsFile
module.ngo
LogiCores
LogiBLOX
VLOG2XIL
EDIF *.edfUser-SpecifiedVerilog Testbench
Verilog Unified
SimulationLibraries
Optional
VHDL or Verilog HDL
Post-Synthesis Functional Simulation
RTL Behavioral Simulation
Implementation Tools
Knowledge Driven
HDL Entry
SYNERGY
Functional Simulation
Verilog-XL
Synergy SynthesisLibraries
.NCF
Timingconstraints
Structural Verilog *.v
- netlister from Cadence
09/04/97 15
HDL Entry
LogiBLOX
Timing
Concept/Synergy Mixed Mode Flow
SYNERGY
Schematic Entry
Genview
SymbolBody
CONCEPT Concept Unified
Schematic Libraries
.UCF ConstraintsFile Implementation Tools
Knowledge Driven
EDIF *.edf
CONCEPT2XIL CONCEPT2XIL -sim_only
.v file .vf file
User-SpecifiedVerilog Testbench
Verilog Unified
SimulationLibraries
Functional Simulation
Verilog-XL
Synergy SynthesisLibraries
Structural Verilog *.v
Concept top level schematic
Structural Verilog *.v.NCF .NGO
- netlister from Cadence
09/04/97 16
Generic Mixed Mode Flow
ConstraintsFile
Concept Unified
Schematic Libraries
module.ngo
module.v
Via HDL_Direct
Non-schematic block:
EDIF, XNF or NGO
Optional
LogiCores
LogiBLOX
Schematic Entry
Genview
SymbolBody
CONCEPT
Implementation Tools
Knowledge Driven
EDIF
CONCEPT2XIL
XIL2CDSBoard-levelSimulationPin
SDF
Testfixture
Verilog
Verilog
VerilogSimprimLibrary
Timing Simulation
Verilog-XL
Functional Simulation
Verilog-XL
EDIF, XNF, or NGO
NGDBuild
NGD2VER
- netlister from Cadence
09/04/97 18
Xilinx Implementation Flow
ImplementationImplementation
KK nowledgenowledge-DDrivenriven
NGDBuild
.ngd
NGDAnno
routed.nga
MAP
.ncd
BITGEN
routed.bit
PAR
routed.ncd
To Post-Implementation Timing Simulation
.edf
To Design Download
.xnf .ngo
To Simprim-Based Functional Sim.
To Post-Map Timing Sim.
NGD2VER
NGD2VER
09/04/97 19
Timing Simulation (Verilog)
NGD2VER -tf -ul -pf
.pin
.nga
VerificationVerification
PointPoint -tf: Generate testfixture-ul: Include `uselib-pf: Generate pin file - (for board-level sim)
.sdf .tv .v
User-SpecifiedVerilog Testbench
Verilog SimprimLibrary
For Board-level Simulation
Chips_prt Body
Timing Simulation
Verilog-XL
Edit
XIL2CDS
- netlister from Cadence
09/04/97 20
Timing Simulation (VHDL)
NGD2VHDL -tb
.nga
VerificationVerification
PointPoint-tb: Generate testfixture
.sdf .tb .vhd
User-SpecifiedVHDL Testbench
** VHDL SimprimLibrary
Timing Simulation
Leapfrog
Edit
[ ]
** This Library must be compiled by user
09/04/97 21
Flow Summary
Implementation Tools
Knowledge Driven Timing Simulation
Verilog-XL
Schematic Entry
CONCEPT
HDL Entry
SYNERGY
EDIF
VLOG2XILConcept2XIL
XIL2CDS
Functional Simulation
Verilog-XL
Board-levelSimulation
Pin
SDF
Testfixture
Verilog
Concept2XIL -sim_only
Verilog
Verilog Unified
SimulationLibraries
Verilog
Concept Unified
Schematic Libraries
VerilogSimprimLibrary
Synergy SynthesisLibraries
- netlister from Cadence
09/04/97 22
Cadence Methodology Changes
Cadence 5.X Environment— lib/cell/view/file structure
PIC flow— Verilog as intermediate format— EDIF interface to Xilinx— Standard HDL Direct methodology
09/04/97 23
XACT to M1 Migration ITERATED INSTANCES instead of
SIZE property (See HDL Direct User Guide)
— modify PATH property— Ex. PATH = I4 changes to PATH=I4(2:0) to
indicate 3 copies of an object
SCALD to HDL Direct schematic conversion (REQUIRED)
X-BLOX to LogiBLOX conversion— all X-BLOX modules must be replaced with their
LogiBLOX counterparts
09/04/97 24
XACT to M1 Migration
Iterated Instances instead of SIZE property— Ex. Set PATH = I4(2:0) to indicate 3 copies of an object
with PATH value of I4
PATH = I4(2:0)PATH = I4
3 instances
D Q D Q
09/04/97 25
XACT to M1 Migration
Tapping Bus Bits— renaming of bits not allowed
ctrl2
ctrl1
ctrl0
ctrl<2..0>
**** WRONG! ****(bits renamed, alias_bit error)CORRECT
ctrl<2>
ctrl<1>
ctrl<0>
ctrl<2..0>
09/04/97 26
XACT to M1 Migration
Other “GOTCHA’s”:
— MERGE bodies--all nets must be named
— Name of each design subblock must match the corresponding SCALD directory name
ctrl<2>
ctrl<1>
ctrl<0>
ctrl<2..0>
09/04/97 27
M1 SCALD to HDL Direct Conversion
SCALD HDL Direct
global.cmd ------------ hdl_direct_lib
Bus taps TAP orCTAP body
SLICE body
Merging signalsinto buses
MERGE bodies CONCAT bodies
Naming netstapped offbuses
mybus0,mybus1
mybus<0>mybus<1>
Interfacesignals
“\I” suffix + FLAGbody
INPORT,OUTPORT,IOPORT
09/04/97 28
M1 SCALD to HDL Direct Conversion
SCALD HDL Direct
global signals Use “\G” suffix.Ex. signal\G
Use “/” prefix.Ex. /signal_name
GND and VCC XVCC andXGNDfromxpads_scald
VCC and GNDfrom xce______architecture-specificlibrary
Synonymbodies
synonym alias
Concatenatingsignals
: (colon) & (ampersand)
Namingconventions
SCALD Must be Verilog- andVHDL-compliant
signals andbodies can sharethe same names
No overlap allowedwhen naming signalsand bodies
09/04/97 29
X-BLOX to LogiBLOX Conversion
Recommended method: Replace all X-BLOX components with LogiBLOX modules
— Generate LogiBLOX module – .v (gate level netlist for simulation
only)– .NGO (for implementation)– Verilog template (for instantiation in Verilog)
— Create symbol body (schematics only)– genview in Concept– Add: parameter cds_action=“ignore”;
— Instantiate module in your design
09/04/97 30
Integrating LogiBLOX modules
Run LogiBLOX standalone:— lbgui (select “cadence” as vendor)
Generate symbol body from .v file— genview -i <module.v> -v logic body verilog
Add line to block/logic/verilog.v module:— parameter cds_action = “ignore”;
Copy .ngo file to Xilinx run directory — (xilinx.run, by default)
09/04/97 31
X-BLOX to LogiBLOX Conversion
Alternate Method (short-term solution only)
— Process design in XACT down to .XTF
— Use .XTF as input to M1 Core tools— Disadvantages
– No support for new architecture features– No support for XNF format will be available in
future M1.5 release
09/04/97 32
New Libraries
M1 Concept Unified Library
M1 Verilog Unified Library
M1 SIMPRIM Verilog Library
M1 Synergy Libraries (available from Cadence only)
No Composer support
09/04/97 33
New Libraries
Concept Unified — $XILINX/cadence/data/xce<family>
(e.g. xce4000ex)— No support for SIZE property
– use Iterated Instances— compatible with pre-M1 Concept Unified
libraries– shape and size of symbols– pin locations– component and pin names
09/04/97 34
New Libraries
Verilog Unified simulation library— $XILINX/cadence/data/ verilogxce______
(e.g., verilogxce4000ex)— for HDL Direct functional simulation
only— no timing checks
09/04/97 35
New Libraries
SIMPRIM Verilog libraries— included as part of Xilinx M1 Core— generic, architecture-independent — located in $XILINX/verilog/data
09/04/97 36
New Libraries
SIMPRIM Verilog libraries— support all post-NGDBUILD simulation
– post-NGDBUILD (functional, gate-level)– post-MAP timing (optional)– post-PAR (post-route) timing
— library primitive naming system– X_FF.vmd (flip-flop)– X_BUF.vmd (buffer)
09/04/97 37
Concept Setup Files
master.local
design.wrk
global.cmd
cds.lib
startup.concept
09/04/97 38
master.local points to location of Xilinx Concept
libraries
file_type = master_library;
“xce4000ex” ‘/tools/xilinx/cadence/data/xce4000ex/xce4000ex.lib’;
“xce4000e” ‘/tools/xilinx/cadence/data/xce4000e/xce4000e.lib’;
“xce5200” ‘/tools/xilinx/cadence/data/xce5200/xce5200.lib’;
“xce3000” ‘/tools/xilinx/cadence/data/xce3000/xc3000.lib’;
“xce7000” ‘/tools/xilinx/cadence/data/xce7000/xce7000.lib’;
“xce9500” ‘/tools/xilinx/cadence/data/xce9500/xce9500.lib’;
end.
*Note: XC5200 and XC3000 architectures are not supported in the M1.3 core tools
09/04/97 39
design.wrk Concept project library file
FILE_TYPE = LOGIC_DIR;
"UNNAMED" 'unnamed';
"MYBLOCK" 'myblock';
END.
09/04/97 40
cds.lib Concept 5.x library file
define xce4000ex_syn /tools/xilinx/cadence/data/xce4000ex_syn
define xce4000e_syn /tools/xilinx/cadence/data/xce4000e_syn
define xce5200_syn / tools/xilinx/cadence/data/xce5200_syn
define xce3000_syn /tools/xilinx/cadence/data/xce3000_syn
define xce7000_syn /tools/xilinx/cadence/data/xce7000_syn
define xce9000_syn /tools/xilinx/cadence/data/xce9000_syn
*Note: XC5200 and XC3000 architectures are not supported in the M1.3 core tools
09/04/97 41
global.cmd Concept project library alias file
master_library "./master.local" ;
library "xce4000ex" ,
"hdl_direct_lib",
"xcepads",
"standard" ;
use "design.wrk" ;
root_drawing "unnamed" ;
09/04/97 42
startup.concept
(reinforces HDL Direct naming conventions)set hdl_direct on
set hdl_checks on
set check_signames on
set check_net_names_hdl_ok on
set check_port_names_hdl_ok on
set check_symbol_names_hdl_ok on
set capslock_off *(preserves case, may be important for TIMESPECs)
runopl /products/cds.ver97a/tools/fet/concept/hdl_direct /bin/autosym
09/04/97 43
Concept Properties
Properties are specified as: name=value—Use xilinx.pff in $XILINX/cadence/data as
a guide to property specification format—Boolean
– must be set to TRUE or FALSE– Example: FAST=TRUE (output slew rate)– KEEP=TRUE (“X” in XACT)
—Normal– Location constraints (LOC=P6)– Timegrps (GRP01=mygrp)
– (names are case-sensitive if you specify “set caps_lock_off” in startup.concept)
09/04/97 44
Concept Properties
Part type property— “PART=XC4028EX-3-PG299”—Attach to CONFIG symbol:
CONFIG
PART=XC4028EX-3-PG299
09/04/97 45
M1Global Signal
Support
09/04/97 46
Global signal support in M1.2/M1.3
M1.2.11: —glbl.v contains declarations of global wires
in “glbl” module—signals referenced as glbl.gsr, glbl.gts, etc.
M1.3.x: —Verilog macros in the test fixture assign the
names of the global signals—`define GSR_SIGNAL sig_name
09/04/97 47
Global signals in M1.2M1.2.11
—module glbl in separate glbl.v file– global signals declared as wires:
–wire gsr; // 4k –wire gts; // 4k, 5k* –wire prld; // 7k, 9k–wire gr; // 3k*, 5k*
* 3K and 5K not supported in M1.3 core tools
—pre-route HDL Direct simulation netlist:X_FF inst_name2 (.IN … .RST(glbl.gsr));
09/04/97 48
Global signals in M1.2—post-NGDBUILD simulation:
– glbl.gsr OR’d with local reset:
X_OR2 inst_name1 (.IN0(glbl.gsr),.IN1(local_clr),
.out(xxxx.GSR.OR));
X_FF inst_name2 (.IN(aaaa), .CLK(bbbb), .CE(cccc), .SET(ssss) … .RST(xxxx.GSR.OR));
—Testbench:–force glbl.gsr = 1;
09/04/97 49
Global signals in M1.2— Verilog-XL command line:
verilog design.tv design.v glbl.v
* glbl.v not supported in M1.3
09/04/97 50
Global signals in M1.3
Utilizes Verilog macros*
Unified Verilog library modifications to support the Verilog macros
Test fixture support
*Verilog macro:
`define xx_SIGNALwhere “xx” = GSR, GR, GTS, or PRLD
09/04/97 51
Global signals in M1.3--LIBRARIES
Global Reset support (4K)— Each 4K Verilog Unified library register
model contains the following block of code to model GSR:
`ifdef GSR_SIGNAL wire GSR = `GSR_SIGNAL;`else wire GSR;`endif
09/04/97 52
Global Tri-state in M1.3--LIBRARIES
Global Tri-state support (4K)— Each Verilog Unified library output buffer
model contains the following block of code to model GTS:
`ifdef GTS_SIGNAL wire GTS = `GTS_SIGNAL;`else wire GTS;`endif
09/04/97 53
Global signals in M1.3:TEST FIXTURES
global reset (4K)—(no Startup block)
module test; <port_list>reg GSR;`define GSR_SIGNAL GSR design uut (<port_list2>);initialbegin `GSR_SIGNAL = 1;#100 `GSR_SIGNAL = 0;
09/04/97 55
Global Tri-state signals in M1.3:TEST FIXTURES
global tri-state (4K, 5K*)reg GTS;`define GTS_SIGNAL GTS`GTS_SIGNAL = 1;#100 `GTS_SIGNAL = 0;
global reset (7K, 9K )reg PRLD;`define PRLD_SIGNAL PRLD`PRLD_SIGNAL = 1;#100 `PRLD_SIGNAL = 0;
* 5K is mentioned here for reference purposes only, not supported in M1.3 release
09/04/97 56
Summary: M1.3 LIBRARY support for
Xilinx globals
* 3K and 5K mentioned here for reference purposes only, not supported in M1.3 release
XC3000*,XC5200*
XC4000E/EX/XL
XC7000,XC9500
GlobalReset
All register macros andprimitive simulationmodels contain:
`ifdef GR_SIGNALwire GR = `GR_SIGNAL ;`else wire GR ;`endif
All register macros andprimitive simulation modelscontain:
`ifdef GSR_SIGNALwire GSR = `GSR_SIGNAL ;`else wire GSR ;`endif
All register macros andprimitive simulationmodels contain:
`ifdef PRLD_SIGNALwire PRLD =`PRLD_SIGNAL ; `else wire PRLD ;`endif
GTS All register macros andprimitive simulationmodels contain (5K only):
`ifdef GTS_SIGNALwire GTS = `GTS_SIGNAL ;`else wire GTS ;`endif
All register macros andprimitive simulation modelscontain:
`ifdef GTS_SIGNALwire GTS = `GTS_SIGNAL ;`else wire GTS ;`endif
N/A
09/04/97 57
M1.3 TEST FIXTURE support for Xilinx globals (XC5200*)
5200 No STARTUP With STARTUP
HDL Directfunctionalsimulation
module test;reg GR;`define GR_SIGNAL test.GR;…initialbegin `GR_SIGNAL=1; #100`GR_SIGNAL=0;…
[reg GR_user_control_pin;] (needed if controlsignal is an external pin)`define GR_SIGNAL net_connected_to_GR_pin;…initialbegin GR_user_control_signal=1; #100 GR_user_control_signal =0;…
Post-NGDBUILDSame methodology as in HDL Direct Functionalsimulation above when there is no STARTUPblock
module test;/* `define GR_SIGNAL test.uut.gr_in; *//* omit `define definition */…initialbegin mygr = 1; #100 mygr = 0;…
* 5K is mentioned here for reference purposes only, not supported in M1.3 release
09/04/97 58
M1.3 TEST FIXTURE support for Xilinx globals ( XC4000)
4000E/EX/XL No STARTUP With STARTUP
HDL Directfunctionalsimulation
module test;reg GSR;`define GSR_SIGNAL test.GSR;…initialbegin `GSR_SIGNAL=1; #100 `GSR_SIGNAL=0;…
module test;[reg GSR_user_control_pin;] (needed ifcontrol signal is an external pin)`define GSR_SIGNAL net_connected_to_GSR_pin;…initialbegin GSR_user_control_signal=1; #100 GSR_user_control_signal =0;…
Post-NGDBUILD
Same methodology as HDL DirectFunctional simulation when there is noSTARTUP block
module test;/* `define GSR_SIGNAL test.uut.gsrin; *//* omit `define definition */…initialbegin mygsr = 1; #100 mygsr = 0;…
09/04/97 59
M1.3 TEST FIXTURE support for Xilinx globals ( XC3000*)
3000A/L No STARTUP
HDL Directfunctionalsimulation
module test;reg GR;`define GR_SIGNAL test.GR;…initialbegin `GR_SIGNAL=0; #100`GR_SIGNAL=1;…
Post-NGDBUILD Same methodology as HDL Direct Functional
simulation when there is no STARTUP block
* 3K is mentioned here for reference purposes only, not supported in M1.3 release
09/04/97 60
Cadence Survival Kit
Use in case of emergency
09/04/97 61
Documentation
Xilinx manuals:•M1 QuickStart Guide•M1 Conversion Guide•M1 Cadence Interface/Tutorial Guide
Key Cadence manuals:•Concept User Guide•HDL Direct User Guide, Appendix C (SCALD to HDL Direct Conversion)
09/04/97 62
Where to go for help
Xilinx Support— Tech support: 1-800-255-7778
or [email protected]— Customer service: 1-800-562-4647— Web: http://www.xilinx.com/answers.htm
– Answers Search– Expert Pages / Cadence
Cadence Support— Tech support: 1-800-cadenc2 or
[email protected]— Web: http://sourcelink.cadence.com
(must be registered customer)