XILINX ISE 9.1/9.2By courtesy of Xilinx

EEP201: Digital ElectronicsIndian Institute of Technology, Delhi

FPGA Environment

How to start an FPGA project? How to describe logic circuit using schematic? How to simulate and check for errors?

simulation

Source Pane

Editor Pane

Process Pane

Transcript Pane

CONTINUE…….

SELECT SCHEMATIC

USEFUL SYMBOLS

ADD WIRE

I/O MARKER

HALF ADDER SCHEMATIC

HALF ADDER SCHEMATIC

ATTRIBUTE THE IO MARKER

HALF ADDER SCHEMATIC

CHECK SCHEMATIC

FIND TOOL OPTION FROM MAIN MENU

Tools > Symbol Wizard

CREATING A MACRO

PIN POSITION

CONTINUE WITH MACRO

MACRO LOOKS LIKE THIS

HERE WE ARE CREATING A NEW SCHEMATIC

4 BIT RIPPLE ADDER

DEFINING THE SIGNALS: TB

DEFINE INPUT TEST PATTERN

SAVE TEST BENCH

PRESS THE PROCESS TAB

DOUBLE CLICK SIMULATE BEHAVIOUR MODEL

SIMULATION RESULTS

References :

http://ece­www.colorado.edu/~ecen3100/lab/9.1_tutorial_3/xilinx_9.1_tutorial_3.htm http://ece­www.colorado.edu/~ecen3100/lab/9.1_tutorial_3/xilinx_9.1_tutorial_3.htm#demo